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Patch from Eric Valette <valette@crf.canon.fr> with two small

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fixes related to GDB over TCP/IP debug.
This commit is contained in:
Joel Sherrill
1999-10-05 14:02:57 +00:00
parent 4075af6f55
commit 133dcd92c9
4 changed files with 20 additions and 0 deletions
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8
c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S
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@@ -6,6 +6,10 @@
* found in found in the file LICENSE in this distribution or at * found in found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
*
* $Id$ * $Id$
*/ */
@@ -219,6 +223,10 @@ nested:
/* /*
* store it at the right place * store it at the right place
*/ */
stw r2, GPR1_OFFSET(r1)
/*
* Call High Level signal handling code
*/
bl _ISR_Signals_to_thread_executing bl _ISR_Signals_to_thread_executing
/* /*
* start restoring exception like frame * start restoring exception like frame

8
c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S
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@@ -6,6 +6,10 @@
* found in found in the file LICENSE in this distribution or at * found in found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
*
* $Id$ * $Id$
*/ */
@@ -219,6 +223,10 @@ nested:
/* /*
* store it at the right place * store it at the right place
*/ */
stw r2, GPR1_OFFSET(r1)
/*
* Call High Level signal handling code
*/
bl _ISR_Signals_to_thread_executing bl _ISR_Signals_to_thread_executing
/* /*
* start restoring exception like frame * start restoring exception like frame

2
c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S
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@@ -25,6 +25,8 @@
PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache) PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
SYM (copyback_data_cache_and_invalidate_instr_cache): SYM (copyback_data_cache_and_invalidate_instr_cache):
/* make sure the data changed is in the cache */
sync
/* r3 address to handle, r4 length in bytes */ /* r3 address to handle, r4 length in bytes */
addi r6, r0, PPC_CACHE_ALIGNMENT addi r6, r0, PPC_CACHE_ALIGNMENT
/* r5 = last address to handle */ /* r5 = last address to handle */

2
c/src/librdbg/src/powerpc/rdbg_cpu_asm.S
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@@ -25,6 +25,8 @@
PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache) PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
SYM (copyback_data_cache_and_invalidate_instr_cache): SYM (copyback_data_cache_and_invalidate_instr_cache):
/* make sure the data changed is in the cache */
sync
/* r3 address to handle, r4 length in bytes */ /* r3 address to handle, r4 length in bytes */
addi r6, r0, PPC_CACHE_ALIGNMENT addi r6, r0, PPC_CACHE_ALIGNMENT
/* r5 = last address to handle */ /* r5 = last address to handle */