Patch from Eric Valette <valette@crf.canon.fr> with two small

fixes related to GDB over TCP/IP debug.

c/src/lib/libbsp/powerpc/mcp750/irq/irq_asm.S

@@ -6,6 +6,10 @@
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
  *
+ *  Modified to support the MCP750.
+ *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
+ *
+ *
  * $Id$
  */
   	
@@ -219,6 +223,10 @@ nested:
         /*
          * store it at the right place
          */
+        stw     r2, GPR1_OFFSET(r1)
+	/*
+	 * Call High Level signal handling code
+	 */
 	bl	_ISR_Signals_to_thread_executing
 	/*
 	 * start restoring exception like frame

c/src/lib/libbsp/powerpc/motorola_powerpc/irq/irq_asm.S

@@ -6,6 +6,10 @@
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
  *
+ *  Modified to support the MCP750.
+ *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
+ *
+ *
  * $Id$
  */
   	
@@ -219,6 +223,10 @@ nested:
         /*
          * store it at the right place
          */
+        stw     r2, GPR1_OFFSET(r1)
+	/*
+	 * Call High Level signal handling code
+	 */
 	bl	_ISR_Signals_to_thread_executing
 	/*
 	 * start restoring exception like frame

c/src/lib/librdbg/powerpc/rdbg_cpu_asm.S

@@ -25,6 +25,8 @@
         PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
 
 SYM (copyback_data_cache_and_invalidate_instr_cache):
+	/* make sure the data changed is in the cache */
+	sync
 	/* r3 address to handle, r4 length in bytes */
 	addi	r6, r0, PPC_CACHE_ALIGNMENT
 	/* r5 = last address to handle */

c/src/librdbg/src/powerpc/rdbg_cpu_asm.S

@@ -25,6 +25,8 @@
         PUBLIC_VAR (copyback_data_cache_and_invalidate_instr_cache)
 
 SYM (copyback_data_cache_and_invalidate_instr_cache):
+	/* make sure the data changed is in the cache */
+	sync
 	/* r3 address to handle, r4 length in bytes */
 	addi	r6, r0, PPC_CACHE_ALIGNMENT
 	/* r5 = last address to handle */