bsp/microblaze-fpga: parameterize linker layout

Add build options for start address, vector base, and BRAM length,
wire them into the microblaze_fpga linker script and BSP group,
and add the dependencies to the kcu105_qemu BSP spec.

spec/build/bsps/microblaze/microblaze_fpga/grp.yml

@@ -20,6 +20,12 @@ links:
   uid: start
 - role: build-dependency
   uid: optconsoleinterrupts
+- role: build-dependency
+  uid: optvectoraddress
+- role: build-dependency
+  uid: optstartaddress
+- role: build-dependency
+  uid: optbramlen
 - role: build-dependency
   uid: optdcachebaseaddress
 - role: build-dependency

spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml

@@ -30,11 +30,12 @@ content: |
 
   ENTRY (_start)
   STARTUP (start.o)
-  _TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x80000000;
+  _TEXT_START_ADDR = ${BSP_MICROBLAZE_FPGA_START_ADDR};
+  _VECTOR_START_ADDR = ${BSP_MICROBLAZE_FPGA_VECTOR_ADDR};
 
   MEMORY
     {
-        BRAM     (AIW) : ORIGIN = 0x00000000, LENGTH = 0x10000
+        BRAM     (AIW) : ORIGIN = 0x00000000, LENGTH = ${BSP_MICROBLAZE_FPGA_BRAM_LENGTH}
         RAM   : ORIGIN = _TEXT_START_ADDR, LENGTH = ${BSP_MICROBLAZE_FPGA_RAM_LENGTH}
     }
 
@@ -54,11 +55,11 @@ content: |
 
   SECTIONS
   {
-    .vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0
-    .vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0
-    .vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0
-    .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0
-    .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0
+    .vectors.reset _VECTOR_START_ADDR + 0x0 : { KEEP (*(.vectors.reset)) } = 0
+    .vectors.sw_exception _VECTOR_START_ADDR + 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0
+    .vectors.interrupt _VECTOR_START_ADDR + 0x10 : { KEEP (*(.vectors.interrupt)) } = 0
+    .vectors.debug_sw_break _VECTOR_START_ADDR + 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0
+    .vectors.hw_exception _VECTOR_START_ADDR + 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0
     . = _TEXT_START_ADDR;
     .text : ALIGN_WITH_INPUT {
       bsp_section_text_begin = .;

spec/build/bsps/microblaze/microblaze_fpga/optbramlen.yml

@@ -0,0 +1,19 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) Sam Price 
+default: 
+- enabled-by: true
+  value: 0x10000
+description: |
+  length of block memory area
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_BRAM_LENGTH
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optstartaddress.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default: 
+- enabled-by: true
+  value: 0x80000000
+default-by-variant: []
+description: |
+  start address of the .text section
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_START_ADDR
+type: build

spec/build/bsps/microblaze/microblaze_fpga/optvectoraddress.yml

@@ -0,0 +1,20 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-uint32: null
+- env-assign: null
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+default: 
+- enabled-by: true
+  value: 0x00000000
+default-by-variant: []
+description: |
+  start address of the .text section
+enabled-by: true
+format: '{:#010x}'
+links: []
+name: BSP_MICROBLAZE_FPGA_VECTOR_ADDR 
+type: build