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contrib/riscv: add zicsr option to csr macros

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These were local changes in the riscv-utility.h but got missed
during the refactor. Fixes build error for riscv.
This commit is contained in:
Gedare Bloom
2026-05-03 10:35:13 -06:00
parent 7fa05a688b
commit 0c7ee5033d
1 changed files with 26 additions and 0 deletions
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26
contrib/cpukit/riscv-opcodes/encoding.h
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@@ -534,6 +534,31 @@
#ifdef __GNUC__
#ifdef __rtems__
#define read_csr(reg) ({ unsigned long __tmp; \
asm volatile (".option push\n.option arch, +zicsr\n" \
"csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
#define write_csr(reg, val) ({ \
asm volatile (".option push\n.option arch, +zicsr\n" \
"csrw " #reg ", %0" :: "rK"(val)); })
#define swap_csr(reg, val) ({ unsigned long __tmp; \
asm volatile (".option push\n.option arch, +zicsr\n" \
"csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
__tmp; })
#define set_csr(reg, bit) ({ unsigned long __tmp; \
asm volatile (".option push\n.option arch, +zicsr\n" \
"csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
asm volatile (".option push\n.option arch, +zicsr\n" \
"csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#else /* __rtems__ */
#define read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; })
@@ -552,6 +577,7 @@
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
__tmp; })
#endif /* __rtems__ */
#define rdtime() read_csr(time)
#define rdcycle() read_csr(cycle)