Prepare for RT-Thread 1.2.4 release.

tools: fix SrcRemove on empty src

.gitignore

@@ -9,28 +9,11 @@
 *.pdb
 *.idb
 *.ilk
-*.old
 build
-Debug
-documentation/html
 *~
 *.o
-*.obj
 *.bak
 *.dep
 *.lib
 *.a
-*.i
-*.d
-tools/kconfig-frontends/kconfig-mconf
-packages
-cconfig.h
-GPUCache
-
-#cscope files
-cscope.*
-ncscope.*
-
-#ctag files
-tags
 

.travis.yml

@@ -6,86 +6,58 @@ notifications:
 before_script:
 # travis has changed to 64-bit and we require 32-bit compatibility libraries
   - sudo apt-get update
-  # clang
-  - "sudo apt-get -qq install gcc-multilib libc6:i386 libgcc1:i386 gcc-4.6-base:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev || true"
-  # - sudo apt-get -qq install gcc-arm-none-eabi
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && export RTT_EXEC_PATH=/usr/bin && arm-none-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2014.05-28-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2014.05/bin && /opt/arm-2014.05/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 && sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt && export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin && /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version || true"
-  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/mips-sde-elf/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/mips-2016.05/bin && /opt/mips-2016.05/bin/mips-sde-elf-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
-  # - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
+  - "sudo apt-get -qq install clang gcc-multilib libc6:i386 libgcc1:i386 gcc-4.6-base:i386 libstdc++5:i386 libstdc++6:i386 libsdl-dev || true"
+  - "[ $RTT_TOOL_CHAIN = 'sourcery-arm' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/arm-none-eabi/arm-2012.09-63-arm-none-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/arm-2012.09/bin && /opt/arm-2012.09/bin/arm-none-eabi-gcc --version || true"
+  - "[ $RTT_TOOL_CHAIN = 'sourcery-mips' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/mips-sde-elf/mips-2012.09-98-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/mips-2012.09/bin && /opt/mips-2012.09/bin/mips-sde-elf-gcc --version || true"
+  - "[ $RTT_TOOL_CHAIN = 'sourcery-ppc' ] && curl -s https://sourcery.mentor.com/public/gnu_toolchain/powerpc-eabi/freescale-2011.03-39-powerpc-eabi-i686-pc-linux-gnu.tar.bz2 | sudo tar xjf - -C /opt && export RTT_EXEC_PATH=/opt/freescale-2011.03/bin && /opt/freescale-2011.03/bin/powerpc-eabi-gcc --version || true"
+  - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
   - export RTT_ROOT=`pwd`
   - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
+  - git clone --depth 1 https://github.com/RT-Thread/RTGUI.git $HOME/RTGUI
+  - export RTT_RTGUI=$HOME/RTGUI/components/rtgui
 
 script:
   - scons -C bsp/$RTT_BSP
 
 env:
-#  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
-  - RTT_BSP='CME_M7' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='apollo2' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt1052-evk' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
+  - RTT_BSP='simulator' RTT_CC='clang-analyze' RTT_EXEC_PATH=/usr/share/clang/scan-build
+  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
+  - RTT_BSP='dev3210' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='jz47xx' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='lpc1114' # no scons
+#  - RTT_BSP='lpc122x' # no scons
   - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc5410x' RTT_TOOL_CHAIN='sourcery-arm'
-#  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm' 
 #  - RTT_BSP='m16c62p' # m32c
   - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='microblaze' # no scons
   - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm' 
 #  - RTT_BSP='mini4020' # no scons
 #  - RTT_BSP='nios_ii' # no scons
-  - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='nuvoton_m05x' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='nuc140' # no scons
 #  - RTT_BSP='pic32ethernet' # no scons
-  - RTT_BSP='qemu-vexpress-a9' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
+#  - RTT_BSP='sam7s' # no scons
   - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='simulator' # x86
   - RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l072' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='stm32f107' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm' 
   - RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f411-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='stm32f429-armfly' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
+  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
 #  - RTT_BSP='upd70f3454' # iar
+#  - RTT_BSP='wh44b0' # no scons
 #  - RTT_BSP='x86' # x86
+  - RTT_BSP='xplorer4330/m4' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='beaglebone' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='zynq7000' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='frdm-k64f' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='fh8620' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='x1000' RTT_TOOL_CHAIN='sourcery-mips'

COPYING

@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+     59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
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+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
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+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
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+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
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+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) year  name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.

Kconfig

@@ -1,3 +0,0 @@
-source "$RTT_DIR/src/Kconfig"
-source "$RTT_DIR/libcpu/Kconfig"
-source "$RTT_DIR/components/Kconfig"

LICENSE

@@ -1,201 +0,0 @@
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-   limitations under the License.

README.md

@@ -1,88 +1,43 @@
 # RT-Thread #
 
-[中文页](README_zh.md) |
+[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.png)](https://travis-ci.org/RT-Thread/rt-thread)
 
-[![GitHub](https://img.shields.io/github/license/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE)
-[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
-[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
-[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
-[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
-[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
-
-RT-Thread is an open source IoT operating system from China, which has strong scalability: from a tiny kernel running on a tiny core, for example ARM Cortex-M0, or Cortex-M3/4/7, to a rich feature system running on MIPS32, ARM Cortex-A8, ARM Cortex-A9 DualCore etc.
+RT-Thread is an open source real-time operating system for embedded devices from China. RT-Thread RTOS is a scalable real-time operating system: a tiny kernel for ARM Cortex-M0, Cortex-M3/4, or a full feature system in ARM Cortex-A8, ARM Cortex-A9 DualCore etc. 
 
 ## Overview ##
 
-RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue, signal etc. However, it has three different things:
+RT-Thread RTOS like a traditional real-time operating system. The kernel has real-time multi-task scheduling, semaphore, mutex, mail box, message queue etc. However, it has two different things:
 
 * Device Driver;
-* Component;
-* Dyanmic Module
+* Component. 
 
-The device driver is more like a driver framework, UART, IIC, SPI, SDIO, USB device/host, EMAC, MTD NAND etc. The developer can easily add low level driver and board configuration, then combined with the upper framework, he/she can use lots of features.
+The device driver is more like a driver framework, UART, SPI, USB device/host, EMAC, MTD NAND etc. The developer can easyly add low level driver and board configuration, then he/she can use lots of features. 
 
-The Component is a software concept upon RT-Thread kernel, for example a shell (finsh/msh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX (thread) interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
-
-The Dyanmic Module, formerly named as User Applicaion (UA) is a dyanmic loaded module or library, it can be compiled standalone without Kernel. Each Dyanmic Module has its own object list to manage thread/semaphore/kernel object which was created or initialized inside this UA. More information about UA, please visit another [git repo](https://github.com/RT-Thread/rtthread-apps).
+The Component is a software concept upon RT-Thread kernel, for example a shell (finsh shell), virtual file system (FAT, YAFFS, UFFS, ROM/RAM file system etc), TCP/IP protocol stack (lwIP), POSIX interface etc. One component must be a directory under RT-Thread/Components and one component can be descripted by a SConscript file (then be compiled and linked into the system).
 
 ## Board Support Package ##
 
 RT-Thread RTOS can support many architectures:
 
 * ARM Cortex-M0
-* ARM Cortex-M3/M4/7
+* ARM Cortex-M3/M4
 * ARM Cortex-R4
 * ARM Cortex-A8/A9
 * ARM920T/ARM926 etc
-* MIPS32
+* MIPS 
 * x86
-* Andes
-* C-Sky
-* RISC-V
 * PowerPC
 
 ## License ##
 
-RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v3.1.1. License and copyright information can be found within the code.
+RT-Thread RTOS is free software; you can redistribute it and/or modify it under terms of the GNU General Public License version 2 as published by the Free Software Foundation. RT-Thread RTOS is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with RT-Thread; see file COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 
-    /*
-     * Copyright (c) 2006-2018, RT-Thread Development Team
-     *
-     * SPDX-License-Identifier: Apache-2.0
-     */
-
-Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).
-
-NOTE:
-
-RT-Thread using the Apache license v2.0 is only launched after the release of v3.1.1, and is still in preparation right now.
+As a special exception, including RT-Thread RTOS header files in a file, instantiating RT-Thread RTOS generics or templates, or linking other files with RT-Thread RTOS objects to produce an executable application, does not by itself cause the resulting executable application to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the executable file might be covered by the GNU Public License.
 
 ## Usage ##
 
-RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly. 
-So far, the RT-Thread scons building system support the command line compile or generate some IDE's project. There are some option varaibles in the scons building script (rtconfig.py):
-
-* ```CROSS_TOOL``` the compiler which you want to use, gcc/keil/iar. 
-* ```EXEC_PATH``` the path of compiler. 
-
-In SConstruct file:
-
-```RTT_ROOT``` This variable is the root directory of RT-Thread RTOS. If you build the porting in the bsp directory, you can use the default setting. Also, you can set the root directory in ```RTT_ROOT``` environment variable and not modify SConstruct files.
-
-When you set these variables correctly, you can use command:
-
-    scons
-
-under BSP directory to simplely compile RT-Thread RTOS.
-
-If you want to generate the IDE's project file, you can use command:
-
-    scons --target=mdk/mdk4/mdk5/iar/cb -s
-
-to generate the project file.
-
-NOTE: RT-Thread scons building system will tailor the system according to your rtconfig.h configuration header file. For example, if you disable the lwIP in the rtconfig.h by commenting the ```#define RT_USING_LWIP```, the generated project file should have no lwIP related files.
+RT-Thread RTOS uses [scons](http://www.scons.org) as its building system. Therefore, please install scons and Python 2.7 firstly. 
 
 ## Contribution ##
 
-Please refer the contributors in the github. Thank all of RT-Thread Developers.
+Thank all of RT-Thread Developers. 

README_zh.md

@@ -1,97 +0,0 @@
-# RT-Thread #
-
-[![GitHub release](https://img.shields.io/github/release/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/releases)
-[![Build Status](https://travis-ci.org/RT-Thread/rt-thread.svg)](https://travis-ci.org/RT-Thread/rt-thread)
-[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/RT-Thread/rt-thread?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
-[![GitHub pull-requests](https://img.shields.io/github/issues-pr/RT-Thread/rt-thread.svg)](https://github.com/RT-Thread/rt-thread/pulls)
-[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg?style=flat)](https://github.com/RT-Thread/rt-thread/pulls)
-
-RT-Thread是一个来自中国的开源物联网操作系统，它提供了非常强的可伸缩能力：从一个可以运行在ARM Cortex-M0芯片上的极小内核，到中等的ARM Cortex-M3/4/7系统，甚至是运行于MIPS32、ARM Cortex-A系列处理器上功能丰富系统。
-
-## 简介 ##
-
-RT-Thread包含了一个自有的、传统的硬实时内核：可抢占的多任务实时调度器，信号量，互斥量，邮箱，消息队列，信号等。当然，它和传统的实时操作系统还存在着三种不同：
-
-* 设备驱动框架；
-* 软件组件；
-* 应用模块
-
-设备驱动框架更类似一套驱动框架，涉及到UART，IIC，SPI，SDIO，USB从设备/主设备，EMAC，NAND闪存设备等。它会把这些设备驱动中的共性抽象/抽取出来，而驱动工程师只需要按照固定的模式实现少量的底层硬件操作及板级配置。通过这样的方式，让一个硬件外设更容易地对接到RT-Thread系统中，并获得RT-Thread平台上的完整软件栈功能。
-
-软件组件是位于RT-Thread内核上的软件单元，例如命令行（finsh/msh shell），虚拟文件系统（FAT，YAFFS，UFFS，ROM/RAM文件系统等），TCP/IP网络协议栈（lwIP），Libc/POSIX标准层等。一般的，一个软件组件放置于一个目录下，例如RT-Thread/components目录下的文件夹，并且每个软件组件通过一个 SConscript文件来描述并被添加到RT-Thread的构建系统中。当系统配置中开启了这一软件组件时，这个组件将被编译并链接到最终的RT-Thread固件中。
-
-注：随着RT-Thread 3.0中的包管理器开启，越来越多的软件组件将以package方式出现在RT-Thread平台中。而RT-Thread平台更多的是指：
-
-* RT-Thread内核；
-* shell命令行；
-* 虚拟文件系统；
-* TCP/IP网络协议栈；
-* 设备驱动框架；
-* Libc/POSIX标准层。
-
-更多的IoT软件包则以package方式被添加到RT-Thread系统中。
-
-应用模块，或者说用户应用（User Application，UA）是一个可动态加载的模块：它可以独立于RT-Thread固件而单独编译。一般的，每个UA都包含一个main函数入口；一个它自己的对象链表，用于管理这个应用的任务/信号量/消息队列等内核对象，创建、初始化、销毁等。更多关于UA的信息，请访问另外一个 [git 仓库](https://github.com/RT-Thread/rtthread-apps) 了解。
-
-## 支持的芯片架构 ##
-
-RT-Thread支持数种芯片体系架构，已经覆盖当前应用中的主流体系架构：
-
-* ARM Cortex-M0
-* ARM Cortex-M3/M4/7
-* ARM Cortex-R4
-* ARM Cortex-A8/A9
-* ARM920T/ARM926 etc
-* MIPS32
-* x86
-* Andes
-* C-Sky
-* RISC-V
-* PowerPC
-
-## 许可证 ##
-
-RT-Thread从v3.1.1版本开始，是一个以Apache许可证2.0版本授权的开源软件，许可证信息以及版权信息一般的可以在代码首部看到：
-
-    /*
-     * Copyright (c) 2006-2018, RT-Thread Development Team
-     *
-     * SPDX-License-Identifier: Apache-2.0
-     */
-
-从2018/09/09开始，开发者提交PR需要签署贡献者许可协议（CLA）。
-
-注意：
-
-以Apache许可协议v2.0版本授权仅在RT-Thread v3.1.1正式版发布之后才正式实施，当前依然在准备阶段（准备所有原有开发者签署CLA协议）。
-
-## 编译 ##
-
-RT-Thread使用了[scons](http://www.scons.org)做为自身的编译构建系统，并进行一定的定制以满足自身的需求（可以通过scons --help查看RT-Thread中额外添加的命令）。在编译RT-Thread前，请先安装Python 2.7.x及scons。
-
-截至目前，RT-Thread scons构建系统可以使用命令行方式编译代码，或者使用scons来生成不同IDE的工程文件。在使用scons时，需要对构建配置文件（rtconfig.py）中如下的变量进行配置：
-
-* ```CROSS_TOOL``` 指定希望使用的工具链，例如gcc/keil/iar. 
-* ```EXEC_PATH``` 工具链的路径. 
-
-注：在SConstruct文件中：
-
-```RTT_ROOT``` 这个变量指向了RT-Thread的发布源代码根目录。如果你仅计划编译bsp目录下的target，这个`RTT_ROOT`可以使用默认配置。另外，你也可以设置同名的环境变量来指向不同的RT-Thread源代码根目录。
-
-当你把相关的配置都配置正确后，你可以在具有目标目录下（这个目录应包括rtconfig.py、SContruct文件）执行以下命令：
-
-    scons 
-
-从而简单地就编译好RT-Thread。
-
-如果你希望使用IDE来编译RT-Thread，你也可以使用命令行：
-
-    scons --target=mdk/mdk4/mdk5/iar/cb -s 
-
-来生成mdk/iar等的工程文件。而后在IDE中打开project前缀的工程文件来编译RT-Thread。
-
-注意：RT-Thread的scons构建系统会根据配置头文件rtconfig.h来裁剪系统。例如，如果你关闭了rtconfig.h中的lwIP定义（通过注释掉```#define RT_USING_LWIP```的方式），则scons生成的IDE工程文件中将自动不包括lwIP相关的文件。而在RT-Thread 3.0版本中，可以通过menuconfig的方式来配置整个系统，而不需要再手工更改rtconfig.h配置头文件。
-
-## 贡献者 ##
-
-请访问github上RT-Thread项目上的contributors了解已经为RT-Thread提交过代码，PR的贡献者。感谢所有为RT-Thread付出的开发者们！

bsp/CME_M7/CME_M7.ld

@@ -1,78 +0,0 @@
-/******************************************************************************
- *
- * CME_M7.ld - Linker configuration file for project.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-11-02     aozima       first implementation
- *
- *****************************************************************************/
-
-/* Program Entry, set to mark it as "used" and avoid gc */
-MEMORY
-{
-    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* !!! real 128K, up to 256K for linker. */
-    SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
-}
-
-SECTIONS
-{
-    .text :
-    {
-        _text = .;
-        KEEP(*(.isr_vector))
-        *(.text*)
-        *(.rodata*)
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        /* section information for components init. */
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-        . = ALIGN(4);
-
-    } > FLASH
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-
-        /* This is used by the startup in order to initialize the .data secion */
-        _sidata = .;
-    } > FLASH
-    __exidx_end = .;
-
-	/* end of all text. */
-    _etext = .;
-	
-    .data : AT(_etext)
-    {
-        _data = .;
-        *(vtable)
-        *(.data*)
-        _edata = .;
-    } > SRAM
-
-    .bss :
-    {
-        _bss = .;
-        *(.bss*)
-        *(COMMON)
-        _ebss = .;
-    } > SRAM
-    __bss_end = .;
-
-}

bsp/CME_M7/CME_M7.sct

@@ -1,22 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-; load 		region 			size_region
-LR_IROM1 	(0)				(1024 * 128)
-{
-	; load address = execution address
-	ER_IROM1 (0) 			(1024 * 128)
-	{
-		*.o (RESET, +First)
-		*(InRoot$$Sections)
-		.ANY (+RO)
-	}
-
-	; RW data
-	RW_IRAM1 0x20000000 (1024 * 48)
-	{
-		.ANY (+RW +ZI)
-	}
-}
-

bsp/CME_M7/CMSIS/CME_M7/cmem7_it.c

@@ -1,93 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_it.c
-	*
-	* @brief    CMEM7 system exception file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note      
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_it.h"
-
-void NMI_Handler(void)
-{
-	while (1);
-}
-
-void HardFault_Handler(void)
-{
-  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
-    __breakpoint (0); // halt program execution here
-  }
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-void MemManage_Handler(void)
-{
-  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
-    __breakpoint (0); // halt program execution here
-  }
-  /* Go to infinite loop when Memory Manage exception occurs */
-  while (1)
-  {
-  }
-}
-
-void BusFault_Handler(void)
-{
-  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
-    __breakpoint (0); // halt program execution here
-  }
-  /* Go to infinite loop when Bus Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-void UsageFault_Handler(void)
-{
-  if (CoreDebug->DHCSR & 1) { // check C_DEBUGEN == 1-> Debugger Connected
-    __breakpoint (0); // halt program execution here
-  }
-  /* Go to infinite loop when Usage Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
-void SVC_Handler(void)
-{
-}
-
-void DebugMon_Handler(void)
-{
-}
-
-void PendSV_Handler(void)
-{
-}
-
-void SysTick_Handler(void)
-{
-}
-

bsp/CME_M7/CMSIS/CME_M7/cmem7_it.h

@@ -1,401 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_it.h
-	*
-	* @brief    CMEM7 system exception interrupt header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note     Actually, you don't have to implement below involved function 
-	*           whick were defined as weak dummy functions in startup file.
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_IT_H
-#define __CMEM7_IT_H
-
-#include "cmem7.h"
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void);
-
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void);
-
-/**
-  * @brief  This function handles Memory Manage exception.
-  * @param  None
-  * @retval None
-  */
-void MemManage_Handler(void);
-
-/**
-  * @brief  This function handles Bus Fault exception.
-  * @param  None
-  * @retval None
-  */
-void BusFault_Handler(void);
-
-/**
-  * @brief  This function handles Usage Fault exception.
-  * @param  None
-  * @retval None
-  */
-void UsageFault_Handler(void);
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void);
-
-/**
-  * @brief  This function handles Debug Monitor exception.
-  * @param  None
-  * @retval None
-  */
-void DebugMon_Handler(void);
-
-/**
-  * @brief  This function handles PendSV_Handler exception.
-  * @param  None
-  * @retval None
-  */
-void PendSV_Handler(void);
-
-/**
-  * @brief  This function handles SysTick Handler.
-  * @param  None
-  * @retval None
-  */
-void SysTick_Handler(void);
-
-/**
-  * @brief  This function handles ethernet interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void ETH_IRQHandler(void);
-
-/**
-  * @brief  This function handles USB interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void USB_IRQHandler(void);
-
-/**
-  * @brief  This function handles DMA interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void DMAC_IRQHandler(void);
-
-/**
-  * @brief  This function handles CAN0 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void CAN0_IRQHandler(void); 
-
-/**
-  * @brief  This function handles CAN1 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void CAN1_IRQHandler(void); 
-
-/**
-  * @brief  This function handles FP0 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP0_IRQHandler(void);  
-
-/**
-  * @brief  This function handles FP1 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP1_IRQHandler(void);          
-
-/**
-  * @brief  This function handles FP2 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP2_IRQHandler(void);          		
-
-/**
-  * @brief  This function handles FP3 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP3_IRQHandler(void); 
-
-/**
-  * @brief  This function handles FP4 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP4_IRQHandler(void); 
-
-/**
-  * @brief  This function handles FP5 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP5_IRQHandler(void); 
-
-/**
-  * @brief  This function handles FP6 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP6_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP7 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP7_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP8 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP8_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP9 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP9_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP10 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP10_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP11 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP11_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP12 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP12_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP13 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP13_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP14 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP14_IRQHandler(void);
-
-/**
-  * @brief  This function handles FP15 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void FP15_IRQHandler(void); 
-
-/**
-  * @brief  This function handles UART0 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void UART0_IRQHandler(void);
-
-/**
-  * @brief  This function handles UART1 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void UART1_IRQHandler(void);
-
-/**
-  * @brief  This function handles ADC interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void ADC_IRQHandler(void); 
-
-/**
-  * @brief  This function handles GPIO interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void GPIO_IRQHandler(void);
-
-/**
-  * @brief  This function handles SPI1 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void SPI1_IRQHandler(void);
-
-/**
-  * @brief  This function handles I2C1 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void I2C1_IRQHandler(void);
-
-/**
-  * @brief  This function handles SPI0 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void SPI0_IRQHandler(void);
-
-/**
-  * @brief  This function handles I2C0 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void I2C0_IRQHandler(void);
-
-/**
-  * @brief  This function handles RTC second interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void RTC_1S_IRQHandler(void); 
-
-/**
-  * @brief  This function handles RTC microsecond interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void RTC_1MS_IRQHandler(void);
-
-/**
-  * @brief  This function handles watchdog interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void WDG_IRQHandler(void); 
-
-/**
-  * @brief  This function handles timer interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void TIMER_IRQHandler(void); 
-
-/**
-  * @brief  This function handles DDR interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void DDRC_SW_PROC_IRQHandler(void); 
-
-/**
-  * @brief  This function handles ethernet pmt interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void ETH_PMT_IRQHandler(void); 
-
-/**
-  * @brief  This function handles pad interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void PAD_IRQHandler(void);
-
-/**
-  * @brief  This function handles DDR interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void DDRC_LANE_SYNC_IRQHandler(void); 
-
-/**
-  * @brief  This function handles UART2 interrupt.
-  * @param  None
-  * @retval None
-	* @note   Implement it in your interrupt handler
-  */
-void UART2_IRQHandler(void);            
-
-#endif /* __CMEM7_IT_H */
-

bsp/CME_M7/CMSIS/CME_M7/startup/arm/startup_cmem7.s

@@ -1,288 +0,0 @@
-;*****************************************************************************
-;* @file     start_cmem7.h
-;*
-;* @brief    CMEM7 startup file
-;*
-;*
-;* @version  V1.0
-;* @date     3. September 2013
-;*
-;* @note               
-;*           
-;*****************************************************************************
-;* @attention
-;*
-;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-;* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-;* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-;* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-;*
-;* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-;*****************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp               ; Top of Stack
-                DCD     Reset_Handler              ; Reset Handler
-                DCD     NMI_Handler                ; NMI Handler
-                DCD     HardFault_Handler          ; Hard Fault Handler
-                DCD     MemManage_Handler          ; MPU Fault Handler
-                DCD     BusFault_Handler           ; Bus Fault Handler
-                DCD     UsageFault_Handler         ; Usage Fault Handler
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     0                          ; Reserved
-                DCD     SVC_Handler                ; SVCall Handler
-                DCD     DebugMon_Handler           ; Debug Monitor Handler
-                DCD     0                          ; Reserved
-                DCD     PendSV_Handler             ; PendSV Handler
-                DCD     SysTick_Handler            ; SysTick Handler
-
-                ; External Interrupts
-				DCD     ETH_IRQHandler             ; ETH
-				DCD     USB_IRQHandler             ; USB
-				DCD     DMAC_IRQHandler            ; DMAC
-				DCD     CAN0_IRQHandler            ; CAN0
-				DCD     CAN1_IRQHandler            ; CAN1
-				DCD     FP0_IRQHandler             ; FP[0:15]
-				DCD     FP1_IRQHandler
-				DCD     FP2_IRQHandler
-				DCD     FP3_IRQHandler
-				DCD     FP4_IRQHandler
-				DCD     FP5_IRQHandler
-				DCD     FP6_IRQHandler
-				DCD     FP7_IRQHandler
-				DCD     FP8_IRQHandler
-				DCD     FP9_IRQHandler
-				DCD     FP10_IRQHandler
-				DCD     FP11_IRQHandler
-				DCD     FP12_IRQHandler
-				DCD     FP13_IRQHandler
-				DCD     FP14_IRQHandler
-				DCD     FP15_IRQHandler			   ; 21
-				DCD     UART0_IRQHandler           ; UART0
-                DCD     UART1_IRQHandler           ; UART1
-				DCD     ADC_IRQHandler             ; ADC
-				DCD     GPIO_IRQHandler            ; GPIO
-				DCD     SPI1_IRQHandler            ; SPI1
-				DCD     I2C1_IRQHandler            ; I2C1
-				DCD     SPI0_IRQHandler            ; SPI0
-				DCD     I2C0_IRQHandler            ; I2C0
-				DCD     RTC_1S_IRQHandler          ; RTC 1S
-				DCD     RTC_1MS_IRQHandler         ; RTC 1MS
-				DCD     WDG_IRQHandler             ; Watchdog
-				DCD     TIMER_IRQHandler           ; Timer 0 || 1 || 2 || 3
-                DCD     DDRC_SW_PROC_IRQHandler    ; DDRC sw proc       				
-				DCD     ETH_PMT_IRQHandler         ; ETH pmt
-				DCD     PAD_IRQHandler             ; PAD
-				DCD     DDRC_LANE_SYNC_IRQHandler  ; DDRC lane sync
-				DCD     UART2_IRQHandler           ; UART2
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC               
-				EXPORT  ETH_IRQHandler             [WEAK]
-                EXPORT  USB_IRQHandler             [WEAK]
-				EXPORT  DMAC_IRQHandler            [WEAK]
-				EXPORT  CAN0_IRQHandler            [WEAK]
-				EXPORT  CAN1_IRQHandler            [WEAK]
-				EXPORT  FP0_IRQHandler             [WEAK]
-				EXPORT  FP1_IRQHandler             [WEAK]
-				EXPORT  FP2_IRQHandler             [WEAK]
-				EXPORT  FP3_IRQHandler             [WEAK]
-				EXPORT  FP4_IRQHandler             [WEAK]
-				EXPORT  FP5_IRQHandler             [WEAK]
-				EXPORT  FP6_IRQHandler             [WEAK]
-				EXPORT  FP7_IRQHandler             [WEAK]
-				EXPORT  FP8_IRQHandler             [WEAK]
-				EXPORT  FP9_IRQHandler             [WEAK]
-				EXPORT  FP10_IRQHandler            [WEAK]
-				EXPORT  FP11_IRQHandler            [WEAK]
-				EXPORT  FP12_IRQHandler            [WEAK]
-				EXPORT  FP13_IRQHandler            [WEAK]
-				EXPORT  FP14_IRQHandler            [WEAK]
-				EXPORT  FP15_IRQHandler            [WEAK]
-				EXPORT  UART0_IRQHandler           [WEAK]
-                EXPORT  UART1_IRQHandler           [WEAK]
-                EXPORT  ADC_IRQHandler             [WEAK]
-				EXPORT  GPIO_IRQHandler            [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-				EXPORT  I2C1_IRQHandler            [WEAK]
-                EXPORT  SPI0_IRQHandler            [WEAK]
-                EXPORT  I2C0_IRQHandler            [WEAK]
-				EXPORT  RTC_1S_IRQHandler          [WEAK]
-				EXPORT  RTC_1MS_IRQHandler         [WEAK]
-                EXPORT  WDG_IRQHandler             [WEAK]				
-                EXPORT  TIMER_IRQHandler           [WEAK] 
-                EXPORT  DDRC_SW_PROC_IRQHandler    [WEAK]           				
-				EXPORT  ETH_PMT_IRQHandler         [WEAK]           				
-				EXPORT  PAD_IRQHandler             [WEAK]           				
-				EXPORT  DDRC_LANE_SYNC_IRQHandler  [WEAK]           				
-				EXPORT  UART2_IRQHandler           [WEAK]           				         				
-ETH_IRQHandler
-USB_IRQHandler
-DMAC_IRQHandler
-CAN0_IRQHandler
-CAN1_IRQHandler
-FP0_IRQHandler
-FP1_IRQHandler
-FP2_IRQHandler
-FP3_IRQHandler
-FP4_IRQHandler
-FP5_IRQHandler
-FP6_IRQHandler
-FP7_IRQHandler
-FP8_IRQHandler
-FP9_IRQHandler
-FP10_IRQHandler
-FP11_IRQHandler
-FP12_IRQHandler
-FP13_IRQHandler
-FP14_IRQHandler
-FP15_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler          
-ADC_IRQHandler 
-GPIO_IRQHandler
-SPI1_IRQHandler          
-I2C1_IRQHandler         
-SPI0_IRQHandler          
-I2C0_IRQHandler  
-RTC_1S_IRQHandler
-RTC_1MS_IRQHandler
-WDG_IRQHandler            
-TIMER_IRQHandler 
-DDRC_SW_PROC_IRQHandler    				
-ETH_PMT_IRQHandler               				
-PAD_IRQHandler                  				
-DDRC_LANE_SYNC_IRQHandler     				
-UART2_IRQHandler          
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;******************* (C) COPYRIGHT 2011 Capital Micro *****END OF FILE*****

bsp/CME_M7/CMSIS/CME_M7/startup/gcc/startup_CME_M7.c

@@ -1,226 +0,0 @@
-//*****************************************************************************
-//
-// Startup code for use with GNU tools.
-//
-//*****************************************************************************
-
-
-//*****************************************************************************
-//
-// Forward declaration of the default fault handlers.
-//
-//*****************************************************************************
-static void Reset_Handler(void);
-static void Default_Handler(void);
-
-//*****************************************************************************
-//
-// External declaration for the interrupt handler used by the application.
-//
-//*****************************************************************************
-void NMI_Handler(void)          __attribute__((weak, alias("Default_Handler")));
-void HardFault_Handler(void)    __attribute__((weak, alias("Default_Handler")));
-void MemManage_Handler(void)    __attribute__((weak, alias("Default_Handler")));
-void BusFault_Handler(void)     __attribute__((weak, alias("Default_Handler")));
-void UsageFault_Handler(void)   __attribute__((weak, alias("Default_Handler")));
-void SVC_Handler(void)          __attribute__((weak, alias("Default_Handler")));
-void DebugMon_Handler(void)     __attribute__((weak, alias("Default_Handler")));
-void PendSV_Handler(void)       __attribute__((weak, alias("Default_Handler")));
-void SysTick_Handler(void)      __attribute__((weak, alias("Default_Handler")));
-
-void ETH_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void USB_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void DMAC_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void CAN0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void CAN1_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-
-void FP0_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP1_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP2_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP3_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP4_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP5_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP6_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP7_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP8_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP9_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void FP10_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void FP11_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void FP12_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void FP13_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void FP14_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void FP15_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void UART0_IRQHandler(void)     __attribute__((weak, alias("Default_Handler")));
-void UART1_IRQHandler(void)     __attribute__((weak, alias("Default_Handler")));
-void ADC_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void GPIO_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void SPI1_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void I2C1_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void SPI0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void I2C0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
-void RTC_1S_IRQHandler(void)    __attribute__((weak, alias("Default_Handler")));
-void RTC_1MS_IRQHandler(void)   __attribute__((weak, alias("Default_Handler")));
-void WDG_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
-void TIMER_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
-void DDRC_SW_PROC_IRQHandler(void)   __attribute__((weak, alias("Default_Handler")));
-void ETH_PMT_IRQHandler(void)        __attribute__((weak, alias("Default_Handler")));
-void PAD_IRQHandler(void)            __attribute__((weak, alias("Default_Handler")));
-void DDRC_LANE_SYNC_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
-void UART2_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
-
-//*****************************************************************************
-//
-// The entry point for the application.
-//
-//*****************************************************************************
-extern int main(void);
-
-//*****************************************************************************
-//
-// Reserve space for the system stack.
-//
-//*****************************************************************************
-static unsigned long pulStack[512];
-
-//*****************************************************************************
-//
-// The vector table.  Note that the proper constructs must be placed on this to
-// ensure that it ends up at physical address 0x0000.0000.
-//
-//*****************************************************************************
-__attribute__ ((section(".isr_vector")))
-void (* const g_pfnVectors[])(void) =
-{
-    (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
-    // The initial stack pointer
-    Reset_Handler,              // Reset Handler
-    NMI_Handler,                // NMI Handler
-    HardFault_Handler,          // Hard Fault Handler
-    MemManage_Handler,          // MPU Fault Handler
-    BusFault_Handler,           // Bus Fault Handler
-    UsageFault_Handler,         // Usage Fault Handler
-    0,                          // Reserved
-    0,                          // Reserved
-    0,                          // Reserved
-    0,                          // Reserved
-    SVC_Handler,                // SVCall Handler
-    DebugMon_Handler,           // Debug Monitor Handler
-    0,                          // Reserved
-    PendSV_Handler,             // PendSV Handler
-    SysTick_Handler,            // SysTick Handler
-
-    // External Interrupts
-    ETH_IRQHandler,
-    USB_IRQHandler,
-    DMAC_IRQHandler,
-    CAN0_IRQHandler,
-    CAN1_IRQHandler,
-    FP0_IRQHandler,
-    FP1_IRQHandler,
-    FP2_IRQHandler,
-    FP3_IRQHandler,
-    FP4_IRQHandler,
-    FP5_IRQHandler,
-    FP6_IRQHandler,
-    FP7_IRQHandler,
-    FP8_IRQHandler,
-    FP9_IRQHandler,
-    FP10_IRQHandler,
-    FP11_IRQHandler,
-    FP12_IRQHandler,
-    FP13_IRQHandler,
-    FP14_IRQHandler,
-    FP15_IRQHandler,
-    UART0_IRQHandler,
-    UART1_IRQHandler,
-    ADC_IRQHandler,
-    GPIO_IRQHandler,
-    SPI1_IRQHandler,
-    I2C1_IRQHandler,
-    SPI0_IRQHandler,
-    I2C0_IRQHandler,
-    RTC_1S_IRQHandler,
-    RTC_1MS_IRQHandler,
-    WDG_IRQHandler,
-    TIMER_IRQHandler,
-    DDRC_SW_PROC_IRQHandler,
-    ETH_PMT_IRQHandler,
-    PAD_IRQHandler,
-    DDRC_LANE_SYNC_IRQHandler,
-    UART2_IRQHandler,
-};
-
-//*****************************************************************************
-//
-// The following are constructs created by the linker, indicating where the
-// the "data" and "bss" segments reside in memory.  The initializers for the
-// for the "data" segment resides immediately following the "text" segment.
-//
-//*****************************************************************************
-extern unsigned long _etext;
-extern unsigned long _data;
-extern unsigned long _edata;
-extern unsigned long _bss;
-extern unsigned long _ebss;
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor first starts execution
-// following a reset event.  Only the absolutely necessary set is performed,
-// after which the application supplied entry() routine is called.  Any fancy
-// actions (such as making decisions based on the reset cause register, and
-// resetting the bits in that register) are left solely in the hands of the
-// application.
-//
-//*****************************************************************************
-static void Reset_Handler(void)
-{
-    unsigned long *pulSrc, *pulDest;
-
-    //
-    // Copy the data segment initializers from flash to SRAM.
-    //
-    pulSrc = &_etext;
-    for(pulDest = &_data; pulDest < &_edata; )
-    {
-        *pulDest++ = *pulSrc++;
-    }
-
-    //
-    // Zero fill the bss segment.
-    //
-    __asm("    ldr     r0, =_bss\n"
-          "    ldr     r1, =_ebss\n"
-          "    mov     r2, #0\n"
-          "    .thumb_func\n"
-          "zero_loop:\n"
-          "        cmp     r0, r1\n"
-          "        it      lt\n"
-          "        strlt   r2, [r0], #4\n"
-          "        blt     zero_loop");
-
-    // call system init.	
-	SystemInit();
-
-    //
-    // Call the application's entry point.
-    //
-    main();
-}
-
-//*****************************************************************************
-//
-// This is the code that gets called when the processor receives an unexpected
-// interrupt.  This simply enters an infinite loop, preserving the system state
-// for examination by a debugger.
-//
-//*****************************************************************************
-static void Default_Handler(void)
-{
-    //
-    // Go into an infinite loop.
-    //
-    while(1)
-    {
-    }
-}

bsp/CME_M7/CMSIS/CME_M7/system_cmem7.c

@@ -1,39 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     system_cmem7.c
-	*
-	* @brief    CMEM7 system initial file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note      
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#include "cmem7.h"
-#include "cmem7_includes.h"
-
-void SystemInit (void) {
-	// Generally, we use DLL clock as system clock, not default oscillator
-	GLB_SelectSysClkSource(SYS_CLK_SEL_DLL);
-
-	// change NMI to PAD IRQ
-	GLB_SetNmiIrqNum(PAD_INT_IRQn);	
-	
-	return ;
-}
-

bsp/CME_M7/CMSIS/SConscript

@@ -1,33 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-CME_M7/system_cmem7.c
-""")
-
-# add for startup script 
-if rtconfig.CROSS_TOOL == 'gcc':
-    src += ['CME_M7/startup/gcc/startup_CME_M7.c']
-elif rtconfig.CROSS_TOOL == 'keil':
-    src += ['CME_M7/startup/arm/startup_cmem7.s']
-elif rtconfig.CROSS_TOOL == 'iar':
-    print('================ERROR============================')
-    print('Not support IAR yet!')
-    print('=================================================')
-    exit(0)
-
-path = [cwd + '/CME_M7']
-
-if GetDepend(['RT_USING_BSP_CMSIS']):
-    path += [cwd + '/CMSIS/Include']
-elif GetDepend(['RT_USING_RTT_CMSIS']):
-    path += [RTT_ROOT + '/components/CMSIS/Include']
-
-group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
-
-Return('group')

bsp/CME_M7/SConstruct

@@ -1,30 +0,0 @@
-import os
-import sys
-import rtconfig
-from rtconfig import RTT_ROOT
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-if rtconfig.PLATFORM == 'iar':
-	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-	env.Replace(ARFLAGS = [''])
-	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
-
-# make a building
-DoBuilding(TARGET, objs)

bsp/CME_M7/StdPeriph_Driver/SConscript

@@ -1,14 +0,0 @@
-import rtconfig
-Import('RTT_ROOT')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-src = Glob('src/*.c')
-
-path = [cwd + '/inc']
-
-group = DefineGroup('StdPeriph_Driver', src, depend = [''], CPPPATH = path)
-
-Return('group')

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_adc.h

@@ -1,269 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_adc.h
-	*
-	* @brief    CMEM7 ADC header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_ADC_H
-#define __CMEM7_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup ADC_PERIPH
-  * @{
-  */
-typedef enum {
-	ADC_PERIPH_1,
-	ADC_PERIPH_2,
-} ADC_PERIPH;
-
-#define IS_ADC_ALL_PERIPH(PERIPH)         (((PERIPH) == ADC_PERIPH_1) || \
-                                           ((PERIPH) == ADC_PERIPH_2))
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_VSEN
-  * @{
-  */
-#define ADC_VSEN_VDDCORE                  1
-#define ADC_VSEN_VDDIO                    2
-#define ADC_VSEN_VDDIO2                   4
-
-#define IS_ADC_VSEN(VSEN)                 (((VSEN) == ADC_VSEN_VDDCORE) || \
-                                           ((VSEN) == ADC_VSEN_VDDIO) || \
-                                           ((VSEN) == ADC_VSEN_VDDIO2))
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_PHASE_CTRL
-  * @{
-  */
-#define ADC_PHASE_CTRL_0DEG_RISE_EDGE     0         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(Rising Edge) */                                               
-#define ADC_PHASE_CTRL_90DEG_AHEAD        1         /* ADC-1 90DEG ahead of ADC-2 */
-#define ADC_PHASE_CTRL_90DEG_LAG          2         /* ADC-1 90DEG lag of ADC-2 */
-#define ADC_PHASE_CTRL_0DEG_FALL_EDGE     3         /* ADC-1 and ADC-2 CLK are 0DEG Phase Difference(falling Edge) */
-
-#define IS_ADC_PHASE_CTRL(CTRL)           (((CTRL) == ADC_PHASE_CTRL_0DEG_RISE_EDGE) || \
-                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_AHEAD) || \
-                                           ((CTRL) == ADC_PHASE_CTRL_90DEG_LAG) || \
-                                           ((CTRL) == ADC_PHASE_CTRL_0DEG_FALL_EDGE))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_CONVERSION
-  * @{
-  */
-#define ADC_SYSTEM_MODE_SINGLE_CONV       1
-#define ADC_SYSTEM_MODE_CONTINUOUS_CONV   2	
-
-#define IS_ADC_CONVERSION(CONV)           (((CONV) == ADC_SYSTEM_MODE_SINGLE_CONV) || \
-                                           ((CONV) == ADC_SYSTEM_MODE_CONTINUOUS_CONV))
-																					 
-/**
-  * @}
-  */
-
-/** @defgroup ADC_CALIBRATION
-  * @{
-  */
-#define ADC_CALIBRATION_OFFSET            3
-#define ADC_CALIBRATION_NEGTIVE_GAIN      4
-#define ADC_CALIBRATION_POSTIVE_GAIN      5
-
-#define IS_ADC_CALIBRATION(CALIB)         (((CALIB) == ADC_CALIBRATION_OFFSET) || \
-                                           ((CALIB) == ADC_CALIBRATION_NEGTIVE_GAIN) || \
-                                           ((CALIB) == ADC_CALIBRATION_POSTIVE_GAIN))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_CHANNEL
-  * @{
-  */
-#define ADC_CHANNEL_CALIBRATION           0x0
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC1_CHANNEL
-  * @{
-  */
-#define ADC1_CHANNEL_VIP                  0x1		
-#define ADC1_CHANNEL_VSEN                 0x2
-#define ADC1_CHANNEL_VADIO_0              0x4
-#define ADC1_CHANNEL_VADIO_1              0x8
-#define ADC1_CHANNEL_VADIO_2              0x10
-#define ADC1_CHANNEL_VADIO_3              0x20
-#define ADC1_CHANNEL_VADIO_4              0x40
-#define ADC1_CHANNEL_VADIO_5              0x80
-#define ADC1_CHANNEL_ALL                  0xFF
-
-#define IS_ADC1_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC1_CHANNEL_ALL) == 0)
-/**
-  * @}
-  */
-
-/** @defgroup ADC2_CHANNEL
-  * @{
-  */																																										 
-#define ADC2_CHANNEL_VIN                  0x1		
-#define ADC2_CHANNEL_VTMP                 0x2
-#define ADC2_CHANNEL_VADIO_6              0x4
-#define ADC2_CHANNEL_VADIO_7              0x8
-#define ADC2_CHANNEL_VADIO_8              0x10
-#define ADC2_CHANNEL_VADIO_9              0x20
-#define ADC2_CHANNEL_VADIO_10             0x40
-#define ADC2_CHANNEL_VADIO_11             0x80
-#define ADC2_CHANNEL_ALL                  0xFF
-
-#define IS_ADC2_CHANNEL(CHANNEL)          (((CHANNEL) != 0) && ((CHANNEL) & ~ADC2_CHANNEL_ALL) == 0)                                          																 
-/**
-  * @}
-  */
-
-/** @defgroup ADC_INT
-  * @{
-  */																					 
-#define ADC1_INT_ALMOST_FULL              0x1 
-#define ADC2_INT_ALMOST_FULL              0x8
-#define ADC_INT_ALL              					0x9
-
-#define IS_ADC_INT(INT)        						(((INT) != 0) && (((INT) & ~ADC_INT_ALL) == 0))
-/**
-  * @}
-  */
-
-/**
-  * @brief  ADC collection data structure
-	*/ 
-typedef struct {
-	uint8_t channel;												/*!< The channel of collected data, is a value of 
-																							 @ref ADC_CHANNEL, @ref ADC1_CHANNEL or @ref ADC2_CHANNEL */
-	uint16_t data;													/*!< collected data                    												*/
-} ADC_Data;
-
-/**
-  * @brief  ADC initialization structure
-	*/ 
-typedef struct
-{
-	uint8_t ADC_PhaseCtrl;                  /*!< Phase between ADC1 and ADC2, is a value of @ref ADC_PHASE_CTRL */
-	uint8_t ADC_VsenSelection;              /*!< ADC1 VSEN selection, is a value of @ref ADC_VSEN					*/
-} ADC_InitTypeDef;
-
-/**
-  * @brief  ADC initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] init A pointer to structure ADC_InitTypeDef
-  * @retval None
-	*/ 
-void ADC_Init(ADC_InitTypeDef* init);
-
-/**
-  * @brief  Enable or disable ADC. 
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @param[in] Enable The bit indicates if the specific ADC is enable or not
-  * @retval None
-	*/ 
-void ADC_Enable(uint8_t adc, BOOL enable);
-
-/**
-  * @brief  Enable or disable ADC interrupt. 
-	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void ADC_EnableInt(uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] Int interrupt mask bits, which can be a combination of @ref ADC_INT
-	* @retval BOOL The bit indicates if the specific interrupts are set or not
-	*/
-BOOL ADC_GetIntStatus(uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] Int interrupt mask bits, which can be a value of @ref ADC_INT
-  * @retval None
-	*/
-void ADC_ClearInt(uint32_t Int);
-
-/**
-  * @brief  ADC starts to convert data 
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @param[in] convMode It should be a value of @ref ADC_CONVERSION
-	* @param[in] channel It should be the value of @ref ADC1_CHANNEL 
-	* 					 or @ref ADC2_CHANNEL according to parameter 'adc'
-  * @retval BOOL The bit indicates if the specific ADC starts to convert data
-	*/ 
-BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel);
-
-/**
-  * @brief  ADC starts to calibrate and produces one sample
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @param[in] convMode It should be a value of @ref ADC_CALIBRATION
-  * @retval BOOL The bit indicates if the specific ADC starts to convert data
-	*/ 
-BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration);
-
-/**
-  * @brief  ADC stops conversion or calibration
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @retval NULL
-	*/ 
-void ADC_Stop(uint8_t adc);
-
-/**
-  * @brief  Check if ADC is busy or not
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @retval BOOL The bit indicates if the specific ADC is busy or not
-	*/ 
-BOOL ADC_IsBusy(uint8_t adc);
-
-/**
-  * @brief  Read data from ADC
-	* @param[in] adc ADC peripheral, which is a value of @ref ADC_PERIPH
-	* @param[in] Size Expected data size to be read
-	* @param[out] data A user-allocated buffer to fetch data to be read
-  * @retval uint8_t Actual read data size
-	*/
-uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CMEM7_ADC_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_aes.h

@@ -1,52 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_aes.h
-	*
-	* @brief    CMEM7 AES header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_AES_H
-#define __CMEM7_AES_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/**
-  * @brief  AES decryption
-	* @param[in] src A pointer to data to be decrypted
-	* @param[out] dst A user-allocated buffer to fetch decrypted data
-  * @param[in] len Expected data size to be decrypted, which should
-	*						 be multiply times of 16
-	* @retval BOOL True if succeed, or flase
-	*/
-BOOL AES_Decrypt(const void *src, void *dst, uint32_t len);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_AES_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_can.h

@@ -1,237 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_can.h
-	*
-	* @brief    CMEM7 CAN header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_CAN_H
-#define __CMEM7_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-	 
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN0) || \
-                                   ((PERIPH) == CAN1))
-
-/** @defgroup CAN_FLT
-  * @{
-  */																
-#define CAN_FLT_STANDARD_SINGLE    0x00000000
-#define CAN_FLT_STANDARD_DUAL      0x00000001
-#define CAN_FLT_EXTENDED_SINGLE    0x00000002
-#define CAN_FLT_EXTENDED_DUAL      0x00000003
-
-#define IS_CAN_FLT_TYPE(FILTER)    (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
-                                    ((FILTER) == CAN_FLT_STANDARD_DUAL) || \
-																		((FILTER) == CAN_FLT_EXTENDED_SINGLE) || \
-                                    ((FILTER) == CAN_FLT_EXTENDED_DUAL))	
-																		
-#define IS_CAN_FLT_SINGLE(FILTER)  (((FILTER) == CAN_FLT_STANDARD_SINGLE) || \
-                                    ((FILTER) == CAN_FLT_EXTENDED_SINGLE))
-
-#define IS_CAN_FLT_DUAL(FILTER)    (IS_CAN_FLT_TYPE(FILTER) && \
-                                    !IS_CAN_FLT_SINGLE(FILTER))
-																		
-/**
-  * @}
-  */
-
-/** @defgroup CAN_CDR_DIV
-  * @{
-  */
-#define CAN_CDR_DIV_1_2            0x0
-#define CAN_CDR_DIV_1_4            0x1
-#define CAN_CDR_DIV_1_6            0x2
-#define CAN_CDR_DIV_1_8            0x3
-#define CAN_CDR_DIV_1_10           0x4
-#define CAN_CDR_DIV_1_12           0x5
-#define CAN_CDR_DIV_1_14           0x6
-#define CAN_CDR_DIV_1_1            0x7
-
-#define IS_CAN_CDR_DIV(DIV)        (((DIV) == CAN_CDR_DIV_1_2) || \
-                                    ((DIV) == CAN_CDR_DIV_1_4) || \
-																		((DIV) == CAN_CDR_DIV_1_6) || \
-																		((DIV) == CAN_CDR_DIV_1_8) || \
-																		((DIV) == CAN_CDR_DIV_1_10) || \
-																		((DIV) == CAN_CDR_DIV_1_12) || \
-																		((DIV) == CAN_CDR_DIV_1_14) || \
-																		((DIV) == CAN_CDR_DIV_1_1))		
-/**
-  * @}
-  */
-
-/** @defgroup CAN_INT
-  * @{
-  */
-#define CAN_INT_RBNF               0x01
-#define CAN_INT_TB_UNLOCK          0x02
-#define CAN_INT_ERR                0x04
-#define CAN_INT_DATA_OVERRUN       0x08
-#define CAN_INT_WAKEUP             0x10
-#define CAN_INT_ERR_PASSIVE        0x20
-#define CAN_INT_ARBITRATION_LOST   0x40
-#define CAN_INT_BUS_ERR            0x80
-#define CAN_INT_All                0xFF
-
-#define IS_CAN_INT(INT)            (((INT) != 0) && (((INT) & ~CAN_INT_All) == 0))                                  
-/**
-  * @}
-  */
-
-/**
-  * @brief  CAN standard filter structure
-	*/ 
-typedef struct {
-	uint16_t  ID28_18;               /*!< 11 bits                                      */
-  BOOL      RTR;                   /*!< if remote frame                              */
-	uint8_t   data1;                 /*!< data byte 1, if not 2nd CAN_FLT_STANDARD_DUAL*/
-	uint8_t   data2;                 /*!< data byte 2, if CAN_FLT_STANDARD_SINGLE      */
-} CAN_STANDARD_FILTER;
-
-/**
-  * @brief  CAN extended filter structure
-	*/
-typedef struct {
-	uint16_t  ID28_13;               /*!< 16 bits                                      */
-	uint16_t  ID12_0;                /*!< 13 bits, if CAN_FLT_EXTENDED_SINGLE          */
-  BOOL      RTR;                   /*!< if remote frame, if CAN_FLT_EXTENDED_SINGLE  */
-} CAN_EXTENDED_FILTER;
-
-/**
-  * @brief  CAN filter structure
-	*/
-typedef struct {
-	uint8_t   type;                  /*!< Filter type, which is a value of @ref CAN_FLT */
-	
-	/**
-  * @brief  accepted filter
-	*/
-	union {
-		CAN_STANDARD_FILTER sf;				 
-		CAN_EXTENDED_FILTER ef;				 
-	} ACCEPT;												 
-	
-	/**
-  * @brief  filter mask 
-	*/
-	union {
-		CAN_STANDARD_FILTER sf;        
-		CAN_EXTENDED_FILTER ef;				 
-	} MASK;													 
-} CAN_FILTER;
-
-/**
-  * @brief  CAN initialization structure
-	*/
-typedef struct {	
-	BOOL CAN_TxEn;            			 /*!< if transmission is enable 										*/
-	BOOL CAN_Loopback;        			 /*!< loop back mode without phy						 				*/
-  uint8_t CAN_ClockDiv;     			 /*!< input clock divider, ref as @ref CAN_CDR_DIV  */                               
-	uint16_t CAN_Prescaler;   			 /*!< Specifies the length of a time quantum. 
-																				Time quantum = (CAN_Prescaler + 1) * 2 * input clock */ 
-  uint8_t CAN_SJW;          			 /*!< Specifies the maximum number of time quanta 
-																				the CAN hardware is allowed to lengthen or 
-																				shorten a bit to perform resynchronization.		*/
-	uint8_t CAN_TSEG1;        			 /*!< the maximum number of time quanta of 
-																				propagation and 1st phase segment 						*/
-  uint8_t CAN_TSEG2;        			 /*!< the maximum number of time quanta of 2nd 
-																				phase segment																	*/	
-  BOOL CAN_HighSpeed;       			 /*!< if CAN is running on high speed bus (class C) */
-} CAN_InitTypeDef;
-
-/**
-  * @brief  CAN frame structure
-	*/
-typedef struct
-{
-  BOOL SFF;        								 /*!< If standard or extended frame format 					*/ 
-	uint32_t Id;     								 /*!< Specifies the identifier.This parameter can 
-																				be a value between 0 to 0x1FFFFFFF. 					*/
-  BOOL RTR;        								 /*!< Specifies if the frame is a remote frame      */
-  uint8_t DLC;     								 /*!< Specifies the length of the frame, which is 
-																				a value between  0 to 8 											*/
-  uint8_t Data[8]; 								 /*!< Frame data																		*/
-} CAN_Frame;
-
-/**
-  * @brief  CAN initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @param[in] Init A pointer to structure CAN_InitTypeDef
-	* @param[in] f1 A pointer to structure CAN_FILTER
-	* @param[in] f2 NULL if single filter, or a pointer to second filter while dual filters
-  * @retval BOOL The bit indicates if specific CAN is initialized or not
-	*/ 
-BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init, 
-  CAN_FILTER *f1, CAN_FILTER *f2);
-
-/**
-  * @brief  CAN is set to sleep or wake up
-  * @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @param[in] Enable The bit indicates if sleep mode is enable or not
-	* @retval None
-	*/
-void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable);
-
-/**
-  * @brief  Enable or disable UART interrupt. 
-	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref CAN_INT
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @note   All interrupts except for receive int are cleared after call this func.
-	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @retval uint8_t CAN interrupt bits, which can be the combination of @ref CAN_INT
-	*/
-uint8_t CAN_GetIntStatus(CAN0_Type* CANx);
-
-/**
-  * @brief  CAN perform to transmit data
-	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @param[in] frame A pointer to the CAN_Frame to be transmitted
-	* @retval BOOL The bit indicates if data is transmitted or not
-	*/ 
-BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame);
-
-/**
-  * @brief  CAN perform to receive data
-	* @param[in] CANx CAN peripheral, which is CAN0 or CAN1
-	* @param[out] frame A user-allocated buffer to fetch received frame
-	* @retval BOOL The bit indicates if data is recieved or not
-	*/
-BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_CAN_H */

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h

@@ -1,115 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_conf.h
-	*
-	* @brief    CMEM7 config file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_CONF_H
-#define __CMEM7_CONF_H
-
-#define _ADC
-#define _AES
-#define _CAN
-#define _DDR
-#define _DMA
-#define _EFUSE
-#define _ETH
-#define _FLASH
-#define _GPIO
-#define _I2C
-#define _MISC
-#define _RTC
-#define _SPI
-#define _TIM
-#define _UART
-#define _USB
-#define _WDG
-
-//#define _MARVELL
-//#define _IP1826D
-#define _M7NORFLASH
-#define _ME_6095_F
-
-#define USE_FULL_ASSERT    1 
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports
-  *         the name of the source file and the source line number of the call
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((unsigned char *)__FILE__, __LINE__))
-
-	static void assert_failed(unsigned char* file, unsigned long line) {
-		while (1) {
-			;
-		}
-	}
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL;
-
-/**
-  * System clock frequency, unit is Hz.
-  */
-#define SYSTEM_CLOCK_FREQ        300000000 
-//250000000
-//300000000
-
-/**
-  * @brief  usecond delay 
-	* @note 	It can't delay in an accurate time
-	* @param[in] usec usecond to be delay
-	* @retval None
-	*/
-static void udelay(unsigned long usec) {
-  unsigned long count = 0;
-  unsigned long utime = SYSTEM_CLOCK_FREQ / 1000000 * usec;
-
-  while(++count < utime) ;
-}
-
-/**
-  * UART definition for print
-	*/
-#define PRINT_UART							UART2
-
-/**
-  * DDR type definition
-  */
-#define DDR_TYPE				3	// 2 for DDR2, 3 for DDR3
-
-#if (DDR_TYPE == 3)
-# define DDR_SIZE				(256 << 20)
-#elif (DDR_TYPE == 2)
-# define DDR_SIZE				(128 << 20)
-#else
-# error
-#endif
-
-#endif /* __CMEM7_CONF_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_ddr.h

@@ -1,185 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_ddr.h
-	*
-	* @brief    CMEM7 AES header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_DDR_H
-#define __CMEM7_DDR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-/** @defgroup _MEM_TYPE
-  * @{
-  */
-enum _MEM_TYPE 
-{
-	MEM_DDR2=1,
-	MEM_DDR3		
-} ;	
-/**
-  * @}
-  */
-
-/** @defgroup _BUS_WIDTH
-  * @{
-  */
-enum _BUS_WIDTH
-{
-	BUS_WIDTH_8,
-	BUS_WIDTH_16,
-	BUS_WIDTH_MAX
-};
-/**
-  * @}
-  */
-/** @defgroup _CHIP_TYPE
-  * @{
-  */  
-enum _CHIP_TYPE
-{
-	_32Mbx8,
-	_64Mbx8,
-	_128Mbx8,
-	_256Mbx8,
-	_512Mbx8,
-	_16Mbx16,
-	_32Mbx16,
-	_64Mbx16,
-	_128Mbx16,
-	_256Mbx16,
-	_512Mbx16,
-	CHIP_TYPE_MAX
-};
-/**
-  * @}
-  */
-
-/** @defgroup _CHIP_NUM
-  * @{
-  */  
-enum _CHIP_NUM
-{
-	CHIP_NUM_x1,
-	CHIP_NUM_x2,
-	CHIP_NUM_MAX
-};
-/**
-  * @}
-  */
-  
-/** @defgroup MEM_CHIP_INFO
-  * @{
-  */
-typedef struct {
-	uint8_t mem_type;     /*!< ddr type @ref _MEM_TYPE*/
-	uint8_t Bus_width;	/*!< ddr qs bus width @ref _BUS_WIDTH*/
-	uint8_t Chip_type;	/*!< chip type @ref _CHIP_TYPE*/
-	uint8_t Chip_num;	/*!< chip number @ref _CHIP_NUM*/
-	uint8_t Chip_bank;      /*!< chip bank number*/		
-} MEM_CHIP_INFO;								
-/**
-  * @}
-  */
-
-
-/** @defgroup DDR2MEM
-  * @{
-  */
-typedef struct {
-	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
-	uint32_t tCL;						/*!< tCL */
-	uint32_t tRCD;						/*!< tRCD */
-	uint32_t tRP;						/*!< tRP */
-	uint32_t tRC;						/*!< tRC */
-	uint32_t tRAS;						/*!< tRAS */
-	uint32_t tWR;						/*!< tWR */
-	uint32_t tRRD;						/*!< tRRD */
-	uint32_t tWTR;						/*!< tWTR */
-	uint32_t tRTP;						/*!< tRTP */
-	uint32_t tFAW;						/*!< tFAW */
-} DDR2MEM;								/*!< DDR2ʱ<32><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
-/**
-  * @}
-  */
-
-/** @defgroup DDR3MEM
-  * @{
-  */
-typedef struct {
-	uint32_t tCK;       		/*!< Period of clock(ps), not data period */ 
-	uint32_t tCL;						/*!< tCL */
-	uint32_t tWCL;						/*!< tWCL */
-	uint32_t tRCD;						/*!< tRCD */
-	uint32_t tRAS;						/*!< tRAS */
-	uint32_t tRP;						/*!< tRP */
-	uint32_t tRC;						/*!< tRC */
-	uint32_t tRRD;						/*!< tRRD */
-	uint32_t tFAW;						/*!< tFAW */
-	uint32_t tWR;						/*!< tWR */
-	uint32_t tRTP;						/*!< tRTP */
-	uint32_t tZQoper;					/*!< tZQCL */
-	uint32_t tZQCS;						/*!< tZQCS */
-} DDR3MEM;								/*!< DDR3ʱ<33><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
-/**
-  * @}
-  */
-
-/** @defgroup DDR2PREDEF
-  * @{
-  */
-extern const DDR2MEM DDR2PREDEF[];		/*!< Pre-defined DDR2 Timing in library */
-#define DDR2_400C			0			/*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
-
-/**
-  * @}
-  */
-
-/** @defgroup DDR3PREDEF
-  * @{
-  */
-extern const DDR3MEM DDR3PREDEF[];		/*!< Pre-defined DDR3 Timing in library */
-#define DDR3_400		  	0
-#define DDR3_667        1
-
-/**
-  * @}
-  */
-
-/**
- * @brief DDR Timing Configuration
-   * @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO
-   * @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF.
- * @retval void
-   */
-BOOL  DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_DDR_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_dma.h

@@ -1,116 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_dma.h
-	*
-	* @brief    CMEM7 DMA header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_DMA_H
-#define __CMEM7_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup DMA_Int
-  * @{
-  */
-#define DMA_Int_TfrComplete                0x00000001    
-#define DMA_Int_Err                        0x00000002
-#define DMA_Int_All                        0x00000003
-
-#define IS_DMA_INT(INT)        (((INT) != 0) && (((INT) & ~DMA_Int_All) == 0))
-/**
-  * @}
-  */ 
-
-/**
-  * @brief  Descriptor structure
-	*	@note		DMA requires users provides a list of descriptors to operation.
-	*					Meanwhile, memory occupied by descriptors should be in physical
-	*					memory and keep valid during DMA transfer.
-	*/ 
-typedef struct {                      
-	uint32_t srcAddr;                  /*!< source address 														*/		
-	uint32_t dstAddr;                  /*!< destination address 											*/	
-	uint32_t number;                   /*!< block byte number, no more than 2K Bytes 	*/
-	uint32_t nextBlock;                /*!< next block descriptor 										*/
-	uint32_t padding;                  /*!< Nonsense, only used to fill 							*/
-} BLOCK_DESC;
-	
-/**
-  * @brief  DMA initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param  None
-	* @retval None
-	*/ 
-void DMA_Init(void);
-
-/**
-  * @brief  Enable or disable DMA interrupt. 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void DMA_EnableInt(uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
-  * @retval BOOL The bit indicates if specific interrupts are set or not
-	*/
-BOOL DMA_GetIntStatus(uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref DMA_Int
-  * @retval None
-	*/
-void DMA_ClearInt(uint32_t Int);
-
-/**
-  * @brief  DMA transfer
-	* @note		Make sure that memory occupied by descriptors should be in physical
-	*					memory and keep valid before DMA transfer is finished (Return false by
-	*					calling DMA_IsBusy after DMA transfer started).
-	* @param[in] blockList A pointer to header of list of BLOCK_DESC
-  * @retval BOOL The bit indicates if DMA begins to transfer
-	* @see		DMA_IsBusy
-	*/
-BOOL DMA_Transfer(BLOCK_DESC *blockList);
-
-/**
-  * @brief  DMA is busy or not
-  * @param  None
-	* @retval BOOL The bit indicates if DMA is busy or not
-	*/ 
-BOOL DMA_IsBusy(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_DMA_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_efuse.h

@@ -1,114 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_efuse.h
-	*
-	* @brief    CMEM7 EFUSE header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_EFUSE_H
-#define __CMEM7_EFUSE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup EFUSE_TMRF_R
-  * @{
-  */
-#define EFUSE_TMRF_R_3000                0
-#define EFUSE_TMRF_R_1200                1
-#define EFUSE_TMRF_R_750                 2
-
-#define IS_EFUSE_TMRF(R)                 (((R) == EFUSE_TMRF_R_3000) || \
-                                          ((R) == EFUSE_TMRF_R_1200) || \
-                                          ((R) == EFUSE_TMRF_R_750))
-/**
-  * @}
-  */
-
-/**
-  * @brief  EFUSE timing structure
-	*/
-typedef struct
-{
-	uint32_t EFUSE_Tpwph;                  /*!< Nano second                                    */
-  uint32_t EFUSE_Trac;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Trah;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Trpw;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Trc;                    /*!< Nano second                                    */
-	uint32_t EFUSE_Tesr;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Tprs;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Tpi;                    /*!< Nano second                                    */
-	uint32_t EFUSE_Tpp;                    /*!< Nano second                                    */
-	uint32_t EFUSE_Teps;                   /*!< Nano second                                    */
-	uint32_t EFUSE_Tpwps;                  /*!< Nano second                                    */
-} EFUSE_Timing;
-
-/**
-  * @brief  EFUSE initialization structure
-	*/
-typedef struct
-{
-	uint8_t EFUSE_ClockDividor;       		 /*!< EFUSE clock dividor, 2 in n times */
-	uint8_t EFUSE_TMRF;                    /*!< EFUSE reference resistor select, @ref EFUSE_TMRF_R */
-  EFUSE_Timing* timing;                  /*!< Timing configuration, null if default           */
-} EFUSE_InitTypeDef;
-
-/**
-  * @brief  EFUSE key structure
-	*/
-typedef struct
-{
-	uint32_t key0;                         /*!< EFUSE AES key [31:0]                            */
-  uint32_t key1;                         /*!< EFUSE AES key [63:32]                           */
-	uint32_t key2;                         /*!< EFUSE AES key [95:64]                           */
-	uint32_t key3;                         /*!< EFUSE AES key [127:96]                          */
-	uint32_t key4;                         /*!< EFUSE AES key [159:128]                         */
-  uint32_t key5;                         /*!< EFUSE AES key [191:160]                         */
-	uint32_t key6;                         /*!< EFUSE AES key [223:192]                         */
-	uint32_t key7;                         /*!< EFUSE AES key [255:224]                         */
-} EFUSE_AesKey;
-
-/**
-  * @brief  EFUSE initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] init A pointer to structure EFUSE_InitTypeDef
-  * @retval None
-	*/ 
-void EFUSE_Init(EFUSE_InitTypeDef* init);
-
-/**
-  * @brief  EFUSE initialization
-  * @param[in] key A pointer to EFUSE_AesKey to be compared
-  * @retval BOOL True if equal, or false if different
-	*/ 
-BOOL EFUSE_Compare(EFUSE_AesKey* key);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_EFUSE_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h

@@ -1,417 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_eth.h
-	*
-	* @brief    CMEM7 ethernet header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_ETH_H
-#define __CMEM7_ETH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup ETH_SPEED
-  * @{
-  */
-#define ETH_SPEED_10M               0x0
-#define ETH_SPEED_100M              0x1
-#define ETH_SPEED_1000M             0x2
-
-#define IS_ETH_SPEED(SPEED)    			(((SPEED) == ETH_SPEED_10M)  || \
-                                     ((SPEED) == ETH_SPEED_100M) || \
-																		 ((SPEED) == ETH_SPEED_1000M))
-/**
-  * @}
-  */
-
-/** @defgroup ETH_DUPLEX
-  * @{
-  */
-#define ETH_DUPLEX_HALF             0x0
-#define ETH_DUPLEX_FULL             0x1
-
-#define IS_ETH_DUPLEX(DUPLEX)  			(((DUPLEX) == ETH_DUPLEX_HALF) || \
-																		 ((DUPLEX) == ETH_DUPLEX_FULL))
-/**
-  * @}
-  */
-
-/** @defgroup ETH_INT
-  * @{
-  */																			
-#define ETH_INT_TX_COMPLETE_FRAME		0x0001
-#define ETH_INT_TX_STOP             0x0002
-#define ETH_INT_TX_BUF_UNAVAI       0x0004
-#define ETH_INT_RX_OVERFLOW					0x0010
-#define ETH_INT_TX_UNDERFLOW				0x0020
-#define ETH_INT_RX_COMPLETE_FRAME   0x0040
-#define ETH_INT_RX_BUF_UNAVAI       0x0080
-#define ETH_INT_RX_STOP             0x0100
-#define ETH_INT_BUS_FATAL_ERROR     0x2000
-#define ETH_INT_ALL                 (ETH_INT_TX_COMPLETE_FRAME | \
-                                     ETH_INT_TX_STOP           | \
-																		 ETH_INT_TX_BUF_UNAVAI     | \
-																		 ETH_INT_RX_OVERFLOW       | \
-																		 ETH_INT_TX_UNDERFLOW      | \
-																		 ETH_INT_RX_COMPLETE_FRAME | \
-																		 ETH_INT_RX_BUF_UNAVAI     | \
-																		 ETH_INT_RX_STOP           | \
-																		 ETH_INT_BUS_FATAL_ERROR)
-
-#define IS_ETH_INT(INT)             (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0))
-/**
-  * @}
-  */
-/**
-  * @brief  EFUSE receive filter structure
-	*/
-typedef struct
-{
-	BOOL ETH_BroadcastFilterEnable;   /*!< Broadcast is dropped or passed								        */ 
-	BOOL ETH_OwnFilterEnable;	        /*!< source address filter is on or off     							*/
-	BOOL ETH_SelfDrop;				  			/*!< Only own address is dropped or passed								*/
-	BOOL ETH_SourceFilterEnable;	    /*!< source address filter is on or off     							*/
-	BOOL ETH_SourceDrop;				      /*!< Only specific source address is dropped or passed  	*/
-	uint8_t ETH_SourceMacAddr[6];     /*!< Source MAC address                                   */
-} ETH_FrameFilter;
-
-/**
-  * @brief  Ethernet initialization structure
-	*/ 
-typedef struct
-{
-    BOOL ETH_LinkUp;                   /*!< If ETH is linked up and it can be retrieved from PHY */																	  
-	uint8_t ETH_Speed;                 /*!< speed of ETH, refer as @ref ETH_SPEED                */
-    uint8_t ETH_Duplex;                /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX				 */
-	BOOL ETH_RxEn;                     /*!< Rx enable                                            */
-	BOOL ETH_TxEn;                     /*!< Tx enable                                            */
-	BOOL ETH_ChecksumOffload;          /*!< Checksum offload enable                              */
-	BOOL ETH_JumboFrame;               /*!< Jumbo Frame Enable                                   */
-	uint8_t ETH_MacAddr[6];            /*!< MAC address                                          */ 
-    ETH_FrameFilter *ETH_Filter;       /*!< Received frame address filter, receive all if null   */
-} ETH_InitTypeDef;
-
-/**
-  * @brief  Ethernet Tx descriptor structure
-	*/ 
-typedef struct { 
-	union {
-    uint32_t  TX0;
-		
-		struct {
-			uint32_t 								:  1;
-			uint32_t UNDERFLOW_ERR  :  1; 	 /*!< [OUT] Underflow error            											*/
-			uint32_t 								:  1;
-			uint32_t COLLISION_CNT	:  4;		 /*!< [OUT] Collision count				                          */
-			uint32_t 								:  1;
-			uint32_t EX_COLLISION 	:  1;		 /*!< [OUT] Excessive collision error	                      */
-			uint32_t LATE_COLLISION :  1;		 /*!< [OUT] Late collision error	                          */
-			uint32_t NO_CARRIER     :  1;		 /*!< [OUT] No carrier error                          			*/
-			uint32_t LOSS_CARRIER   :  1;		 /*!< [OUT] loss of carrier error                          	*/
-			uint32_t PAYLOAD_ERR 		:  1;		 /*!< [OUT] IP payload error                          			*/
-			uint32_t 								:  2;
-			uint32_t ERR_SUM 				:  1;		 /*!< [OUT] Error summary		                          			*/
-			uint32_t HEADER_ERR 		:  1;		 /*!< [OUT] IP header error                          				*/
-			uint32_t 								:  8;
-			uint32_t TTSE           :  1; 	 /*!< enables IEEE1588 hardware timestamping in first segment */
-			uint32_t 								:  2;
-			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
-			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
-			uint32_t 								:  2;
-		} TX0_b;
-	} TX_0;
-	
-	union {
-    uint32_t  TX1;
-		
-		struct {
-			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
-			uint32_t                : 19;
-		} TX1_b;
-	} TX_1;
-	
-	uint32_t bufAddr;											/*!< address of buffer						                     */
-	uint32_t nextDescAddr;								/*!< address of next descriptor		                     */
-  uint64_t reserved;
-	uint64_t timeStamp;									 	/*!< time stamp while last segment                     */
-} ETH_TX_DESC;
-
-/**
-  * @brief  Ethernet Rx descriptor structure
-	*/ 
-typedef struct { 
-	union {
-    uint32_t  RX0;
-		
-		struct {
-			uint32_t 								:  1;
-			uint32_t CRC_ERR        :  1; 	 /*!< [OUT] CRC error while last segment                		*/
-			uint32_t 								:  5;
-			uint32_t TTSE           :  1; 	 /*!< timestamp available while last segment                */
-			uint32_t LS           	:  1; 	 /*!< [OUT] last segment flag                               */
-			uint32_t FS           	:  1; 	 /*!< [OUT] first segment flag                              */
-			uint32_t 								:  1;
-			uint32_t OVERFLOW_ERR   :  1; 	 /*!< [OUT] FIFO overflow while last segment                */
-			uint32_t LENGTH_ERR     :  1; 	 /*!< [OUT] length error while last segment                	*/
-			uint32_t 								:  2;
-			uint32_t ERR_SUM        :  1; 	 /*!< [OUT] Error summary while last segment              	*/
-			uint32_t FL           	: 14; 	 /*!< [OUT] frame length while last segment                 */
-			uint32_t 		           	:  2;
-		} RX0_b;
-	} RX_0;
-	
-	union {
-    uint32_t  RX1;
-		
-		struct {
-			uint32_t SIZE						: 13; 	 	/*!< buffer size                                       */
-			uint32_t                : 19;
-		} RX1_b;
-	} RX_1;
-	
-	uint32_t bufAddr;											/*!< buffer address                                    */
-	uint32_t nextDescAddr;								/*!< address of next descriptor                        */
-  uint64_t reserved;
-	uint64_t timeStamp;									 	/*!< time stamp while the last segment                 */
-} ETH_RX_DESC;
-
-/**
-  * @brief  Read data from phy chip
-	* @param[in] phyAddr Address of phy chip
-	* @param[in] phyReg Address of phy's register to be read
-  * @retval uint32_t value of phy's register
-	*/
-uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg);
-
-/**
-  * @brief  Write data to phy chip
-	* @param[in] phyAddr Address of phy chip
-	* @param[in] phyReg Address of phy's register to be written
-	* @param[in] data Data to be written
-  * @retval None
-	*/
-void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data);
-/**
-  * @brief  Fills each ETH_InitStruct member with its default value.
-  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
-  *   which will be initialized.
-  * @retval : None
-  */
-void ETH_StructInit(ETH_InitTypeDef* init);
-/**
-  * @brief  Ethernet initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] init A pointer to structure ETH_InitTypeDef
-  * @retval BOOL The bit indicates if ethernet is initialized successfully
-	*/ 
-BOOL ETH_Init(ETH_InitTypeDef *init);
-
-/**
-  * @brief  Enable or disable ethernet interrupt. 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void ETH_ITConfig(uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
-  * @retval BOOL The bit indicates if specific interrupts are set or not
-	*/
-BOOL ETH_GetITStatus(uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT
-  * @retval None
-	*/
-void ETH_ClearITPendingBit(uint32_t Int);
-
-/**
-  * @brief  Get ethernte MAC address
-	* @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes.
-	* @retval None
-	*/
-void ETH_GetMacAddr(uint8_t *mac);
-
-/**
-  * @brief  Set ethernet transmission descriptor ring 
-	* @note		Make sure that memory occupied by descriptors should be in physical
-	*					memory and keep valid before ethernet transmission is finished.
-	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
-	*					has a 'nextDescAddr' pointed to first node.
-  * @retval BOOL The bit indicates if valid ring is set
-	*/
-BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring);
-
-/**
-  * @brief  Start ethernet transmission
-	* @param	None
-  * @retval None
-	*/
-void ETH_StartTx(void);
-
-/**
-  * @brief  Stop ethernet transmission
-	* @param	None
-  * @retval None
-	*/
-void ETH_StopTx(void);
-
-/**
-  * @brief  Resume ethernet transmission\n
-	* 				While ethernet doesn't have enough buffer to transmit data, it will
-	*					pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users
-	*					must call this function to start ethernet again after new buffer 
-	*					prepared.
-	* @param	None
-  * @retval None
-	*/
-void ETH_ResumeTx(void);
-
-/**
-  * @brief  Get free transmission descriptor\n
-	* @param	None
-  * @retval ETH_TX_DESC* A pointer of free transmission descriptor, 
-	*					NULL if no free descriptor
-	*/
-ETH_TX_DESC *ETH_AcquireFreeTxDesc(void);
-
-/**
-  * @brief  Check if a transmission descriptor is free or not
-	* @param[in] desc A pointer of a transmission descriptor
-  * @retval BOOL True if the transmission descriptor is free, or flase.
-	*/
-BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc);
-
-/**
-  * @brief  Release a transmission descriptor to ethernet\n
-	*					After users prepared data in the buffer of a free descriptor,
-	*					They must call this function to change ownership of the 
-	*					descriptor to hardware.
-	* @param[in] desc A pointer of a transmission descriptor
-  * @retval None
-	*/
-void ETH_ReleaseTxDesc(ETH_TX_DESC *desc);
-
-/**
-  * @brief  Set buffer address of the specific TX descriptor
-	* @param[in] desc A pointer of a transmission descriptor
-  * @param[in] bufAddr buffer address to be sent
-  * @retval None
-	*/
-void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr);
-
-/**
-  * @brief  Get buffer address of the specific TX descriptor
-	* @param[in] desc A pointer of a transmission descriptor
-  * @retval uint32_t buffer address to be gotten
-	*/
-uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc);
-
-/**
-  * @brief  Set ethernet receive descriptor ring
-	* @note		Make sure that memory occupied by descriptors should be in physical
-	*					memory and keep valid before ethernet receive is finished.
-	* @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node 
-	*					has a 'nextDescAddr' pointed to first node.
-  * @retval BOOL The bit indicates if valid ring is set
-	*/
-BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring);
-
-/**
-  * @brief  Start ethernet receive
-	* @param	None
-  * @retval None
-	*/
-void ETH_StartRx(void);
-
-/**
-  * @brief  Stop ethernet receive
-	* @param	None
-  * @retval None
-	*/
-void ETH_StopRx(void);
-
-/**
-  * @brief  Resume ethernet receive\n
-	* 				While ethernet doesn't have enough buffer to receive data, it will
-	*					pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users
-	*					must call this function to start ethernet again after new buffer 
-	*					prepared.
-	* @param	None
-  * @retval None
-	*/
-void ETH_ResumeRx(void);
-
-/**
-  * @brief  Get the free descriptor which contains received data\n
-	* @param	None
-  * @retval ETH_RX_DESC* A pointer of free receive descriptor, 
-	*					NULL if no free descriptor
-	*/
-ETH_RX_DESC *ETH_AcquireFreeRxDesc(void);
-
-/**
-  * @brief  Check if a receive descriptor is free or not
-	* @param[in] desc A pointer of a receive descriptor
-  * @retval BOOL True if the receive descriptor is free, or flase.
-	*/
-BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc);
-
-/**
-  * @brief  Release a receive descriptor to ethernet\n
-	*					After users handled data in the buffer of a free descriptor,
-	*					They must call this function to change ownership of the 
-	*					descriptor to hardware.
-	* @param[in] desc A pointer of a transmission descriptor
-  * @retval None
-	*/
-void ETH_ReleaseRxDesc(ETH_RX_DESC *desc);
-
-/**
-  * @brief  Set buffer address of the specific RX descriptor
-	* @param[in] desc A pointer of a receive descriptor
-  * @param[in] bufAddr buffer address to be received
-  * @retval None
-	*/
-void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr);
-
-/**
-  * @brief  Get buffer address of the specific RX descriptor
-	* @param[in] desc A pointer of a receive descriptor
-  * @retval uint32_t buffer address to be gotten
-	*/
-uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_ETH_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h

@@ -1,218 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_flash.h
-	*
-	* @brief    CMEM7 flash controller source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_FLASH_H
-#define __CMEM7_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup FLASH_PROTECT_MODE
-  * @{
-  */
-#define FLASH_PROTECT_MODE_SW           0       /*!< The Status Register can be written to after a Write 
-                                                     Enable command.(Default) */
-#define FLASH_PROTECT_MODE_HW           1       /*!< WP pin decides if the Status Register can be written 
-                                                     WP#=0, the Status Register locked
-																									   WP#=1, the Status Register is unlocked and can be written to
-                                                     after a Write Enable command */
-#define FLASH_PROTECT_MODE_POWERDOWN    2				/*!< Status Register is protected and can not be written to again
-                                                     until the next Power-Down, Power-Up cycle */	
-#define FLASH_PROTECT_MODE_OTP          3       /*!< Status Register is permanently protected */	
-
-#define IS_FLASH_PROTECT_MODE(MODE)     (((MODE) == FLASH_PROTECT_MODE_SW) || \
-                                         ((MODE) == FLASH_PROTECT_MODE_HW) || \
-                                         ((MODE) == FLASH_PROTECT_MODE_POWERDOWN) || \
-                                         ((MODE) == FLASH_PROTECT_MODE_OTP))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_PROTECT_REGION
-  * @{
-  */
-#define FLASH_PROTECT_REGION_NONE       0x00    /*!< no region is protected */
-#define FLASH_PROTECT_REGION_UP_64K     0x01    /*!< region(0F0000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_128K    0x02    /*!< region(0E0000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_256K    0x03    /*!< region(0C0000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_512K    0x04    /*!< region(080000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_64K    0x09    /*!< region(000000H-00FFFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_128K   0x0A    /*!< region(000000H-01FFFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_256K   0x0B    /*!< region(000000H-03FFFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_512K   0x0C    /*!< region(000000H-07FFFFH) is protected */
-#define FLASH_PROTECT_REGION_ALL        0x0D    /*!< region(000000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_4K      0x11    /*!< region(0FF000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_8K      0x12    /*!< region(0FE000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_16K     0x13    /*!< region(0FC000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_UP_32K     0x14    /*!< region(0F8000H-0FFFFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_4K     0x19    /*!< region(000000H-000FFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_8K     0x1A    /*!< region(000000H-001FFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_16K    0x1B    /*!< region(000000H-003FFFH) is protected */
-#define FLASH_PROTECT_REGION_LOW_32K    0x1C    /*!< region(000000H-007FFFH) is protected */
-
-#define IS_FLASH_PROTECT_REGION(REGION) (((REGION) == FLASH_PROTECT_REGION_NONE) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_UP_64K) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_UP_128K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_UP_256K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_UP_512K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_64K) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_LOW_128K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_256K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_512K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_ALL) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_UP_4K) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_UP_8K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_UP_16K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_UP_32K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_4K) || \
-                                         ((REGION) == FLASH_PROTECT_REGION_LOW_8K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_16K) || \
-																				 ((REGION) == FLASH_PROTECT_REGION_LOW_32K))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_READ_MODE
-  * @{
-  */
-#define FLASH_READ_MODE_NORMAL         0        /*!< normal read, 1 bitwidth, highest freqency is 90MHz */
-#define FLASH_READ_MODE_FAST           1        /*!< fast read, 1 bitwidth, highest freqency is 120MHz */
-#define FLASH_READ_MODE_FAST_DUAL      2        /*!< fast read, 2 bitwidth, highest freqency is 120MHz */
-#define FLASH_READ_MODE_FAST_QUAD      3        /*!< fast read, 4 bitwidth, highest freqency is 90MHz */
-
-#define IS_FLASH_READ_MODE(MODE)       (((MODE) == FLASH_READ_MODE_NORMAL) || \
-                                        ((MODE) == FLASH_READ_MODE_FAST) || \
-                                        ((MODE) == FLASH_READ_MODE_FAST_DUAL) || \
-																				((MODE) == FLASH_READ_MODE_FAST_QUAD))																								
-/**
-  * @}
-  */
-
-/**
-  * @brief  UART initialization structure
-	*/ 
-typedef struct
-{
-  uint8_t FLASH_ClockDividor;       /*!< flash clock dividor, 2 in n times */
-	uint8_t FLASH_ProtectMode;        /*!< Status Register protection mode */
-	uint8_t FLASH_ProtectRegion;      /*!< flash protection region */
-	BOOL FLASH_QuadEnable;            /*!< if allows Quad operation */
-	void (*FLASH_Wait)(void);         /*!< When the former read or write operation is excuting, 
-	                                       Flash has to call a callback to wait it finish. 
-	                                       If null, Flash will wait forever until finish */
-} FLASH_InitTypeDef;
-
-/**
-  * @brief  flash initialization
-  * @note   This function should be called at first before any other interfaces.
-	*					Users should make sure that doesn't erase or write data in a 
-	*					write-protected region.
-	* @param[in] init A pointer to structure FLASH_InitTypeDef
-  * @retval None
-	*/ 
-void FLASH_Init(FLASH_InitTypeDef* init);
-
-/**
-  * @brief  Get flash status 
-  * @param[out] ProtectMode flash protect mode, ref as @ref FLASH_PROTECT_MODE
-  * @param[out] ProtectRegion flash protect region, ref as @ref FLASH_PROTECT_REGION
-	* @param[out] QuadEnable quad speed mode enable bit
-	* @retval None
-	*/ 
-void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable);
-
-/**
-  * @brief  Erase a sector, which is 4K bytes large.
-  * @param[in] addr Start address of a sector
-	* @retval None
-	*/
-void FLASH_EraseSector(uint32_t addr);
-
-/**
-  * @brief  Erase a block, which is 32K bytes large.
-  * @param[in] addr Start address of a block
-	* @retval None
-	*/
-void FLASH_Erase32kBlock(uint32_t addr);
-
-/**
-  * @brief  Erase a block, which is 64K bytes large.
-  * @param[in] addr Start address of a block
-	* @retval None
-	*/
-void FLASH_Erase64kBlock(uint32_t addr);
-
-/**
-  * @brief  Erase all chip
-  * @param	None
-	* @retval None
-	*/
-void FLASH_EraseChip(void);
-
-/**
-  * @brief  Enable flash power down mode or not
-  * @param[in] enable The bit indicates if flash power down mode is enable or not
-	* @retval None
-	*/
-void FLASH_EnableDeepPowerDown(BOOL enable);
-
-/**
-  * @brief  Read data from flash
-	* @param[in] ReadMode Normal or fast read, ref as @ref FLASH_READ_MODE
-	* @param[in] addr Start address to be read
-	* @param[in] size Expected data size to be read
-	* @param[out] data A user-allocated buffer to fetch data to be read
-  * @retval None
-	*/
-void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data);
-
-/**
-  * @brief  Write data to flash
-	* @param[in] addr Start address to be read
-	* @param[in] size Expected data size to be read
-	* @param[out] data A pointer to the data to be written
-  * @retval None
-	*/
-void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data);
-
-
-void flash_WaitInWritting(void) ;
-
-void flash_WaitReadFifoNotEmpty(void);
-
-uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_FLASH_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h

@@ -1,159 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_gpio.h
-	*
-	* @brief    CMEM7 GPIO header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_GPIO_H
-#define __CMEM7_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup GPIO_GROUP
-  * @{
-  */
-typedef enum {
-	GPIO_GROUP_GPIO,
-} GPIO_GROUP;
-
-#define IS_GPIO_GROUP(GROUP)  (((GROUP) == GPIO_GROUP_GPIO))
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_PWM_CHANNEL
-  * @{
-  */
-typedef enum {
-	GPIO_PWM_CHANNEL_GPIO_31,
-} GPIO_PWM_CHANNEL;
-        
-#define IS_GPIO_PWM_CHANNEL(CHANNEL)  (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31))
-/**
-  * @}
-  */
-	
-/**
-  * @brief  GPIO initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @param[in] PositiveTrigger Positive edge interrupt trigger if true, or negative edge
-  * @retval None
-	*/ 	
-void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger);
-
-/**
-  * @brief  Enable or disable GPIO output in the specific group. 
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @param[in] Enable each bit indicates if the corresponding GPIO pin 
-	*						in the specific GPIO group is enable or not
-  * @retval None
-	*/ 
-void GPIO_EnableOutput(uint8_t Group, uint32_t Enable);
-
-/**
-  * @brief  Enable or disable GPIO interrupt in the specific group. 
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @param[in] Enable each bit indicates if the corresponding GPIO pin interrupt 
-	*						in the specific GPIO group is enable or not
-  * @retval None
-	*/ 
-void GPIO_EnableInt(uint8_t Group, uint32_t Enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @retval uint32_t each bit indicates if the corresponding GPIO pin interrupt 
-	*					in the specific GPIO group is set or not
-	*/
-uint32_t GPIO_GetIntStatus(uint8_t Group);
-
-/**
-  * @brief  Clear GPIO interrupt in the specific group. 
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @param[in] Clear each bit indicates if the corresponding GPIO pin interrupt 
-	*						in the specific GPIO group is clear or not
-  * @retval None
-	*/ 
-void GPIO_ClearInt(uint8_t Group, uint32_t Clear);
-
-/**
-  * @brief  Get value of each GPIO pin in the specific group
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @retval uint32_t each bit indicates value of the corresponding GPIO pin 
-	*					in the specific GPIO group
-	*/
-uint32_t GPIO_Read(uint8_t Group);
-
-/**
-  * @brief  Set value of each GPIO pin in the specific group
-	* @param[in] Group GPIO group, which is a value of @ref GPIO_GROUP
-	* @param[in] Unmask each bit indicates value of the corresponding GPIO pin 
-	*						 in the specific GPIO group is set or not
-	* @param[in] data each bit indicates value of the corresponding GPIO pin
-	*						 in the specific GPIO group to be set
-  * @retval None
-	*/ 
-void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data);
-
-/**
-  * @brief  Initialize PWM for the specific GPIO pin
-	* @note		It can work before call GPIO_EnableOutput for the specific GPIO pin
-	* @param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
-	* @param[in] HighLevelNanoSecond Nanosecond which high level lasts 
-	* @param[in] LowLevelNanoSecond Nanosecond which low level lasts 
-  * @retval None
-	* @see		GPIO_EnableOutput
-	*/ 
-void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond);
-
-/**
-  * @brief  Enable or disable GPIO PWM in the specific channel. 
-	*	@param[in] Channel PWM channel, which is a value of @ref GPIO_PWM_CHANNEL
-	* @param[in] Enable The bit indicates if the specific channel is enable or not
-  * @retval None
-	*/ 
-void GPIO_EnablePwm(uint8_t Channel, BOOL Enable);
-
-
-
-/**
-  xjf 20150324
-  
-**/
-void GPIO_SetBits(uint32_t mask);
-void GPIO_clrBits(uint32_t mask);
-uint32_t GPIO_getBits(uint32_t mask); 
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_GPIO_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_i2c.h

@@ -1,247 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_i2c.h
-	*
-	* @brief    CMEM7 I2C header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_I2C_H
-#define __CMEM7_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C0) || \
-                                   ((PERIPH) == I2C1))
-
-/** @defgroup I2C_Mode
-  * @{
-  */
-#define I2C_Mode_Slave                  0
-#define I2C_Mode_Master                 1
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Slave) || \
-                           ((MODE) == I2C_Mode_Master))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ADDR_WIDTH
-  * @{
-  */
-#define I2C_ADDR_WIDTH_7BIT                  0
-#define I2C_ADDR_WIDTH_10BIT                 1
-#define IS_I2C_ADDR_WIDTH(WIDTH) (((WIDTH) == I2C_ADDR_WIDTH_7BIT) || \
-                                  ((WIDTH) == I2C_ADDR_WIDTH_10BIT))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_INT
-  * @{
-  */			
-#define I2C_INT_RX_FIFO_NOT_EMPTY      0x00000004 		/*!< Can't be clear but read FIFO */
-#define I2C_INT_RD_REQUEST             0x00000020     /*!< Slave was requested to send data */
-#define I2C_INT_TX_ABORT               0x00000040     /*!< Error while sending data */
-#define I2C_INT_RX_DONE                0x00000080     /*!< Slave sent all requested data */
-#define I2C_INT_TX_DONE                0x00000100     /*!< Master accomplish to send all data */
-
-#define I2C_INT_ALL                    (I2C_INT_RX_FIFO_NOT_EMPTY | \
-																				I2C_INT_RD_REQUEST | \
-																				I2C_INT_TX_ABORT | \
-																				I2C_INT_RX_DONE | \
-																				I2C_INT_TX_DONE)
-
-#define IS_I2C_INT(INT)                (((INT) != 0) && (((INT) & ~I2C_INT_ALL) == 0))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_STATUS
-  * @{
-  */
-#define I2C_STATUS_RX_FIFO_NOT_EMPTY   0x00200000 		/*!< Can't be clear but read FIFO */
-#define I2C_STATUS_RD_REQUEST          0x01000000     /*!< Slave was requested to send data */
-#define I2C_STATUS_TX_ABORT            0x02000000     /*!< Error while sending data */
-#define I2C_STATUS_RX_DONE             0x04000000     /*!< Slave sent all requested data */
-#define I2C_STATUS_TX_DONE             0x08000000     /*!< Master accomplish to send all data */
-
-#define I2C_STATUS_ALL                 (I2C_STATUS_RX_FIFO_NOT_EMPTY | \
-																				I2C_STATUS_RD_REQUEST | \
-																				I2C_STATUS_TX_ABORT | \
-																				I2C_STATUS_RX_DONE | \
-																				I2C_STATUS_TX_DONE)
-
-#define IS_I2C_STATUS(STATUS)          (((STATUS) != 0) && (((STATUS) & ~I2C_STATUS_ALL) == 0))
-/**
-  * @}
-  */
-
-/**
-  * @brief  I2C timing structure
-	*/
-typedef struct
-{
-  uint32_t I2C_Freq;                /*!< I2C frquency */
-
-	uint16_t I2C_TsuDat;              /*!< nano second of TSU:DAT */
-  uint16_t I2C_Tsetup;              /*!< nano second of THD:STA and TSU:STO */ 
-  uint16_t I2C_Tbuf;                /*!< nano second of TBUF */       	
-	uint16_t I2C_TsuSta;              /*!< nano second of TSU:STA */ 
-	
-	BOOL I2C_SdaFilterEn;             /*!< enabled flag of SDA filter */
-	uint8_t I2C_SdaFilterSpike;       /*!< spikes of SDA filter */
-	BOOL I2C_SclFilterEn;             /*!< enabled flag of SCL filter */
-	uint8_t I2C_SclFilterSpike;       /*!< spikes of SCL filter */
-	
-} I2C_InitTimingDef;
-
-/**
-  * @brief  I2C initialization structure
-	*/
-typedef struct
-{
-  uint8_t I2C_Mode;                 /*!< Specifies the I2C mode.
-                                         This parameter can be a value of @ref I2C_mode */
-	uint8_t I2C_AddressWidth;         /*!< 7- or 10-bits width address, ref as @ref I2C_ADDR_WIDTH */
-	uint8_t I2C_Address;              /*!< 7- or 10-bits address */
-	I2C_InitTimingDef* timing;        /*!< timing structure, null if don't set */		
-} I2C_InitTypeDef;
-
-/**
-  * @brief  I2C initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] init A pointer to structure I2C_InitTypeDef
-  * @retval None
-	*/ 
-void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init);
-
-/**
-  * @brief  Enable or disable I2C. 
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Enable The bit indicates if the specific I2C is enable or not
-  * @retval None
-	*/ 
-void I2C_Enable(I2C0_Type* I2Cx, BOOL enable);
-
-/**
-  * @brief  Enable or disable I2C interrupt. 
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
-  * @retval BOOL The bit indicates if specific interrupts are enable or not
-	*/
-BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @note   Specific interrupt clear will clear correspective status as well
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref I2C_Int
-  * @retval None
-	*/
-void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int);
-
-/**
-  * @brief  Check specific status are set or not 
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
-  * @retval BOOL The bit indicates if specific status are set or not
-	*/
-BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status);
-
-/**
-  * @brief  Clear specific status
-	* @note   Specific status clear will clear correspective interrupt as well
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] Status Status mask bits, which can be the combination of @ref I2C_STATUS
-  * @retval None
-	*/
-void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status);
-
-/**
-  * @brief  I2C send read request in master mode
-	* @note   Users must call I2C_StopReq between 2 requests
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] size Expected data size to be read
-  * @retval BOOL The bit indicates if read request to be sent is valid
-	* @see		I2C_StopReq
-	*/
-BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size);
-
-/**
-  * @brief  Read data from I2C
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] size Expected data size to be read
-	* @param[out] Data A user-allocated buffer to fetch data to be read
-  * @retval uint8_t Actual read data size
-	*/
-uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
-
-/**
-  * @brief  I2C send write request in master or slave mode
-	* @note   Users must call I2C_StopReq between 2 requests
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] size Expected data size to be written, includes the first data
-	* @param[in] firstData The first data to be written
-  * @retval BOOL The bit indicates if write request to be sent is valid
-	* @see		I2C_StopReq
-	*/
-BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData);
-
-/**
-  * @brief  Write data to I2C
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @param[in] size Expected data size to be written
-	* @param[in] Data A pointer to the data to be written
-  * @retval uint8_t Actual written data size
-	*/
-uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data);
-
-/**
-  * @brief  I2C stop request
-	* @note   Users must call I2C_StopReq between 2 requests
-	* @param[in] I2Cx I2C peripheral, which is I2C0 or I2C1
-	* @retval BOOL The bit indicates if request is stopped.
-	* @see		I2C_MasterReadReq I2C_WriteReq 
-	*/
-BOOL I2C_StopReq(I2C0_Type* I2Cx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CMEM7_I2C_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h

@@ -1,120 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_includes.h
-	*
-	* @brief    CMEM7 includes file, easy to use CMEM7 library
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_INCLUDES_H
-#define __CMEM7_INCLUDES_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7_conf.h"
-#include "cmem7_it.h"
-	 
-#ifdef _ADC
-	#include "cmem7_adc.h"
-#endif
-	 
-#ifdef _AES
-	#include "cmem7_aes.h"
-#endif
-	 
-#ifdef _CAN
-	#include "cmem7_can.h"
-#endif
-	 
-#ifdef _DDR
-	#include "cmem7_ddr.h"
-#endif
-	 
-#ifdef _DMA
-	#include "cmem7_dma.h"
-#endif
-	 
-#ifdef _EFUSE
-	#include "cmem7_efuse.h"
-#endif
-	 
-#ifdef _ETH
-	#include "cmem7_eth.h"
-#endif
-	 
-#ifdef _FLASH
-	#include "cmem7_flash.h"
-#endif
-	 
-#ifdef _GPIO
-	#include "cmem7_gpio.h"
-#endif
-	 
-#ifdef _I2C
-	#include "cmem7_i2c.h"
-#endif
-	 
-#ifdef _MISC
-	#include "cmem7_misc.h"
-#endif
-	 
-#ifdef _RTC
-	#include "cmem7_rtc.h"
-#endif
-	 
-#ifdef _SPI
-	#include "cmem7_spi.h"
-#endif
-	 
-#ifdef _TIM
-	#include "cmem7_tim.h"
-#endif
-	 
-#ifdef _UART
-	#include "cmem7_uart.h"
-#endif
-
-#ifdef _USB
-	#include "cmem7_usb.h"
-#endif
-
-#ifdef _WDG
-	#include "cmem7_wdg.h"
-#endif
-
-
-#ifdef _MARVELL
-  #include <marvel_98dx242.h>
-	#include <s24g_i2c.h>
-#endif	
-	
-#ifdef _IP1826D
-  #include <ip1826d_v00.h>
-#endif	
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_INCLUDES_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h

@@ -1,276 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_misc.h
-	*
-	* @brief    CMEM7 miscellaneous header file
-	* 
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_MISC_H
-#define __CMEM7_MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/**
-  * @brief  NVIC initialization structure
-	*/
-/**
-@code  
-	The table below gives the allowed values of the pre-emption priority and subpriority according
-	to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
-	============================================================================================================================
-		NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  | Description
-	============================================================================================================================
-	 NVIC_PriorityGroup_0  |                0                  |            0-15             |   0 bits for pre-emption priority
-												 |                                   |                             |   4 bits for subpriority
-	----------------------------------------------------------------------------------------------------------------------------
-	 NVIC_PriorityGroup_1  |                0-1                |            0-7              |   1 bits for pre-emption priority
-												 |                                   |                             |   3 bits for subpriority
-	----------------------------------------------------------------------------------------------------------------------------    
-	 NVIC_PriorityGroup_2  |                0-3                |            0-3              |   2 bits for pre-emption priority
-												 |                                   |                             |   2 bits for subpriority
-	----------------------------------------------------------------------------------------------------------------------------    
-	 NVIC_PriorityGroup_3  |                0-7                |            0-1              |   3 bits for pre-emption priority
-												 |                                   |                             |   1 bits for subpriority
-	----------------------------------------------------------------------------------------------------------------------------    
-	 NVIC_PriorityGroup_4  |                0-15               |            0                |   4 bits for pre-emption priority
-												 |                                   |                             |   0 bits for subpriority                       
-	============================================================================================================================
-@endcode
-	*/
-	
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be a value of @ref IRQn_Type 
-                                                   (For the complete Capital-micro Devices IRQ Channels list, please
-                                                    refer to cmem7.h file) */
-
-  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
-                                                   specified in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
-  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
-                                                   in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref NVIC_Priority_Table */
-
-  BOOL NVIC_IRQChannelCmd;                    /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled. 
-                                                   This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
- 
-
-/** @defgroup NVIC_VectTab
-  * @{
-  */
-
-#define NVIC_VectTab_CME_CODE        ((uint32_t)0x00000000)
-#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
-                                  ((VECTTAB) == NVIC_VectTab_RAM) || \
-                                  ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
-  * @}
-  */
-
-/** @defgroup NVIC_LP
-  * @{
-  */
-#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup NVIC_PriorityGroup
-  * @{
-  */
-#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
-                                                            4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
-                                                            3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
-                                                            2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
-                                                            1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
-                                                            0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
-                                       ((GROUP) == NVIC_PriorityGroup_1) || \
-                                       ((GROUP) == NVIC_PriorityGroup_2) || \
-                                       ((GROUP) == NVIC_PriorityGroup_3) || \
-                                       ((GROUP) == NVIC_PriorityGroup_4))
-/**
-  * @}
-  */
-	
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
-
-/**
-  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
-  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
-  *   This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
-  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
-  *                                4 bits for subpriority
-  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
-  *                                3 bits for subpriority
-  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
-  *                                2 bits for subpriority
-  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
-  *                                1 bits for subpriority
-  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
-  *                                0 bits for subpriority
-  * @retval None
-  */
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-
-/**
-  * @brief  Initializes the NVIC peripheral according to the specified
-  *         parameters in the NVIC_InitStruct.
-  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
-  *         the configuration information for the specified NVIC peripheral.
-  * @retval None
-  */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-
-/**
-  * @brief  Sets the vector table location and Offset.
-  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
-  *   This parameter can be one of the following values, ref as @ref NVIC_VectTab:
-  *     @arg NVIC_VectTab_RAM
-  *     @arg NVIC_VectTab_FLASH
-  * @param  Offset: Vector Table base offset field. This value must be a multiple 
-  *         of 0x200.
-  * @retval None
-  */
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-
-/**
-  * @brief  Selects the condition for the system to enter low power mode.
-  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
-  *   This parameter can be one of the following values, ref as @ref NVIC_LP:
-  *     @arg NVIC_LP_SEVONPEND
-  *     @arg NVIC_LP_SLEEPDEEP
-  *     @arg NVIC_LP_SLEEPONEXIT
-  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
-
-/**
-  * @brief  Memory map from address 'from' to 'address 'to' and open icache or not
-	* @param[in] from address to be mapped from
-	* @param[in] to address to be mapped to
-	* @param[in] isIcacheOn icache is on or off
-  * @retval None
-	*/
-void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
-
-/**
-  * @brief  Convert the mapping destination address to source address
-	* @param[in] to address to be mapped to
-  * @retval uint32_t address to be mapped from
-	*/
-uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
-
-/**
-  * @brief  Convert the mapping source address to destination address
-	* @param[in] from address to be mapped from
-  * @retval uint32_t address to be mapped to
-	*/
-uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
-
-/**
-  * @brief  Set NMI irq number, it should be one of @ref IRQn_Type.
-	* @Note		You can assign any valid IRQn_Type to NMI. After that, you will enter NMI 
-	*					interrupt routine if the specific 'irq' occurs. By default, NMI irq number
-	*					is 0, same as ETH_INT_IRQn
-	* @param[in] irq irq number 
-  * @retval None
-	*/
-void GLB_SetNmiIrqNum(uint32_t irq);
-
-/** @defgroup SYS_CLK_SEL
-  * @{
-  */
-#define SYS_CLK_SEL_OSC					0x0
-#define SYS_CLK_SEL_DLL					0x1
-#define SYS_CLK_SEL_CRYSTAL			0x2
-#define SYS_CLK_SEL_EXTERNAL		0x3	
-/**
-  * @}
-  */
-	
-/**
-  * @brief  Select system clock source, it should be one of @ref SYS_CLK_SEL.
-	* @Note		You MUST make sure externel clock has been stabled if clock 
-	*				  source is external before call this function. 
-	* 				Default value is SYS_CLK_SEL_OSC
-	* @param[in] irq irq number 
-  * @retval None
-	*/
-void GLB_SelectSysClkSource(uint8_t source);
-
-/**
-  * @brief  Simulate instruction 'STRB' or 'STRH' with 'BFI'
-	* @Note		In M7, you have to write a register in 32-bit alignment,
-	*				  not in 8-bit or 16-bit. 
-	* @param[in] addr register address to be written 
-  * @param[in] value value to be written
-  * @param[in] lsb LSB in register to be written
-  * @param[in] len bit length to be written
-  * @retval None
-	*/
-	
-	
-//#define aaaa(len) __asm("LDR len, 11")
-
-#define CMEM7_BFI(addr, value, lsb, len)        \
-  do {                                          \
-    unsigned long tmp;                          \
-    unsigned long tmp1 = (unsigned long)addr;   \
-                                                \
-    __asm("LDR tmp, [tmp1]\n"                   \
-      "BFI tmp, "#value", "#lsb", "#len" \n"    \
-      "STR tmp, [tmp1]\n");                     \
-		} while (0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_MISC_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_retarget.h

@@ -1,87 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_retarget.h
-	*
-	* @brief    CMEM7 retarget header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_RETARGET_H
-#define __CMEM7_RETARGET_H
-
-#include <stdio.h>
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-#pragma import(__use_no_semihosting_swi)
-
-struct __FILE { int handle; /* Add whatever you need here */ };
-FILE __stdout;
-FILE __stdin;
-FILE __stderr;
-
-
-int fputc(int c, FILE *f) {
-  uint8_t ch = c;
-	if (c == '\n')  {
-		ch = '\r';
-    while (0 == UART_Write(PRINT_UART, 1, &ch));
-		ch = '\n';
-  }
-	
-	while (0 == UART_Write(PRINT_UART, 1, &ch)) ;
-  return ch;
-}
-
-
-int fgetc(FILE *f) {
-	uint8_t ch;
-	
-	while (0 == UART_Read(PRINT_UART, 1, &ch)) ;
-  return ch;
-}
-
-int ferror(FILE *f) {
-  /* Your implementation of ferror */
-  return EOF;
-}
-
-
-void _ttywrch(int c) {
-  while (0 == UART_Write(PRINT_UART, 1, (uint8_t *)&c));
-}
-
-
-void _sys_exit(int return_code) {
-label:  goto label;  /* endless loop */
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_RETARGET_H */

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h

@@ -1,89 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_rtc.h
-	*
-	* @brief    CMEM7 RTC header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_RTC_H
-#define __CMEM7_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup RTC_Int
-  * @{
-  */
-#define RTC_Int_Second                     ((uint32_t)0x00000001)
-#define RTC_Int_Millsecond                 ((uint32_t)0x00000002)
-#define RTC_Int_All                        ((uint32_t)0x00000003)
-#define IS_RTC_INT(INT)                    (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0))
-/**
-  * @}
-  */
-   
-/**
-  * @brief  Enable or disable RTC interrupt. 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void RTC_ITConfig(uint32_t Int, BOOL Enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
-  * @retval BOOL The bit indicates if specific interrupts are set or not
-	*/
-BOOL RTC_GetITStatus(uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int
-  * @retval None
-	*/
-void RTC_ClearITPendingBit(uint32_t Int);
-
-/**
-  * @brief  Get seconds since power up
-	* @param	None
-  * @retval uint32_t Seconds since power up
-	*/
-uint32_t RTC_GetSecond(void);
-
-/**
-  * @brief  Get current millseconds
-	* @param	None
-  * @retval uint32_t Current millseconds
-	*/
-uint16_t RTC_GetMillSecond(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_RTC_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_spi.h

@@ -1,167 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_spi.h
-	*
-	* @brief    CMEM7 SPI header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_SPI_H
-#define __CMEM7_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
-                                   ((PERIPH) == SPI1))
-
-
-/** @defgroup SPI_MODE
-  * @{
-  */
-#define SPI_MODE_CPOL_0_CPHA_0         0   	/*!< CPOL : Idle clock level is low level. 
-																								 CPHA : Capture data at the first edge */
-#define SPI_MODE_CPOL_0_CPHA_1         1		/*!< CPOL : Idle clock level is low level. 
-																								 CPHA : Capture data at the second edge */	
-#define SPI_MODE_CPOL_1_CPHA_0         2		/*!< CPOL : Idle clock level is high level. 
-																								 CPHA : Capture data at the first edge */
-#define SPI_MODE_CPOL_1_CPHA_1         3	 	/*!< CPOL : Idle clock level is high level. 
-																								 CPHA : Capture data at the first edge */    
-#define IS_SPI_MODE(MODE)              (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
-                                        ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
-                                        ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
-																				((MODE) == SPI_MODE_CPOL_1_CPHA_1))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_INT
-  * @{
-  */	
-#define SPI_INT_RX_FIFO_UNDERFLOW      0x00000001    
-#define SPI_INT_RX_FIFO_OVERFLOW       0x00000002
-#define SPI_INT_RX_FIFO_ALMOST_FULL    0x00000004
-#define SPI_INT_TX_FIFO_UNDERFLOW      0x00000008    
-#define SPI_INT_TX_FIFO_OVERFLOW       0x00000010
-#define SPI_INT_TX_FIFO_ALMOST_FULL    0x00000020
-#define SPI_INT_DONE                   0x00000040
-#define SPI_INT_ALL                    0x0000007F
-
-#define IS_SPI_INT(INT)                (((INT) != 0) && (((INT) & ~SPI_INT_ALL) == 0))
-/**
-  * @}
-  */
-
-/**
-  * @brief  SPI initialization structure
-	*/ 
-typedef struct
-{
-  uint8_t SPI_Mode;                 /*!< indicates SPI's CPOL and CPHA, ref as @ref SPI_MODE */
-  BOOL SPI_RxEn;                    /*!< indicates if SPI receiver is enabled or not */
-  uint8_t SPI_BitLength;            /*!< bit length while transmitting and receiving */
-  uint8_t SPI_Gap;                  /*!< cycle number between continuous data frame */ 
-	uint8_t SPI_ClockDividor;         /*!< SPI clock dividor, 1 / ((1 + DIV) * 2) */
-} SPI_InitTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @brief  SPI initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] init A pointer to structure SPI_InitTypeDef
-  * @retval None
-	*/ 
-void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
-
-/**
-  * @brief  Enable or disable SPI. 
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] Enable The bit indicates if the specific SPI is enable or not
-  * @retval None
-	*/ 
-void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
-
-/**
-  * @brief  Enable or disable SPI interrupt. 
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
-  * @retval BOOL The bit indicates if specific interrupts are set or not
-	*/
-BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref SPI_Int
-  * @retval None
-	*/
-void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
-
-/**
-  * @brief  Read data from SPI FIFO
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] size Expected data size to be read
-	* @param[out] data A user-allocated buffer to fetch data to be read
-  * @retval uint8_t Actual read data size
-	*/
-uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
-
-/**
-  * @brief  Write data to SPI FIFO
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] size Expected data size to be written
-	* @param[in] data A pointer to the data to be written
-  * @retval uint8_t Actual written data size
-	*/
-uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
-
-/**
-  * @brief  send a SPI transcation request 
-	* @param[in] SPIx SPI peripheral, which is SPI0 or SPI1
-	* @param[in] size Expected data size to be written and read
-	* @retval BOOL The bit indicates if the request is sent
-	*/
-BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CMEM7_SPI_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_tim.h

@@ -1,101 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_tim.h
-	*
-	* @brief    CMEM7 timer header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_TIM_H
-#define __CMEM7_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIMER0) || \
-                                   ((PERIPH) == TIMER1) || \
-                                   ((PERIPH) == TIMER2) || \
-                                   ((PERIPH) == TIMER3))
-																	 
-/**
-  * @brief  Timer initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @param[in] Ms overflow micro-seconds of the specific timer
-  * @retval None
-	*/
-void TIM_Init(TIMER0_Type* Timx, uint16_t Ms);
-
-/**
-  * @brief  Enable or disable timer interrupt. 
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @param[in] Enable The bit indicates if the specific interrupt is enable or not
-  * @retval None
-	*/ 
-void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable);
-
-/**
-  * @brief  Check the specific interrupt is set or not 
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @retval BOOL The bit indicates if the specific interrupt is set or not
-	*/
-BOOL TIM_GetIntStatus(TIMER0_Type* Timx);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @retval None
-	*/
-void TIM_ClearInt(TIMER0_Type* Timx);
-
-/**
-  * @brief  Enable or disable timer. 
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @param[in] Enable The bit indicates if the specific timer is enable or not
-  * @retval None
-	*/ 
-void TIM_Enable(TIMER0_Type* Timx, BOOL Enable);
-
-/**
-  * @brief  Check the specific timer is overflow or not 
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @retval BOOL The bit indicates if the specific timer is overflow or not
-	*/
-BOOL TIM_IsOverflow(TIMER0_Type* Timx);
-
-/**
-  * @brief  Get current counter of timer
-	* @param[in] Timx Timer peripheral, which is timer0, timer1, timer2 or timer3
-	* @retval uint32_t current counter
-	*/
-uint32_t TIM_GetCounter(TIMER0_Type* Timx);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CMEM7_TIM_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_uart.h

@@ -1,172 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_uart.h
-	*
-	* @brief    CMEM7 uart header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_UART_H
-#define __CMEM7_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-#define IS_UART_ALL_PERIPH(PERIPH) (((PERIPH) == UART0) || \
-                                     ((PERIPH) == UART1) || \
-                                     ((PERIPH) == UART2))
-	
-/** @defgroup UART_StopBits
-  * @{
-  */
-#define UART_StopBits_0_5                 0
-#define UART_StopBits_1                   1
-#define UART_StopBits_1_5                 2
-#define UART_StopBits_2                   3
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
-                                     ((STOPBITS) == UART_StopBits_0_5) || \
-                                     ((STOPBITS) == UART_StopBits_2) || \
-                                     ((STOPBITS) == UART_StopBits_1_5))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity
-  * @{
-  */
-#define UART_Parity_Even                  0
-#define UART_Parity_Odd                   1
-#define UART_Parity_None                  2
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_Even) || \
-                                 ((PARITY) == UART_Parity_Odd) || \
-																 ((PARITY) == UART_Parity_None))										 
-/**
-  * @}
-  */
-
-/** @defgroup UART_Int
-  * @{
-  */
-#define UART_Int_RxNotEmpty               0x00000001    
-#define UART_Int_TxEmpty                  0x00000002
-#define UART_Int_TxHalfEmpty              0x00000004
-#define UART_Int_TxTimeoutNotEmpty        0x00000008
-#define UART_Int_TxTimeoutEmpty           0x00000010
-#define UART_Int_RxHalfFull               0x00000020
-#define UART_Int_TxFull                   0x00000040
-#define UART_Int_ParityError              0x00000080
-#define UART_Int_FrameError               0x00000100
-#define UART_Int_OverrunError             0x00000200
-#define UART_Int_RxThresholdReach         0x00000400
-#define UART_Int_All                      0x000007FF
-
-#define IS_UART_INT(INT)        (((INT) != 0) && (((INT) & ~UART_Int_All) == 0))
-
-/**
-  * @}
-  */
-	
-/**
-  * @brief  UART initialization structure
-	*/ 
-typedef struct
-{
-	uint32_t UART_BaudRate;            /*!< Baudrate */																	  
-	uint8_t UART_StopBits;             /*!< Specifies the number of stop bits transmitted, 
-																					It's a value of @ref UART_StopBits */
-	uint8_t UART_Parity;               /*!< Specifies the parity mode. 
-																					It's a value of @ref UART_Parity */
-	BOOL UART_LoopBack;                /*!< loop back mode */
-	BOOL UART_RxEn;                    /*!< Receive enable bit */
-	BOOL UART_CtsEn;                   /*!< Clear to set */
-} UART_InitTypeDef;
-
-/**
-  * @brief  UART initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] init A pointer to structure UART_InitTypeDef
-  * @retval None
-	*/ 
-void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init);
-
-/**
-  * @brief  Enable or disable UART interrupt. 
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
-	* @param[in] Enable The bit indicates if specific interrupts are enable or not
-  * @retval None
-	*/ 
-void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL Enable);
-
-/**
-  * @brief  Enable or disable UART. 
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Enable The bit indicates if the specific UART is enable or not
-  * @retval None
-	*/ 
-void UART_Enable(UART0_Type* UARTx, BOOL enable);
-
-/**
-  * @brief  Check specific interrupts are set or not 
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
-  * @retval BOOL The bit indicates if specific interrupts are set or not
-	*/
-BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int);
-
-/**
-  * @brief  Clear specific interrupts
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Int interrupt mask bits, which can be the combination of @ref UART_Int
-  * @retval None
-	*/
-void UART_ClearInt(UART0_Type* UARTx, uint32_t Int);
-
-/**
-  * @brief  Write data to UART
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Size Expected data size to be written
-	* @param[in] Data A pointer to the data to be written
-  * @retval uint8_t Actual written data size
-	*/
-uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
-
-/**
-  * @brief  Read data from UART
-	* @param[in] UARTx UART peripheral, which is UART0, UART1 or UART2
-	* @param[in] Size Expected data size to be read
-	* @param[out] Data A user-allocated buffer to fetch data to be read
-  * @retval uint8_t Actual read data size
-	*/
-uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_UART_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_usb.h

@@ -1,588 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_usb.h
-	*
-	* @brief    CMEM7 USB header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __CMEM7_USB_H
-#define __CMEM7_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-#include "string.h"
-
-/**
- *
- */
-#define SET_HCDMA_DESC_ADDR(a)		(((uint32_t)(a)) >> 9)
-#define MIN(a, b)					(((a) <= (b)) ? (a) : (b))
-#define MAX(a, b)					(((a) >= (b)) ? (a) : (b))
-#define BIT(b)						(0x1u << (b))
-
-/** @defgroup USB_HOST_PID
-  * @{
-  */
-#define USB_HOST_PID_DATA0			0x0				/*!< Indicates the Data PID is DATA0                                       */
-#define USB_HOST_PID_DATA2			0x1				/*!< Indicates the Data PID is DATA2                                       */
-#define USB_HOST_PID_DATA1			0x2				/*!< Indicates the Data PID is DATA1                                       */
-#define USB_HOST_PID_MDATA			0x3				/*!< Indicates the Data PID is MDATA (non-control)                         */
-#define USB_HOST_PID_SETUP			0x3				/*!< Indicates the Data PID is SETUP (control)                             */
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP_TYPE
-  * @{
-  */
-typedef enum {
-	USB_EP_TYPE_CONTROL =			0x0,			/*!< Control                                                               */
-	USB_EP_TYPE_ISO =				0x1,			/*!< Isochronous                                                           */
-	USB_EP_TYPE_BULK =				0x2,			/*!< Bulk                                                                  */
-	USB_EP_TYPE_INT =				0x3,			/*!< Interrupt                                                             */
-} USB_EP_TYPE;
-/**
-  * @}
-  */
-
-/** @defgroup USB_ENUM_SPEED
-  * @{
-  */
-typedef enum {
-	USB_ENUM_SPEED_HS =				0x0,			/*!< Enumerated Speed is High Speed                                        */
-	USB_ENUM_SPEED_FS =				0x1,			/*!< Enumerated Speed is Full Speed                                        */
-	USB_ENUM_SPEED_LS =				0x2,			/*!< Enumerated Speed is Low  Speed                                        */
-	USB_ENUM_SPEED_FS_48M =			0x3,			/*!< Enumerated Speed is Full Speed (PHY clock is running at 48MHz)        */
-} USB_ENUM_SPEED;
-/**
-  * @}
-  */
-
-/** @defgroup USB_INT_GP
-  * @{
-  */
-typedef enum {
-	USB_INT_GP_HOST_DISC,							/*!< Device disconnection interrupt (Only for HOST Mode)                   */
-	USB_INT_GP_DEV_RESET,							/*!< USB Port Reset Interrupt (Only for DEVICE Mode)                       */
-	USB_INT_GP_DEV_ENUMDONE,						/*!< Enumeration Done Interrupt (Only for DEVICE Mode)                     */
-	USB_INT_GP_DEV_SUSP,							/*!< USB Suspend Interrupt (Only for DEVICE Mode)                          */
-	USB_INT_GP_DEV_EARLY,							/*!< USB Idle Interrupt (Only for DEVICE Mode)                             */
-	USB_INT_GP_SOF,									/*!< SOF Interrupt                                                         */
-	USB_INT_GP_MIS,									/*!< USB access overstep the boundary Interrupt                            */
-	USB_INT_GP_IDCHG,								/*!< OTG Connector ID Status Change Interrupt                              */
-	USB_INT_GP_SESSREQ,								/*!< Session Request / Create Interrupt                                    */
-} USB_INT_GP;
-/**
-  * @}
-  */
-
-/** @defgroup USB_INT_OTG
-  * @{
-  */
-typedef enum {
-	USB_INT_OTG_SESEND,								/*!< Session End Interrupt                                                 */
-	USB_INT_OTG_STANDAUP,							/*!< B Device timeout to connect Interrupt                                 */
-	USB_INT_OTG_HNDETECT,							/*!< Host Negotiation Detected Interrupt                                   */
-	USB_INT_OTG_HNSUCCHG,							/*!< Host Negotiation Success Status Change Interrupt                      */
-	USB_INT_OTG_KEEPAPP,							/*!< Debounce Done Interrupt (Only for HOST Mode)                          */
-} USB_INT_OTG;
-/**
-  * @}
-  */
-
-/** @defgroup USB_OTG_CTL
-  * @{
-  */
-typedef enum {
-	USB_OTG_DEV_HNSUCC = 8,							/*!< Host Negotiation Success (Only for DEVICE Mode, Read Only)            */
-	USB_OTG_DEV_HNPREQ = 9,							/*!< HNP Request (Only for DEVICE Mode)                                    */
-	USB_OTG_HST_HNPENABLE = 10,						/*!< Host Set HNP Enable (Only for HOST Mode)                              */
-	USB_OTG_DEV_HNPENABLE = 11,						/*!< Device HNP Enabled (Only for DEVICE Mode)                             */
-} USB_OTG_CTL;
-
-/**
-  * @}
-  */
-
-typedef union {
-    __IO uint32_t  HPRT;                            /*!< Host Port Control and Status Register                                 */
-    
-    struct {
-      __I  uint32_t  PCS        :  1;               /*!< If a device is attached to the port                                   */
-      __IO uint32_t  PCD        :  1;               /*!< A device connection is detected                                       */
-      __IO uint32_t  PE         :  1;               /*!< Port Enable                                                           */
-      __IO uint32_t  PEDC       :  1;               /*!< Set if when the status of the Port Enable (bit 2) of this register
-                                                         changes                                                               */
-      __I  uint32_t  POA        :  1;               /*!< Indicates the overcurrent condition of the port                       */
-      __IO uint32_t  POC        :  1;               /*!< Set if when the status of the Port Overcurrent Active bit (bit
-                                                         4) in this register changes                                           */
-      __IO uint32_t  PR         :  1;               /*!< Application and Core all can perform resume by setting, then
-                                                         clear it whatever resume is success or not                            */
-      __IO uint32_t  PS         :  1;               /*!< Sets this bit to put this port in Suspend mode                        */
-      __IO uint32_t  PRESET     :  1;               /*!< sets this bit, a reset sequence is started on this port               */
-           uint32_t             :  1;
-      __IO uint32_t  PLSDP      :  1;               /*!< Logic level of D+                                                     */
-      __IO uint32_t  PLSDN      :  1;               /*!< Logic level of D-                                                     */
-      __IO uint32_t  PP         :  1;               /*!< this field to control power to this port. 1, power on                 */
-      __IO uint32_t  PTC        :  4;               /*!< The application writes a nonzero value to this field to put
-                                                         the port into a Test mode                                             */
-      __I  uint32_t  SPEED      :  2;               /*!< Indicates the speed of the device attached to this port               */
-    } HPRT_b;                                       /*!< BitSize                                                               */
-} USB_REG_HPRT;
-
-typedef struct {
-  union {
-    uint32_t VALUE;                                 /*!< provide the status of the buffer                                            */
-    struct {
-      __IO uint32_t  SIZE       : 17;               /*!< Total bytes to transfer for OUT; the expected transfer size for IN    */
-      __IO uint32_t  AQTD       :  6;               /*!< IN Only, Alternated Queue Transfer Descriptor Valid                   */
-      __IO uint32_t  AQTD_VLD   :  1;               /*!< IN Only, Alternated Queue Transfer Descriptor Valid                   */
-      __IO uint32_t  SUP        :  1;               /*!< OUT Only, it indicates that the buffer data pointed by this descriptor
-                                                       is a setup packet of 8 bytes                                            */
-      __IO uint32_t  IOC        :  1;               /*!< It indicates that that the core must generate a XferCompl interrupt   */
-      __IO uint32_t  EOL        :  1;               /*!< It indicates that this is the last descriptor in the list             */
-           uint32_t             :  1;
-      __IO uint32_t  STS        :  2;               /*!< The status of the rx/tx data:
-                                                       00=Success; 01=PKTERR; 10=Reserved; 11=Reserved                         */
-           uint32_t             :  1;
-      __IO uint32_t  A          :  1;               /*!< Active: 0=descriptor is not ready; 1=descriptor is ready              */
-    } HOST_NISO_b;                                  /*!< BitSize                                                               */
-    struct {
-      __IO uint32_t  SIZE       : 16;               /*!< Total bytes to transfer for OUT; the expected transfer size for IN    */
-           uint32_t             :  7;
-      __IO uint32_t  MTRF       :  1;               /*!< IN Only, Alternated Queue Transfer Descriptor Valid                   */
-      __IO uint32_t  SR         :  1;               /*!< IN Only, Alternated Queue Transfer Descriptor Valid                   */
-      __IO uint32_t  IOC        :  1;               /*!< It indicates that that the core must generate a XferCompl interrupt   */
-      __IO uint32_t  SP         :  1;               /*!< It indicates that this is the last descriptor in the list             */
-      __IO uint32_t  L          :  1;               /*!< It indicates that this is the last descriptor in the list             */
-      __IO uint32_t  STS        :  2;               /*!< The status of the rx/tx data:
-                                                       00=Success; 01=PKTERR; 10=Reserved; 11=Reserved                         */
-      __IO uint32_t  BS         :  2;               /*!< Active: 0=descriptor is not ready; 1=descriptor is ready              */
-    } DEV_NISO_OUT_b;                               /*!< BitSize                                                               */
-    struct {
-      __IO uint32_t  SIZE       : 16;               /*!< Total bytes to transfer for OUT; the expected transfer size for IN    */
-           uint32_t             :  7;
-      __IO uint32_t  PID        :  2;               /*!< IN Only, Alternated Queue Transfer Descriptor Valid                   */
-      __IO uint32_t  IOC        :  1;               /*!< It indicates that that the core must generate a XferCompl interrupt   */
-      __IO uint32_t  SP         :  1;               /*!< It indicates that this is the last descriptor in the list             */
-      __IO uint32_t  L          :  1;               /*!< It indicates that this is the last descriptor in the list             */
-      __IO uint32_t  STS        :  2;               /*!< The status of the rx/tx data:
-                                                       00=Success; 01=PKTERR; 10=Reserved; 11=Reserved                         */
-      __IO uint32_t  BS         :  2;               /*!< Active: 0=descriptor is not ready; 1=descriptor is ready              */
-    } DEV_NISO_IN_b;                                /*!< BitSize                                                               */
-  } QUADLET;
-  uint32_t  BUIFFER;                                /*!< points to a data buffer                                               */
-} OTG_DESCRIPTOR;
-
-/**
- * @brief Get OTG Connector ID Status (Is B-Device)
- * @retval BOOL TRUE: High; FALSE: Low
-   */
-BOOL USB_ogtIsBdevID(void);
-
-/**
- * @brief Set USB Global Interrupt Enable
-   * @param[in] enable TRUE: Enable; FALSE: Disable
- * @retval void
-   */
-void USB_EnableInt(BOOL enable);
-
-/**
- * @brief Flush TX/RX FIFO
-   * @param[in] num Flush FIFO<46><4F>0: non-periodic TX FIFO (HOST Mode) or FIFO 0 (DEVICE Mode); 1: Periodic TX FIFO (HOST Mode) or FIFO 1 (DEVICE Mode); 2-15: FIFO n in DEVICE Mode; 16: Flush All TX FIFO; otherwise: Flush RX FIFO
- * @retval void
-   */
-void USB_FlushFIFO(uint32_t num);
-
-/**
- * @brief Initialize USB
-   * @param[in] type USB Mode, Bit0: Force HOST Mode; Bit1: Force DEVICE Mode; Bit4: Enable SRP; Bit5: Enable HNP
- * @retval void
-   */
-void USB_coreInit(uint32_t type);
-
-/**
- * @brief Get USB Mode (Is Host Mode?)
- * @retval BOOL TRUE: HOST Mode; FALSE: DEVICE Mode
-   */
-BOOL USB_roleIsHost(void);
-
-/**
- * @brief Control and get VBus Status (Only for HOST Mode)
-   * @param[in] opt Bit1: Set VBus using Bit0; Bit0: Turn VBus On or Off
- * @retval BOOL TRUE: VBus is on; FALSE<53><45>VBus is off
- * @note It cannot control VBus actually due to HW problem
-   */
-BOOL USB_hostVBus(uint32_t opt);
-
-/**
- * @brief Initialize USB HOST Module (Only for HOST Mode)
- * @retval void
-   */
-void USB_hostInit(void);
-
-/**
- * @brief Set USB Port Reset Status (Only for HOST Mode)
-   * @param[in] rst TRUE: Port is reseting; FALSE: Port stop reseting
- * @retval void
-   */
-void USB_HostResetPort(BOOL rst);
-
-/**
- * @brief Frame Number of the next SOF (Only for HOST Mode)
- * @retval uint16_t Frame Number of the next SOF will be send
-   */
-uint16_t USB_HostGetCurFrame(void);
-
-/**
- * @brief Suspend USP Port (Only for HOST Mode)
- * @retval void
-   */
-void USB_HostSuspendPort(void);
-
-/**
- * @brief Get the device enumerated speed (Only for HOST Mode)
- * @retval USB_ENUM_SPEED A value of @ref USB_ENUM_SPEED defined
-   */
-USB_ENUM_SPEED USB_hostGetEnumSpd(void);
-
-/**
- * @brief Get USB Port Connection Status (Only for HOST Mode)
- * @retval BOOL TRUE: A device is attached; FALSE: No device is attached
-   */
-BOOL USB_hostPrtConn(void);
-
-/**
- * @brief Channel 0 Transaction (Only for HOST Mode)
-   * @param[in] devaddr USB Device Address
-   * @param[in] desc A pointer to DMA Descriptor (512-byte alignment)
-   * @param[in] ctd In terms of number of DMA descriptors (0 means start from 1st DMA descriptor)
-   * @param[in] ntd Number of Transfer Descriptors (from 0 to 63 which means from 1 to 64 descriptors)
-   * @param[in] ping TRUE: Do PING protocol (Only for OUT Transfer); Must be 0 for IN Transfer
-   * @param[in] pid PID: A value of @ref USB_HOST_PID defined: USB_HOST_PID_DATA0, USB_HOST_PID_DATA2, USB_HOST_PID_DATA1, USB_HOST_PID_MDATA or USB_HOST_PID_SETUP
-   * @param[in] mps Maximum Packet Size (in bytes)
-   * @param[in] epnum Endpoint Address
-   * @param[in] in Is IN Transfer, TRUE: IN Transfer; FALSE: OUT Transfer
-   * @param[in] eptype Endpoint Type, A value of @ref USB_EP_TYPE defined
-   * @param[in] speed Device Speed, A value of @ref USB_ENUM_SPEED defined
-   */
-void USB_hostCH0(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
-
-/**
- * @brief Channel 1 Transaction (Only for HOST Mode)
- * @see USB_hostCH0
- */
-void USB_hostCH1(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
-
-/**
- * @brief Channel 2 Transaction (Only for HOST Mode)
- * @see USB_hostCH0
- */
-void USB_hostCH2(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
-
-/**
- * @brief Channel n Transaction (Only for HOST Mode)
-   * @param[in] ch Channel number will be used
-   * @param[in] devaddr USB Device Address
-   * @param[in] desc A pointer to DMA Descriptor (512-byte alignment)
-   * @param[in] ctd In terms of number of DMA descriptors (0 means start from 1st DMA descriptor)
-   * @param[in] ntd Number of Transfer Descriptors (from 0 to 63 which means from 1 to 64 descriptors)
-   * @param[in] ping TRUE: Do PING protocol (Only for OUT Transfer); Must be 0 for IN Transfer
-   * @param[in] pid PID: A value of @ref USB_HOST_PID defined: USB_HOST_PID_DATA0, USB_HOST_PID_DATA2, USB_HOST_PID_DATA1, USB_HOST_PID_MDATA or USB_HOST_PID_SETUP
-   * @param[in] mps Maximum Packet Size (in bytes)
-   * @param[in] epnum Endpoint Address
-   * @param[in] in Is IN Transfer, TRUE: IN Transfer; FALSE: OUT Transfer
-   * @param[in] eptype Endpoint Type, A value of @ref USB_EP_TYPE defined
-   * @param[in] speed Device Speed, A value of @ref USB_ENUM_SPEED defined
- * @retval int returns 0 if success, otherwise returns a negative value
-   */
-int USB_hostCHn(uint32_t ch, uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed);
-
-/**
- * @brief Halt Channel n (Only for HOST Mode)
-   * @param[in] ch Channel number will be halted
- * @retval int returns 0 if success, otherwise returns a negative value
-   */
-int USB_hostCHnHalt(uint32_t ch);
-
-/**
- * @brief Disable USB Port (Only for HOST Mode)
-   * @param[in] dis TRUE: Disable USB Port; FALSE: Do NOT Disable USB Port
- * @retval BOOL If USB Port is disabled, TRUE: USB Port Disabled; FALSE: USB Port Enabled
- * @note It CANNOT Enable USB Port; Port will be enabled automatically after the port was reset successfully.
-   */
-BOOL USB_hostPortDisable(BOOL dis);
-
-/**
- * @brief Enable Connection Interrupt (Only for HOST Mode)
-   * @param[in] en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
- * @retval void
-   */
-void USB_hostINT_enConn(BOOL en);
-
-/**
- * @brief Connection Interrupt Asserted (Only for HOST Mode)
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
- * @note PCD or PEDC asserted, please call USB_hostINT_clrPCD or USB_hostINT_clrPEDC function to clear it.
-   */
-BOOL USB_hostINT_isConn(void);
-
-/**
- * @brief Port Connection Detected (PCD) Interrupt Asserted (Only for HOST Mode)
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
-   */
-BOOL USB_hostINT_isPCD(void);
-
-/**
- * @brief Clear Port Connection Detected (PCD) Interrupt Flag (Only for HOST Mode)
- * @retval void
-   */
-void USB_hostINT_clrPCD(void);
-
-/**
- * @brief Port Enable/Disable Change<67><65>PEDC<44><43>Interrupt Asserted (Only for HOST Mode)
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
-   */
-BOOL USB_hostINT_isPEDC(void);
-
-/**
- * @brief Clear Port Enable/Disable Change<67><65>PEDC<44><43>Interrupt Flag (Only for HOST Mode)
- * @retval void
-   */
-void USB_hostINT_clrPEDC(void);
-
-/**
- * @brief Enable Transaction Done Interrupt (Only for HOST Mode)
-   * @param[in] ch Channel to enable
- * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
- * @retval int returns 0 if success, otherwise returns a negative value
-   */
-int USB_hostINT_enDone(uint32_t ch, BOOL en);
-
-/**
- * @brief Transaction Done Interrupt Asserted (Only for HOST Mode)
-   * @param[in] ch Channel to check
- * @retval uint32_t result, Bit0: Done; Bit1: Buffer Not Available Error; Bit2: Channel Idle; Bit3: Transaction Error
-   */
-uint32_t USB_hostINT_isDone(uint32_t ch);
-
-/**
- * @brief Transaction Done Interrupt Asserted (Only for HOST Mode)
-   * @param[in] ch Channel to check
- * @retval uint32_t result, 0: No interrupt is pendding
-   */
-uint32_t USB_hostINT_isPend(uint32_t ch);
-
-/**
- * @brief Initialize USB DEVICE Module (Only for DEVICE Mode)
- * @retval void
-   */
-void USB_devInit(void);
-
-/**
- * @brief Get the device enumerated speed (Only for DEVICE Mode)
- * @retval USB_ENUM_SPEED A value of @ref USB_ENUM_SPEED defined
-   */
-USB_ENUM_SPEED USB_devGetEnumSpd(void);
-
-/**
- * @brief Set Device Address (Only for DEVICE Mode)
-   * @param[in] Device Address
- * @retval void
-   */
-void USB_devSetAddress(uint32_t addr);
-
-
-/**
- * @brief Endpoint 0 OUT Transation (Only for DEVICE Mode)
-   * @param[in] size Transation length (in bytes)
-   * @param[in] pktcnt Packet Count
-   * @param[in] stpcnt The number of back-to-back SETUP data packets the endpoint can receive. (0 - 3)
-   * @param[in] desc A pointer to DMA descriptors
-   * @param[in] snoop Snoop Mode, TRUE: Enable Snoop Mode, which means it does not check if the OUT packets are correct before transferring them to application memory; FLASE: Disable Snoop Mode
- * @retval void
-   */
-void USB_devEP0out(uint32_t size, uint32_t pktcnt, uint32_t stpcnt, void *desc, BOOL snoop);
-
-/**
- * @brief Endpoint 0 IN Transation (Only for DEVICE Mode)
-   * @param[in] size Transation length (in bytes)
-   * @param[in] pktcnt Packet Count
-   * @param[in] desc A pointer to DMA descriptors
-   * @param[in] mps Maximum Packet Size (in bytes), only 8,, 32, 64 is valid
- * @retval BOOL TRUE: Parameter mps is valid; FLASE: Parameter mps is invalid
-   */
-BOOL USB_devEP0in(uint32_t size, uint32_t pktcnt, void *desc, uint32_t mps/*8,16,32,64-byte*/);
-
-/**
- * @brief Active Endpoint 1 (Only for DEVICE Mode)
-   * @param[in] in Endpoint direction, TRUE: IN; FALSE: OUT
-   * @param[in] mps Maximum Packet Size (in bytes), 0 means inactive the endpoint
-   * @param[in] type Endpoint type, A value of @ref USB_EP_TYPE defined
- * @retval void
- * @note All Endpoint but EP0 will be inactived after USB Port reseted
-   */
-void USB_devActEP1(const BOOL in, const uint32_t mps, USB_EP_TYPE type);
-
-/**
- * @brief Active Endpoint 2 (Only for DEVICE Mode)
- * @see USB_devActEP1
- */
-void USB_devActEP2(const BOOL in, const uint32_t mps, USB_EP_TYPE type);
-
-/**
- * @brief Endpoint 1 IN Transation (Only for DEVICE Mode)
-   * @param[in] size Maximum Packet Size (in bytes)
-   * @param[in] pktcnt Packet Count
-   * @param[in] pid PID (only for interrupt/bulk), 0x1 means DATA0; 0x2 means DATA1
-   * @param[in] desc A pointer to DMA descriptors
- * @retval void
- * @see
- */
-void USB_devEP1in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc);
-
-/**
- * @brief Endpoint 1 OUT Transation (Only for DEVICE Mode)
-   * @param[in] size Data length (in bytes)
-   * @param[in] pktcnt Packet Count
-   * @param[in] PID (only for interrupt/bulk), 0x1 means DATA0; 0x2 means DATA1
-   * @param[in] stpcnt The number of back-to-back SETUP data packets the endpoint can receive. (0 - 3)
-   * @param[in] desc A pointer to DMA descriptors
-   * @param[in] snoop Snoop Mode, TRUE: Enable Snoop Mode, which means it does not check if the OUT packets are correct before transferring them to application memory; FLASE: Disable Snoop Mode
- * @retval void
-   */
-void USB_devEP1out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop);
-
-/**
- * @brief Endpoint 2 IN Transation (Only for DEVICE Mode)
- * @see USB_devEP1in
- */
-void USB_devEP2in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc);
-
-/**
- * @brief Endpoint 2 OUT Transation (Only for DEVICE Mode)
- * @see USB_devEP1out
- */
-void USB_devEP2out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop);
-
-/**
- * @brief Set NAK handshake (Only for DEVICE Mode)
-   * @param[in] ep Endpoint
-   * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
-   * @param[in] en TRUE: Enable NAK handshake; FALSE: Disable NAK handshake
- * @retval void
-   */
-void USB_devNAKhandshake(uint32_t ep, BOOL in, BOOL en);
-
-/**
- * @brief Set STALL handshake (Only for DEVICE Mode)
-   * @param[in] ep Endpoint
-   * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
-   * @param[in] en TRUE: Enable STALL handshake; FALSE: Disable STALL handshake
- * @retval BOOL Return the old status before en is set.
- * @note Not for ISO Endpoint; For Endpoint 0 it clears itself when a SETUP token is received.
-   */
-BOOL USB_devSTALLhandshake(uint32_t ep, BOOL in, BOOL en);
-
-/**
- * @brief Enable Transaction Done Interrupt (Only for DEVICE Mode)
-   * @param[in] ep Endpoint
-   * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
- * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
- * @retval void
-   */
-void USB_devINT_enDone(uint32_t ep, BOOL in, BOOL en);
-
-/**
- * @brief Transaction Done Interrupt Asserted (Only for DEVICE Mode)
-   * @param[in] ep Endpoint
-   * @param[in] in Endpoint Direction, TRUE: IN; FALSE: OUT
- * @retval uint32_t Result, Bit0: Done; Bit1<74><31>Buffer Not Available Error; Bit2: SETUP Phase Done
-   */
-uint32_t USB_devINT_isDone(uint32_t ep, BOOL in);
-
-/**
- * @brief Enable OTG Interrupt (Only for DEVICE Mode)
- * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
- * @retval void
-   */
-void USB_INT_enOTG(BOOL en);
-
-/**
- * @brief OTG Interrupt Asserted
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
-   */
-BOOL USB_INT_isOTG(void);
-
-/**
- * @brief OTG Function Interrupt Asserted
-   * @param[in] otg OTG Function Interrupt to check, A value of @ref USB_INT_OTG defined
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
-   */
-BOOL USB_INT_isOTGon(USB_INT_OTG otg);
-
-/**
- * @brief Clear OTG Function Interrupt Flag
-   * @param[in] otg OTG Function Interrupt to clear, A value of @ref USB_INT_OTG defined
- * @retval void
-   */
-void USB_INT_clrOTGon(USB_INT_OTG otg);
-
-/**
- * @brief Enable @ref USB_INT_GP Interrupt
- * @para in name Interrupt to operate, A value of @ref USB_INT_GP defined
- * @para in en TRUE: Enable Interrupt; FALSE: Mask the Interrupt
- * @retval void
- */
-void USB_INT_enGP(USB_INT_GP name, BOOL en);
-
-/**
- * @brief @ref USB_INT_GP Interrupt Asserted
- * @para in name Interrupt to check, A value of @ref USB_INT_GP defined
- * @retval BOOL TRUE: Interrupt Asserted; FALSE: Interrupt is NOT asserted
-   */
-BOOL USB_INT_isGP(USB_INT_GP name);
-
-/**
- * @brief Clear @ref USB_INT_GP Interrupt Flag
- * @para in name Interrupt to clear, A value of @ref USB_INT_GP defined
- * @retval void
-   */
-void USB_INT_clrGP(USB_INT_GP name);
-
-/**
- * @brief Enable OTG Function
-   * @param[in] ctl OTG Function to operate, A value of @ref USB_OTG_CTL defined
-   * @param[in] val TRUE: Enable the function; FALSE: Disable the function
- * @retval BOOL The old value before it configure
-   */
-BOOL USB_otgControl(USB_OTG_CTL ctl, BOOL val);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_USB_H */

bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h

@@ -1,110 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_wdg.h
-	*
-	* @brief    CMEM7 watchdog header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#ifndef __CMEM7_WDG_H
-#define __CMEM7_WDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7.h"
-#include "cmem7_conf.h"
-
-/** @defgroup WDG_INT
-  * @{
-  */
-#define WDG_INT_QUARTER                 0
-#define WDG_INT_HALF                    1
-#define IS_WDG_INT(INT)                 (((INT) == WDG_INT_QUARTER) || \
-                                         ((INT) == WDG_INT_HALF))
-/**
-  * @}
-  */
-
-/** @defgroup WDG_TRIGGER_MODE
-  * @{
-  */
-#define WDG_TRIGGER_MODE_EDGE           0
-#define WDG_TRIGGER_MODE_LEVEL          1
-#define IS_WDG_TRIGGER_MODE(TRI)        (((TRI) == WDG_TRIGGER_MODE_EDGE) || \
-                                         ((TRI) == WDG_TRIGGER_MODE_LEVEL))
-/**
-  * @}
-  */
-
-/**
-  * @brief  Deinitializes the Watchdog peripheral registers to their default reset values.
-	* @param[in] None
-  * @retval None
-	*/ 
-void WDG_DeInit(void);
-
-/**
-  * @brief  Watchdog initialization
-  * @note   This function should be called at first before any other interfaces.
-	* @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE
-	* @param[in] ResetMillSecond MillSeconds lasts before global reset
-  * @retval None
-	*/ 
-void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond);
-
-/**
-  * @brief  Enable or disable watchdog interrupt. 
-	* @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT
-	* @param[in] Enable The bit indicates if the specific interrupt are enable or not
-  * @retval None
-	*/ 
-void WDG_ITConfig(uint8_t Int, BOOL Enable);
-
-/**
-  * @brief  Check the specific interrupt are set or not 
-	* @param	None
-  * @retval BOOL The bit indicates if the specific interrupt are set or not
-	*/
-BOOL WDG_GetITStatus(void);
-
-/**
-  * @brief  Clear the specific interrupt
-	* @param	None
-  * @retval None
-	*/
-void WDG_ClearITPendingBit(void);
-
-/**
-  * @brief  Enable or disable watchdog. 
-	* @param[in] Enable The bit indicates if watchdog is enable or not
-  * @retval None
-	*/ 
-void WDG_Cmd(BOOL Enable);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CMEM7_WDG_H */
-

bsp/CME_M7/StdPeriph_Driver/inc/system_cmem7.h

@@ -1,47 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     system_cmem7.h
-	*
-	* @brief    CMEM7 system initial header file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note      
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#ifndef __SYSTEM_CMEM7_H
-#define __SYSTEM_CMEM7_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @note   This function should be used only after reset.
-	* @param  None
-  * @retval None
-	*/  
-void SystemInit(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_CMEM7_H */
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_adc.c

@@ -1,309 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_adc.c
-	*
-	* @brief    CMEM7 ADC source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_adc.h"
-#include "cmem7.h"
-
-#define ADC_SYSTEM_MODE_IDLE       0
-
-static BOOL adc_IsMultiChannel(uint32_t channel) {
-	uint32_t i = 0;
-  
-	for (i = 0; channel != 0; i++) {
-    channel &= (channel - 1);
-	}
-	
-	return ((i > 1) ? TRUE : FALSE);
-}
-
-static uint8_t adc_GetChannel(uint32_t channel) {
-	uint32_t i = 0;
-  
-	for (i = 0; channel > 1; i++) {
-    channel >>= 1;
-	}
-	
-	return i;
-}
-
-static void adc_Reset(uint8_t adc, BOOL enable) {
-	if (adc == ADC_PERIPH_1) {
-		ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = TRUE;
-		ADC->POWERDOWN_RESET_b.RESET_ADC1 = TRUE;
-		udelay(8000);
-		if (enable) {
-			ADC->POWERDOWN_RESET_b.POWERDOWN_ADC1 = FALSE;
-			ADC->POWERDOWN_RESET_b.RESET_ADC1 = FALSE;
-			udelay(8000);
-		}
-	} else {
-		ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = TRUE;
-		ADC->POWERDOWN_RESET_b.RESET_ADC2 = TRUE;
-		udelay(8000);
-		if (enable) {
-			ADC->POWERDOWN_RESET_b.POWERDOWN_ADC2 = FALSE;
-			ADC->POWERDOWN_RESET_b.RESET_ADC2 = FALSE;
-			udelay(8000);
-		}
-	}
-}
-
-void ADC_Init(ADC_InitTypeDef* init) {
-	assert_param(init);
-	assert_param(IS_ADC_PHASE_CTRL(init->ADC_PhaseCtrl));
-	assert_param(IS_ADC_VSEN(init->ADC_VsenSelection));
-	
-	SOFT_RESET->SOFTRST_b.ADC_n = 0;
-	SOFT_RESET->SOFTRST_b.ADC_n = 1;
-	
-	ADC->CFG0_b.PHASE_CTRL = init->ADC_PhaseCtrl;
-	ADC->CFG0_b.VSEN = init->ADC_VsenSelection;
-}
-
-void ADC_Enable(uint8_t adc, BOOL enable) {
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	
-	adc_Reset(adc, enable);
-}
-
-void ADC_EnableInt(uint32_t Int, BOOL enable) {
-	assert_param(IS_ADC_INT(Int));
-	
-	if (enable) {
-	  ADC->INT_MASK &= ~Int;
-	} else {
-		ADC->INT_MASK |= Int;
-	}
-}
-
-BOOL ADC_GetIntStatus(uint32_t Int) {
-	assert_param(IS_ADC_INT(Int));
-	
-	if (0 != (ADC->INT_STATUS & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-
-void ADC_ClearInt(uint32_t Int) {
-	assert_param(IS_ADC_INT(Int));
-	
-	ADC->INT_STATUS = Int;
-}
-
-BOOL ADC_StartConversion(uint8_t adc, uint8_t convMode, uint32_t channel) {
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	assert_param(IS_ADC_CONVERSION(convMode));
-	
-	if (adc == ADC_PERIPH_1) {
-		assert_param(IS_ADC1_CHANNEL(channel));
-		if (ADC->BUSY_b.ADC1_BUSY) {
-			return FALSE;
-		}
-		
-		if (adc_IsMultiChannel(channel)) {
-			ADC->CFG_ADC1_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
-			ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
-			ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 
-				(convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
-		} else {
-			ADC->CFG_ADC1_b.SYSTEM_MODE = convMode;
-				
-			if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
-				ADC->CFG_ADC1_b.CHANNEL_SEL = adc_GetChannel(channel);
-			} else {
-				ADC->CFG_ADC1_b.MULTI_CHANNEL_BIT = channel;
-				ADC->CFG_ADC1_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
-			}				
-		}
-				
-		ADC->ADC1_START_b.EN = TRUE;
-	} else {
-		assert_param(IS_ADC2_CHANNEL(channel));
-		if (ADC->BUSY_b.ADC2_BUSY) {
-			return FALSE;
-		}		
-		
-		if (adc_IsMultiChannel(channel)) {
-			ADC->CFG_ADC2_b.SYSTEM_MODE = ADC_SYSTEM_MODE_SINGLE_CONV;
-			ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
-			ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 
-				(convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) ? 1 : 0;
-		} else {
-			ADC->CFG_ADC2_b.SYSTEM_MODE = convMode;
-				
-			if (convMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV) {
-				ADC->CFG_ADC2_b.CHANNEL_SEL = adc_GetChannel(channel);
-			} else {
-				ADC->CFG_ADC2_b.MULTI_CHANNEL_BIT = channel;
-				ADC->CFG_ADC2_b.MULTI_CHANNEL_CONTINUE_SCAN = 0;
-			}				
-		}
-				
-		ADC->ADC2_START_b.EN = TRUE;
-	}
-	
-	return TRUE;
-}
-
-BOOL ADC_StartCalibration(uint8_t adc, uint8_t calibration) {
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	assert_param(IS_ADC_CALIBRATION(calibration));
-	
-	if (adc == ADC_PERIPH_1) {
-		if (ADC->BUSY_b.ADC1_BUSY) {
-			return FALSE;
-		}
-		
-		ADC->CFG_ADC1_b.SYSTEM_MODE = calibration;
-		ADC->ADC1_START_b.EN = TRUE;
-	} else {
-		if (ADC->BUSY_b.ADC2_BUSY) {
-			return FALSE;
-		}
-
-		ADC->CFG_ADC2_b.SYSTEM_MODE = calibration;
-		ADC->ADC2_START_b.EN = TRUE;
-	}
-	
-	return TRUE;	
-}
-
-void ADC_Stop(uint8_t adc) {
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	
-	if (adc == ADC_PERIPH_1) {
-		if (IS_ADC_CONVERSION(ADC->CFG_ADC1_b.SYSTEM_MODE)) {
-			ADC->ADC1_STOP_b.EN = TRUE;
-		}
-		while (ADC->BUSY_b.ADC1_BUSY) ;
-		
-		ADC->ADC1_FIFO_CLEAR_b.CLEAR = TRUE;
-		//udelay(1000);
-		ADC->ADC1_FIFO_CLEAR_b.CLEAR = FALSE;
-	} else {
-		if (IS_ADC_CONVERSION(ADC->CFG_ADC2_b.SYSTEM_MODE)) {
-			ADC->ADC2_STOP_b.EN = TRUE;
-		}
-		while (ADC->BUSY_b.ADC2_BUSY) ;
-			
-		ADC->ADC2_FIFO_CLEAR_b.CLEAR = TRUE;
-		//udelay(1000);
-		ADC->ADC2_FIFO_CLEAR_b.CLEAR = FALSE;
-	}	
-}
-
-BOOL ADC_IsBusy(uint8_t adc) {
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	
-	if (adc == ADC_PERIPH_1) {
-		if (ADC->BUSY_b.ADC1_BUSY) {
-			return TRUE;
-		}
-	} else {
-		if (ADC->BUSY_b.ADC2_BUSY) {
-			return TRUE;
-		}
-	}
-	
-	return FALSE;
-}
-
-/* return value is actual read data size */
-uint8_t ADC_Read(uint8_t adc, uint8_t size, ADC_Data* data) {
-	uint8_t count = 0;
-	uint8_t sysMode;
-	uint32_t tmp = 0;
-	assert_param(IS_ADC_ALL_PERIPH(adc));
-	assert_param(data);
-	
-	if (adc == ADC_PERIPH_1) {
-		sysMode = ADC->CFG_ADC1_b.SYSTEM_MODE;
-	} else {
-		sysMode = ADC->CFG_ADC2_b.SYSTEM_MODE;
-	}
-	
-	if ((sysMode == ADC_SYSTEM_MODE_SINGLE_CONV) ||
-		(sysMode == ADC_SYSTEM_MODE_CONTINUOUS_CONV)) {
-		while (count < size) {
-			if (adc == ADC_PERIPH_1) {
-				if (ADC->STATUS_b.ADC1_READ_EMPTY) {
-					break;
-				}
-				
-				tmp = ADC->ADC1_FIFO_READ;
-				(data + count)->channel = 1 << ((tmp&0xf000) >> 12);
-				(data + count++)->data = (tmp & 0xfff);
-			} else {
-				if (ADC->STATUS_b.ADC2_READ_EMPTY) {
-					break;
-				}
-				tmp = ADC->ADC2_FIFO_READ;
-				(data + count)->channel = 1 << ((tmp&0xf000) >> 12);
-				(data + count++)->data = (tmp & 0xfff);
-			}
-		}
-	} else if (sysMode == ADC_CALIBRATION_OFFSET) {
-		if (adc == ADC_PERIPH_1) {
-			if (!ADC->BUSY_b.ADC1_BUSY) {
-				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC1_OUT_OFFSET_CALIBRATION;
-		  }	
-		} else {
-			if (!ADC->BUSY_b.ADC2_BUSY) {
-				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC2_OUT_OFFSET_CALIBRATION;
-		  }
-		}
-	} else if (sysMode == ADC_CALIBRATION_NEGTIVE_GAIN) {	
-		if (adc == ADC_PERIPH_1) {
-			if (!ADC->BUSY_b.ADC1_BUSY) {
-				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC1_OUT_NEGTIVE_GAIN_CALIBRATION;
-			}	
-		} else {
-			if (!ADC->BUSY_b.ADC2_BUSY) {
-			  (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC2_OUT_NEGTIVE_GAIN_CALIBRATION;
-		  }
-		}
-	} else {
-		if (adc == ADC_PERIPH_1) {
-			if (!ADC->BUSY_b.ADC1_BUSY) {
-				(data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC1_OUT_POSITIVE_GAIN_CALIBRATION;
-			}	
-		} else {
-			if (!ADC->BUSY_b.ADC2_BUSY) {
-			  (data + count)->channel = ADC_CHANNEL_CALIBRATION;
-				(data + count++)->data = ADC->ADC2_OUT_POSITIVE_GAIN_CALIBRATION;
-		  }
-		}
-	}
-	
-	return count;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_aes.c

@@ -1,53 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_aes.c
-	*
-	* @brief    CMEM7 AES source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_aes.h"
-
-BOOL AES_Decrypt(const void *src, void *dst, uint32_t len)
-{
-	uint32_t *po = dst;
-	const uint32_t *pi = src;
-
-	if (len & 0xF)
-		return FALSE;
-
-	AES->FIFO_CLEAR = 1;
-	AES->FIFO_CLEAR = 0;
-	GLOBAL_CTRL->AES_BURST_TYPE = 0x1;						// Cannot be 0
-	while (len > 0) {
-		while (0 == GLOBAL_CTRL->AES_STATUS_b.IDLE);		// 0x41007010
-		udelay(2);
-		GLOBAL_CTRL->AES_TARGET_ADDR = (uint32_t)po;		// 0x41800000;
-		po += 4;
-		len -= 4 * sizeof(uint32_t);
-		while (0 == GLOBAL_CTRL->AES_STATUS_b.RD_EMPTY);	// 0x41007010
-		AES->FIFO = *pi++;
-		AES->FIFO = *pi++;
-		AES->FIFO = *pi++;
-		AES->FIFO = *pi++;
-	}
-	return TRUE;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_can.c

@@ -1,386 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_can.c
-	*
-	* @brief    CMEM7 CAN source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_can.h"
-
-typedef struct {
-  union {
-    __IO uint8_t   FI;                        /*!< Transmit Frame Information if writting or Receive Frame Information
-                                                   if reading, ACR[0] if reset mode                                      */
-                                                    
-    struct {
-      __IO uint8_t   DLC        :  4;         /*!< byte number in the data                                               */
-           uint8_t              :  2;
-      __IO uint8_t   RTR        :  1;         /*!< 1 indicates a remote frame; 0 indicates a data frame                  */
-      __IO uint8_t   FF         :  1;         /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame
-                                                   Format (SFF)                                                          */
-    } FI_b;                                   /*!< BitSize                                                               */
-  } U;
-} CAN_FRAME_INFO;
-
-typedef struct {
-	union {
-    uint16_t  ID;                             /*!< ID                                  */
-    
-    struct {
-      uint16_t  ID28_21   :  8;               /*!< ID28 to ID21                        */
-      uint16_t            :  4;               
-      uint16_t  RTR       :  1;               /*!< if remote frame                     */
-      uint16_t  ID20_18   :  3;               /*!< ID20 to ID18                        */
-    } ID_b;                                   /*!< BitSize                             */
-  } U;
-} CAN_STANDARD_ID;
-
-typedef struct {
-  union {
-    uint32_t  ID;                             /*!< ID                                  */
-    
-    struct {
-      uint32_t  ID28_21   :  8;               /*!< ID28 to ID21                        */
-      uint32_t  ID20_13   :  8;               /*!< ID20 to ID13                        */
-			uint32_t  ID12_5    :  8;               /*!< ID12 to ID5                         */
-			uint32_t            :  2;
-      uint32_t  RTR       :  1;               /*!< if remote frame                     */
-      uint32_t  ID4_0     :  5;               /*!< ID4 to ID0                          */
-    } ID_b;                                   /*!< BitSize                             */
-  } U;
-} CAN_EXTENDED_ID;
-
-#define CAN_MODE_NORMAL            0x00000000
-#define CAN_MODE_RESET             0x00000001
-#define CAN_MODE_LISTEN_ONLY       0x00000002
-#define CAN_MODE_SELF_TEST         0x00000004
-#define CAN_MODE_SINGLE_FILTER     0x00000008
-#define CAN_MODE_SLEEP             0x00000010
-
-#define CAN_OCR_NORMAL             0x02
-#define CAN_OCR_CLOCK              0x03
-
-static BOOL can_SetFilter(CAN0_Type* CANx, CAN_FILTER *f1, CAN_FILTER *f2) {
-	if (!f1) {
-		return FALSE;
-	}
-	
-	if (!IS_CAN_FLT_TYPE(f1->type)) {
-		return FALSE;
-	}
-	
-	if(IS_CAN_FLT_DUAL(f1->type)) {
-		if (!f2 || IS_CAN_FLT_SINGLE(f2->type)) {
-			return FALSE;
-		}
-	}
-	
-	if (f1->type == CAN_FLT_STANDARD_SINGLE) {
-	  CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
-		CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
-		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
-		CANx->DI1_OR_ACR2 = f1->ACCEPT.sf.data1;
-		CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data2;
-		
-		CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
-		CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
-		CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
-		CANx->DI5_OR_AMR2 = f1->MASK.sf.data1;
-		CANx->DI6_OR_AMR3 = f1->MASK.sf.data2;
-	} else if (f1->type == CAN_FLT_STANDARD_DUAL) {
-	  CANx->FI_OR_ACR0 = f1->ACCEPT.sf.ID28_18 >> 3;
-		CANx->DI0_OR_ACR1 = (f1->ACCEPT.sf.ID28_18 & 0x07) << 5;
-		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.RTR << 4;
-		CANx->DI0_OR_ACR1 |= f1->ACCEPT.sf.data1 >> 4;
-		CANx->DI2_OR_ACR3 = f1->ACCEPT.sf.data1 & 0x0F;
-		
-		CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3;
-		CANx->DI4_OR_AMR1 = (f1->MASK.sf.ID28_18 & 0x07) << 5;
-		CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4;
-		CANx->DI4_OR_AMR1 = f1->MASK.sf.data1 >> 4;
-		CANx->DI6_OR_AMR3 = f1->MASK.sf.data1 & 0x0F;
-	} else if (f1->type == CAN_FLT_EXTENDED_SINGLE) {
-	  CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
-		CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
-		CANx->DI1_OR_ACR2 = f1->ACCEPT.ef.ID12_0 >> 5;
-		CANx->DI2_OR_ACR3 = (f1->ACCEPT.ef.ID12_0 & 0x1F) << 3;
-		CANx->DI2_OR_ACR3 |= f1->ACCEPT.ef.RTR << 2;
-		
-		CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
-		CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
-		CANx->DI5_OR_AMR2 = f1->MASK.ef.ID12_0 >> 5;
-		CANx->DI6_OR_AMR3 = (f1->MASK.ef.ID12_0 & 0x1F) << 3;
-		CANx->DI6_OR_AMR3 |= f1->MASK.ef.RTR << 2;
-	} else {
-	  CANx->FI_OR_ACR0 = f1->ACCEPT.ef.ID28_13 >> 8;
-		CANx->DI0_OR_ACR1 = f1->ACCEPT.ef.ID28_13 & 0xFF;
-		
-		CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8;
-		CANx->DI4_OR_AMR1 = f1->MASK.ef.ID28_13 & 0xFF;
-	}
-	
-	if (IS_CAN_FLT_DUAL(f1->type)) {
-		if (f2->type == CAN_FLT_STANDARD_DUAL) {
-			CANx->DI1_OR_ACR2 = f2->ACCEPT.sf.ID28_18 >> 3;
-			CANx->DI2_OR_ACR3 |= (f2->ACCEPT.sf.ID28_18 & 0x07) << 5;
-			CANx->DI2_OR_ACR3 |= f2->ACCEPT.sf.RTR << 4;
-			
-			CANx->DI5_OR_AMR2 = f2->MASK.sf.ID28_18 >> 3;
-			CANx->DI6_OR_AMR3 |= (f2->MASK.sf.ID28_18 & 0x07) << 5;
-			CANx->DI6_OR_AMR3 |= f2->MASK.sf.RTR << 4;
-		} else {
-			CANx->DI1_OR_ACR2 = f2->ACCEPT.ef.ID28_13 >> 8;
-			CANx->DI2_OR_ACR3 = f2->ACCEPT.ef.ID28_13 & 0xFF;
-			
-			CANx->DI5_OR_AMR2 = f2->MASK.ef.ID28_13 >> 8;
-			CANx->DI6_OR_AMR3 = f2->MASK.ef.ID28_13 & 0xFF;
-		}
-	}
-	
-	if (IS_CAN_FLT_SINGLE(f1->type)) {
-		CANx->MODE_b.AFM = 1;
-	} else {
-	  CANx->MODE_b.AFM = 0;
-	}
-	
-	return TRUE;
-}
-
-BOOL CAN_Init(CAN0_Type* CANx, CAN_InitTypeDef* Init, 
-  CAN_FILTER *f1, CAN_FILTER *f2) {
-	assert_param(IS_CAN_ALL_PERIPH(CANx));
-	assert_param(Init);
-	assert_param(IS_CAN_CDR_DIV(Init->CAN_ClockDiv));
-		
-	/* Quit to sleep mode in operation mode */
-	if (CANx->MODE_b.SM) {
-		CANx->MODE_b.RM = FALSE;
-		CANx->MODE_b.SM = FALSE;
-	}
-	
-	/* switch to reset mode to set parameter */
-	CANx->MODE_b.RM = TRUE;
-
-	/* disable all interrupts and clear except receive interrupt */
-	{
-		uint8_t tmp;
-		CANx->INT_EN &= ~CAN_INT_All;
-		tmp = CANx->INT;
-		tmp = tmp;
-	}
-	
-	CANx->MODE_b.LOM = (Init->CAN_TxEn) ? FALSE : TRUE;
-	
-	CANx->MODE_b.STM = Init->CAN_Loopback;
-		
-	CANx->CDR_b.OFF = FALSE;
-	CANx->CDR_b.DIVIDER = Init->CAN_ClockDiv;
-	
-	CANx->BTR0_b.BRP = Init->CAN_Prescaler;
-	CANx->BTR0_b.SJW = Init->CAN_SJW;
-	
-	CANx->BTR1_b.TSEG1 = Init->CAN_TSEG1;
-	CANx->BTR1_b.TSEG2 = Init->CAN_TSEG2;
-	CANx->BTR1_b.SAM = !Init->CAN_HighSpeed;
-	
-	CANx->OCR_b.MODE = CAN_OCR_CLOCK;
-	
-  if (!can_SetFilter(CANx, f1, f2)) {
-		return FALSE;
-	}
-	
-	/* switch to operation mode */
-	CANx->MODE_b.RM = FALSE;
-
-	return TRUE;
-}
-
-void CAN_SetSleepMode(CAN0_Type* CANx, BOOL enable) {
-	assert_param(IS_CAN_ALL_PERIPH(CANx));
-	
-	/* switch to operation mode */
-	CANx->MODE_b.RM = FALSE;
-	
-	CANx->MODE_b.SM = enable;
-}
-
-void CAN_EnableInt(CAN0_Type* CANx, uint32_t Int, BOOL enable) {
-  assert_param(IS_CAN_ALL_PERIPH(CANx));
-	assert_param(IS_CAN_INT(Int));
-	
-	if (enable) {
-		CANx->INT_EN |= CAN_INT_All;
-	} else {
-		CANx->INT_EN &= ~CAN_INT_All;
-	}
-}
-
-uint8_t CAN_GetIntStatus(CAN0_Type* CANx) {
-	assert_param(IS_CAN_ALL_PERIPH(CANx));
-	
-	return CANx->INT;
-}
-
-BOOL CAN_Transmit(CAN0_Type* CANx, CAN_Frame* frame) {
-	assert_param(IS_CAN_ALL_PERIPH(CANx));
-	
-	if (!frame) {
-		return FALSE;
-	}
-	
-	if (CANx->MODE_b.LOM) {
-		return FALSE;
-	}
-	
-	if (CANx->MODE_b.SM) {
-		CANx->MODE_b.RM = FALSE;
-		CANx->MODE_b.SM = FALSE;
-	}
-	
-	{
-		CAN_FRAME_INFO fi;
-		
-		fi.U.FI_b.FF = !frame->SFF;
-		fi.U.FI_b.RTR = frame->RTR;
-		fi.U.FI_b.DLC = frame->DLC;
-
-		CANx->FI_OR_ACR0 = fi.U.FI;
-  }
-	
-  if (frame->SFF) {
-		CAN_STANDARD_ID id;
-		
-		id.U.ID_b.ID28_21 = frame->Id >> 3;
-		id.U.ID_b.RTR = frame->RTR;
-		id.U.ID_b.ID20_18 = frame->Id & 0x07;
-		
-		CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
-		CANx->DI1_OR_ACR2 = id.U.ID >> 8;
-		
-		CANx->DI2_OR_ACR3 = frame->Data[0];
-		CANx->DI3_OR_AMR0 = frame->Data[1];
-		CANx->DI4_OR_AMR1 = frame->Data[2];
-		CANx->DI5_OR_AMR2 = frame->Data[3];
-		CANx->DI6_OR_AMR3 = frame->Data[4];
-		CANx->DI7 = frame->Data[5];
-		CANx->DI8 = frame->Data[6];
-		CANx->DI9 = frame->Data[7];
-	} else {
-		CAN_EXTENDED_ID id;
-		
-		id.U.ID_b.ID28_21 = frame->Id >> 21;
-		id.U.ID_b.ID20_13 = (frame->Id >> 13) & 0xFF;
-		id.U.ID_b.ID12_5 = (frame->Id >> 5) & 0xFF;
-		id.U.ID_b.RTR = frame->RTR;
-		id.U.ID_b.ID4_0 = frame->Id & 0x1F;
-		
-		CANx->DI0_OR_ACR1 = id.U.ID & 0xFF;
-		CANx->DI1_OR_ACR2 = (id.U.ID >> 8) & 0xFF;
-		CANx->DI2_OR_ACR3 = (id.U.ID >> 16) & 0xFF;
-		CANx->DI3_OR_AMR0 = (id.U.ID >> 24) & 0xFF;
-		
-		CANx->DI4_OR_AMR1 = frame->Data[0];
-		CANx->DI5_OR_AMR2 = frame->Data[1];
-		CANx->DI6_OR_AMR3 = frame->Data[2];
-		CANx->DI7 = frame->Data[3];
-		CANx->DI8 = frame->Data[4];
-		CANx->DI9 = frame->Data[5];
-		CANx->DI10 = frame->Data[6];
-		CANx->DI11 = frame->Data[7];
-	}
-
-  if (CANx->MODE_b.STM) {
-	  CANx->CMD_b.SSR = TRUE;
-	} else {
-		CANx->CMD_b.TR = TRUE;
-	}
-
-  return TRUE;
-}
-
-BOOL CAN_Receive(CAN0_Type* CANx, CAN_Frame* frame) {
-	assert_param(IS_CAN_ALL_PERIPH(CANx));
-	
-	if (!frame) {
-		return FALSE;
-	}
-	
-	if (CANx->MODE_b.SM) {
-		CANx->MODE_b.RM = FALSE;
-		CANx->MODE_b.SM = FALSE;
-	}
-	
-	{
-		CAN_FRAME_INFO fi;
-		
-		fi.U.FI = CANx->FI_OR_ACR0;
-		
-		frame->SFF = fi.U.FI_b.FF ? FALSE : TRUE;
-		frame->RTR = fi.U.FI_b.RTR ? TRUE : FALSE;
-		frame->DLC = fi.U.FI_b.DLC;
-  }
-	
-  if (frame->SFF) {
-		CAN_STANDARD_ID id;
-		
-		id.U.ID = CANx->DI0_OR_ACR1;
-		id.U.ID |= CANx->DI1_OR_ACR2 << 8;
-		
-		frame->Id = id.U.ID_b.ID28_21 << 3;
-		frame->Id |= id.U.ID_b.ID20_18;
-		
-		frame->Data[0] = CANx->DI2_OR_ACR3;
-		frame->Data[1] = CANx->DI3_OR_AMR0;
-		frame->Data[2] = CANx->DI4_OR_AMR1;
-		frame->Data[3] = CANx->DI5_OR_AMR2;
-		frame->Data[4] = CANx->DI6_OR_AMR3;
-		frame->Data[5] = CANx->DI7;
-		frame->Data[6] = CANx->DI8;
-		frame->Data[7] = CANx->DI9;
-	} else {
-		CAN_EXTENDED_ID id;
-		
-		id.U.ID = CANx->DI0_OR_ACR1;
-		id.U.ID |= CANx->DI1_OR_ACR2 << 8;
-		id.U.ID |= CANx->DI2_OR_ACR3 << 16;
-		id.U.ID |= CANx->DI3_OR_AMR0 << 24;
-		
-    frame->Id = id.U.ID_b.ID28_21 << 21;
-		frame->Id |= id.U.ID_b.ID20_13 << 13;
-		frame->Id |= id.U.ID_b.ID12_5 << 5;
-		frame->Id |= id.U.ID_b.ID4_0;
-		
-		frame->Data[0] = CANx->DI4_OR_AMR1;
-		frame->Data[1] = CANx->DI5_OR_AMR2;
-		frame->Data[2] = CANx->DI6_OR_AMR3;
-		frame->Data[3] = CANx->DI7;
-		frame->Data[4] = CANx->DI8;
-		frame->Data[5] = CANx->DI9;
-		frame->Data[6] = CANx->DI10;
-		frame->Data[7] = CANx->DI11;
-	}
-
-  CANx->CMD_b.RRB = TRUE;
-
-  return TRUE;	
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_ddr.c

@@ -1,523 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_ddr.c
-	*
-	* @brief    CMEM7 DDR source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_ddr.h"
-
-#define MAX(a, b)	((a >= b) ? (a) : (b))
-#define CAL_DDR3_CL(cl)   ((cl>11)?(((cl-12)<<MR_CL_OFFSET)|0x4):((cl-4)<<MR_CL_OFFSET))
-
-#define CHIP_MIN_CAPACITY  32
-#define CHIP_CAPACITY_32MB  CHIP_MIN_CAPACITY
-#define CHIP_CAPACITY_64MB (CHIP_CAPACITY_32MB*2)
-#define CHIP_CAPACITY_128MB (CHIP_CAPACITY_64MB*2)
-#define CHIP_CAPACITY_256MB (CHIP_CAPACITY_128MB*2)
-#define CHIP_CAPACITY_512MB (CHIP_CAPACITY_256MB*2)
-#define CHIP_CAPACITY_1024MB (CHIP_CAPACITY_512MB*2)
-
-/** @defgroup DDR time
-  * @{
-  */
-  #define POWER_UP_NOP		200*1000        /*ns*//*JEDEC Standard No. 79-2E   page 17   */
-  #define PRE_ALL_NOP			400        /*ns*/
-  #define POWER_UP_MIN_CK    200
-  #define DDR2_TMRD                2            /*JEDEC Standard No. 79-2E   page 80   */
-  #define DDR3_TMRD                4            /*JEDEC Standard No. 79-2E   page 80   */
-  #define DDR3_TMOD_CK                12            /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define DDR3_TMOD                15          /*ns*/  /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define DDR3_TZQINIT_CK                512         /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define DDR3_TZQINIT                640   /*ns*/      /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define DDR3_TDLLK_CK                512         /*JEDEC Standard No. 79-3E   page 171  table 68   */
-  #define RSTH_NOP		500*1000        /*ns*//*JEDEC Standard No. 79-3E   page 20   */
-  #define DDR_TREF      7800 /*ns*/
-  /**
-  * @}
-  */
-#ifndef NULL
-#define	NULL	0
-#endif
-
-/** @defgroup DDRC_SW_PROC_CMD
-  * @{
-  */
-#define SW_CMD_NO_PARM        0
-#define SW_CMD_DES			0x0       /*des 5'b00000     [31:29]=3'b000           [28:0] DES time cke hold*/	
-#define SW_CMD_NOP			0x20000000        /*nop 5'b00100     [31:29]=3'b001           [28:0] NOP time cke hold*/		
-#define SW_CMD_DESCKE         0x40000000	   /*descke 5'b01000     [31:29]=3'b010           [28:0] DES time change cke high*/			
-#define SW_CMD_NOPCKE         0x60000000	 /*nopcke 5'b01100     [31:29]=3'b011           [28:0] NOP time change cke high*/	
-#define SW_CMD_PREA         	0x80000000	 /*nopcke 5'b10000     [31:27]=5'b10000           */	
-
-#define SW_CMD_MR         	0x88000000		/*JEDEC Standard No. 79-2E   page 19   */
-#define SW_CMD_EMR1         	0x88010000	/*JEDEC Standard No. 79-2E   page 19   */
-#define SW_CMD_EMR2         	0x88020000
-#define SW_CMD_EMR3         	0x88030000
-#define SW_CMD_EMR1_TEST  0x88010004	
-#define SW_CMD_REF         	0x90000000  /*REF 5'b10010     [31:27]=5'b10010       */	
-
-#define SW_CMD_RSTH        	0xb0000000  /*RSTH 5'b10110    [31:27]=5'b10110       */	
-#define SW_CMD_ZQCL       	0xb8000000  /*ZQCL 5'b10111    [31:27]=5'b10111       */	
-
-#define SW_CMD_DLL_EN         0x880103C4
-#define SW_CMD_DLL_RST        0x88000953
-/**
-  * @}
-  */
-/** @defgroup DDR2  mode register 
-  * @{
-  */
- /*JEDEC Standard    */
-#define MR_BURST_LEN_4          0x2
-#define MR_BURST_LEN_8          0x3
-#define MR_BT_SEQ                    0x0
-#define MR_BT_INT                    0x08
-#define MR_CL_OFFSET             4 
-#define MR_TM_NORMAL            0
-#define MR_TM_TEST                 0x80
-#define MR_DLL_NO                   0
-#define MR_DLL_YES                 0x100
-#define MR_WR_OFFSET           9
-#define MR_PPD_FAST              0x1000
-#define MR2_CWL_OFFSET        3
-#define MR1_RZQ_4                 0x4
-/**
-  * @}
-  */
-const uint8_t DDR2_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
-{
-	{
-		{0x20,0x23,0x28,0x2a,0x30,0x21,0x22,0x29,0x2b,0x31,0xff},/*chip x1*/
-		{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-	},/*bus width x8*/
-
-	{
-		{0xff,0xff,0xff,0xff,0xff,0x25,0x26,0x2d,0x2f,0x33,0xff},/*chip x1*/
-		{0x24,0x27,0x2c,0x2e,0x32,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-	}/*bus width x16*/
-};
-const uint8_t DDR3_MODE[BUS_WIDTH_MAX][CHIP_NUM_MAX][CHIP_TYPE_MAX]=
-{
-	{
-		{0xff,0x00,0x01,0x02,0x03,0xff,0x04,0x05,0x06,0x07,0x10},/*chip x1*/
-		{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-	},/*bus width x8*/
-
-	{
-		{0xff,0xff,0xff,0xff,0xff,0xff,0x0c,0x0d,0x0e,0x0f,0x11},/*chip x1*/
-		{0xff,0x08,0x09,0x0a,0x0b,0xff,0xff,0xff,0xff,0xff,0xff}/*chip x2*/
-	}/*bus width x16*/
-};
-const DDR2MEM DDR2PREDEF[] = {
-	{
-// #define DDR2_400C			4	// sg5E //DDR2-400C CL=4, tCK=5000 ps (dev-brd using)
-		/*tCK*/ 5000,
-		/*tCL*/ 6,//4,
-		/*RCD*/4, /*RP*/4, /*RC*/13, /*RAS*/9, /*WR*/3, /*RRD*/2, /*WTR*/11, /*RTP*/4,
-		/*FAW*/10,
-	},
-	 
-	{
-// #define DDR2_800D			0	// sg25E //DDR2-800D CL=5, tCK=2500 ps
-		/*tCK*/ 2500,
-		/*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/24, //from sim model
-		/*RAS*/18, /*WR*/6, /*RRD*/4, /*WTR*/11, /*RTP*/5,
-		/*FAW*/30, //from sim model
-	}, {
-// #define DDR2_667C			1	// sg3E //DDR2-667C CL=4, tCK=3000 ps
-		/*tCK*/ 3000,
-		/*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/19, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/10, /*RTP*/5,
-		/*FAW*/17,
-	}, {
-// #define DDR2_667D			2	// sg3 //DDR2-667D CL=5, tCK=3000 ps
-		/*tCK*/ 3000,
-		/*tCL*/ 5, /*RCD*/5, /*RP*/5, /*RC*/20, /*RAS*/15, /*WR*/5, /*RRD*/4, /*WTR*/3, /*RTP*/3,
-		/*FAW*/17,
-	}, {
-// #define DDR2_533C			3	// sg37E //DDR2-533C CL=4, tCK=3750 ps
-		/*tCK*/ 3750,
-		/*tCL*/ 4, /*RCD*/4, /*RP*/4, /*RC*/16, /*RAS*/12, /*WR*/4, /*RRD*/3, /*WTR*/9, /*RTP*/4,
-		/*FAW*/14,
-	},
-};
-
-const DDR3MEM DDR3PREDEF[] = {
-	{
-// #define DDR3_400			14	//  Base on DDR3-800D (5-5-5) tCK=5ns
-		/*tCK*/ 2500,
-		/*tCL*//*9*/ 5, /*WCL*/7/*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/8, /*RP*//*9*/5, /*RC*//*33*/10, /*RRD*/ 100,
-		/*FAW*//*30*/10, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-	}  ,
-
-	{
-// #define DDR3_667			15	//  Base on DDR3-800D (5-5-5) tCK=5ns
-		/*tCK*/ 3000,
-		/*tCL*//*9*/ 5, /*WCL*/7 /*cwl should be 5 ,but phy has 2 cycles delay.So,wcl should plus the 2 cycles delay.*/ , /*RCD*//*9*/5, /*RAS*//*24*/30, /*RP*//*9*/5, /*RC*//*33*/60, /*RRD*/16,
-		/*FAW*//*30*/17, /*WR*/5/*10*/, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-	},
-
-	{
-// #define DDR3_2133N			0	// sg093 //DDR3-2133N (14-14-14) tCK=0.938ns
-		/*tCK*/ 938,
-		/*tCL*/ 14, /*WCL*/10, /*RCD*/14, /*RAS*/36, /*RP*/14, /*RC*/50, /*RRD*/7,
-		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-	}, {
-// #define DDR3_2133M			1	// sg093E //DDR3-2133M (13-13-13) tCK=0.938ns
-		/*tCK*/ 938,
-		/*tCL*/ 13, /*WCL*/10, /*RCD*/13, /*RAS*/36, /*RP*/13, /*RC*/49, /*RRD*/7,
-		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-	}, {
-// #define DDR3_2133L			2	// sg093F //DDR3-2133L (12-12-12) tCK=0.938ns
-		/*tCK*/ 938,
-		/*tCL*/ 12, /*WCL*/10, /*RCD*/12, /*RAS*/36, /*RP*/12, /*RC*/48, /*RRD*/7,
-		/*FAW*/38, /*WR*/16, /*RTP*/10, /*ZQCL*/342, /*ZQCS*/86,
-	}, {
-// #define DDR3_1866L			3	// sg107E //DDR3-1866L (12-12-12) tCK=1.07ns
-		/*tCK*/ 1070,
-		/*tCL*/ 12, /*WCL*/9, /*RCD*/12, /*RAS*/32, /*RP*/12, /*RC*/44, /*RRD*/6,
-		/*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
-	}, {
-// #define DDR3_1866K			4	// sg107F //DDR3-1866K (11-11-11) tCK=1.07ns
-		/*tCK*/ 1070,
-		/*tCL*/ 11, /*WCL*/9, /*RCD*/11, /*RAS*/32, /*RP*/11, /*RC*/43, /*RRD*/6,
-		/*FAW*/33, /*WR*/14, /*RTP*/9, /*ZQCL*/300, /*ZQCS*/75,
-	}, {
-// #define DDR3_1600J			5	// sg125E //DDR3-1600J (10-10-10) tCK=1.25ns
-		/*tCK*/ 1250,
-		/*tCL*/ 10, /*WCL*/8, /*RCD*/10, /*RAS*/28, /*RP*/10, /*RC*/38, /*RRD*/6,
-		/*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_1600K			6	// sg125 //DDR3-1600K (11-11-11) tCK=1.25ns
-		/*tCK*/ 1250,
-		/*tCL*/ 11, /*WCL*/8, /*RCD*/11, /*RAS*/28, /*RP*/11, /*RC*/37, /*RRD*/6,
-		/*FAW*/32, /*WR*/12, /*RTP*/8, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_1333H			7	// sg15E //DDR3-1333H (9-9-9) tCK=1.5ns
-		/*tCK*/ 1500,
-		/*tCL*/ 9, /*WCL*/7, /*RCD*/9, /*RAS*/24, /*RP*/9, /*RC*/33, /*RRD*/5,
-		/*FAW*/30, /*WR*/10, /*RTP*/5, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_1333J			8	// sg15 //DDR3-1333J (10-10-10) tCK=1.5ns
-		/*tCK*/ 1500,
-		/*tCL*/ 10, /*WCL*/7, /*RCD*/10, /*RAS*/24, /*RP*/10, /*RC*/34, /*RRD*/5,
-		/*FAW*/30, /*WR*/10, /*RTP*/7, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_1066F			9	// sg187E //DDR3-1066F (7-7-7) tCK=1.875ns
-		/*tCK*/ 1875,
-		/*tCL*/ 7, /*WCL*/6, /*RCD*/7, /*RAS*/20, /*RP*/7, /*RC*/27, /*RRD*/6,
-		/*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_1066G			10	// sg187 //DDR3-1066G (8-8-8) tCK=1.875ns
-		/*tCK*/ 1875,
-		/*tCL*/ 8, /*WCL*/6, /*RCD*/8, /*RAS*/20, /*RP*/8, /*RC*/28, /*RRD*/6,
-		/*FAW*/27, /*WR*/8, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_800D			11	// sg25E //DDR3-800D (5-5-5) tCK=2.5ns
-		/*tCK*/ 2500,
-		/*tCL*/ 5, /*WCL*/5, /*RCD*/5, /*RAS*/15, /*RP*/5, /*RC*/20, /*RRD*/4,
-		/*FAW*/17, /*WR*/5, /*RTP*/3, /*ZQCL*/256, /*ZQCS*/64,
-	}, {
-// #define DDR3_800E			12	// sg25 //DDR3-800E (6-6-6) tCK=2.5ns
-		/*tCK*/ 2500,
-		/*tCL*/ 6, /*WCL*/5, /*RCD*/6, /*RAS*/15, /*RP*/6, /*RC*/21, /*RRD*/4,
-		/*FAW*/20, /*WR*/6, /*RTP*/6, /*ZQCL*/256, /*ZQCS*/64,
-	},
-	{
-	// #define DDR3_266MPW			13	// sg25 //DDR3-800E (5-5-5) tCK=2.5ns
-//		/*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
-//		/*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-// #define DDR3_250MPW			13	// sg25 //DDR3-800E (5-5-5) tCK=2.5ns
-		/*tCK*/ 2500,
-		/*tCL*/ 5, /*WCL*/7, /*RCD*/5, /*RAS*/9/*37.5/4*/, /*RP*/5, /*RC*/13, /*RRD*/4,
-		/*FAW 50/4*/15, /*WR6*/5, /*RTP*/4, /*ZQCL*/256, /*ZQCS*/64,
-
-	},
-};
-uint32_t Get_DDR_Capacity(const MEM_CHIP_INFO *chip_info)
-{
-	uint32_t n=0;
-	uint32_t capacity=0;
-
-	assert_param(chip_info);
-	n=(chip_info->Chip_type<_16Mbx16)?(chip_info->Chip_type):(chip_info->Chip_type-_16Mbx16);
-	capacity=(chip_info->Chip_type<_16Mbx16)?(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Chip_num+1)):(CHIP_MIN_CAPACITY*(1<<n)*(chip_info->Bus_width+1)/(BUS_WIDTH_16+1));
-	return capacity;
-	
-	
-}
-uint32_t Calc_DDR_RFC(const MEM_CHIP_INFO *chip_info)
-{
-	uint32_t capacity=0;
-	uint32_t tRFC=0;
-	assert_param(chip_info);
-
-	
-	capacity=Get_DDR_Capacity(chip_info);
-	if (chip_info->mem_type==MEM_DDR2) {
-	
-		switch(capacity){
-			case CHIP_CAPACITY_32MB:tRFC=75;break;
-			case CHIP_CAPACITY_64MB:tRFC=105;break;
-			case CHIP_CAPACITY_128MB:tRFC=128;break;
-			case CHIP_CAPACITY_256MB:tRFC=195;break;
-			case CHIP_CAPACITY_512MB:tRFC=328;break;
-		}
-	}
-	else{
-		switch(capacity){
-			case CHIP_CAPACITY_64MB:tRFC=90;break;
-			case CHIP_CAPACITY_128MB:tRFC=110;break;
-			case CHIP_CAPACITY_256MB:tRFC=160;break;
-			case CHIP_CAPACITY_512MB:tRFC=300;break;
-			case CHIP_CAPACITY_1024MB:tRFC=350;break;
-		}
-	}
-
-	return tRFC;
-	
-	
-}
-static void DDR_Cmd(const uint32_t cmd ,const uint32_t param)
-{
-		DDRC->CMD =((cmd)|(param));
-	
-}
-static void DDR_Latency(const uint32_t cycle  )
-{
-	DDR_Cmd(SW_CMD_NOP,cycle);
-}
-static void DDR2_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
-{
-	uint32_t period=0;
-	const DDR2MEM *ptr = (const DDR2MEM *)ddr;
-	uint32_t tRFC=0;
-	
-	assert_param(ddr);
-	tRFC=Calc_DDR_RFC(chip_info);
-	period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));	
-	CFG_CTRL->DONE_b.CMD = 0x1;
-
-	DDRC->MODE_b.LANE = 1;
-	DDRC->MODE_b.B16 = 1;
-	DDRC->REF_b.TIME =( DDR_TREF/period);
-	DDRC->RP_b.RPA = 1;
-	DDRC->RFC_b.DI = (tRFC/period);
-	DDRC->PHUNG_b.MODE = 1;
-	DDRC->RD_SEL_b.PHY_SEL = 5;
-
-	DDRC->DQSEN0_b.DL = 2;
-	DDRC->DQSEN1_b.DL = 2;
-	DDRC->DQSEN2_b.DL = 2;
-	DDRC->DQSEN3_b.DL = 2;
-	DDRC->INTCTL_b.DONE = 1;
-	DDRC->INTCTL_b.ERR = 0;
-	DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32;
-	DDRC->ITMDLY_b.I0 = DDRC->ITMDLY_b.IS0 = DDRC->ITMDLY_b.I1 = DDRC->ITMDLY_b.IS1 = 
-		DDRC->ITMDLY_b.I2 = DDRC->ITMDLY_b.IS2 = DDRC->ITMDLY_b.I3 = DDRC->ITMDLY_b.IS3 = 3;
-
-	
-	DDR_Latency((POWER_UP_NOP/period));
-	DDR_Cmd(SW_CMD_NOPCKE,(PRE_ALL_NOP/period));
-	DDR_Cmd(SW_CMD_PREA,NULL);
-	DDR_Latency(ptr->tRP);/*tRP*/
-	DDR_Cmd(SW_CMD_EMR2,NULL);
-	DDR_Latency(DDR2_TMRD);
-	DDR_Cmd(SW_CMD_EMR3,NULL);
-	DDR_Latency(DDR2_TMRD);
-	DDR_Cmd(SW_CMD_DLL_EN,NULL);
-	DDR_Latency(DDR2_TMRD);
-	DDR_Cmd(SW_CMD_DLL_RST,NULL);
-	DDR_Latency(DDR2_TMRD);
-	DDR_Cmd(SW_CMD_PREA,NULL);
-	DDR_Latency(ptr->tRP);
-	DDR_Cmd(SW_CMD_REF,NULL);
-	DDR_Latency((tRFC/period));/*tRFC*/
-	DDR_Cmd(SW_CMD_REF,NULL);
-	DDR_Latency((tRFC/period));
-	DDR_Cmd(SW_CMD_MR,(((ptr->tWR-1)<<MR_WR_OFFSET)|(ptr->tCL<<MR_CL_OFFSET)|MR_BURST_LEN_8));
-	DDR_Latency(POWER_UP_MIN_CK);
-	DDR_Cmd(SW_CMD_EMR1_TEST,NULL);
-	DDR_Latency(DDR2_TMRD);
-}
-
-static void DDR3_conf(const MEM_CHIP_INFO *chip_info ,const void *ddr)
-{
-
-	uint32_t period = 0;
-	uint32_t tRFC = 0;
-	const DDR3MEM *ptr = (const DDR3MEM *)ddr;
-
-	tRFC = Calc_DDR_RFC(chip_info);
-	period = (1000 / (SYSTEM_CLOCK_FREQ / 1000000));	
-	
-	DDRC->MODE_b.LANE = 0x1;
-	DDRC->QUE_b.DEPTH=1;
-	DDRC->REF_b.TIME = (DDR_TREF / period);////// //2Gb periodic refresh interval 7.8us 7.8us/5ns
-	DDRC->REF_b.TRIG = 1;
-	DDRC->REF_b.THRD = 8; 
-	DDRC->ZQCSR_b.EN = 1;
-	DDRC->ZQCSI = 128 * 1000000 / period;
-	DDRC->RP_b.RPA = 1;
-	DDRC->RFC_b.DI = (tRFC / period);
-	
-	if (ptr->tCK == 2500) { // 200MHz 
-		DDRC->RD_SEL_b.PHY_SEL = 5;
-	} else if (ptr->tCK == 3000) { // 333MHz 
-		DDRC->RD_SEL_b.PHY_SEL = 6;
-	}
-	
-	DDRC->PHUNG_b.MODE = 1;	
-	DDRC->DQSEN0_b.DL = 2;
-	DDRC->DQSEN1_b.DL = 2;
-	DDRC->DQSEN2_b.DL = 2;
-	DDRC->DQSEN3_b.DL = 2;
-
-	// config MR#
-	DDR_Latency((POWER_UP_NOP/period));//200us nop
-	DDR_Cmd(SW_CMD_RSTH,NULL);// RESET H
-	DDR_Latency((RSTH_NOP/period));// 500us nop  
-	DDR_Cmd(SW_CMD_NOPCKE,((tRFC+10)/period));//	 cke high 170/tck tck txpr max(5nck, trfc(min) + 10ns)	 2Gb refresh time 160ns
-	DDR_Cmd(SW_CMD_EMR2,((ptr->tWCL-5)<<MR2_CWL_OFFSET)); //MR2
-	DDR_Latency(DDR3_TMRD);// tmrd  4nck
-	DDR_Cmd(SW_CMD_EMR3,NULL);// MR3
-	DDR_Latency(DDR3_TMRD); // tmrd
-	DDR_Cmd(SW_CMD_EMR1,MR1_RZQ_4); // MR1	
-	DDR_Latency(DDR3_TMRD); // tmrd
-	DDR_Cmd(SW_CMD_MR,(MR_PPD_FAST|MR_DLL_YES|((ptr->tWR-1)<<MR_WR_OFFSET)|(CAL_DDR3_CL(ptr->tCL))));
-														// MR0
-														// A1 , A0 2'b0 fixed 8 
-														// A2 CL 0 
-														// A3 nibble sequential 0  Interleave 1
-														// A6,A5,A4 CL 101 CL =9 
-														// A7 normal mode 0
-														// A8 DLL reset 1
-														// A11,A10,A9 wr=(twr/ck)=(15/3)=5	=001
-														// A12 DLL control for precharge PD fast exit 1
-														// MR0 =0xb50
-	DDR_Latency(MAX(DDR3_TMOD_CK,(DDR3_TMOD/period)));// tmod max (12nck,15ns) 
-	DDR_Cmd(SW_CMD_ZQCL,NULL);// ZQCL starting ZQ calibration
-	DDR_Latency(MAX(DDR3_TZQINIT_CK,(DDR3_TZQINIT/period))); // tdllk 512nck (should be 500nck)
-	DDR_Latency(DDR3_TDLLK_CK); // tZQinit max(512nck,640ns) 
-
-}
-
-BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr)
-{
-	uint32_t tCL, tWR, tWCL, tWTR, tCK,mode;
-	
-	assert_param(chip_info);
-	assert_param(ddr);
-	if((chip_info->Bus_width<BUS_WIDTH_MAX)
-		&&(chip_info->Chip_num<CHIP_NUM_MAX)
-		&&(chip_info->Chip_type<	CHIP_TYPE_MAX))
-	{
-		if(chip_info->mem_type==MEM_DDR2)
-		{
-			mode=DDR2_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
-		}
-		else
-		{
-			mode=DDR3_MODE[chip_info->Bus_width][chip_info->Chip_num][chip_info->Chip_type];
-		}
-		if(mode==0xff)
-		{
-			return FALSE;
-		}
-		
-	
-	}
-	else
-	{
-		return FALSE;
-	}
-		
-	
-	PDPROT->LOCK_b.EN = 0;
-	do {
-		CFG_CTRL->PDLLSTR_b.C2R1D = 0; // rst dll_c2r1
-		udelay(10);
-		CFG_CTRL->PDLLSTR_b.C2R1D = 1; // releset rst
-		udelay(10);
-	} while ((PDLOCK->GCLK & 0x40) != 0x40);
-	PDPROT->LOCK_b.EN = 1;
-
-	DDRC->MODE_b.MODE = mode;
-
-	if (chip_info->mem_type==MEM_DDR2) {
-		const DDR2MEM *ptr = (const DDR2MEM *)ddr;
-		DDRC->RL_b.VAL = ptr->tCL;
-		DDRC->RCD_b.DI = ptr->tRCD;
-		DDRC->RP_b.DI = ptr->tRP;
-		DDRC->RC_b.DI = ptr->tRC;
-		DDRC->RAS_b.DI = ptr->tRAS;
-		tWR = ptr->tWR;
-		tWTR = ptr->tWTR;
-		DDRC->RRD_b.DI = ptr->tRRD;
-		DDRC->RTP_b.DI = ptr->tRTP;
-		DDRC->FAW_b.DI = ptr->tFAW;
-		DDR2_conf(chip_info,ptr);
-	} else {
-		const DDR3MEM *ptr = (const DDR3MEM *)ddr;
-		DDRC->RL_b.VAL = ptr->tCL;
-		tWCL = ptr->tWCL;
-		DDRC->RCD_b.DI = ptr->tRCD;
-		DDRC->RAS_b.DI = ptr->tRAS;
-		DDRC->RP_b.DI = ptr->tRP;
-		DDRC->RC_b.DI = ptr->tRC;
-		DDRC->RRD_b.DI = ptr->tRRD;
-		DDRC->FAW_b.DI = ptr->tFAW;
-		tWR = ptr->tWR;
-		tCK = ptr->tCK;
-		DDRC->RTP_b.DI = ptr->tRTP;
-		DDRC->ZQCL_b.DI = ptr->tZQoper;
-		DDRC->ZQCS_b.DI = ptr->tZQCS;
-		DDR3_conf(chip_info,ptr);
-	}
-
-	tCL = DDRC->RL_b.VAL;
-
-	DDRC->WTR_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? 
-		(tWCL + tWTR + (DDRC->BURST_b.LEN ? 2 : 4)) : 
-		((tCK * 4) > 7500) ? 18 : (tCK * 4 + 7500 - 1) / 7500;				 //4
-
-	DDRC->CCD_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 2 : 4) : 4;
-	DDRC->RTW_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? 4 : 6) : (tCL + DDRC->CCD_b.DI - tWCL + (DDRC->BURST_b.LEN ? 0 : 2));
-	DDRC->WTP_b.DI  = (DDRC->MODE_b.MODE & 0x20) ? (tCL + tWR + (DDRC->BURST_b.LEN ? 1 : 3)) : (tWCL + tWR + (DDRC->BURST_b.LEN ? 2 : 4));
-	DDRC->WL_b.VAL  = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 3) - 3) : (tWCL - 2);
-	DDRC->ODTH_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (MAX(tCL, 4) - 4) : 0;
-	if (tCK == 2500) { // 200MHz 
-		DDRC->ODTL_b.DL = (DDRC->MODE_b.MODE & 0x20) ? (DDRC->BURST_b.LEN ? (tCL - 1) : (tCL + 1)) : (DDRC->BURST_b.LEN ? 4 : 6);
-	} else if (tCK == 3000) { // 333MHz 
-		DDRC->ODTL_b.DL = 0x1f;
-	}
-
-	
-	// DEBUG INFO HERE
-	DDRC->CTRL_b.STR = 1;
-
-	while (0 == DDRC->STA_b.EMPTY);
-	while(0 == DDRC->INTRAW_b.DONE);
-	DDRC->CTRL_b.STR = DDRC->CTRL_b.TO = 0;
-
-	return TRUE;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_dma.c

@@ -1,262 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_dma.c
-	*
-	* @brief    CMEM7 DMA source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_dma.h"
-
-typedef struct {
-	union {
-    uint32_t  CTL_LOW;                              
-    
-    struct {
-      uint32_t  INT_EN     :  1;               
-      uint32_t  DST_TR_WIDTH:  3;              
-      uint32_t  SRC_TR_WIDTH:  3;              
-      uint32_t  DINC       :  2;              
-      uint32_t  SINC       :  2;               
-      uint32_t  DEST_MSIZE :  3;              
-      uint32_t  SRC_MSIZE  :  3;              
-      uint32_t  SRC_GATHER_EN:  1;           
-      uint32_t  DST_SCATTER_EN:  1;          
-      uint32_t             :  1;
-      uint32_t  TT_FC      :  3;           
-      uint32_t  DMS        :  2;              
-      uint32_t  SMS        :  2;            
-      uint32_t  LLP_DST_EN :  1;              
-      uint32_t  LLP_SRC_EN :  1;              
-    } CTL_LOW_b;                                
-  } INNER;
-} INNER_CTL_LOW;
-
-typedef struct {
-  union {
-    uint32_t  CTL_HI;     
-    
-    struct {
-      uint32_t  BLOCK_TS   : 12;    
-      uint32_t  DONE       :  1;                   
-    } CTL_HI_b;                                      
-  } INNER;
-} INNER_CTL_HIGH;
-
-typedef struct {                      
-	uint32_t srcAddr;                  
-	uint32_t dstAddr;                  
-	uint32_t nextBlock;              
-	INNER_CTL_LOW low;                 
-	INNER_CTL_HIGH high;                 
-} INNER_BLOCK_DESC;
-
-
-#define DMA_MAX_CHANNEL_NUM                  8
-
-#define DMA_TR_WIDTH_8_BIT                   0
-#define DMA_TR_WIDTH_16_BIT                  1
-#define DMA_TR_WIDTH_32_BIT                  2
-#define DMA_TR_WIDTH_64_BIT                  3
-#define DMA_TR_WIDTH_128_BIT                 4
-#define DMA_TR_WIDTH_256_BIT                 5
-
-#define DMA_INC_INCREMENT                    0
-#define DMA_INC_DECREMENT                    1
-#define DMA_INC_NO_CHANGE                    2
-
-#define DMA_LOCK_DMA_TRANSFER                0
-#define DMA_LOCK_DMA_BLOCK_TRANSFER          1
-#define DMA_LOCK_DMA_BLOCK_TRANSACTION       2
-
-            
-void DMA_Init() {
-	DMA->DMA_EN_b.EN = TRUE;
-	
-	// only open channel 0
-	DMA->CH_EN = (0xFF << DMA_MAX_CHANNEL_NUM) | 0x0;
-	
-	DMA_ClearInt(DMA_Int_All);
- 	DMA_EnableInt(DMA_Int_All, FALSE);
-	
-	DMA->SAR0 = 0x0;
-	DMA->DAR0 = 0x0;
-	
-	DMA->CTL_HI0_b.BLOCK_TS 			= 0;
-	DMA->CTL_LOW0_b.INT_EN 				= FALSE;
-	DMA->CTL_LOW0_b.DST_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
-	DMA->CTL_LOW0_b.SRC_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
-	DMA->CTL_LOW0_b.DINC 					= DMA_INC_INCREMENT;
-	DMA->CTL_LOW0_b.SINC 					= DMA_INC_INCREMENT;
-	DMA->CTL_LOW0_b.DEST_MSIZE 		= 0;
-	DMA->CTL_LOW0_b.SRC_MSIZE 		= 0;
-	DMA->CTL_LOW0_b.SRC_GATHER_EN = FALSE;
-	DMA->CTL_LOW0_b.DST_SCATTER_EN = FALSE;
-	DMA->CTL_LOW0_b.TT_FC 				= 0;
-  DMA->CTL_LOW0_b.DMS    				= 0;
-	DMA->CTL_LOW0_b.SMS    				= 0;
-	DMA->CTL_LOW0_b.LLP_DST_EN   	= FALSE;
-	DMA->CTL_LOW0_b.LLP_SRC_EN   	= FALSE;
-	
-  DMA->LLP0_b.LOC = 0; 
-	DMA->LLP0_b.LMS = 0;
-
-  DMA->SGR0_b.SGC = 0x1;
-	DMA->SGR0_b.SGI = 0x0;
-	
-	DMA->DSR0_b.DSC = 0x0;
-	DMA->DSR0_b.DSI = 0x0;
-
-  DMA->SSTATAR0 = 0x0;
-	DMA->DSTATAR0 = 0x0;
-	
-	DMA->CFG_HI0 								= 0x0;
-	DMA->CFG_LOW0_b.CH_PRIOR 		= 0;
-	DMA->CFG_LOW0_b.CH_SUSP 		= 0;
-	DMA->CFG_LOW0_b.HS_SEL_DST 	= 0;
-	DMA->CFG_LOW0_b.LOCK_B_L 		= 0;
-  DMA->CFG_LOW0_b.HS_SEL_SRC 	= 0;
-	DMA->CFG_LOW0_b.LOCK_CH_L 	= DMA_LOCK_DMA_TRANSFER;
-  DMA->CFG_LOW0_b.LOCK_B_L 		= DMA_LOCK_DMA_TRANSFER;
-	DMA->CFG_LOW0_b.LOCK_CH 		= TRUE;
-	DMA->CFG_LOW0_b.LOCK_B 			= TRUE;
-	DMA->CFG_LOW0_b.DST_HS_POL 	= 0;
-	DMA->CFG_LOW0_b.SRC_HS_POL 	= 0;
-	DMA->CFG_LOW0_b.RELOAD_SRC 	= FALSE;
-	DMA->CFG_LOW0_b.RELOAD_DST 	= FALSE;
-}
-
-void DMA_EnableInt(uint32_t Int, BOOL enable) {
-	assert_param(IS_DMA_INT(Int));
-	
-  if (enable) {
-		if (Int & DMA_Int_TfrComplete) {
-			DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-		} 
-		
-		if (Int & DMA_Int_Err) {
-			DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-		}
-	} else {
-		if (Int & DMA_Int_TfrComplete) {
-			DMA->INT_EN_TFR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
-		} 
-		
-		if (Int & DMA_Int_Err) {
-			DMA->INT_EN_ERR = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x0;
-		}
-	}
-}
-
-BOOL DMA_GetIntStatus(uint32_t Int) {
-	assert_param(IS_DMA_INT(Int));
-	
-	if (Int & DMA_Int_TfrComplete) {
-		if (DMA->INT_TFR) {
-			return TRUE;
-		}
-	}
-	
-	if (Int & DMA_Int_Err) {
-		if (DMA->INT_ERR) {
-			return TRUE;
-		}
-	}
-		
-	return FALSE;
-}
-
-void DMA_ClearInt(uint32_t Int) {
-	assert_param(IS_DMA_INT(Int));
-	
-	if (Int & DMA_Int_TfrComplete) {
-		DMA->INT_CLEAR_TFR = 0x1;
-	}
-	
-	if (Int & DMA_Int_Err) {
-		DMA->INT_CLEAR_ERR = 0x1;
-	}
-}
-
-BOOL DMA_IsBusy() {
-	return (DMA->CH_EN_b.EN) ? TRUE : FALSE;
-}
-
-BOOL DMA_Transfer(BLOCK_DESC *blockList) {
-	BLOCK_DESC *p;
-	if (!blockList) {
-		return FALSE;
-	}
-	
-	if (DMA_IsBusy()) {
-		return FALSE;
-	}
-	
-	p = blockList;
-	while (p) {
-		BOOL llp = FALSE;
-		INNER_BLOCK_DESC *inner = (INNER_BLOCK_DESC *)p;
-		if (p->nextBlock) {
-			llp = TRUE;
-		}
-		
-		inner->high.INNER.CTL_HI = 0;
-		inner->high.INNER.CTL_HI_b.BLOCK_TS = (p->number >> DMA_TR_WIDTH_32_BIT);
-		inner->high.INNER.CTL_HI_b.DONE = 0;
-		
-		inner->nextBlock = p->nextBlock;
-		
-		inner->low.INNER.CTL_LOW = 0;
-		inner->low.INNER.CTL_LOW_b.INT_EN = TRUE;
-		inner->low.INNER.CTL_LOW_b.DST_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
-	  inner->low.INNER.CTL_LOW_b.SRC_TR_WIDTH 	= DMA_TR_WIDTH_32_BIT;
-	  inner->low.INNER.CTL_LOW_b.DINC 					= DMA_INC_INCREMENT;
-	  inner->low.INNER.CTL_LOW_b.SINC 					= DMA_INC_INCREMENT;
-	  inner->low.INNER.CTL_LOW_b.DEST_MSIZE 		= 0;
-	  inner->low.INNER.CTL_LOW_b.SRC_MSIZE 		  = 0;
-	  inner->low.INNER.CTL_LOW_b.SRC_GATHER_EN  = FALSE;
-	  inner->low.INNER.CTL_LOW_b.DST_SCATTER_EN = FALSE;
-	  inner->low.INNER.CTL_LOW_b.TT_FC 					= 0;
-    inner->low.INNER.CTL_LOW_b.DMS    				= 0;
-	  inner->low.INNER.CTL_LOW_b.SMS    				= 0;
-	  inner->low.INNER.CTL_LOW_b.LLP_DST_EN   	= llp;
-	  inner->low.INNER.CTL_LOW_b.LLP_SRC_EN   	= llp;
-		
-		if ((uint32_t)inner == (uint32_t)blockList) {
-			// copy to DMA
-			DMA->SAR0 = llp ? 0x0 : inner->srcAddr ;
-			DMA->DAR0 = llp ? 0x0 : inner->dstAddr ;
-			
-			DMA->CTL_HI0 = llp ? 0x0 : inner->high.INNER.CTL_HI;
-			DMA->CTL_LOW0 = inner->low.INNER.CTL_LOW;
-			
-			DMA->LLP0 = llp ? (uint32_t)inner : 0x0;
-		}
-		
-		p = (BLOCK_DESC *)inner->nextBlock;
-	}
-
-	// open channel 0
-	DMA->CH_EN = (0x1 << DMA_MAX_CHANNEL_NUM) | 0x1;
-	
-	return TRUE;
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_efuse.c

@@ -1,255 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_efuse.c
-	*
-	* @brief    CMEM7 EFUSE source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_efuse.h"
-
-static void efuse_SetClock(uint8_t dividor) {
-	if (dividor <= 2) {
-		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 0;
-	} else if (dividor <= 4) {
-		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 1;
-	} else if (dividor <= 8) {
-		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 2;
-	} else {
-		GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK = 3;
-	}
-}
-
-static uint32_t efuse_GetClock() {
-	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_1_b.EFUSE_CLK + 1));
-}
-
-// static uint8_t efuse_Crc8Bit(uint8_t data, uint8_t crc) {
-// 	uint8_t newCrc;
-// 	uint8_t d[8], c[8], i;
-// 	
-// 	for (i = 0; i < 8; i++) {
-// 		d[i] = (data >> i) & 0x01;
-// 		c[i] = (crc >> i) & 0x01;
-// 	}
-// 	
-// 	newCrc = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
-// 	newCrc |= (d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6]) << 1;
-// 	newCrc |= (d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6]) << 2;
-// 	newCrc |= (d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7]) << 3;
-// 	newCrc |= (d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4]) << 4;
-// 	newCrc |= (d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5]) << 5;
-// 	newCrc |= (d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6]) << 6;
-// 	newCrc |= (d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7]) << 1;
-// 	
-// 	return newCrc;
-// }
-
-// static uint8_t efuse_Crc(EFUSE_AesKey* key, uint8_t lock, BOOL isLowRegion) {
-// 	uint8_t crc = 0;
-// 	
-// 	if (isLowRegion) {
-// 		crc = efuse_Crc8Bit(key->key0, crc);
-// 		crc = efuse_Crc8Bit(key->key0 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key0 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key0 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key1, crc);
-// 		crc = efuse_Crc8Bit(key->key1 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key1 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key1 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key2, crc);
-// 		crc = efuse_Crc8Bit(key->key2 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key2 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key2 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key3, crc);
-// 		crc = efuse_Crc8Bit(key->key3 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key3 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key3 >> 24, crc);
-// 		crc = efuse_Crc8Bit(lock, crc);
-// 		crc = efuse_Crc8Bit(0x0, crc);
-// 		crc = efuse_Crc8Bit(0x0, crc);
-// 	} else {
-// 		crc = efuse_Crc8Bit(key->key4, crc);
-// 		crc = efuse_Crc8Bit(key->key4 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key4 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key4 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key5, crc);
-// 		crc = efuse_Crc8Bit(key->key5 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key5 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key5 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key6, crc);
-// 		crc = efuse_Crc8Bit(key->key6 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key6 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key6 >> 24, crc);
-// 		crc = efuse_Crc8Bit(key->key7, crc);
-// 		crc = efuse_Crc8Bit(key->key7 >> 8, crc);
-// 		crc = efuse_Crc8Bit(key->key7 >> 16, crc);
-// 		crc = efuse_Crc8Bit(key->key7 >> 24, crc);
-// 		crc = efuse_Crc8Bit(lock, crc);
-// 		crc = efuse_Crc8Bit(0x0, crc);
-// 		crc = efuse_Crc8Bit(0x0, crc);
-// 	}
-// 	
-// 	return crc;
-// }
-
-void EFUSE_Init(EFUSE_InitTypeDef* init) {
-	assert_param(init);
-	assert_param(IS_EFUSE_TMRF(init->EFUSE_TMRF));
-	
-	efuse_SetClock(init->EFUSE_ClockDividor);
-	EFUSE->USER_CTRL_LOW_b.TMRF = init->EFUSE_TMRF;
-	EFUSE->USER_CTRL_HI_b.TMRF = init->EFUSE_TMRF;
-	if (init->timing) {
-		uint32_t value;
-		
-		value = (init->timing->EFUSE_Tpwph * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TPWPH = value >> 2;
-		EFUSE->TIMING_1_b.TPWPH = value & 0x00000003;
-
-		value = (init->timing->EFUSE_Trac * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TRAC = value;
-
-		value = (init->timing->EFUSE_Trah * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TRAH = value;
-		
-		value = (init->timing->EFUSE_Trpw * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TRPW = value;
-
-		value = (init->timing->EFUSE_Trc * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TRC = value;
-		
-		value = (init->timing->EFUSE_Tesr * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TESR = value;
-
-		value = (init->timing->EFUSE_Tprs * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_0_b.TPRS = value;
-
-		value = (init->timing->EFUSE_Tpi * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_1_b.TPIT = value;
-
-		value = (init->timing->EFUSE_Tpp * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_1_b.TPP = value;
-
-		value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_1_b.TEPS = value;
-
-		value = (init->timing->EFUSE_Teps * (efuse_GetClock() / 1000000) / 1000);
-		value = (value == 0) ? 1 : value;
-		EFUSE->TIMING_1_b.TPWPS = value;
-	}
-}
-
-/* It only can be written once */
-// BOOL EFUSE_Write(EFUSE_AesKey* key) {
-//   assert_param(key);	
-// 	
-// 	if ((EFUSE->USER_CTRL_LOW_b.LOCK || EFUSE->USER_CTRL_LOW_b.BUSY) ||
-// 		(EFUSE->USER_CTRL_HI_b.LOCK || EFUSE->USER_CTRL_HI_b.BUSY)) {
-// 		return FALSE;
-// 	}
-// 	
-// 	// write low region
-// 	EFUSE->USER_DATA0_LOW = key->key0;
-// 	EFUSE->USER_DATA1_LOW = key->key1;
-// 	EFUSE->USER_DATA2_LOW = key->key2;
-// 	EFUSE->USER_DATA3_LOW = key->key3;
-// 	EFUSE->USER_DATA4_LOW_b.CRC = efuse_Crc(key, 0x1, TRUE);
-// 	EFUSE->USER_DATA4_LOW_b.LOCK = 1;
-// 	EFUSE->USER_CTRL_LOW_b.WR_EN = FALSE;
-// 	EFUSE->USER_CTRL_LOW_b.WR_EN = TRUE;
-// 	
-// 	udelay(1000);
-// 	while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
-// 	
-// 	if (EFUSE->USER_CTRL_LOW_b.WR_CRC_ERR) {
-// 		return FALSE;
-// 	}
-// 	
-// 	// write high region
-// 	EFUSE->USER_DATA0_HI = key->key4;
-// 	EFUSE->USER_DATA1_HI = key->key5;
-// 	EFUSE->USER_DATA2_HI = key->key6;
-// 	EFUSE->USER_DATA3_HI = key->key7;
-// 	EFUSE->USER_DATA4_HI_b.CRC = efuse_Crc(key, 0x1, FALSE);
-// 	EFUSE->USER_DATA4_HI_b.LOCK = 1;
-// 	EFUSE->USER_CTRL_HI_b.WR_EN = FALSE;
-// 	EFUSE->USER_CTRL_HI_b.WR_EN = TRUE;
-// 	
-// 	udelay(1000);
-// 	while (EFUSE->USER_CTRL_HI_b.BUSY) ;
-// 	
-// 	if (EFUSE->USER_CTRL_HI_b.WR_CRC_ERR) {
-// 		return FALSE;
-// 	}
-// 	return TRUE;
-// }
-
-BOOL EFUSE_Compare(EFUSE_AesKey* key) {
-  assert_param(key);	
-	
-	if (EFUSE->USER_CTRL_LOW_b.BUSY || EFUSE->USER_CTRL_HI_b.BUSY) {
-		return FALSE;
-	}
-	
-	// compare low region
-	EFUSE->USER_DATA0_LOW = key->key0;
-	EFUSE->USER_DATA1_LOW = key->key1;
-	EFUSE->USER_DATA2_LOW = key->key2;
-	EFUSE->USER_DATA3_LOW = key->key3;
-	EFUSE->USER_CTRL_LOW_b.RD_EN = FALSE;
-	EFUSE->USER_CTRL_LOW_b.RD_EN = TRUE;
-	
-	udelay(2);
-	while (EFUSE->USER_CTRL_LOW_b.BUSY) ;
-	
-	if (EFUSE->USER_CTRL_LOW_b.COMPARE_FAIL) {
-		return FALSE;
-	}
-	
-	// compare high region
-	EFUSE->USER_DATA0_HI = key->key4;
-	EFUSE->USER_DATA1_HI = key->key5;
-	EFUSE->USER_DATA2_HI = key->key6;
-	EFUSE->USER_DATA3_HI = key->key7;
-	EFUSE->USER_CTRL_HI_b.RD_EN = FALSE;
-	EFUSE->USER_CTRL_HI_b.RD_EN = TRUE;
-	
-	udelay(2);
-	while (EFUSE->USER_CTRL_HI_b.BUSY) ;
-	
-	if (EFUSE->USER_CTRL_HI_b.COMPARE_FAIL) {
-		return FALSE;
-	}
-	
-	return TRUE;	
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c

@@ -1,692 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_eth.c
-	*
-	* @brief    CMEM7 ethernet source file
-	*
-	*
-	* @version  V2.0
-	* @date     3. September 2014
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_eth.h"
-#include "cmem7_misc.h"
-
-typedef struct { 
-	union {
-    uint32_t  TX0;
-		
-		struct {
-			uint32_t 								:  1;
-			uint32_t UNDERFLOW_ERR  :  1; 	 /*!< [OUT] Underflow error            											*/
-			uint32_t 								:  1;
-			uint32_t COLLISION_CNT	:  4;		 /*!< [OUT] Collision count				                          */
-			uint32_t 								:  1;
-			uint32_t EX_COLLISION 	:  1;		 /*!< [OUT] Excessive collision error	                      */
-			uint32_t LATE_COLLISION :  1;		 /*!< [OUT] Late collision error	                          */
-			uint32_t NO_CARRIER     :  1;		 /*!< [OUT] No carrier error                          			*/
-			uint32_t LOSS_CARRIER   :  1;		 /*!< [OUT] loss of carrier error                          	*/
-			uint32_t PAYLOAD_ERR 		:  1;		 /*!< [OUT] IP payload error                          			*/
-			uint32_t 								:  2;
-			uint32_t ERR_SUM 				:  1;		 /*!< [OUT] Error summary		                          			*/
-			uint32_t HEADER_ERR 		:  1;		 /*!< [OUT] IP header error                          				*/
-			uint32_t 								:  3;
-			uint32_t TCH						:  1;		 /*!< Second Address Chained                                */
-			uint32_t 								:  4;
-			uint32_t TTSE           :  1; 	 /*!< enables IEEE1588 hardware timestamping in first segment */
-			uint32_t 							  :  2;  
-			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
-			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
-			uint32_t IC	           	:  1; 	 /*!< Interrupt on Completion                               */
-			uint32_t OWN          	:  1; 	 /*!< Descriptor is owned by self or hardware               */
-		} TX0_b;
-	} TX_0;
-	
-	union {
-    uint32_t  TX1;
-		
-		struct {
-			uint32_t SIZE						: 13; 	 /*!< buffer size                                           */
-			uint32_t                : 19;
-		} TX1_b;
-	} TX_1;
-	
-	uint32_t bufAddr;
-	uint32_t nextDescAddr;
-  uint64_t reserved;
-	uint64_t timeStamp;									 /*!< time stamp in the last segment                         */
-} INNER_ETH_TX_DESC;
-
-typedef struct { 
-	union {
-    uint32_t  RX0;
-		
-		struct {
-			uint32_t 								:  1;
-			uint32_t CRC_ERR        :  1; 	 /*!< [OUT] CRC error while last segment                		*/
-			uint32_t 								:  5;
-			uint32_t TTSE           :  1; 	 /*!< timestamp available while last segment                */
-			uint32_t LS           	:  1; 	 /*!< last segment flag                                     */
-			uint32_t FS           	:  1; 	 /*!< first segment flag                                    */
-			uint32_t 								:  1;
-			uint32_t OVERFLOW_ERR   :  1; 	 /*!< [OUT] FIFO overflow while last segment                */
-			uint32_t LENGTH_ERR     :  1; 	 /*!< [OUT] length error while last segment                	*/
-			uint32_t 								:  2;
-			uint32_t ERR_SUM        :  1; 	 /*!< [OUT] Error summary while last segment              	*/
-			uint32_t FL           	: 14; 	 /*!< frame length while last segment                       */
-			uint32_t 		           	:  1;
-			uint32_t OWN          	:  1; 	 /*!< Descriptor is owned by self or hardware               */
-		} RX0_b;
-	} RX_0;
-	
-	union {
-    uint32_t  RX1;
-		
-		struct {
-			uint32_t SIZE						: 13; 	 /*!< buffer size                                           */
-			uint32_t 		           	:  1;
-			uint32_t RCH            :  1;    /*!< Second Address Chained                                */
-			uint32_t 		           	: 16;
-			uint32_t DIC	          :  1; 	 /*!< Disable interrupt on Completion                       */
-		} RX1_b;
-	} RX_1;
-	
-	uint32_t bufAddr;
-	uint32_t nextDescAddr;
-  uint64_t reserved;
-	uint64_t timeStamp;									 /*!< time stamp while the last segment                     */
-} INNER_ETH_RX_DESC;
-
-
-#define PHY_OP_READ                 0x0
-#define PHY_OP_WRITE                0x1
-
-#define ETH_BURST_MODE_FIXED        0x0
-#define ETH_BURST_MODE_UNDERSIZE    0x1
-#define ETH_BURST_MODE_MIXED        0x2
-
-#define ETH_BURST_LENGTH_MIN        1
-#define ETH_BURST_LENGTH_MAX        256
-#define ETH_BURST_LENGTH_8X_SWITCH  32
-#define ETH_BURST_LENGTH_8X_MIN     8
-
-#define ETH_DMA_ARBITRATION_ROUND_ROBIN			0x0
-#define ETH_DMA_ARBITRATION_FIXED_PRIORITY	0x1
-
-#define ETH_RX_THRESHOLD_64         0x0
-#define ETH_RX_THRESHOLD_32         0x1
-#define ETH_RX_THRESHOLD_96         0x2
-#define ETH_RX_THRESHOLD_128        0x3
-
-#define ETH_TX_THRESHOLD_64         0x0
-#define ETH_TX_THRESHOLD_128        0x1
-#define ETH_TX_THRESHOLD_192        0x2
-#define ETH_TX_THRESHOLD_256        0x3
-#define ETH_TX_THRESHOLD_40         0x4
-#define ETH_TX_THRESHOLD_32         0x5
-#define ETH_TX_THRESHOLD_24         0x6
-#define ETH_TX_THRESHOLD_16         0x7
-
-#define ETH_INT_ABNORMAL_SUMMARY    0x8000
-#define ETH_INT_NORMAL_SUMMARY      0x10000
-
-#define IS_ETH_INT_NORMAL(INT)      ((INT & ETH_INT_TX_COMPLETE_FRAME) 	|| \
-																		 (INT & ETH_INT_TX_BUF_UNAVAI) 			|| \
-																		 (INT & ETH_INT_RX_COMPLETE_FRAME))
-																		 
-#define IS_ETH_INT_ABNORMAL(INT)    ((INT & ETH_INT_TX_STOP) 						|| \
-																		 (INT & ETH_INT_RX_OVERFLOW)        || \
-																		 (INT & ETH_INT_TX_UNDERFLOW)       || \
-																		 (INT & ETH_INT_RX_BUF_UNAVAI) 			|| \
-																		 (INT & ETH_INT_RX_STOP) 						|| \
-																		 (INT & ETH_INT_BUS_FATAL_ERROR))																		 
-						
-#define ETH_PREAMBLE_7_BYTE         0x0
-#define ETH_PREAMBLE_5_BYTE         0x1
-#define ETH_PREAMBLE_3_BYTE         0x2
-
-#define ETH_LINE_SPEED_1000M_BPS		0x0
-#define ETH_LINE_SPEED_10_100M_BPS	0x1
-
-#define ETH_EXACT_SPEED_10M_BPS			0x0
-#define ETH_EXACT_SPEED_100M_BPS		0x1
-
-#define ETH_SOURCE_ADDR_REPLACE     0x3
-
-#define ETH_PASS_CTRL_FRAME_ALL     0x0
-
-#define ETH_DESC_OWN_BY_SELF        0x0
-#define ETH_DESC_OWN_BY_HW          0x1
-
-
-static void mac_SwReset(void) {
-	ETH->BUS_MODE_b.SWR = 1;
-	while (ETH->BUS_MODE_b.SWR) ;
-	while (ETH->AHB_STATUS_b.BUSY) ;
-}
-
-static void mac_SetConfig(ETH_InitTypeDef *init) {	
-	ETH->CONFIG_b.PRELEN = ETH_PREAMBLE_7_BYTE;
-	ETH->CONFIG_b.RX_EN = init->ETH_RxEn;
-	ETH->CONFIG_b.TX_EN = init->ETH_TxEn;
-	ETH->CONFIG_b.DC_EN = FALSE;
-	ETH->CONFIG_b.ACS = FALSE;
-	ETH->CONFIG_b.LUD = init->ETH_LinkUp;
-	ETH->CONFIG_b.IPC = init->ETH_ChecksumOffload;
-	ETH->CONFIG_b.DM = init->ETH_Duplex;
-	ETH->CONFIG_b.LM = FALSE;
-	ETH->MMCRIMR = 0xFFFFFFFF;
-	ETH->MMCTIMR = 0xFFFFFFFF;
-	ETH->MMCIRCOIM = 0xFFFFFFFF;
-	
-	if (init->ETH_Speed == ETH_SPEED_10M) {
-		ETH->CONFIG_b.FES = ETH_EXACT_SPEED_10M_BPS;
-		ETH->CONFIG_b.PS = ETH_LINE_SPEED_10_100M_BPS;
-	} else if (init->ETH_Speed == ETH_SPEED_100M) {
-		ETH->CONFIG_b.FES = ETH_EXACT_SPEED_100M_BPS;
-		ETH->CONFIG_b.PS = ETH_LINE_SPEED_10_100M_BPS;
-	} else {
-		ETH->CONFIG_b.FES = ETH_EXACT_SPEED_100M_BPS;
-		ETH->CONFIG_b.PS = ETH_LINE_SPEED_1000M_BPS;
-	}
-
-	ETH->CONFIG_b.JE = init->ETH_JumboFrame;
-	
-	ETH->CONFIG_b.JD = TRUE;
-	ETH->CONFIG_b.WD = TRUE;
-	ETH->CONFIG_b.TC = FALSE;
-	ETH->CONFIG_b.CST = TRUE;
-	ETH->CONFIG_b.TWOKPE = FALSE;
-	ETH->CONFIG_b.SARC = ETH_SOURCE_ADDR_REPLACE;
-}
-
-static void mac_SetMacAddr(uint8_t *mac) {
-	ETH->ADDR0_HIGH = (mac[5] << 8) | mac[4];
-	ETH->ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | 
-		  (mac[1] << 8) | mac[0];
-}
-
-static void mac_SetBurst(
-  uint8_t mode, uint32_t rxBurstLen, uint32_t txBurstLen) {
-	ETH->BUS_MODE_b.RIB = FALSE;
-	ETH->BUS_MODE_b.AAL = FALSE;
-		
-	if (mode == ETH_BURST_MODE_FIXED) {
-		ETH->BUS_MODE_b.FB = TRUE;
-		ETH->BUS_MODE_b.MB = FALSE;
-	} else if (mode == ETH_BURST_MODE_UNDERSIZE) {
-		ETH->BUS_MODE_b.FB = FALSE;
-		ETH->BUS_MODE_b.MB = FALSE;
-	} else {
-		ETH->BUS_MODE_b.FB = TRUE;
-		ETH->BUS_MODE_b.MB = TRUE;
-	}
-	
-	rxBurstLen = 1 << rxBurstLen;
-	rxBurstLen = (rxBurstLen > ETH_BURST_LENGTH_MAX) ? 
-	  ETH_BURST_LENGTH_MAX : rxBurstLen;
-	
-	txBurstLen = 1 << txBurstLen;
-	txBurstLen = (txBurstLen > ETH_BURST_LENGTH_MAX) ? 
-	  ETH_BURST_LENGTH_MAX : txBurstLen;
-	
-	// Regrading PBLx8 register, if one of PBL and RPBL is more than 
-	// ETH_BURST_LENGTH_8X_SWITCH, another should be more than 
-	// ETH_BURST_LENGTH_8X_MIN.
-	// If not, the greater level down to ETH_BURST_LENGTH_8X_SWITCH.
-	if ((txBurstLen < ETH_BURST_LENGTH_8X_MIN) ||
-		(rxBurstLen < ETH_BURST_LENGTH_8X_MIN)) {
-		if (rxBurstLen > ETH_BURST_LENGTH_8X_SWITCH) {
-			rxBurstLen = ETH_BURST_LENGTH_8X_SWITCH;
-		}
-		
-		if (txBurstLen > ETH_BURST_LENGTH_8X_SWITCH) {
-			txBurstLen = ETH_BURST_LENGTH_8X_SWITCH;
-		}
-	}
-		
-	ETH->BUS_MODE_b.USP = (rxBurstLen == txBurstLen) ? FALSE : TRUE;
-  if ((txBurstLen > ETH_BURST_LENGTH_8X_SWITCH) ||
-		(rxBurstLen > ETH_BURST_LENGTH_8X_SWITCH)) {
-		ETH->BUS_MODE_b.PBLx8 = TRUE;
-	} else {
-		ETH->BUS_MODE_b.PBLx8 = FALSE;
-	}
-	
-	if (ETH->BUS_MODE_b.PBLx8) {
-		ETH->BUS_MODE_b.RPBL = rxBurstLen >> 3;
-		ETH->BUS_MODE_b.PBL = txBurstLen >> 3;
-	} else {
-		ETH->BUS_MODE_b.RPBL = rxBurstLen;
-		ETH->BUS_MODE_b.PBL = txBurstLen;
-	}	
-}
-
-static void mac_SetPriority(BOOL isRxPrior, uint8_t priorityRate) {
-  ETH->BUS_MODE_b.PRWG = 0;
-	ETH->BUS_MODE_b.DA = ETH_DMA_ARBITRATION_ROUND_ROBIN;
-	
-	ETH->BUS_MODE_b.TXPR = isRxPrior ? FALSE : TRUE;
-	ETH->BUS_MODE_b.PR = priorityRate;
-}
-
-static void mac_SetDescMode(BOOL isAlternate, uint8_t gap) {
-  ETH->BUS_MODE_b.ATDS = isAlternate;
-	ETH->BUS_MODE_b.DSL = gap;
-}
-
-static void mac_SetOpertionMode(void) {
-	ETH->OPERATION_b.OSF = FALSE;
-	ETH->OPERATION_b.RT = ETH_RX_THRESHOLD_32;
-	ETH->OPERATION_b.RSF = FALSE;
-	
-	ETH->OPERATION_b.DGF = FALSE;
-	ETH->OPERATION_b.FUF = FALSE;
-	ETH->OPERATION_b.FEF = FALSE;
-	ETH->OPERATION_b.TT = ETH_TX_THRESHOLD_64;
-	ETH->OPERATION_b.TSF = FALSE;
-	
-	ETH->OPERATION_b.FTF = TRUE;
-	ETH->OPERATION_b.DFF = TRUE;
-}
-
-static void mac_SetFrameFilter(ETH_FrameFilter *filter) {
-	ETH->FF_b.PR = FALSE;
-	ETH->FF_b.HUC = FALSE;
-	ETH->FF_b.HMC = FALSE;
-	ETH->FF_b.DAIF = FALSE;
-	ETH->FF_b.PM = FALSE;
-	ETH->FF_b.DBF = FALSE;
-	ETH->FF_b.PCF = ETH_PASS_CTRL_FRAME_ALL;
-	ETH->FF_b.SAIF = FALSE;
-	ETH->FF_b.SAF = FALSE;
-	ETH->FF_b.HPF = FALSE;
-	ETH->FF_b.VTFE = FALSE;
-	ETH->FF_b.IPFE = FALSE;
-	ETH->FF_b.DNTU = FALSE;
-	ETH->FF_b.RA = FALSE;//TRUE
-	
-	// receive all
-	if (!filter) {
-		return ;
-	}
-	
-	// broadcast 
-	if (filter->ETH_BroadcastFilterEnable) {
-		ETH->FF_b.RA = FALSE;
-		ETH->FF_b.DBF = TRUE;
-	}
-	
-	// DA
-	if (filter->ETH_OwnFilterEnable) {
-		ETH->FF_b.RA = FALSE;
-		ETH->FF_b.DAIF = filter->ETH_SelfDrop;
-	}
-	
-	// SA
-	if (filter->ETH_SourceFilterEnable) {
-		uint32_t value;
-    
-    ETH->FF_b.RA = FALSE;
-		ETH->FF_b.SAF = TRUE;
-		ETH->FF_b.SAIF = filter->ETH_SourceDrop;
-		ETH->ADDR1_HIGH_b.AE = TRUE;
-		ETH->ADDR1_HIGH_b.SA = TRUE; 
-    ETH->ADDR1_HIGH_b.ADDR = 
-			(filter->ETH_SourceMacAddr[5] << 8) | filter->ETH_SourceMacAddr[4];
-		
-		
-// 		value = (filter->ETH_SourceMacAddr[5] << 8) | filter->ETH_SourceMacAddr[4];
-//     CMEM7_BFI(&(ETH->ADDR1_HIGH), value, 0, 16);
-    ETH->ADDR1_LOW = (filter->ETH_SourceMacAddr[3] << 24) | 
-			(filter->ETH_SourceMacAddr[2] << 16) | 
-		  (filter->ETH_SourceMacAddr[1] << 8) | 
-			filter->ETH_SourceMacAddr[0];
-	}
-}
-
-static void mac_setFlowControl(void) {
-  ETH->FC_b.FCB = FALSE;
-	ETH->FC_b.TFE = FALSE;//TRUE
-	ETH->FC_b.RFE = FALSE;//TRUE
-	ETH->FC_b.UP = FALSE;//TRUE
-}
-
-uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg) {
-	ETH->GMII_ADDR_b.PA = phyAddr;
-	ETH->GMII_ADDR_b.GR = phyReg;
-	ETH->GMII_ADDR_b.GW = PHY_OP_READ;
-
-	ETH->GMII_ADDR_b.BUSY = TRUE;
-	while (ETH->GMII_ADDR_b.BUSY) ;
-	
-	return ETH->GMII_DATA;
-}
-
-void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data) {
-	ETH->GMII_ADDR_b.PA = phyAddr;
-	ETH->GMII_ADDR_b.GR = phyReg;
-	ETH->GMII_ADDR_b.GW = PHY_OP_WRITE;
-  ETH->GMII_DATA = data;
-	
-	ETH->GMII_ADDR_b.BUSY = TRUE;
-	while (ETH->GMII_ADDR_b.BUSY) ;
-}
-
-void ETH_StructInit(ETH_InitTypeDef* init)
-{
-    init->ETH_Speed = ETH_SPEED_10M;
-    init->ETH_Duplex = ETH_DUPLEX_FULL;
-    init->ETH_JumboFrame = FALSE;
-    init->ETH_LinkUp = FALSE;
-    init->ETH_RxEn = TRUE;
-    init->ETH_TxEn = TRUE;
-    init->ETH_ChecksumOffload = FALSE;
-    init->ETH_Filter = 0;
-    init->ETH_MacAddr[0] = 0;
-    init->ETH_MacAddr[1] = 0;
-    init->ETH_MacAddr[2] = 0;
-    init->ETH_MacAddr[3] = 0;
-    init->ETH_MacAddr[4] = 0;
-    init->ETH_MacAddr[5] = 0;
-    
-}
-BOOL ETH_Init(ETH_InitTypeDef *init) {
-    assert_param(init);
-    assert_param(IS_ETH_SPEED(init->ETH_Speed));
-    assert_param(IS_ETH_DUPLEX(init->ETH_Duplex));
-	
-    mac_SwReset();
-    mac_SetConfig(init);
-    mac_SetMacAddr(init->ETH_MacAddr);
-	
-    mac_SetBurst(ETH_BURST_MODE_MIXED, 3, 4);
-    mac_SetPriority(TRUE, 0);
-    mac_SetDescMode(TRUE, 0);
-    mac_SetOpertionMode();
-    mac_SetFrameFilter(init->ETH_Filter);
-    mac_setFlowControl();
-	
-    return TRUE;
-}
-
-void ETH_ITConfig(uint32_t Int, BOOL enable) {
-	assert_param(IS_ETH_INT(Int));
-	
-	if (enable) {
-		if (IS_ETH_INT_NORMAL(Int)) {
-			ETH->INT_EN_b.NIE = TRUE;
-		}
-		
-		if (IS_ETH_INT_ABNORMAL(Int)) {
-			ETH->INT_EN_b.AIE = TRUE;
-		}
-		
-		ETH->INT_EN |= Int;
-	} else {
-		ETH->INT_EN &= ~Int;
-		
-		if (!IS_ETH_INT_NORMAL(ETH->INT_EN)) {
-			ETH->INT_EN_b.NIE = FALSE;
-		}
-		
-		if (!IS_ETH_INT_ABNORMAL(ETH->INT_EN)) {
-			ETH->INT_EN_b.AIE = FALSE;
-		}
-	}
-}
-BOOL ETH_GetITStatus(uint32_t Int) {
-	assert_param(IS_ETH_INT(Int));
-	
-	Int &= ETH->INT_EN;
-	if (0 != (ETH->STATUS & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-void ETH_ClearITPendingBit(uint32_t Int) {
-	uint32_t sta;
-	assert_param(IS_ETH_INT(Int));
-		
-	sta = ETH->STATUS;
-	sta &= ETH->INT_EN;
-	sta &= ~Int;
-	
-	// write 1 clear
-	ETH->STATUS = Int;
-	
-	if (IS_ETH_INT_NORMAL(Int)) {
-		if (!IS_ETH_INT_NORMAL(sta)) {
-			// write 1 clear NIS
-			ETH->STATUS = ETH_INT_NORMAL_SUMMARY;
-		}
-	}
-	
-	if (IS_ETH_INT_ABNORMAL(Int)) {
-		if (!IS_ETH_INT_ABNORMAL(sta)) {
-			// write 1 clear AIS
-			ETH->STATUS = ETH_INT_ABNORMAL_SUMMARY;
-		}
-	}
-}
-
-void ETH_GetMacAddr(uint8_t *mac) {
-  uint32_t tmp;
-	
-	if (!mac) {
-		return ;
-	}
-	
-	tmp = ETH->ADDR0_LOW;
-	*(mac + 0) = (tmp >> 0) & 0xFF;
-	*(mac + 1) = (tmp >> 8) & 0xFF;
-	*(mac + 2) = (tmp >> 16) & 0xFF;
-	*(mac + 3) = (tmp >> 24) & 0xFF;
-	tmp = ETH->ADDR0_HIGH;
-	*(mac + 4) = (tmp >> 0) & 0xFF;
-	*(mac + 5) = (tmp >> 8) & 0xFF;
-}
-
-BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring) {
-	ETH_TX_DESC *buf = ring;
-	
-	if (!ring) {
-		return FALSE;
-	}
-	
-	if (ETH->OPERATION_b.ST) {
-		return FALSE;
-	}
-
-  /* If code mapping */
-  ring = (ETH_TX_DESC *)GLB_ConvertToMappingFromAddr((uint32_t)ring);
-  buf = ring;
-  
-	do {
-		INNER_ETH_TX_DESC *desc = (INNER_ETH_TX_DESC *)buf;
-    uint8_t first = desc->TX_0.TX0_b.FS;
-    uint8_t last = desc->TX_0.TX0_b.LS;
-    
-    // clear all bits
-    desc->TX_0.TX0 = 0;
-    desc->TX_0.TX0_b.FS = first;
-    desc->TX_0.TX0_b.LS = last;
-		desc->TX_0.TX0_b.TCH = TRUE;
-		desc->TX_0.TX0_b.IC = TRUE;
-		desc->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_SELF;
-		
-    buf->bufAddr = GLB_ConvertToMappingFromAddr(buf->bufAddr);
-    buf->nextDescAddr = GLB_ConvertToMappingFromAddr(buf->nextDescAddr);
-		buf = (ETH_TX_DESC *)buf->nextDescAddr;
-	} while (buf != ring);
-	
-	ETH->TDESLA = (uint32_t)ring;
- 
-	return TRUE;
-}
-
-void ETH_StartTx() {
-	ETH->OPERATION_b.ST = TRUE;
-}
-
-void ETH_StopTx() {
-	ETH->OPERATION_b.ST = FALSE;
-}
-
-void ETH_ResumeTx() {
-	ETH->TPD = 0;
-}
-
-ETH_TX_DESC *ETH_AcquireFreeTxDesc(void) {
-	uint32_t cur = ETH->CURTDESAPTR;
-	INNER_ETH_TX_DESC *desc = (INNER_ETH_TX_DESC *)cur;
-	
-	do {
-		if (desc->TX_0.TX0_b.OWN == ETH_DESC_OWN_BY_SELF) {
-			return (ETH_TX_DESC *)desc;
-		}
-		desc = (INNER_ETH_TX_DESC *)desc->nextDescAddr;
-	} while ((uint32_t)desc != cur);
-	
-  return 0;		
-}
-
-BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc) {
-	INNER_ETH_TX_DESC *inner;
-	
-	if (!desc) {
-		return FALSE;
-	}
-	
-	inner = (INNER_ETH_TX_DESC *)desc;
-	return (inner->TX_0.TX0_b.OWN == ETH_DESC_OWN_BY_SELF) ? TRUE : FALSE;
-}
-
-void ETH_ReleaseTxDesc(ETH_TX_DESC *desc) {
-	INNER_ETH_TX_DESC *inner;
-	
-	if (!desc) {
-		return;
-	}
-	
-	inner = (INNER_ETH_TX_DESC *)desc;
-	inner->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_HW;
-}
-
-void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr) {
-	if (desc) {
-		desc->bufAddr = GLB_ConvertToMappingFromAddr(bufAddr);;
-	}
-}
-
-uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc) {
-  return (desc ? GLB_ConvertToMappingToAddr(desc->bufAddr) : 0);
-}
-
-BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring) {
-	ETH_RX_DESC *buf = ring;
-	
-	if (!ring) {
-		return FALSE;
-	}
-	
-	if (ETH->OPERATION_b.SR) {
-		return FALSE;
-	}
-
-  /* If code mapping */
-  ring = (ETH_RX_DESC *)GLB_ConvertToMappingFromAddr((uint32_t)ring);
-  buf = ring;
-	do {
-		INNER_ETH_RX_DESC *desc = (INNER_ETH_RX_DESC *)buf;
-		desc->RX_1.RX1_b.RCH = TRUE;
-		desc->RX_1.RX1_b.DIC = FALSE;
-		desc->RX_0.RX0_b.OWN = ETH_DESC_OWN_BY_HW;
-
-    buf->bufAddr = GLB_ConvertToMappingFromAddr(buf->bufAddr);
-    buf->nextDescAddr = GLB_ConvertToMappingFromAddr(buf->nextDescAddr);
-		buf = (ETH_RX_DESC *)buf->nextDescAddr;
-	} while (buf != ring);
-	
-	ETH->RDESLA = (uint32_t)ring;
- 
-	return TRUE;
-}
-
-void ETH_StartRx() {
-	ETH->OPERATION_b.SR = TRUE;
-}
-
-void ETH_StopRx() {
-	ETH->OPERATION_b.SR = FALSE;
-}
-
-void ETH_ResumeRx() {
-	ETH->RPD = 0;
-}
-
-ETH_RX_DESC *ETH_AcquireFreeRxDesc(void) {
-	uint32_t cur = ETH->CURRDESAPTR;
-	INNER_ETH_RX_DESC *desc = (INNER_ETH_RX_DESC *)cur;
-	
-	do {
-		if (desc->RX_0.RX0_b.OWN == ETH_DESC_OWN_BY_SELF) {
-			return (ETH_RX_DESC *)desc;
-		}
-		desc = (INNER_ETH_RX_DESC *)desc->nextDescAddr;
-	} while ((uint32_t)desc != cur);
-	
-  return 0;		
-}
-
-BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc) {
-	INNER_ETH_RX_DESC *inner;
-	
-	if (!desc) {
-		return FALSE;
-	}
-	
-	inner = (INNER_ETH_RX_DESC *)desc;
-	return (inner->RX_0.RX0_b.OWN == ETH_DESC_OWN_BY_SELF) ? TRUE : FALSE;
-}
-
-void ETH_ReleaseRxDesc(ETH_RX_DESC *desc) {
-	INNER_ETH_RX_DESC *inner;
-	
-	if (!desc) {
-		return;
-	}
-	
-	inner = (INNER_ETH_RX_DESC *)desc;
-	inner->RX_0.RX0_b.OWN = ETH_DESC_OWN_BY_HW;
-}
-
-
-void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr) {
-	if (desc) {
-		desc->bufAddr = GLB_ConvertToMappingFromAddr(bufAddr);;
-	}
-}
-
-uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc) {
-  return (desc ? GLB_ConvertToMappingToAddr(desc->bufAddr) : 0);
-}
-
-
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c

@@ -1,400 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_flash.c
-	*
-	* @brief    CMEM7 flash controller source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_flash.h"
-
-typedef struct {
-  union {
-    uint16_t  STATUS;                         /*!< status register                     */
-    
-    struct {
-      uint16_t  WIP:  1;                      /*!< in writting                         */
-      uint16_t  WEL:  1;                      /*!< write enable                        */
-      uint16_t  BP:  5;                       /*!< protection region                   */
-      uint16_t  SRP:  2;                      /*!< protection mode                     */
-      uint16_t  QE:  1;                       /*!< Quad mode                           */
-    } STATUS_b;                               /*!< BitSize                             */
-  } INNER;
-} FLASH_INNER_STATUS;
-
-
-#define NS_IN_A_SECOND                            (1000000000)
-
-#define FLASH_MAX_SIZE                            0x800000
-#define FLASH_PAGE_SIZE                           0x100
-#define FLASH_SECTOR_SIZE                         0x001000
-#define FLASH_BLOCK_32K_SIZE                      0x008000
-#define FLASH_BLOCK_64K_SIZE                      0x010000
-
-#define FLASH_CMD_RD_INNER_STATUS_LOW             0x05
-#define FLASH_CMD_RD_INNER_STATUS_HIGH            0x35
-
-#define FLASH_CMD_WR_WRITE_ENABLE                 0x06
-#define FLASH_CMD_WR_WRITE_DISABLE                0x04
-
-#define FLASH_CME_WR_STATUS_REG                   0x01
-
-#define FLASH_CME_ERASE_SECTOR                    0x20
-#define FLASH_CME_ERASE_BLOCK_32K                 0x52
-#define FLASH_CME_ERASE_BLOCK_64K                 0xD8
-#define FLASH_CME_ERASE_CHIP                      0xC7
-
-#define FLASH_CME_WR_ENTER_DEEP_PD                0xB9
-#define FLASH_CME_WR_EXIT_DEEP_PD                 0xAB
-
-#define FLASH_CME_RD_NORMAL                       0x03
-#define FLASH_CME_RD_FAST                         0x0B
-#define FLASH_CME_RD_FAST_DUAL                    0x3B
-#define FLASH_CME_RD_FAST_QUAD                    0x6B
-
-#define FLASH_CME_WR                              0x02
-
-typedef void (*WAIT)(void);
-static WAIT wait;
-
-static void flash_setClock(uint8_t dividor) {
-	dividor = (dividor < 2) ? 2 : dividor;
-	NOR_FLASH->CTRL0_b.DIV = dividor / 2 - 1;
-}
-
-static void flash_cleanOperation() {
-	NOR_FLASH->TRIGGER_b.OP_CLEAN = TRUE;	
-	while (NOR_FLASH->STATUS_b.BUSY);
-	
-	NOR_FLASH->TRIGGER_b.OP_CLEAN = FALSE;	
-	while (NOR_FLASH->STATUS_b.BUSY);
-}
-
-static uint8_t flash_ReadInnerStatusLow() {
-	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
-	NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_LOW;
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	while (NOR_FLASH->STATUS_b.BUSY);
-	
-	return (uint8_t)NOR_FLASH->DATA;
-}
-
-static uint8_t flash_ReadInnerStatusHigh() {
-  NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 1;
-	NOR_FLASH->CTRL1_b.CMD = FLASH_CMD_RD_INNER_STATUS_HIGH;
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	while (NOR_FLASH->STATUS_b.BUSY);
-	
-	return (uint8_t)NOR_FLASH->DATA;	
-}
-
-//static void flash_WaitInWritting() {
-void flash_WaitInWritting(void) {
-	FLASH_INNER_STATUS s;
-	
-	while (NOR_FLASH->STATUS_b.BUSY);
-	
-	do {
-		s.INNER.STATUS = flash_ReadInnerStatusLow();
-		if (!s.INNER.STATUS_b.WIP) {
-			break;
-		}
-		
-		if (wait) {
-			(*wait)();
-		}
-	} while (1);
-}
-
-static void flash_WriteWriteEnable(BOOL enable) {
-  NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-	NOR_FLASH->CTRL1_b.CMD = 
-	  enable ? FLASH_CMD_WR_WRITE_ENABLE : FLASH_CMD_WR_WRITE_DISABLE;
-	
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	flash_WaitInWritting();
-}
-
-static void flash_WriteStatusReg(FLASH_INNER_STATUS *s) {
-  uint16_t tmp = s->INNER.STATUS;
-	
-	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 2;
-	NOR_FLASH->CTRL1_b.CMD = FLASH_CME_WR_STATUS_REG;
-	NOR_FLASH->DATA = ((tmp << 8) | (tmp >> 8)) << 16;
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	flash_WaitInWritting();
-}
-
-static void flash_Erase(uint8_t cmd, uint32_t addr) {	
-	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-	NOR_FLASH->CTRL1_b.CMD = cmd;
-	NOR_FLASH->CTRL1_b.ADDRESS = addr;
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	flash_WaitInWritting();
-}
-
-static void flash_WriteDeepPowerDownEnable(BOOL enable) {
-  NOR_FLASH->CTRL0_b.RW_BYTE_CNT = 0;
-	NOR_FLASH->CTRL1_b.CMD = 
-	  enable ? FLASH_CME_WR_ENTER_DEEP_PD : FLASH_CME_WR_EXIT_DEEP_PD;
-	
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-	
-	flash_WaitInWritting();
-}
-
-static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) {
-	NOR_FLASH->CTRL0_b.RW_BYTE_CNT = size;
-	NOR_FLASH->CTRL1_b.CMD = cmd;
-	NOR_FLASH->CTRL1_b.ADDRESS = addr;
-	
-	NOR_FLASH->TRIGGER_b.OP_START = TRUE;
-}
-
-//static void flash_WaitReadFifoNotEmpty() {
-void flash_WaitReadFifoNotEmpty(void) {
-	while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) {
-		if (wait) {
-			(*wait)();
-		}
-	}
-}
-
-//static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
-uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) {
-	uint16_t count = 0;
-	
-	while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) {
-  	uint32_t d =	NOR_FLASH->DATA;
-		if (size > 3) {
-			*(data + count++) = d >> 24;
-			*(data + count++) = (d & 0x00FF0000) >> 16;
-			*(data + count++) = (d & 0x0000FF00) >> 8;
-			*(data + count++) = (d & 0x000000FF);
-			size -= 4;
-		} else if (size == 3) {
-			*(data + count++) = (d & 0x00FF0000) >> 16;
-			*(data + count++) = (d & 0x0000FF00) >> 8;
-			*(data + count++) = (d & 0x000000FF);
-			size -= 3;
-		} else if (size == 2) {
-			*(data + count++) = (d & 0x0000FF00) >> 8;
-			*(data + count++) = (d & 0x000000FF);
-			size -= 2;
-		} else if (size == 1) {
-			*(data + count++) = (d & 0x000000FF);
-			size -= 1;
-		}
-	}
-	
-	return count;
-}
-
-static uint16_t flash_WriteFifo(uint16_t size, uint8_t* data) {
-	uint16_t count = 0;
-	
-	while (!NOR_FLASH->STATUS_b.WR_FIFO_FULL && size != 0) { 	
-		uint32_t d = 0;
-		
-		if (size > 3) {
-			d = *(data + count++) << 24;
-			d |= *(data + count++) << 16;
-			d |= *(data + count++) << 8;
-			d |= *(data + count++);
-			size -= 4;
-		} else if (size == 3) {
-			d = *(data + count++) << 24;
-			d |= *(data + count++) << 16;
-			d |= *(data + count++) << 8;
-			size -= 3;
-		} else if (size == 2) {
-			d = *(data + count++) << 24;
-			d |= *(data + count++) << 16;
-			size -= 2;
-		} else if (size == 1) {
-			d = *(data + count++) << 24;
-			size -= 1;
-		}
-		
-		NOR_FLASH->DATA = d;		
-	}
-	
-	return count;
-}
-
-static uint16_t flash_WritePage(uint32_t addr, uint16_t size, uint8_t* data) {
-	uint16_t actualSize, retSize;
-  
-	flash_WriteWriteEnable(TRUE);
-	
-	actualSize = FLASH_PAGE_SIZE - (addr & (FLASH_PAGE_SIZE - 1)); 
-	actualSize = (size > actualSize) ? actualSize : size;
-  retSize = actualSize;
-	
-	flash_RwReq(FLASH_CME_WR, addr, actualSize);
-	
-	while (actualSize != 0) {
-		uint8_t count = flash_WriteFifo(actualSize, data);
-		
-		actualSize -= count;
-		data += count;
-	}
-	
-	flash_WaitInWritting();
-	
-	return retSize;
-}
-
-void FLASH_Init(FLASH_InitTypeDef* init) {
-	FLASH_INNER_STATUS s;
-	
-	assert_param(init);
-	assert_param(IS_FLASH_PROTECT_MODE(init->FLASH_ProtectMode));
-	assert_param(IS_FLASH_PROTECT_REGION(init->FLASH_ProtectRegion));
-	
-	wait = init->FLASH_Wait;
-	flash_setClock(init->FLASH_ClockDividor);
-	
-	flash_cleanOperation();
-	
-	flash_WaitInWritting();
-	
-	s.INNER.STATUS = flash_ReadInnerStatusLow();
-	s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
-	s.INNER.STATUS_b.BP = init->FLASH_ProtectRegion;
-	s.INNER.STATUS_b.SRP = init->FLASH_ProtectMode;
-	s.INNER.STATUS_b.QE = init->FLASH_QuadEnable;
-
-	flash_WriteWriteEnable(TRUE);
-	flash_WriteStatusReg(&s);
-}
-
-void FLASH_GetStatus(uint8_t* ProtectMode, uint8_t* ProtectRegion, BOOL* QuadEnable) {
-	FLASH_INNER_STATUS s;
-	
-	assert_param(ProtectMode);
-	assert_param(ProtectRegion);
-	assert_param(QuadEnable);
-	
-	flash_WaitInWritting();
-	
-	s.INNER.STATUS = flash_ReadInnerStatusLow();
-	s.INNER.STATUS |= ((uint16_t)flash_ReadInnerStatusHigh()) << 8;
-	*ProtectRegion = s.INNER.STATUS_b.BP;
-	*ProtectMode = s.INNER.STATUS_b.SRP;
-	*QuadEnable = (s.INNER.STATUS_b.QE == 1) ?  TRUE : FALSE;
-}
-
-void FLASH_EraseSector(uint32_t addr) {
-	flash_WaitInWritting();
-	flash_WriteWriteEnable(TRUE);
-	
-	addr = (addr << 8) >> 8;
-	addr = addr / FLASH_SECTOR_SIZE * FLASH_SECTOR_SIZE;
-	flash_Erase(FLASH_CME_ERASE_SECTOR, addr);
-}
-
-void FLASH_Erase32kBlock(uint32_t addr) {
-	flash_WaitInWritting();
-	flash_WriteWriteEnable(TRUE);
-	
-	addr = (addr << 8) >> 8;
-	addr = addr / FLASH_BLOCK_32K_SIZE * FLASH_BLOCK_32K_SIZE;
-	flash_Erase(FLASH_CME_ERASE_BLOCK_32K, addr);
-}
-
-void FLASH_Erase64kBlock(uint32_t addr) {
-	flash_WaitInWritting();
-	flash_WriteWriteEnable(TRUE);
-	
-	addr = (addr << 8) >> 8;
-	addr = addr / FLASH_BLOCK_64K_SIZE * FLASH_BLOCK_64K_SIZE;
-	flash_Erase(FLASH_CME_ERASE_BLOCK_64K, addr);
-}
-
-void FLASH_EraseChip(void) {
-	flash_WaitInWritting();
-	flash_WriteWriteEnable(TRUE);
-	flash_Erase(FLASH_CME_ERASE_CHIP, 0x0);
-}
-
-void FLASH_EnableDeepPowerDown(BOOL enable) {
-	flash_WaitInWritting();
-	flash_WriteWriteEnable(TRUE);
-	flash_WriteDeepPowerDownEnable(enable);
-}
-
-void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data) {
-	uint8_t cmd;
-	
-	assert_param(IS_FLASH_READ_MODE(ReadMode));
-	assert_param(addr + size <= FLASH_MAX_SIZE);
-	assert_param(data);
-	
-	if (size == 0) {
-		return ;
-	}
-	
-	flash_WaitInWritting();
-	
-	if (ReadMode == FLASH_READ_MODE_NORMAL) {
-		cmd = FLASH_CME_RD_NORMAL;
-	} else if (ReadMode == FLASH_READ_MODE_FAST) {
-		cmd = FLASH_CME_RD_FAST;
-	} else if (ReadMode == FLASH_READ_MODE_FAST_DUAL) {
-		cmd = FLASH_CME_RD_FAST_DUAL;
-	} else {
-		cmd = FLASH_CME_RD_FAST_QUAD;
-	}
-	
-	flash_RwReq(cmd, addr, size);
-	
-  while (size > 0) {
-		uint16_t count = 0;
-		
-    flash_WaitReadFifoNotEmpty();
-	
-	  count = flash_ReadFifo(size, data);
-		size -= count;
-		data += count;
-	}
-}
-
-void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data) {
-	assert_param(addr + size <= FLASH_MAX_SIZE);
-	assert_param(data);
-	
-	flash_WaitInWritting();
-	
-	while (size > 0) {
-	  uint16_t count = flash_WritePage(addr, size, data);
-
-		addr += count;
-		size -= count;
-		data += count;
-	}
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c

@@ -1,256 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_gpio.c
-	*
-	* @brief    CMEM7 GPIO source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_gpio.h"
-
-#define GPIO_GROUP_GPIO_H 					(GPIO_GROUP_GPIO + 1)
-#define GPIO_GROUP_GPIO_N 					(GPIO_GROUP_GPIO + 2)
-
-#define IS_INNER_GPIO_GROUP(GROUP)  (((GROUP) == GPIO_GROUP_GPIO) || \
-																			((GROUP) == GPIO_GROUP_GPIO_H) || \
-																			((GROUP) == GPIO_GROUP_GPIO_N))
-
-#define GPIO_PWM_CHANNEL_GPIO_H_9 	(GPIO_PWM_CHANNEL_GPIO_31 + 1)
-#define GPIO_PWM_CHANNEL_GPIO_H_19 	(GPIO_PWM_CHANNEL_GPIO_31 + 2)
-#define GPIO_PWM_CHANNEL_GPIO_H_20 	(GPIO_PWM_CHANNEL_GPIO_31 + 3)
-        
-#define IS_INNER_GPIO_PWM_CHANNEL(CHANNEL)  (((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_31) || \
-                                       ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_9) || \
-                                       ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_19) || \
-                                       ((CHANNEL) == GPIO_PWM_CHANNEL_GPIO_H_20))
-static uint32_t gpio_GetClock() {
-	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.GPIO_CLK + 1));
-}
-
-void GPIO_Init(uint8_t Group, uint32_t PositiveTrigger) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  GPIO->GPIO_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		GPIO->GPIO_H_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-	} else {
-		GPIO->GPIO_N_POSITIVE_EDGE_INT_TRIGGER = PositiveTrigger;
-	}
-}
-
-void GPIO_EnableOutput(uint8_t Group, uint32_t Enable) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  GPIO->GPIO_OE = Enable;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		GPIO->GPIO_H_OE = Enable;
-	} else {
-		GPIO->GPIO_N_OE = Enable;
-	}
-}
-
-void GPIO_EnableInt(uint8_t Group, uint32_t Enable) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  GPIO->GPIO_INT_MASK = ~Enable;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		GPIO->GPIO_H_INT_MASK = ~Enable;
-	} else {
-		GPIO->GPIO_N_INT_MASK = ~Enable;
-	}
-}
-
-uint32_t GPIO_GetIntStatus(uint8_t Group) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  return GPIO->GPIO_INT_STATUS;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		return GPIO->GPIO_H_INT_STATUS;
-	} 
-	
-	return GPIO->GPIO_N_INT_STATUS;
-}
-
-void GPIO_ClearInt(uint8_t Group, uint32_t Clear) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  GPIO->GPIO_INT_STATUS = Clear;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		GPIO->GPIO_H_INT_STATUS = Clear;
-	} else {
-		GPIO->GPIO_N_INT_STATUS = Clear;
-	}
-}
-
-uint32_t GPIO_Read(uint8_t Group) {
-  uint32_t data;
-	
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-	  data = GPIO->GPIO_IN;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		data = GPIO->GPIO_H_IN;
-	} else {
-		data = GPIO->GPIO_N_IN;
-	}
-	
-	return data;
-}
-
-void GPIO_Write(uint8_t Group, uint32_t Unmask, uint32_t data) {
-	assert_param(IS_GPIO_GROUP(Group));
-	
-	if (Group == GPIO_GROUP_GPIO) {
-		GPIO->GPIO_OUT_UNMASK = Unmask;
-	  GPIO->GPIO_OUT_DATA = data;
-	} else if (Group == GPIO_GROUP_GPIO_H) {
-		GPIO->GPIO_H_OUT_UNMASK = Unmask;
-	  GPIO->GPIO_H_OUT_DATA = data;
-	} else {
-		GPIO->GPIO_N_OUT_UNMASK = Unmask;
-	  GPIO->GPIO_N_OUT_DATA = data;
-	}
-}
-
-void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLevelNanoSecond) {
-	uint16_t lowTick, highTick;
-	
-	assert_param(IS_GPIO_PWM_CHANNEL(Channel));
-	
-	lowTick = LowLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
-	highTick = HighLevelNanoSecond * (gpio_GetClock() / 1000000) / 1000;
-	lowTick = (lowTick < 1) ? lowTick : lowTick - 1;
-	highTick = (highTick < 1) ? highTick : highTick - 1;
-	
-	if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
-		GPIO->PWM_OUT0_LEN_b.LOW_LEVEL_TICK = lowTick; 
-		GPIO->PWM_OUT0_LEN_b.HIGH_LEVEL_TICK = highTick; 
-	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
-		GPIO->PWM_OUT1_LEN_b.LOW_LEVEL_TICK = lowTick; 
-		GPIO->PWM_OUT1_LEN_b.HIGH_LEVEL_TICK = highTick; 
-	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
-		GPIO->PWM_OUT2_LEN_b.LOW_LEVEL_TICK = lowTick; 
-		GPIO->PWM_OUT2_LEN_b.HIGH_LEVEL_TICK = highTick; 
-  } else {
-		GPIO->PWM_OUT3_LEN_b.LOW_LEVEL_TICK = lowTick; 
-		GPIO->PWM_OUT3_LEN_b.HIGH_LEVEL_TICK = highTick; 
-	}
-}
-
-void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) {
-	assert_param(IS_GPIO_PWM_CHANNEL(Channel));
-	
-	if (Channel == GPIO_PWM_CHANNEL_GPIO_31) {
-		GPIO->PWM_OUT_EN_b.GPIO_31 = Enable; 
-		GPIO->PWM_OUT_SEL_b.GPIO_31 = Enable; 
-	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_9) {
-		GPIO->PWM_OUT_EN_b.GPIO_H_9 = Enable; 
-		GPIO->PWM_OUT_SEL_b.GPIO_H_9 = Enable;
-	} else if (Channel == GPIO_PWM_CHANNEL_GPIO_H_19) {
-		GPIO->PWM_OUT_EN_b.GPIO_H_19 = Enable;
-	GPIO->PWM_OUT_SEL_b.GPIO_H_19 = Enable;		
-  } else {
-		GPIO->PWM_OUT_EN_b.GPIO_H_20 = Enable; 
-		GPIO->PWM_OUT_SEL_b.GPIO_H_20 = Enable;
-	}
-}
-
-/**
-   xjf 20150324
-   
-**/
-void GPIO_SetBits(uint32_t mask)
-{
-  static uint32_t g_GPIO_OUT_UNMASK;
-  static uint32_t g_GPIO_OUT_DATA;
-  static uint32_t g_GPIO_OE;
-	
-	g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
-  g_GPIO_OUT_DATA   = GPIO->GPIO_OUT_DATA   ;
-	g_GPIO_OE         = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK |=mask;  
-  g_GPIO_OE         |=mask;
-	g_GPIO_OUT_DATA   |=mask;
-	
-	GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
-  GPIO->GPIO_OUT_DATA   =g_GPIO_OUT_DATA ;
-	GPIO->GPIO_OE         =g_GPIO_OE       ;
-}
-
-void GPIO_clrBits(uint32_t mask)
-{
-  static uint32_t g_GPIO_OUT_UNMASK;
-  static uint32_t g_GPIO_OUT_DATA;
-  static uint32_t g_GPIO_OE;
-	
-	g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ;
-  g_GPIO_OUT_DATA   = GPIO->GPIO_OUT_DATA   ;
-	g_GPIO_OE         = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK |=mask;  
-  g_GPIO_OE         |=mask;
-	g_GPIO_OUT_DATA   &=(~ mask);
-	
-	GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ;
-  GPIO->GPIO_OUT_DATA   =g_GPIO_OUT_DATA ;
-	GPIO->GPIO_OE         =g_GPIO_OE       ;
-}
-
-uint32_t GPIO_getBits(uint32_t mask)
-{
-  static uint32_t g_GPIO_OUT_UNMASK;
-  //static uint32_t g_GPIO_OUT_DATA;
-  static uint32_t g_GPIO_OE;
-	
-	uint32_t  get_delay = 0;
-	uint32_t  saved_mask;
-	
-	saved_mask=mask;
-	
-	g_GPIO_OUT_UNMASK      = GPIO->GPIO_OUT_UNMASK ;
-	g_GPIO_OE              = GPIO->GPIO_OE ;
-  g_GPIO_OUT_UNMASK     &=(~mask);  
-  g_GPIO_OE             &=(~mask);
-	GPIO->GPIO_OUT_UNMASK  =g_GPIO_OUT_UNMASK ;
-	GPIO->GPIO_OE          =g_GPIO_OE       ;
-	for(get_delay=0;get_delay<100;get_delay++)
-	  {
-    }
-	//get_delay=(GPIO->GPIO_IN)&saved_mask;
-  if(((GPIO->GPIO_IN)&saved_mask)==saved_mask)	
-	   {
-			 return(1);
-	    }		
-	else
-   	{
-			return(0);
-    }
-	
-}
-/**
-   xjf 20150324
-   
-**/

bsp/CME_M7/StdPeriph_Driver/src/cmem7_i2c.c

@@ -1,321 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_i2c.c
-	*
-	* @brief    CMEM7 I2C source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_i2c.h"
-
-#define I2C_INNER_INT_ALL				0x3FF
-
-typedef struct {
-	union {
-    uint32_t  DATA_CMD;                                                           
-    
-    struct {
-      uint32_t  DATA       :  8;                                                                   
-      uint32_t  RD_CMD     :  1;              
-      uint32_t  WR_CMD     :  1;                
-      uint32_t  WR_RD_CMD  :  1;               
-    } DATA_CMD_b;                                   
-  } INNER;
-} I2C_INNER_DATA_CMD;
-
-static uint32_t i2c_GetClock(I2C0_Type* I2Cx) {
-	uint32_t dividor;
-
-	if ((uint32_t)I2Cx == (uint32_t)I2C0) {
-		dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C0_CLK;
-	} else if ((uint32_t)I2Cx == (uint32_t)I2C1) {
-		dividor = GLOBAL_CTRL->CLK_SEL_0_b.I2C1_CLK;
-	} 
-	
-	return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
-}
-
-static uint16_t i2c_NormalizeAddr(I2C0_Type* I2Cx, uint16_t addr) {
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	
-	if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
-		if (I2Cx->CTRL_b.MASTER_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
-			addr &= 0x007F;
-		} else {
-			addr &= 0x3FF;
-		}
-	}
-	
-	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-		if (I2Cx->CTRL_b.SLAVE_ADDR_WIDTH == I2C_ADDR_WIDTH_7BIT) {
-			addr &= 0x007F;
-		} else {
-			addr &= 0x3FF;
-		}
-	}
-	
-	return addr;
-}
-
-static void i2c_ReadClear(uint32_t bit) {
-	uint32_t tmp;
-	tmp = bit;
-	tmp = tmp;	
-}
-		
-void I2C_Init(I2C0_Type* I2Cx, I2C_InitTypeDef* I2C_Init) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(I2C_Init);
-	assert_param(IS_I2C_MODE(I2C_Init->I2C_Mode));
-	assert_param(IS_I2C_ADDR_WIDTH(I2C_Init->I2C_AddressWidth));
-	
-	// reset
-	I2Cx->ENABLE_b.RESET = FALSE;
-	I2Cx->ENABLE_b.RESET = TRUE;
-	
-	// clear interrupt
-	I2Cx->INT_MASK = I2C_INNER_INT_ALL;
-	i2c_ReadClear(I2Cx->CLR_ALL_INT_b.CLEAR);
-	
-	I2Cx->CTRL_b.MODE = I2C_Init->I2C_Mode;
-	if (I2Cx->CTRL_b.MODE == I2C_Mode_Master) {
-	  I2Cx->CTRL_b.MASTER_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
-		I2Cx->TAR_b.START_BYTE = TRUE;
-		I2Cx->TAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
-	}
-	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-	  I2Cx->CTRL_b.SLAVE_ADDR_WIDTH = I2C_Init->I2C_AddressWidth;
-		I2Cx->SAR_b.ADDR10 = i2c_NormalizeAddr(I2Cx, I2C_Init->I2C_Address);
-	}
-	
-	I2Cx->RX_TL_b.THRESHOLD = 0;
-	I2Cx->TX_TL_b.THRESHOLD = 0;
-	
-	I2Cx->SLAVE_NACK_b.NACK = FALSE;
-	
-	if (I2C_Init->timing) {
-		I2Cx->SCL_CNT_b.HIGH_LEVEL_TICK = 
-		  i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
-		I2Cx->SCL_CNT_b.LOW_LEVEL_TICK = 
-		  i2c_GetClock(I2Cx) / I2C_Init->timing->I2C_Freq / 2;
-	  I2Cx->SDA_SETUP_b.TSU_DAT = ((uint64_t)I2C_Init->timing->I2C_TsuDat) * 
-		  i2c_GetClock(I2Cx) / 1000000000;
-		I2Cx->SDA_SETUP_b.TSETUP = ((uint64_t)I2C_Init->timing->I2C_Tsetup) * 
-		  i2c_GetClock(I2Cx) / 1000000000;
-		I2Cx->TSU_STA_SETUP_b.TBUF = ((uint64_t)I2C_Init->timing->I2C_Tbuf) * 
-		  i2c_GetClock(I2Cx) / 1000000000;
-	  I2Cx->TSU_STA_SETUP_b.TSU_STA = ((uint64_t)I2C_Init->timing->I2C_TsuSta) * 
-		  i2c_GetClock(I2Cx) / 1000000000;
-		I2Cx->TSU_STA_SETUP_b.SDA_FILTER_EN = I2C_Init->timing->I2C_SdaFilterEn;
-		I2Cx->TSU_STA_SETUP_b.SDA_FILTER_CNT = I2C_Init->timing->I2C_SdaFilterSpike;
-		I2Cx->TSU_STA_SETUP_b.SCL_FILTER_EN = I2C_Init->timing->I2C_SclFilterEn;
-		I2Cx->TSU_STA_SETUP_b.SCL_FILTER_CNT = I2C_Init->timing->I2C_SclFilterSpike;
-  }
-}
-
-void I2C_Enable(I2C0_Type* I2Cx, BOOL enable) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	
-  I2Cx->ENABLE_b.EN = enable;
-}
-
-void I2C_EnableInt(I2C0_Type* I2Cx, uint32_t Int, BOOL enable) {
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(IS_I2C_INT(Int));
-	
-  if (enable) {
-	  I2Cx->INT_MASK &= ~Int;
-	} else {
-		I2Cx->INT_MASK |= Int;
-	}
-}
-
-BOOL I2C_GetIntStatus(I2C0_Type* I2Cx, uint32_t Int) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(IS_I2C_INT(Int));
-	
-	if (0 != (I2Cx->INT_STATUS & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-void I2C_ClearInt(I2C0_Type* I2Cx, uint32_t Int) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(IS_I2C_INT(Int));
-	
-	if (Int == I2C_INT_RX_FIFO_NOT_EMPTY) {
-		// It can't be clear by sw but read data
-	} 
-	
-	if (Int == I2C_INT_RD_REQUEST) {
-		i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
-	} 
-	
-	if (Int == I2C_INT_TX_ABORT) {
-		i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
-	} 
-	
-	if (Int == I2C_INT_RX_DONE) {
-		i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
-	} 
-	
-	if (Int == I2C_INT_TX_DONE) {
-		i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
-	} 
-}
-
-BOOL I2C_GetStatus(I2C0_Type* I2Cx, uint32_t Status) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(IS_I2C_STATUS(Status));
-	
-	if (0 != (I2Cx->STATUS & Status)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-
-void I2C_ClearStatus(I2C0_Type* I2Cx, uint32_t Status) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(IS_I2C_STATUS(Status));
-	
-	if (Status & I2C_STATUS_RX_FIFO_NOT_EMPTY) {
-		// It can't be clear by sw but read
-	} 
-	
-	if (Status & I2C_STATUS_RD_REQUEST) {
-		i2c_ReadClear(I2Cx->CLR_RD_REQ_b.CLEAR);
-	} 
-	
-	if (Status & I2C_STATUS_TX_ABORT) {
-		i2c_ReadClear(I2Cx->CLR_TX_ABRT_b.CLEAR);
-	} 
-	
-	if (Status & I2C_STATUS_RX_DONE) {
-		i2c_ReadClear(I2Cx->CLR_RX_DONE_b.CLEAR);
-	} 
-	
-	if (Status & I2C_STATUS_TX_DONE) {
-		i2c_ReadClear(I2Cx->CLR_TX_DONE_b.CLEAR);
-	} 
-}
-
-BOOL I2C_MasterReadReq(I2C0_Type* I2Cx, uint8_t size) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	
-	if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
-		return FALSE;
-	}
-
-	if (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) {
-	  return FALSE;
-	}
-	
-	if (size == 0) {
-		return FALSE;
-	}
-	
-	I2Cx->WRITE_READ_CNT_b.RD_BYTE_CNT = size;
-	if (size != 0) {
-    I2C_INNER_DATA_CMD inner;
-    
-    inner.INNER.DATA_CMD_b.DATA = 0;
-		inner.INNER.DATA_CMD_b.RD_CMD = TRUE;
-		inner.INNER.DATA_CMD_b.WR_CMD = FALSE;
-		inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
-		
-		I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
-	}
-	
-	return TRUE;
-}
-
-uint8_t I2C_ReadFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
-	uint8_t count;
-	
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(data);
-	
-	if (!I2Cx->ENABLE_b.EN) {
-		return 0;
-	}
-	
-	count = 0;
-	while (I2Cx->STATUS_b.RX_FIFO_NOT_EMPTY && count < size) {
-		*(data + count++) = I2Cx->DATA_CMD_b.DATA;
-	}
-	
-	return count;
-}
-
-BOOL I2C_WriteReq(I2C0_Type* I2Cx, uint8_t size, uint8_t firstData) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	
-	if (!I2Cx->ENABLE_b.EN || I2Cx->STATUS_b.BUSY) {
-		return FALSE;
-	}
-	
-	if (size == 0) {
-		return FALSE;
-	}
-	
-	I2Cx->WRITE_READ_CNT_b.WR_BYTE_CNT = size;
-	if (size != 0) {
-    I2C_INNER_DATA_CMD inner;
-    
-    inner.INNER.DATA_CMD_b.DATA = firstData	;
-		inner.INNER.DATA_CMD_b.RD_CMD = FALSE;
-		inner.INNER.DATA_CMD_b.WR_CMD = 
-		  (I2Cx->CTRL_b.MODE == I2C_Mode_Slave) ? FALSE : TRUE;
-		inner.INNER.DATA_CMD_b.WR_RD_CMD = FALSE;
-
-		I2Cx->DATA_CMD = inner.INNER.DATA_CMD;
-	}
-
-	return TRUE;
-}
-
-uint8_t I2C_WriteFifo(I2C0_Type* I2Cx, uint8_t size, uint8_t* data) {
-	uint8_t count;
-	
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	assert_param(data);
-	
-	if (!I2Cx->ENABLE_b.EN) {
-		return 0;
-	}
-
-	count = 0;
-	while (I2Cx->STATUS_b.TX_FIFO_NOT_FULL && count < size) {
-	  I2Cx->DATA_CMD_b.DATA = *(data + count++);
-	}
-	
-	return count;	
-}
-
-BOOL I2C_StopReq(I2C0_Type* I2Cx) {
-	assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-	
-	udelay(600);
-	
-	return TRUE;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c

@@ -1,183 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_misc.c
-	*
-	* @brief    CMEM7 miscellaneous file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#include "cmem7_misc.h"
-
-#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
-  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
-}
-
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
-  uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
-  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
-    
-  if (NVIC_InitStruct->NVIC_IRQChannelCmd != FALSE)
-  {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/    
-    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
-    tmppre = (0x4 - tmppriority);
-    tmpsub = tmpsub >> tmppriority;
-
-    tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
-    tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
-    tmppriority = tmppriority << 0x04;
-        
-    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
-    
-    /* Enable the Selected IRQ Channels --------------------------------------*/
-    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-  else
-  {
-    /* Disable the Selected IRQ Channels -------------------------------------*/
-    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
-      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-}
-
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
-{ 
-  /* Check the parameters */
-  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
-  assert_param(IS_NVIC_OFFSET(Offset));  
-   
-  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
-}
-
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_LP(LowPowerMode));
-  
-  if (!NewState)
-  {
-    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
-  } else {
-		SCB->SCR |= LowPowerMode;
-	}
-}
-
-#define DEF_IBUS_OFFSET     0x1FFE0000
-#define DEF_EXT_ADDR        0x08020000
-static BOOL isMappingOn() {
-  /* If default values aren't changed */
-  if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) && 
-    (GLOBAL_CTRL->EXTADDR == DEF_EXT_ADDR)) {
-    return FALSE;
-  }
-
-  return TRUE;
-}
-
-void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) {
-	volatile int n;
-	
-	GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to);
-	GLOBAL_CTRL->EXTADDR = to;
-	
-	// Delay several cycles 
-	for (n = 0; n < 100; n++);
-	GLOBAL_CTRL->ICACHE_b.EN = isIcacheOn;
-	for (n = 0; n < 100; n++);
-}
-
-/*
- * ------------------------------------------------------------------
- * | 0 - 0x20000 | --> 0x20000000 | -> 0x40000000 | -> 0xFFFFFFFF   |
- * |  code SRAM  | map to region  | data SRAM     | map from region |
- * ------------------------------------------------------------------
- */
-#define MAPPING_FROM_REGION_START   0x40000000
-#define MAPPING_TO_REGION_END       0x20000000
-uint32_t GLB_ConvertToMappingFromAddr(uint32_t to) {
-  if (!isMappingOn()) {
-    return to;
-  }
-  
-  if ((to > MAPPING_TO_REGION_END) || (to < GLOBAL_CTRL->EXTADDR)) {
-    return to;
-  }
-  
-  return (to + GLOBAL_CTRL->IBUSOFF);
-}
-
-uint32_t GLB_ConvertToMappingToAddr(uint32_t from) {
-  if (!isMappingOn()) {
-    return from;
-  }
-  
-  if (from < MAPPING_FROM_REGION_START) {
-    return from;
-  }
-  
-  return (from - GLOBAL_CTRL->IBUSOFF);
-}
-
-void GLB_SetNmiIrqNum(uint32_t irq) {
-	GLOBAL_CTRL->NMI_SEL_b.NMI = irq;
-}
-
-void GLB_SelectSysClkSource(uint8_t source) {
-	switch (source) {
-	case SYS_CLK_SEL_DLL :
-		// M7's DLL clock should be fixed at PLL loation 2
-		// In constrast, it's C2R1.
-		// Wait DLL clock stable
-		while (PDLOCK->GCLK_b.C2R1D == 0) ;
-		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_DLL;
-		break;
-	case SYS_CLK_SEL_CRYSTAL :
-		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_CRYSTAL;
-		break;
-	case SYS_CLK_SEL_EXTERNAL :
-		// TODO, Add the condition that makes sure input
-		// external clock is stable
-		// For example :
-		//	PLL location 0
-		// 	while (PDLOCK->GCLK_b.C1R1P == 0) ;
-		// 	DLL location 0
-		// 	while (PDLOCK->GCLK_b.C1R1D == 0) ;
-		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_EXTERNAL;
-		break;
-	case SYS_CLK_SEL_OSC :
-		// Fall through
-	default :
-		GLOBAL_CTRL->CLK_SEL_1_b.SYS_CLK = SYS_CLK_SEL_OSC;
-		break;		
-	}
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c

@@ -1,63 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_rtc.c
-	*
-	* @brief    CMEM7 RTC source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_rtc.h"
-
-#define SECONDS_IN_A_DAY                (86400)
-
-void RTC_ITConfig(uint32_t Int, BOOL Enable) {
-	assert_param(IS_RTC_INT(Int));  
-	
-	if (Enable) {
-	  GLOBAL_CTRL->RTC_INT_EN |= Int;
-	} else {
-		GLOBAL_CTRL->RTC_INT_EN &= ~Int;
-	}
-}
-
-BOOL RTC_GetITStatus(uint32_t Int) {
-	assert_param(IS_RTC_INT(Int)); 
-	
-	if (0 != (RTC->INT_STATUS & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-
-void RTC_ClearITPendingBit(uint32_t Int) {
-  assert_param(IS_RTC_INT(Int));  
-	
-	RTC->INT_STATUS = Int;
-}
-
-uint32_t RTC_GetSecond() {
-	return RTC->SECOND;
-}
-
-uint16_t RTC_GetMillSecond() {
-	return RTC->MILLSECOND_b.MS;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_spi.c

@@ -1,145 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_spi.c
-	*
-	* @brief    CMEM7 SPI source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_spi.h"
-
-void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init) {
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(init);
-	assert_param(IS_SPI_MODE(init->SPI_Mode));
-	assert_param(init->SPI_BitLength != 0);
-	
-	if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_0) {
-		SPIx->CTRL_b.CLK_HIGH = FALSE;
-		SPIx->CTRL_b.NEG_EDGE = TRUE;
-  } else if (init->SPI_Mode == SPI_MODE_CPOL_0_CPHA_1) {
-		SPIx->CTRL_b.CLK_HIGH = FALSE;
-		SPIx->CTRL_b.NEG_EDGE = FALSE;
-  } else if (init->SPI_Mode == SPI_MODE_CPOL_1_CPHA_0) {
-		SPIx->CTRL_b.CLK_HIGH = TRUE;
-		SPIx->CTRL_b.NEG_EDGE = FALSE;
-  } else {
-		SPIx->CTRL_b.CLK_HIGH = TRUE;
-		SPIx->CTRL_b.NEG_EDGE = TRUE;
-  } 		
-
-	SPIx->CTRL_b.RX_EN = init->SPI_RxEn;
-	SPIx->BCNT_b.CNT = init->SPI_BitLength - 1;
-	SPIx->DIV = init->SPI_ClockDividor;
-	SPIx->GAP = (init->SPI_Gap == 0) ? 0 : init->SPI_Gap / 2 + 1;
-}
-
-void SPI_Enable(SPI0_Type* SPIx, BOOL enable) {
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	
-  SPIx->CTRL_b.EN = enable;
-}
-
-void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable) {
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(IS_SPI_INT(Int));
-	
-  if (enable) {
-	  SPIx->INT_MASK &= ~Int;
-	} else {
-		SPIx->INT_MASK |= Int;
-	}
-	
-	SPIx->INT_MASK &= SPI_INT_ALL;
-}
-
-BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int) {
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(IS_SPI_INT(Int));
-	
-	if (0 != (SPIx->INT_STATUS & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int) {
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(IS_SPI_INT(Int));
-	
-	SPIx->INT_STATUS = Int;
-}
-
-uint8_t SPI_ReadFifo(SPI0_Type* SPIx, uint8_t size, uint32_t* data) {
-	uint8_t count;
-	
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(data);
-	
-	if (!SPIx->CTRL_b.EN) {
-		return 0;
-	}
-	
-	count = 0;
-	while (!SPIx->STATUS_b.RFIFO_EMPTY && count < size) {
-	  uint32_t d = SPIx->RW_DATA;
-	  d <<= (32 - SPIx->BCNT_b.CNT - 1);
-	  d >>= (32 - SPIx->BCNT_b.CNT - 1);
-		*(data + count++) = d;
-	}
-	
-	return count;
-}
-	
-uint8_t SPI_WriteFifo(SPI0_Type* SPIx, uint8_t Size, uint32_t* data) {
-	uint8_t count;
-	
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(data);
-	
-	if (!SPIx->CTRL_b.EN) {
-		return 0;
-	}
-	
-	count = 0;
-	while (!SPIx->STATUS_b.TFIFO_FULL && count < Size) {
-	  uint32_t d = *(data + count++);
-		d <<= (32 - SPIx->BCNT_b.CNT - 1);
-		SPIx->RW_DATA = d;
-	}
-	
-	return count;
-}
-
-BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size) {
-	assert_param(IS_SPI_ALL_PERIPH(SPIx));
-	assert_param(size);
-	
-	if (!SPIx->CTRL_b.EN) {
-		return FALSE;
-	}
-	
-	SPIx->TRANS_CNT = size - 1;
-	SPIx->TRANS_START_b.TX_TRIGGER = TRUE;
-	
-	return TRUE;
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_tim.c

@@ -1,80 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_tim.c
-	*
-	* @brief    CMEM7 timer source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_tim.h"
-
-static uint32_t tim_GetClock() {
-	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.TIMER_CLK + 1));
-}
-
-void TIM_Init(TIMER0_Type* Timx, uint16_t Ms) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	Timx->CTRL_b.EN = FALSE;
-	Timx->LEN = tim_GetClock() / 1000 * Ms;
-	Timx->TYPE_b.SIGNLE_SHOT = TRUE;
-}
-
-void TIM_EnableInt(TIMER0_Type* Timx, BOOL Enable) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	if (Enable == TRUE) {
-	  Timx->INT_EN_b.EN_REVERSE = FALSE;
-	} else {
-		Timx->INT_EN_b.EN_REVERSE = TRUE;
-	}
-}
-
-BOOL TIM_GetIntStatus(TIMER0_Type* Timx) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	return (Timx->INT_STA_b.STA ? TRUE : FALSE);
-}
-
-void TIM_ClearInt(TIMER0_Type* Timx) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	Timx->INT_STA_b.STA = 1;
-}
-
-void TIM_Enable(TIMER0_Type* Timx, BOOL Enable) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	Timx->CTRL_b.EN = Enable;
-}
-
-BOOL TIM_IsOverflow(TIMER0_Type* Timx) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	return (Timx->CNT == 0) ? TRUE : FALSE;
-}
-
-uint32_t TIM_GetCounter(TIMER0_Type* Timx) {
-	assert_param(IS_TIM_ALL_PERIPH(Timx));
-	
-	return Timx->CNT;
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_uart.c

@@ -1,177 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_uart.c
-	*
-	* @brief    CMEM7 uart file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-
-#include "cmem7_uart.h"
-
-#define UART_Mode_8b                        1
-#define UART_Mode_8b_Parity                 7
-
-#define UART_BaudMode_0                     0
-#define UART_BaudMode_1                     1
-#define UART_BaudMode_Division							19200
-
-#define UART_WR_MAX_FIFO_SIZE               16	
-
-static uint32_t UART_GetClock(UART0_Type* UARTx) {
-	uint32_t dividor;
-
-	if ((uint32_t)UARTx == (uint32_t)UART0) {
-		dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART0_CLK;
-	} else if ((uint32_t)UARTx == (uint32_t)UART1) {
-		dividor = GLOBAL_CTRL->CLK_SEL_0_b.UART1_CLK;
-	} else if ((uint32_t)UARTx == (uint32_t)UART2) {
-		dividor = GLOBAL_CTRL->CLK_SEL_1_b.UART2_CLK;
-	}
-	
-	return SYSTEM_CLOCK_FREQ / (1 << (dividor + 1));
-}
-
-static uint16_t UART_CalcBaudrateReload(uint32_t FreqHz, uint32_t Baudrate) {
-  if (Baudrate <= UART_BaudMode_Division) {                     
-		/** reload in mode 0
-		  *    reload = FreqHz / 16 * Baudrate
-		  * round up 
-		  *    reload = FreqHz / 16 * Baudrate + 1/ 2
-		  *    reload = (2 * FreqHz + 16 * Baudrate) / 2 * 16 * Baudrate
-		  */
-		return ((FreqHz << 1) + (Baudrate << 4)) / (Baudrate << 5);
-	} 
-	
-	/** reload in mode 1
-		*    reload = Baudrate * 16 * 65536 / FreqHz
-		* round up 
-		*    reload = Baudrate * 16 * 65536 / FreqHz + 1/ 2
-		*    reload = (2 * Baudrate * 16 * 65536 + FreqHz) / 2 * FreqHz
-		*/
-	return ((((uint64_t)(Baudrate)) << 21) + FreqHz) / (FreqHz << 1);
-}
-            
-void UART_Init(UART0_Type* UARTx, UART_InitTypeDef *init) {
- 	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(init);
- 	assert_param(IS_UART_STOPBITS(init->UART_StopBits));
- 	assert_param(IS_UART_PARITY(init->UART_Parity));
-	
-	/* TODO : assume clock is 50MHz */
-	UARTx->BAUDRATE = UART_CalcBaudrateReload(
-	  UART_GetClock(UARTx), init->UART_BaudRate);
-	UARTx->CTRL_b.MODE = 
-	  (init->UART_Parity == UART_Parity_None) ? 
-	  UART_Mode_8b : UART_Mode_8b_Parity;	
-	UARTx->CTRL_b.STOP = init->UART_StopBits;
-	UARTx->CTRL_b.PARITY = 
-	  (init->UART_Parity == UART_Parity_None) ? 
-	  UART_Parity_Even : init->UART_Parity;
-	UARTx->CTRL_b.LOOPBACK = init->UART_LoopBack;
-	UARTx->CTRL_b.RX_EN = init->UART_RxEn;
-	UARTx->CTRL_b.CTS = init->UART_CtsEn;
-	UARTx->CTRL_b.BAUD_MODE = 
-	  (init->UART_BaudRate > UART_BaudMode_Division) ? 
-	  UART_BaudMode_1 : UART_BaudMode_0;
-	UARTx->CTRL_b.FIFO_EN = TRUE;
-	UARTx->CTRL_b.RX_THRESHOLD = UART_WR_MAX_FIFO_SIZE;
-	UARTx->CTRL_b.RX_HALF_FULL = (UART_WR_MAX_FIFO_SIZE >> 1);
-	UARTx->TIMEOUT = 0xFF;
-	
-	UARTx->INT_MASK |= UART_Int_All;
-	UARTx->INT_SEEN &= UART_Int_All;
-}
-
-void UART_EnableInt(UART0_Type* UARTx, uint32_t Int, BOOL enable) {
-	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(IS_UART_INT(Int));
-	
-  if (enable) {
-	  UARTx->INT_MASK &= ~Int;
-	} else {
-		UARTx->INT_MASK |= Int;
-	}
-	
-	UARTx->INT_MASK &= UART_Int_All;
-}
-
-void UART_Enable(UART0_Type* UARTx, BOOL enable) {
-	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	
-	UARTx->RUN_b.EN = enable;
-}
-
-BOOL UART_GetIntStatus(UART0_Type* UARTx, uint32_t Int) {
-	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(IS_UART_INT(Int));
-	
-	if (0 != (UARTx->INT_SEEN & Int)) {
-		return TRUE;
-	}
-	
-	return FALSE;
-}
-
-void UART_ClearInt(UART0_Type* UARTx, uint32_t Int) {
-	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(IS_UART_INT(Int));
-	
-	UARTx->INT_SEEN = Int;
-}
-
-uint8_t UART_Write(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
-	uint8_t count;
-	
-	/* Check the parameters */
-  assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(Data);
-	
-	if (!UARTx->RUN_b.EN) {
-		return 0;
-	}
-	
-	count = 0;
-	while (!UARTx->STATUS_b.TF && count < Size) {
-		UARTx->TX_BUF = *(Data + count++);
-	}
-  
-	return count;
-}
-
-/* return value is actual read data size */
-uint8_t UART_Read(UART0_Type* UARTx, uint8_t Size, uint8_t* Data) {
-	uint8_t count;
-	
-	assert_param(IS_UART_ALL_PERIPH(UARTx));
-	assert_param(Data);
-	
-	if (!UARTx->RUN_b.EN) {
-		return 0;
-	}
-	
-	count = 0;
-	while (UARTx->STATUS_b.RNE && count < Size) {
-		*(Data + count++) = (UARTx->RX_BUF & 0x00FF);
-	}
-	
-	return count;	
-}
-

bsp/CME_M7/StdPeriph_Driver/src/cmem7_usb.c

@@ -1,842 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_usb.c
-	*
-	* @brief    CMEM7 USB source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_usb.h"
-
-static void USB_SET_REG_HPRT(const USB_REG_HPRT *clr, const USB_REG_HPRT *set)
-{
-	USB_REG_HPRT hprt;
-	hprt.HPRT = USB->__HPRT;					// @0x41300440
-	hprt.HPRT_b.POC = hprt.HPRT_b.PEDC = hprt.HPRT_b.PE = hprt.HPRT_b.PCD = 0;
-	if (clr)
-		hprt.HPRT &= (~clr->HPRT);
-	if (set)
-		hprt.HPRT |= (set->HPRT);
-	USB->__HPRT = hprt.HPRT;
-}
-
-void USB_coreInit(uint32_t type)
-{
-	USB->GINTEN = 0;
-	USB->GINTSTS = ~0;
-	GLOBAL_CTRL->USB_PHY_CTRL_b.CKISEL = 0;		// Crystal
-	// core initialization
-	// choose PHY and soft reset
-	USB->GUSBCFG_b.PHY_IF = 0;					// 60MHz, 8bit
-	USB->GUSBCFG_b.ULPI_UTMI_SEL = 0;			// UTMI
-	USB->GUSBCFG_b.PHY_SEL = 0;					// USB 2.0 HS UTMI+
-	USB->GRSTCTL_b.CORE_SOFT_RST = 1;
-	while (USB->GRSTCTL_b.CORE_SOFT_RST == 1) ;
-	while (USB->GRSTCTL_b.AHB_IDLE == 0) ;
-
-	USB->GAHBCFG_b.DMA_EN = 1;
-	USB->GAHBCFG_b.GLBL_INTR_EN = 1;
-	USB->GAHBCFG_b.BST_LEN = 0x1;   			// INCR
-
-	USB->GINTEN_b.RFNE = FALSE;
-
-	USB->GUSBCFG_b.USB_TRD_TIM = 0x9; 			// 8-bit UTMI+
-	USB->GUSBCFG_b.SRP_CAP = (type & 0x10) ? 1 : 0;
-	USB->GUSBCFG_b.HNP_CAP = (type & 0x20) ? 1 : 0;
-	if (type & 0x1) {
-		USB->GUSBCFG_b.FORCE_HOST_MODE = 1;
-		USB->GUSBCFG_b.FORCE_DEVICE_MODE = 0;
-	} else if (type & 0x2) {
-		USB->GUSBCFG_b.FORCE_DEVICE_MODE = 1;
-		USB->GUSBCFG_b.FORCE_HOST_MODE = 0;
-	}
-	udelay(50000);
-}
-
-void USB_EnableInt(BOOL enable)
-{
-	USB->GAHBCFG_b.GLBL_INTR_EN = enable;
-}
-
-void USB_FlushFIFO(uint32_t num)
-{
-	if (num < 0x10) {
-		USB->GRSTCTL_b.TX_FIFO_FLUSH_NUM = num;
-		USB->GRSTCTL_b.TX_FIFO_FLUSH = 1;
-		while (USB->GRSTCTL_b.TX_FIFO_FLUSH);
-	} else if (num > 0x10) {
-		USB->GRSTCTL_b.RX_FIFO_FLUSH = 1;
-		while (USB->GRSTCTL_b.RX_FIFO_FLUSH);
-	} else {
-		USB->GRSTCTL_b.TX_FIFO_FLUSH_NUM = 0;
-		USB->GRSTCTL_b.TX_FIFO_ALL = 1;
-		USB->GRSTCTL_b.TX_FIFO_FLUSH = 1;
-		while (USB->GRSTCTL_b.TX_FIFO_FLUSH);
-	}
-}
-
-BOOL USB_ogtIsBdevID()
-{
-	return USB->GOTGCTL_b.CON_ID_STS ? TRUE : FALSE;
-}
-
-BOOL USB_hostVBus(uint32_t opt)
-{
-	if (opt & 0x2) {
-		USB_REG_HPRT hprt;
-		hprt.HPRT = 0;
-		hprt.HPRT_b.PP = 1;
-		if (opt & 0x1)
-			USB_SET_REG_HPRT(NULL, &hprt);
-		else
-			USB_SET_REG_HPRT(&hprt, NULL);
-	}
-	return USB->__HPRT_b.PP ? TRUE : FALSE;
-}
-
-void USB_hostInit()
-{
-	USB_REG_HPRT hprt;
-	// HOST MODE
-	USB->HCFG_b.FS_LS_PCS = 0x0;				// PHY clock is running at 30/60 MHz
-	USB->HCFG_b.FS_LS_SUPPORT = 0x0;			// HS/FS/LS
-	USB->HCFG_b.EN_SG_DMA = 0x1;				// Enable Scatter/Gather DMA
-	hprt.HPRT = 0;
-	hprt.HPRT_b.PP = 1;
-	USB_SET_REG_HPRT(NULL, &hprt);
-}
-
-void USB_HostResetPort(BOOL rst)
-{
-	USB_REG_HPRT hprt;
-	hprt.HPRT = 0;
-	hprt.HPRT_b.PRESET = 1;
-	if (rst)
-		USB_SET_REG_HPRT(NULL, &hprt);
-	else
-		USB_SET_REG_HPRT(&hprt, NULL);
-}
-
-uint16_t USB_HostGetCurFrame()
-{
-	return USB->HFNUM_b.FN;
-}
-
-void USB_HostSuspendPort()
-{
-	USB_REG_HPRT hprt;
-	hprt.HPRT = 0;
-	hprt.HPRT_b.PS = 1;
-	USB_SET_REG_HPRT(NULL, &hprt);
-}
-
-USB_ENUM_SPEED USB_hostGetEnumSpd()
-{
-	return (USB_ENUM_SPEED)USB->__HPRT_b.SPEED;
-}
-
-BOOL USB_hostPrtConn()
-{
-	return USB->__HPRT_b.PCS ? TRUE : FALSE;
-}
-
-void USB_hostCH0(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
-{
-	USB->HCDMA0_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
-	USB->HCDMA0_b.CTD = ctd;
-	USB->HCTSIZ0_b.PING = ping ? 1 : 0;
-	USB->HCTSIZ0_b.NTD = ntd;
-	USB->HCTSIZ0_b.PID = pid;
-	USB->HCC0_b.MPS = mps;
-	USB->HCC0_b.EP_NUM = epnum;
-	USB->HCC0_b.EP_DIR = in ? 1 : 0;
-	USB->HCC0_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
-	USB->HCC0_b.EP_TYPE = eptype;
-	USB->HCC0_b.EC = 0;
-	USB->HCC0_b.DA = devaddr;
-	USB->HCC0_b.CE = 1;
-}
-
-void USB_hostCH1(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
-{
-	USB->HCDMA1_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
-	USB->HCDMA1_b.CTD = ctd;
-	USB->HCTSIZ1_b.PING = ping ? 1 : 0;
-	USB->HCTSIZ1_b.NTD = ntd;
-	USB->HCTSIZ1_b.PID = pid;
-	USB->HCC1_b.MPS = mps;
-	USB->HCC1_b.EP_NUM = epnum;
-	USB->HCC1_b.EP_DIR = in ? 1 : 0;
-	USB->HCC1_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
-	USB->HCC1_b.EP_TYPE = eptype;
-	USB->HCC1_b.EC = 0;
-	USB->HCC1_b.DA = devaddr;
-	USB->HCC1_b.CE = 1;
-}
-
-void USB_hostCH2(uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
-{
-	USB->HCDMA2_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
-	USB->HCDMA2_b.CTD = ctd;
-	USB->HCTSIZ2_b.PING = ping ? 1 : 0;
-	USB->HCTSIZ2_b.NTD = ntd;
-	USB->HCTSIZ2_b.PID = pid;
-	USB->HCC2_b.MPS = mps;
-	USB->HCC2_b.EP_NUM = epnum;
-	USB->HCC2_b.EP_DIR = in ? 1 : 0;
-	USB->HCC2_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
-	USB->HCC2_b.EP_TYPE = eptype;
-	USB->HCC2_b.EC = 0;
-	USB->HCC2_b.DA = devaddr;
-	USB->HCC2_b.CE = 1;
-}
-
-int USB_hostCHn(uint32_t ch, uint32_t devaddr, OTG_DESCRIPTOR *desc, uint32_t ctd, uint32_t ntd, BOOL ping, uint32_t pid, uint32_t mps, uint32_t epnum, BOOL in, USB_EP_TYPE eptype, USB_ENUM_SPEED speed)
-{
-	USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
-
-	if (ch > 15)
-		return -1;
-	USBn->HCDMA0_b.ADDR = SET_HCDMA_DESC_ADDR(desc);
-	USBn->HCDMA0_b.CTD = ctd;
-	USBn->HCTSIZ0_b.PING = ping ? 1 : 0;
-	USBn->HCTSIZ0_b.NTD = ntd;
-	USBn->HCTSIZ0_b.PID = pid;
-	USBn->HCC0_b.MPS = mps;
-	USBn->HCC0_b.EP_NUM = epnum;
-	USBn->HCC0_b.EP_DIR = in ? 1 : 0;
-	USBn->HCC0_b.LSD = (USB_ENUM_SPEED_LS == speed) ? 1 : 0;
-	USBn->HCC0_b.EP_TYPE = eptype;
-	USBn->HCC0_b.EC = 0;
-	USBn->HCC0_b.DA = devaddr;
-	USBn->HCC0_b.CE = 1;
-	return 0;
-}
-
-int USB_hostCHnHalt(uint32_t ch)
-{
-	uint32_t hcchar;
-	USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
-
-	if (ch > 15)
-		return -1;
-	hcchar = USBn->HCC0;
-	hcchar |= (0x3 << 30);
-	USBn->HCC0 = hcchar;
-	return 0;
-}
-
-BOOL USB_hostPortDisable(BOOL dis)
-{
-	if (dis) {
-		USB_REG_HPRT hprt;
-		hprt.HPRT = 0;
-		hprt.HPRT_b.PE = 1;
-		USB_SET_REG_HPRT(&hprt, NULL);
-	}
-	return USB->__HPRT_b.PE ? FALSE : TRUE;
-}
-
-BOOL USB_roleIsHost()
-{
-	return USB->GINTSTS_b.CUR_MOD ? TRUE : FALSE;
-}
-
-void USB_hostINT_enConn(BOOL en)
-{
-	USB->GINTEN_b.HP = en;
-}
-
-BOOL USB_hostINT_isConn()
-{
-	return USB->GINTSTS_b.HP ? TRUE : FALSE;
-}
-
-BOOL USB_hostINT_isPCD()
-{
-	return USB->__HPRT_b.PCD ? TRUE : FALSE;
-}
-
-void USB_hostINT_clrPCD()
-{
-	USB_REG_HPRT hprt;
-	hprt.HPRT = 0;
-	hprt.HPRT_b.PCD = 1;
-	USB_SET_REG_HPRT(NULL, &hprt);
-}
-
-BOOL USB_hostINT_isPEDC()
-{
-	return USB->__HPRT_b.PEDC ? TRUE : FALSE;
-}
-
-void USB_hostINT_clrPEDC()
-{
-	USB_REG_HPRT hprt;
-	hprt.HPRT = 0;
-	hprt.HPRT_b.PEDC = 1;
-	USB_SET_REG_HPRT(NULL, &hprt);
-}
-
-int USB_hostINT_enDone(uint32_t ch, BOOL en)
-{
-	USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
-
-	if (ch > 15)
-		return -1;
-
-	if (en) {
-		USB->GINTEN_b.HC = 1;
-		USB->HAINT_EN_b.EN |= BIT(ch);
-	} else
-		USB->HAINT_EN_b.EN &= ~BIT(ch);
-
-	USBn->HCINT_EN0_b.TC = USBn->HCINT_EN0_b.CH_HALT = USBn->HCINT_EN0_b.BNA = en ? 1 : 0;
-	return 0;
-}
-
-uint32_t USB_hostINT_isDone(uint32_t ch)
-{
-	uint32_t retval = 0;
-
-	if (ch > 15)
-		return 0;
-
-	if ((USB->GINTSTS_b.HC) && ((USB->HAINT & BIT(ch)))) {
-		USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
-		if (USBn->HCINT0_b.TC) {
-			USBn->HCINT0 = BIT(0);
-			retval |= 0x1;
-		}
-		if (USBn->HCINT0_b.BNA) {
-			USBn->HCINT0 = BIT(11);
-			retval |= 0x2;
-		}
-		if (USBn->HCINT0_b.CH_HALT) {
-			USBn->HCINT0 = BIT(1);
-			retval |= 0x4;
-		}
-		if (USBn->HCINT0_b.ETE) {
-			USBn->HCINT0 = BIT(12);
-			retval |= 0x8;
-		}
-	}
-	return retval;
-}
-
-uint32_t USB_hostINT_isPend(uint32_t ch)
-{
-	uint32_t retval = 0;
-
-	if (ch > 15)
-		return 0;
-
-	if ((USB->GINTSTS_b.HC) && ((USB->HAINT & BIT(ch)))) {
-		USB_Type *USBn = (USB_Type *)(((char *)USB) + (ch * 0x20));
-		retval = USBn->HCINT0;
-		USBn->HCINT0 = retval;
-	}
-	return retval;
-}
-
-void USB_devInit()
-{
-	// If still has some int needed to be enable
-	USB->GINTEN_b.MODE_MIS = TRUE;
-	USB->GINTEN_b.OTG_INT = TRUE;
-
-	// DEVICE MODE
-	USB->GINTEN_b.RFNE = FALSE;					// REG_CS(0x018/*GINTMSK*/, BIT(5)/*NPTxFEmpMsk*/ | BIT(4)/*RxFLvlMsk*/, 0);
-	USB->GINTEN_b.NPTFE = FALSE;
-	USB->DCFG_b.DSPEED = 0;						// HS DEV
-	USB->DCFG_b.NZLSOH = 0;						// REG_CS(0x800/*DCFG*/, BIT(2)/*NZStsOUTHShk*/ | BIT(1) | BIT(0)/*DevSpd: HS*/, BIT(23)/*DescDMA*/ | BIT(13)/*EnDevOutNak*/);
-	USB->DCFG_b.EN_SG_DMA = 1;
-	USB->DCFG_b.EDON = 1;
-	USB->DCTL_b.SD = 0;
-}
-
-USB_ENUM_SPEED USB_devGetEnumSpd()
-{
-	return (USB_ENUM_SPEED)USB->DSTS_b.SPEED;
-}
-
-void USB_devSetAddress(uint32_t addr)
-{
-	USB->DCFG_b.DEVICE_ADDR = addr;
-}
-
-void USB_devEP0out(uint32_t size, uint32_t pktcnt, uint32_t stpcnt, void *desc, BOOL snoop)
-{
-	USB->DOEPTSIZ0_b.SIZE = size;
-	USB->DOEPTSIZ0_b.PACKET_CNT = pktcnt;
-	USB->DOEPTSIZ0_b.SETUP_CNT = stpcnt;
-	USB->DOEPDMA0 = (uint32_t)(desc);
-	USB->DOEPCTL0_b.SNOOP = snoop;
-	USB->DOEPCTL0_b.CNAK = 1;
-	USB->DOEPCTL0_b.EPE = 1;					// REG_CS(0xB00/*DOEPCTL0*/, 0, BIT(31)/*EPEna*/);
-}
-
-BOOL USB_devEP0in(uint32_t size, uint32_t pktcnt, void *desc, uint32_t mps/*8,16,32,64-byte*/)
-{
-	switch (mps) {
-		case 64:	mps = 0x0; break;
-		case 32:	mps = 0x1; break;
-		case 16:	mps = 0x2; break;
-		case 8:		mps = 0x3; break;
-		default:	return FALSE;
-	}
-	USB->DIEPTSIZ0_b.SIZE = size;
-	USB->DIEPTSIZ0_b.PACKET_CNT = pktcnt;
-	USB->DIEPDMA0 = (uint32_t)(desc);
-	USB->DIEPCTL0_b.MPS = mps;
-	USB->DIEPCTL0_b.TX_FIFO_NUM = 0;
-	USB->DIEPCTL0_b.CNAK = 1;
-	USB->DIEPCTL0_b.EPE = 1;					// REG_CS(0xB00/*DOEPCTL0*/, 0, BIT(31)/*EPEna*/);
-	return TRUE;
-}
-
-void USB_devActEP1(const BOOL in, const uint32_t mps, USB_EP_TYPE type)
-{
-	if (in) {
-		USB->DIEPCTL1_b.MPS = mps;
-		USB->DIEPCTL1_b.EP_TYPE = type;
-		USB->DIEPCTL1_b.UAE = (mps != 0) ? 1 : 0;
-	} else {
-		USB->DOEPCTL1_b.MPS = mps;
-		USB->DOEPCTL1_b.EP_TYPE = type;
-		USB->DOEPCTL1_b.UAE = (mps != 0) ? 1 : 0;
-	}
-}
-
-void USB_devActEP2(const BOOL in, const uint32_t mps, USB_EP_TYPE type)
-{
-	if (in) {
-		USB->DIEPCTL2_b.MPS = mps;
-		USB->DIEPCTL2_b.EP_TYPE = type;
-		USB->DIEPCTL2_b.UAE = (mps != 0) ? 1 : 0;
-	} else {
-		USB->DOEPCTL2_b.MPS = mps;
-		USB->DOEPCTL2_b.EP_TYPE = type;
-		USB->DOEPCTL2_b.UAE = (mps != 0) ? 1 : 0;
-	}
-}
-
-void USB_devEP1in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc)
-{
-	USB->DIEPTSIZ1_b.SIZE = size;
-	USB->DIEPTSIZ1_b.PACKET_CNT = pktcnt;
-	USB->DIEPDMA1 = (uint32_t)(desc);
-	USB->DIEPCTL1_b.CNAK = 1;
-	USB->DIEPCTL1_b.SET_D0_PID = (pid >> 0) & 0x1;
-	USB->DIEPCTL1_b.SET_D1_PID = (pid >> 1) & 0x1;
-	USB->DIEPCTL1_b.EPE = 1;
-}
-
-void USB_devEP1out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop)
-{
-	USB->DOEPTSIZ1_b.SIZE = size;
-	USB->DOEPTSIZ1_b.PACKET_CNT = pktcnt;
-	USB->DOEPTSIZ1_b.SETUPCNT_PID = stpcnt;
-	USB->DOEPDMA1 = (uint32_t)(desc);
-	USB->DOEPCTL1_b.EC = snoop;
-	USB->DOEPCTL1_b.CNAK = 1;
-	USB->DOEPCTL1_b.SET_D0_PID = (pid >> 0) & 0x1;
-	USB->DOEPCTL1_b.SET_D1_PID = (pid >> 1) & 0x1;
-	USB->DOEPCTL1_b.EPE = 1;
-}
-
-
-void USB_devEP2in(uint32_t size, uint32_t pktcnt, uint32_t pid, void *desc)
-{
-	USB->DIEPTSIZ2_b.SIZE = size;
-	USB->DIEPTSIZ2_b.PACKET_CNT = pktcnt;
-	USB->DIEPDMA2 = (uint32_t)(desc);
-	USB->DIEPCTL2_b.CNAK = 1;
-	USB->DIEPCTL2_b.SET_D0_PID = (pid >> 0) & 0x1;
-	USB->DIEPCTL2_b.SET_D1_PID = (pid >> 1) & 0x1;
-	USB->DIEPCTL2_b.EPE = 1;
-}
-
-void USB_devEP2out(uint32_t size, uint32_t pktcnt, uint32_t pid, uint32_t stpcnt, void *desc, BOOL snoop)
-{
-	USB->DOEPTSIZ2_b.SIZE = size;
-	USB->DOEPTSIZ2_b.PACKET_CNT = pktcnt;
-	USB->DOEPTSIZ2_b.SETUPCNT_PID = stpcnt;
-	USB->DOEPDMA2 = (uint32_t)(desc);
-	USB->DOEPCTL2_b.EC = snoop;
-	USB->DOEPCTL2_b.CNAK = 1;
-	USB->DOEPCTL2_b.SET_D0_PID = (pid >> 0) & 0x1;
-	USB->DOEPCTL2_b.SET_D1_PID = (pid >> 1) & 0x1;
-	USB->DOEPCTL2_b.EPE = 1;
-}
-
-void USB_devNAKhandshake(uint32_t ep, BOOL in, BOOL en)
-{
-	switch (ep) {
-	case 0:
-		if (in) {
-			if (en) USB->DIEPCTL0_b.SNAK = 1; else USB->DIEPCTL0_b.CNAK = 1;
-		} else {
-			if (en) USB->DOEPCTL0_b.SNAK = 1; else USB->DOEPCTL0_b.CNAK = 1;
-		}
-		break;
-	case 1:
-		if (in) {
-			if (en) USB->DIEPCTL1_b.SNAK = 1; else USB->DIEPCTL1_b.CNAK = 1;
-		} else {
-			if (en) USB->DOEPCTL1_b.SNAK = 1; else USB->DOEPCTL1_b.CNAK = 1;
-		}
-		break;
-	case 2:
-		if (in) {
-			if (en) USB->DIEPCTL2_b.SNAK = 1; else USB->DIEPCTL2_b.CNAK = 1;
-		} else {
-			if (en) USB->DOEPCTL2_b.SNAK = 1; else USB->DOEPCTL2_b.CNAK = 1;
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-BOOL USB_devSTALLhandshake(uint32_t ep, BOOL in, BOOL en)
-{
-	BOOL retval = FALSE;
-	switch (ep) {
-	case 0:
-		if (in) {
-			retval = USB->DIEPCTL0_b.STALL;
-			USB->DIEPCTL0_b.STALL = en ? 1 : 0;
-		} else {
-			retval = USB->DOEPCTL0_b.STALL;
-			USB->DOEPCTL0_b.STALL = en ? 1 : 0;
-		}
-		break;
-	case 1:
-		if (in) {
-			retval = USB->DIEPCTL1_b.STALL;
-			USB->DIEPCTL1_b.STALL = en ? 1 : 0;
-		} else {
-			retval = USB->DOEPCTL1_b.STALL;
-			USB->DOEPCTL1_b.STALL = en ? 1 : 0;
-		}
-		break;
-	case 2:
-		if (in) {
-			retval = USB->DIEPCTL2_b.STALL;
-			USB->DIEPCTL2_b.STALL = en ? 1 : 0;
-		} else {
-			retval = USB->DOEPCTL2_b.STALL;
-			USB->DOEPCTL2_b.STALL = en ? 1 : 0;
-		}
-		break;
-	default:
-		break;
-	}
-	return retval;
-}
-
-void USB_devINT_enDone(uint32_t ep, BOOL in, BOOL en)
-{
-	if (in) {
-		USB->DIEPEN_b.TIMEOUT = en ? 1 : 0;
-		USB->DIEPEN_b.TC = en ? 1 : 0;
-		if (en) {
-			USB->GINTEN_b.IEP_INT = 1;
-			USB->DAINT_EN_b.IN_EN |= BIT(ep);
-		} else
-			USB->DAINT_EN_b.IN_EN &= ~BIT(ep);
-	} else {
-		USB->DOEPEN_b.SPD = en ? 1 : 0;
-		USB->DOEPEN_b.TC = en ? 1 : 0;
-		if (en) {
-			USB->GINTEN_b.OEP_INT = 1;
-			USB->DAINT_EN_b.OUT_EN |= BIT(ep);
-		} else
-			USB->DAINT_EN_b.OUT_EN &= ~BIT(ep);
-	}
-}
-
-uint32_t USB_devINT_isDone(uint32_t ep, BOOL in)
-{
-	int32_t retval = 0;
-	if (in) {
-		if (USB->GINTSTS_b.IEP_INT)
-		switch (ep) {
-		case 0:
-			if (USB->DIEPINT0_b.TC) {
-				retval |= 0x1;
-				USB->DIEPINT0 = BIT(0);
-			}
-			if (USB->DIEPINT0_b.BNA) {
-				retval |= 0x2;
-				USB->DIEPINT0 = BIT(9);
-			}
-			break;
-		case 1:
-			if (USB->DIEPINT1_b.TC) {
-				retval |= 0x1;
-				USB->DIEPINT1 = BIT(0);
-			}
-			if (USB->DIEPINT1_b.BNA) {
-				retval |= 0x2;
-				USB->DIEPINT1 = BIT(9);
-			}
-			break;
-		case 2:
-			if (USB->DIEPINT2_b.TC) {
-				retval |= 0x1;
-				USB->DIEPINT2 = BIT(0);
-			}
-			if (USB->DIEPINT2_b.BNA) {
-				retval |= 0x2;
-				USB->DIEPINT2 = BIT(9);
-			}
-		default:
-			break;
-		}
-	} else {
-		if (USB->GINTSTS_b.OEP_INT)
-		switch (ep) {
-		case 0:
-			if (USB->DOEPINT0_b.TC) {
-				retval |= 0x1;
-				USB->DOEPINT0 = BIT(0);
-			}
-			if (USB->DOEPINT0_b.SETUP) {
-				retval |= 0x4;
-				USB->DOEPINT0 = BIT(3);
-			}
-			break;
-		case 1:
-			if (USB->DOEPINT1_b.TC) {
-				retval |= 0x1;
-				USB->DOEPINT1 = BIT(0);
-			}
-			if (USB->DOEPINT1_b.BNA) {
-				retval |= 0x2;
-				USB->DOEPINT1 = BIT(9);
-			}
-			break;
-		case 2:
-			if (USB->DOEPINT2_b.TC) {
-				retval |= 0x1;
-				USB->DOEPINT2 = BIT(0);
-			}
-			if (USB->DOEPINT2_b.BNA) {
-				retval |= 0x2;
-				USB->DOEPINT2 = BIT(9);
-			}
-			break;
-		default:
-			break;
-		}
-	}
-	return retval;
-}
-
-void USB_INT_enOTG(BOOL en)
-{
-	USB->GINTEN_b.OTG_INT = en;
-}
-
-BOOL USB_INT_isOTG()
-{
-	return USB->GINTSTS_b.OTG_INT ? TRUE : FALSE;
-}
-
-BOOL USB_INT_isOTGon(USB_INT_OTG otg)
-{
-	switch (otg) {
-	case USB_INT_OTG_SESEND:
-		return USB->GOTGINT_b.SES_END_DET ? TRUE : FALSE;
-		break;
-	case USB_INT_OTG_STANDAUP:
-		return USB->GOTGINT_b.A_DEV_TOUT_CHG ? TRUE : FALSE;
-		break;
-	case USB_INT_OTG_HNDETECT:
-		return USB->GOTGINT_b.HST_NEG_DET ? TRUE : FALSE;
-		break;
-	case USB_INT_OTG_HNSUCCHG:
-		return USB->GOTGINT_b.HST_NEG_SUC_STS_CHNG ? TRUE : FALSE;
-		break;
-	case USB_INT_OTG_KEEPAPP:
-		return USB->GOTGINT_b.DBNCE_DONE ? TRUE : FALSE;
-		break;
-	default:
-		break;
-	}
-	return FALSE;
-}
-
-void USB_INT_clrOTGon(USB_INT_OTG otg)
-{
-	switch (otg) {
-	case USB_INT_OTG_SESEND:
-		USB->GOTGINT = BIT(2);
-		break;
- 	case USB_INT_OTG_STANDAUP:
-		USB->GOTGINT = BIT(18);
-		break;
-	case USB_INT_OTG_HNDETECT:
-		USB->GOTGINT = BIT(17);
-		break;
-	case USB_INT_OTG_HNSUCCHG:
-		USB->GOTGINT = BIT(9);
-		break;
-	case USB_INT_OTG_KEEPAPP:
-		USB->GOTGINT = BIT(19);
-		break;
-	default:
-		break;
-	}
-}
-
-void USB_INT_enGP(USB_INT_GP name, BOOL en)
-{
-	switch (name) {
-	case USB_INT_GP_HOST_DISC:
-		USB->GINTEN_b.DD = en ? 1 : 0;
-		break;
-	case USB_INT_GP_DEV_RESET:
-		USB->GINTEN_b.USB_RST = en ? 1 : 0;
-		break;
-	case USB_INT_GP_DEV_ENUMDONE:
-		USB->GINTEN_b.ENUM_DONE = en ? 1 : 0;
-		break;
-	case USB_INT_GP_DEV_SUSP:
-		USB->GINTEN_b.USB_SUS = en ? 1 : 0;
-		break;
-	case USB_INT_GP_DEV_EARLY:
-		USB->GINTEN_b.EARLY_SUS = en ? 1 : 0;
-		break;
-	case USB_INT_GP_SOF:
-		USB->GINTEN_b.SOF = en ? 1 : 0;
-		break;
-	case USB_INT_GP_MIS:
-		USB->GINTEN_b.MODE_MIS = en ? 1 : 0;
-		break;
-	case USB_INT_GP_IDCHG:
-		USB->GINTEN_b.CIDSC = en ? 1 : 0;
-		break;
-	case USB_INT_GP_SESSREQ:
-		USB->GINTEN_b.SR = en ? 1 : 0;
-		break;
-	default:
-		break;
-	}
-}
-
-BOOL USB_INT_isGP(USB_INT_GP name)
-{
-	switch (name) {
-	case USB_INT_GP_HOST_DISC:
-		return USB->GINTSTS_b.DD ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_DEV_RESET:
-		return USB->GINTSTS_b.USB_RST ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_DEV_ENUMDONE:
-		return USB->GINTSTS_b.ENUM_DONE ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_DEV_SUSP:
-		return USB->GINTSTS_b.USB_SUS ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_DEV_EARLY:
-		return USB->GINTSTS_b.EARLY_SUS ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_SOF:
-		return USB->GINTSTS_b.SOF ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_MIS:
-		return USB->GINTSTS_b.MODE_MIS ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_IDCHG:
-		return USB->GINTSTS_b.CIDSC ? TRUE : FALSE;
-		break;
-	case USB_INT_GP_SESSREQ:
-		return USB->GINTSTS_b.SR ? TRUE : FALSE;
-		break;
-	default:
-		break;
-	}
-	return FALSE;
-}
-
-void USB_INT_clrGP(USB_INT_GP name)
-{
-	switch (name) {
-	case USB_INT_GP_HOST_DISC:
-		USB->GINTSTS = BIT(29);
-		break;
-	case USB_INT_GP_DEV_RESET:
-		USB->GINTSTS = BIT(12);
-		break;
-	case USB_INT_GP_DEV_ENUMDONE:
-		USB->GINTSTS = BIT(13);
-		break;
-	case USB_INT_GP_DEV_SUSP:
-		USB->GINTSTS = BIT(11);
-		break;
-	case USB_INT_GP_DEV_EARLY:
-		USB->GINTSTS = BIT(10);
-		break;
-	case USB_INT_GP_SOF:
-		USB->GINTSTS = BIT(3);
-		break;
-	case USB_INT_GP_MIS:
-		USB->GINTSTS = BIT(1);
-		break;
-	case USB_INT_GP_IDCHG:
-		USB->GINTSTS = BIT(28);
-		break;
-	case USB_INT_GP_SESSREQ:
-		USB->GINTSTS = BIT(30);
-		break;
-	default:
-		break;
-	}
-}
-
-BOOL USB_otgControl(USB_OTG_CTL ctl, BOOL val)
-{
-	BOOL retval = FALSE;
-	switch (ctl) {
-	case USB_OTG_DEV_HNSUCC:
-		retval = USB->GOTGCTL_b.HST_NEG_SCS ? TRUE : FALSE;
-		break;
-	case USB_OTG_DEV_HNPREQ:
-		retval = USB->GOTGCTL_b.HNP_REQ ? TRUE : FALSE;
-		USB->GOTGCTL_b.HNP_REQ = val ? 1 : 0;
-		break;
-	case USB_OTG_HST_HNPENABLE:
-		retval = USB->GOTGCTL_b.HST_SET_HNP_EN ? TRUE : FALSE;
-		USB->GOTGCTL_b.HST_SET_HNP_EN = val ? 1 : 0;
-		break;
-	case USB_OTG_DEV_HNPENABLE:
-		retval = USB->GOTGCTL_b.DEV_HNP_EN ? TRUE : FALSE;
-		USB->GOTGCTL_b.DEV_HNP_EN = val ? 1 : 0;
-		break;
-	default:
-		break;
-	}
-	return retval;
-}

bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c

@@ -1,63 +0,0 @@
-/**
-	*****************************************************************************
-	* @file     cmem7_wdg.c
-	*
-	* @brief    CMEM7 watchdog source file
-	*
-	*
-	* @version  V1.0
-	* @date     3. September 2013
-	*
-	* @note               
-	*           
-	*****************************************************************************
-	* @attention
-	*
-	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
-	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
-	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
-	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
-	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
-	*
-	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
-	*****************************************************************************
-	*/
-	
-#include "cmem7_wdg.h"
-
-static uint32_t wdg_GetClock() {
-	return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1));
-}
-
-void WDG_DeInit(void){
-  SOFT_RESET->SOFTRST_b.WDT_n = 0;
-	SOFT_RESET->SOFTRST_b.WDT_n = 1;
-}
-
-void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond) {
-	assert_param(IS_WDG_TRIGGER_MODE(trigger));
-	
-	WDG->INT_CTRL_b.TRIGGER_MODE = trigger;
-	WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000;
-}
-
-void WDG_ITConfig(uint8_t Int, BOOL Enable) {
-	assert_param(IS_WDG_INT(Int));
-	
-	WDG->CTRL_b.INT_LEN = Int;
-	WDG->INT_CTRL_b.MASK = !Enable;
-}
-
-BOOL WDG_GetITStatus() {
-	return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE;
-}
-
-void WDG_ClearITPendingBit() {
-	WDG->INT_STA_b.STA = 1;
-}
-
-void WDG_Cmd(BOOL Enable) {
-	WDG->CTRL_b.EN = Enable;
-}
-

bsp/CME_M7/applications/application.c

@@ -1,46 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-08-03     aozima       first implementation
- */
-
-#include <board.h>
-#include <rtthread.h>
-
-void rt_init_thread_entry(void* parameter)
-{
-    rt_components_init();
-
-#ifdef RT_USING_LWIP
-    cme_m7_eth_init();
-
-    set_if("e0", "192.168.1.99", "192.168.1.1", "255.255.255.0");
-#endif /* RT_USING_LWIP */
-}
-
-int rt_application_init()
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init",
-        rt_init_thread_entry,
-		RT_NULL,
-        2048,
-		RT_THREAD_PRIORITY_MAX/3,
-		20);
-
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
-    return 0;
-}
-
-/*@}*/

bsp/CME_M7/applications/led.c

@@ -1,39 +0,0 @@
-#include <rtthread.h>
-#include <board.h>
-
-static void led_thread_entry(void* parameter)
-{
-    /* Configure GPIO as Output mode */
-    GPIO_Init(GPIO_GROUP_GPIO, 0xFFFFFFFF);
-    GPIO_EnableOutput(GPIO_GROUP_GPIO, 0x81010101);
-
-    // LED4, 200ns period
-    GPIO_InitPwm(GPIO_PWM_CHANNEL_GPIO_31, 100, 100);
-    GPIO_EnablePwm(GPIO_PWM_CHANNEL_GPIO_31, TRUE);
-
-    while(1)
-    {
-        GPIO_Write(GPIO_GROUP_GPIO, 0x01010101, 0x55555555);
-        rt_thread_delay(RT_TICK_PER_SECOND/3);
-        GPIO_Write(GPIO_GROUP_GPIO, 0x01010101, 0xAAAAAAAA);
-        rt_thread_delay(RT_TICK_PER_SECOND/3);
-    }
-}
-
-static int led_thread_init(void)
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("led",
-                           led_thread_entry,
-                           RT_NULL,
-                           2048,
-                           RT_THREAD_PRIORITY_MAX - 1,
-                           1);
-
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
-    return 0;
-}
-INIT_APP_EXPORT(led_thread_init);

bsp/CME_M7/applications/startup.c

@@ -1,91 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-08-03     aozima       first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-/**
- * @addtogroup CME_M7
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define SRAM_BEGIN    (&__bss_end)
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init tick */
-    rt_system_tick_init();
-
-    /* init kernel object */
-    rt_system_object_init();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-    rt_system_heap_init((void*)SRAM_BEGIN, (void*)SRAM_END);
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int main(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    return 0;
-}
-
-/*@}*/

bsp/CME_M7/drivers/SConscript

@@ -1,20 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'drivers')
-
-src	= ['board.c']
-
-# add uart driver.
-src	+= ['uart.c']
-
-# add EMAC driver for Lwip.
-if GetDepend('RT_USING_LWIP') == True:
-    src += ['emac.c', 'app_phy.c']
-
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/CME_M7/drivers/app_phy.c

@@ -1,125 +0,0 @@
-#include <stdio.h>
-#include "app_phy.h"
-
-#define PHY_BASE_ADDR   						0x7
-
-#define PHY_REG_CONTROL             0x0
-#define PHY_REG_STATUS              0x1
-#define PHY_REG_ANE                 0x6
-#define PHY_REG_SPEC_STATUS         0x11
-#define PHY_REG_EXTEND_STATUS				0x1B
-
-#define PHY_BIT_CONTROL_RESET           0x8000			/*!< Control reg : reset */
-#define PHY_BIT_CONTROL_ANEN            0x1000			/*!< Control reg : auto-negotiation enable */
-#define PHY_BIT_CONTROL_RSAN            0x0200			/*!< Control reg : auto-negotiation restart */
-
-#define PHY_BIT_STATUS_ANC              0x0020			/*!< Status reg : auto-negotiation complete */
-#define PHY_BIT_STATUS_LINK             0x0004			/*!< Status reg : link is up */
-
-#define PHY_BIT_ANE_LPAN                0x0001			/*!< ANE reg : link partner can auto-neg */
-
-#define PHY_BIT_SPEED                   0xC000      /*!< specific status reg : speed */
-#define PHY_BIT_DUPLEX                  0x2000      /*!< specific status reg : duplex */
-
-#define PHY_BIT_AUTO_MEDIA_DISABLE      0x8000      /*!< extended status reg : auto media select disable */
-#define PHY_BIT_AUTO_MEDIA_REG_DISABLE  0x0200      /*!< extended status reg : auto media register select disable */
-
-void phy_Reset() {
-	ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_CONTROL, PHY_BIT_CONTROL_RESET);
-
-	while (1) {
-		uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_CONTROL);
-	  if ((ret & PHY_BIT_CONTROL_RESET) == 0) {
-			break;
-		}
-	}
-}
-
-void phy_AutoMediaSelect() {
-	uint32_t data;
-
-	// auto media and auto media register selection
-	data = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_EXTEND_STATUS);
-	data &= ~PHY_BIT_AUTO_MEDIA_DISABLE;
-	data &= ~PHY_BIT_AUTO_MEDIA_REG_DISABLE;
-	ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_EXTEND_STATUS, data);
-}
-
-void phy_AutoNeg()
-{
-    uint32_t data;
-
-    data = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_CONTROL);
-    data |= (PHY_BIT_CONTROL_ANEN | PHY_BIT_CONTROL_RSAN);
-    ETH_PhyWrite(PHY_BASE_ADDR, PHY_REG_CONTROL, data);
-
-    while (1)
-    {
-        uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_STATUS);
-        if ((ret & PHY_BIT_STATUS_ANC) == PHY_BIT_STATUS_ANC)
-        {
-            break;
-        }
-        rt_thread_delay(1);
-    }
-}
-
-BOOL phy_IsLink() {
-	uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_STATUS);
-	return (ret & PHY_BIT_STATUS_LINK) ? TRUE : FALSE;
-}
-
-BOOL phy_PartnerCanAutoNeg() {
-	uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_ANE);
-	return (ret & PHY_BIT_ANE_LPAN) ? TRUE : FALSE;
-}
-
-uint32_t phy_GetSpeed() {
-	uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_SPEC_STATUS);
-	return ((ret & PHY_BIT_SPEED) >> 14);
-}
-
-uint32_t phy_GetDuplex() {
-	uint32_t ret = ETH_PhyRead(PHY_BASE_ADDR, PHY_REG_SPEC_STATUS);
-	return ((ret & PHY_BIT_DUPLEX) >> 13);
-}
-
-BOOL phy_Init() {
-	phy_AutoMediaSelect();
-	phy_AutoNeg();
-
-	if (!phy_PartnerCanAutoNeg()) {
-		printf("Warning:: PHY's partner can't do auto-negotiation\n");
-	}
-
-	if (!phy_IsLink()) {
-		printf("link is down\n");
-		return FALSE;
-	}
-
-	{
-		uint32_t speed = phy_GetSpeed();
-		if (speed == PHY_SPEED_10) {
-			speed = 10;
-		} else if (speed == PHY_SPEED_100) {
-			speed = 100;
-		} else if (speed == PHY_SPEED_1000) {
-			speed = 1000;
-		}
-
-		printf("PHY runs in %dM speed %s duplex\n",
-			speed, (phy_GetDuplex() == PHY_DUPLEX_HALF) ? "half" : "full");
-	}
-
-	// After auto-negcioation, Mawell PHY need some
-	// time to initial itself.
-	// So we have to delay some time since different
-	// connection way, such as direct wire, hub, switch.
-	// If not to delay, the first several sent frame
-	// may be lost.
-	// Please according to actual environment to tune
-	// this delay.
-	udelay(200000);
-
-	return TRUE;
-}

bsp/CME_M7/drivers/app_phy.h

@@ -1,32 +0,0 @@
-#ifndef __APP_PHY_H
-#define __APP_PHY_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "cmem7_includes.h"
-
-#define PHY_SPEED_10           			0x0         /*!< SPEED : 10M  */
-#define PHY_SPEED_100          			0x1         /*!< SPEED : 100M  */
-#define PHY_SPEED_1000         			0x2         /*!< SPEED : 1000M  */
-	 
-#define PHY_DUPLEX_HALF        			0x0         /*!< DUPLEX : half  */
-#define PHY_DUPLEX_FULL        			0x1         /*!< DUPLEX : full  */
-	 
-void phy_Reset(void);
-void phy_AutoNeg(void);
-BOOL phy_IsLink(void);
-BOOL phy_PartnerCanAutoNeg(void);
-uint32_t phy_GetSpeed(void);
-uint32_t phy_GetDuplex(void);
-BOOL phy_Init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif 
-
-
-

bsp/CME_M7/drivers/board.c

@@ -1,62 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2014, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-08-03     aozima       first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-/**
- * @addtogroup CME_M7
- */
-
-/*@{*/
-
-/**
- * This is the timer interrupt service routine.
- *
- */
-void SysTick_Handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void idle_hook(void)
-{
-    __WFI();
-}
-
-/**
- * This function will initial board.
- */
-void rt_hw_board_init()
-{
-    //rt_thread_idle_sethook(idle_hook);
-
-    /* Configure the NVIC Preemption Priority Bits */
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-
-    SysTick_Config(SYSTEM_CLOCK_FREQ / RT_TICK_PER_SECOND);
-
-    rt_components_board_init();
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-}
-
-/*@}*/

bsp/CME_M7/drivers/board.h

@@ -1,31 +0,0 @@
-/*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2014, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-08-03     aozima       first implementation
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include "cmem7_includes.h"
-//#include "cmem7_retarget.h"
-
-#define SRAM_SIZE         64	// KB
-#define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
-
-//#define RT_USING_UART0
-//#define RT_USING_UART1
-#define RT_USING_UART2
-
-void rt_hw_board_init(void);
-
-#endif
-

bsp/CME_M7/drivers/emac.c

@@ -1,444 +0,0 @@
-/*
- * File      : emac.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-08-29     aozima       first implementation
- */
-
-#include <rtthread.h>
-#include <netif/ethernetif.h>
-#include "lwipopts.h"
-
-#include "board.h"
-
-#include "app_phy.h"
-
-/* debug option */
-#define ETH_DEBUG
-//#define ETH_RX_DUMP
-//#define ETH_TX_DUMP
-
-#ifdef ETH_DEBUG
-#define CME_ETH_PRINTF          rt_kprintf
-#else
-#define CME_ETH_PRINTF(...)
-#endif
-
-#define MAX_ADDR_LEN 6
-struct rt_cme_eth
-{
-    /* inherit from ethernet device */
-    struct eth_device parent;
-
-    /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
-
-    uint32_t    ETH_Speed;
-    uint32_t    ETH_Mode;
-
-    struct rt_semaphore tx_buf_free;
-    struct rt_mutex     lock;
-};
-static struct rt_cme_eth cme_eth_device;
-
-#if defined(ETH_RX_DUMP) ||  defined(ETH_TX_DUMP)
-static void packet_dump(const char * msg, const struct pbuf* p)
-{
-    const struct pbuf* q;
-    rt_uint32_t i,j;
-    rt_uint8_t *ptr;
-
-    rt_kprintf("%s %d byte\n", msg, p->tot_len);
-
-    i=0;
-    for(q=p; q != RT_NULL; q= q->next)
-    {
-        ptr = q->payload;
-
-        for(j=0; j<q->len; j++)
-        {
-            if( (i%8) == 0 )
-            {
-                rt_kprintf("  ");
-            }
-            if( (i%16) == 0 )
-            {
-                rt_kprintf("\r\n");
-            }
-            rt_kprintf("%02x ",*ptr);
-
-            i++;
-            ptr++;
-        }
-    }
-
-    rt_kprintf("\n\n");
-}
-#else
-#define packet_dump(...)
-#endif /* dump */
-
-/////////////////////////////////////////////////////////////////
-uint32_t rxTotalMemory = 0x2000;
-uint32_t rxDescNum = 3;
-uint32_t rxBufSize = 0x400;
-uint32_t rxBaseAddr = 0x2000C000;// C000-48K
-uint32_t txBaseAddr = 0x2000E000;// E000-56K
-uint32_t txTotalMemory = 0x2000;
-BOOL isRxNoBuf = FALSE;
-
-#define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_RXBUFNB        	4
-#define ETH_TXBUFNB        	2
-
-struct eth_rx_buffer
-{
-    ETH_RX_DESC desc;
-    uint32_t buffer[ETH_MAX_PACKET_SIZE/4];
-};
-
-struct eth_tx_buffer
-{
-    ETH_TX_DESC desc;
-    uint32_t buffer[ETH_MAX_PACKET_SIZE/4];
-};
-
-static struct eth_rx_buffer rx_buffer[ETH_RXBUFNB];
-static struct eth_tx_buffer tx_buffer[ETH_TXBUFNB];
-
-static void RxDescChainInit(void)
-{
-    uint32_t i;
-
-    // initialize rx descriptor
-    ETH_RX_DESC *desc = &rx_buffer[0].desc;
-
-    for (i = 0; i < ETH_RXBUFNB; i++)
-    {
-        desc->RX_1.RX1_b.SIZE = ETH_MAX_PACKET_SIZE;
-        desc->bufAddr = (uint32_t)rx_buffer[i].buffer;
-
-        if((i+1) == ETH_RXBUFNB)
-            desc->nextDescAddr = (uint32_t)&rx_buffer[0].desc;
-        else
-            desc->nextDescAddr = (uint32_t)&rx_buffer[i+1].desc;
-
-        desc = (ETH_RX_DESC *)desc->nextDescAddr;
-    }
-
-    ETH_SetRxDescRing(&rx_buffer[0].desc);
-}
-
-static void TxDescChainInit(void)
-{
-    uint32_t i;
-
-    // initialize tx descriptor
-    ETH_TX_DESC *desc = &tx_buffer[0].desc;
-
-    for (i = 0; i < ETH_TXBUFNB; i++)
-    {
-        desc->TX_1.TX1_b.SIZE = ETH_MAX_PACKET_SIZE;
-        desc->bufAddr = (uint32_t)tx_buffer[i].buffer;
-
-        if((i+1) == ETH_TXBUFNB)
-            desc->nextDescAddr = (uint32_t)&tx_buffer[0].desc;
-        else
-            desc->nextDescAddr = (uint32_t)&tx_buffer[i+1].desc;
-
-        desc = (ETH_TX_DESC *)desc->nextDescAddr;
-    }
-
-    ETH_SetTxDescRing(&tx_buffer[0].desc);
-}
-
-/////////////////////////////////////////////////////////////////
-
-/* initialize the interface */
-static rt_err_t rt_cme_eth_init(rt_device_t dev)
-{
-    struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
-
-    ETH_InitTypeDef init;
-    ETH_FrameFilter flt;
-
-    init.ETH_Speed = phy_GetSpeed();
-    init.ETH_Duplex = phy_GetDuplex();
-    init.ETH_LinkUp = phy_IsLink();
-    init.ETH_RxEn = TRUE;
-    init.ETH_TxEn = TRUE;
-    init.ETH_ChecksumOffload = FALSE;
-    init.ETH_JumboFrame = FALSE;
-
-    memcpy(init.ETH_MacAddr, cme_eth->dev_addr, sizeof(init.ETH_MacAddr));
-
-    // Disable broadcast;
-    // TODO: why?
-    memset(&flt, 0, sizeof(ETH_FrameFilter));
-    flt.ETH_BroadcastFilterEnable = FALSE;
-    flt.ETH_OwnFilterEnable = FALSE;
-    flt.ETH_SelfDrop = FALSE;
-    flt.ETH_SourceFilterEnable = FALSE;
-    flt.ETH_SourceDrop = FALSE;
-
-    init.ETH_Filter = &flt;
-
-    if (!phy_Init())
-    {
-        rt_kprintf("phy_Init failed!\n");
-        while (1);
-    }
-
-    if (!ETH_Init(&init))
-    {
-        rt_kprintf("ETH_Init failed!\n");
-        while (1);
-    }
-
-    RxDescChainInit();
-    TxDescChainInit();
-
-    ETH_ITConfig(ETH_INT_BUS_FATAL_ERROR, TRUE);
-
-    ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
-    ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
-    ETH_ITConfig(ETH_INT_RX_STOP, TRUE);
-    ETH_StartRx();
-
-    ETH_ITConfig(ETH_INT_TX_COMPLETE_FRAME, TRUE);
-    ETH_StartTx();
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_cme_eth_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    return RT_EOK;
-}
-
-static rt_err_t rt_cme_eth_close(rt_device_t dev)
-{
-    return RT_EOK;
-}
-
-static rt_size_t rt_cme_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_set_errno(-RT_ENOSYS);
-    return 0;
-}
-
-static rt_size_t rt_cme_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    rt_set_errno(-RT_ENOSYS);
-    return 0;
-}
-
-static rt_err_t rt_cme_eth_control(rt_device_t dev, int cmd, void *args)
-{
-    switch(cmd)
-    {
-    case NIOCTL_GADDR:
-        /* get mac address */
-        if(args) rt_memcpy(args, cme_eth_device.dev_addr, 6);
-        else return -RT_ERROR;
-        break;
-
-    default :
-        break;
-    }
-
-    return RT_EOK;
-}
-
-/* ethernet device interface */
-/* transmit packet. */
-rt_err_t rt_cme_eth_tx( rt_device_t dev, struct pbuf* p)
-{
-    rt_err_t result = RT_EOK;
-    ETH_TX_DESC *desc;
-    struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
-
-    rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
-
-#ifdef ETH_TX_DUMP
-    packet_dump("TX dump", p);
-#endif /* ETH_TX_DUMP */
-
-    /* get free tx buffer */
-    {
-        rt_err_t result;
-        result = rt_sem_take(&cme_eth->tx_buf_free, RT_TICK_PER_SECOND/10);
-        if (result != RT_EOK)
-        {
-            result = -RT_ERROR;
-            goto _exit;
-        }
-    }
-
-    desc = ETH_AcquireFreeTxDesc();
-    if(desc == RT_NULL)
-    {
-        CME_ETH_PRINTF("TxDesc not ready!\n");
-        RT_ASSERT(0);
-            result = -RT_ERROR;
-            goto _exit;
-    }
-
-    desc->TX_0.TX0_b.FS = TRUE;
-    desc->TX_0.TX0_b.LS = TRUE;
-    desc->TX_1.TX1_b.SIZE = p->tot_len;
-
-    pbuf_copy_partial(p, ( void *)(desc->bufAddr), p->tot_len, 0);
-
-    ETH_ReleaseTxDesc(desc);
-    ETH_ResumeTx();
-
-_exit:
-    rt_mutex_release(&cme_eth->lock);
-    return result;
-}
-
-/* reception packet. */
-struct pbuf *rt_cme_eth_rx(rt_device_t dev)
-{
-    struct pbuf* p = RT_NULL;
-    ETH_RX_DESC *desc;
-    uint32_t framelength;
-    struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
-
-    rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
-
-    desc = ETH_AcquireFreeRxDesc();
-    if(desc == RT_NULL)
-    {
-        ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE);
-        ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE);
-        ETH_ResumeRx();
-        goto _exit;
-    }
-
-    framelength = desc->RX_0.RX0_b.FL;
-
-    /* allocate buffer */
-    p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM);
-    if (p != RT_NULL)
-    {
-        pbuf_take(p, (const void *)(desc->bufAddr), framelength);
-#ifdef ETH_RX_DUMP
-        packet_dump("RX dump", p);
-#endif /* ETH_RX_DUMP */
-    }
-
-    ETH_ReleaseRxDesc(desc);
-
-_exit:
-    rt_mutex_release(&cme_eth->lock);
-    return p;
-}
-
-static void NVIC_Configuration(void)
-{
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    /* Enable the USARTy Interrupt */
-    NVIC_InitStructure.NVIC_IRQChannel = ETH_INT_IRQn;
-    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = TRUE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-int cme_m7_eth_init(void)
-{
-//    /* PHY RESET: PA4 */
-//    {
-//        GPIO_ResetBits(GPIOA, GPIO_Pin_4);
-//        rt_thread_delay(2);
-//        GPIO_SetBits(GPIOA, GPIO_Pin_4);
-//        rt_thread_delay(2);
-//    }
-
-//    GPIO_Configuration();
-    NVIC_Configuration();
-
-//    cme_eth_device.ETH_Speed = ETH_Speed_100M;
-//    cme_eth_device.ETH_Mode  = ETH_Mode_FullDuplex;
-
-    /* OUI 00-80-E1 STMICROELECTRONICS. */
-    cme_eth_device.dev_addr[0] = 0x00;
-    cme_eth_device.dev_addr[1] = 0x80;
-    cme_eth_device.dev_addr[2] = 0xE1;
-    /* generate MAC addr from 96bit unique ID (only for test). */
-//    cme_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+4);
-//    cme_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+2);
-//    cme_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+0);
-    cme_eth_device.dev_addr[3] = 12;
-    cme_eth_device.dev_addr[4] = 34;
-    cme_eth_device.dev_addr[5] = 56;
-
-    cme_eth_device.parent.parent.init       = rt_cme_eth_init;
-    cme_eth_device.parent.parent.open       = rt_cme_eth_open;
-    cme_eth_device.parent.parent.close      = rt_cme_eth_close;
-    cme_eth_device.parent.parent.read       = rt_cme_eth_read;
-    cme_eth_device.parent.parent.write      = rt_cme_eth_write;
-    cme_eth_device.parent.parent.control    = rt_cme_eth_control;
-    cme_eth_device.parent.parent.user_data  = RT_NULL;
-
-    cme_eth_device.parent.eth_rx     = rt_cme_eth_rx;
-    cme_eth_device.parent.eth_tx     = rt_cme_eth_tx;
-
-    /* init EMAC lock */
-    rt_mutex_init(&cme_eth_device.lock, "emac0", RT_IPC_FLAG_PRIO);
-
-    /* init tx buffer free semaphore */
-    rt_sem_init(&cme_eth_device.tx_buf_free,
-                "tx_buf",
-                ETH_TXBUFNB,
-                RT_IPC_FLAG_FIFO);
-
-    /* register eth device */
-    eth_device_init(&(cme_eth_device.parent), "e0");
-
-    return RT_EOK;
-}
-
-void ETH_IRQHandler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    if (ETH_GetITStatus(ETH_INT_TX_COMPLETE_FRAME))
-    {
-        rt_sem_release(&cme_eth_device.tx_buf_free);
-        ETH_ClearITPendingBit(ETH_INT_TX_COMPLETE_FRAME);
-    }
-
-    if (ETH_GetITStatus(ETH_INT_RX_STOP))
-    {
-        CME_ETH_PRINTF("ETH_INT_RX_STOP\n");
-        ETH_ClearITPendingBit(ETH_INT_RX_STOP);
-    }
-
-    if ((ETH_GetITStatus(ETH_INT_RX_BUF_UNAVAI)) ||
-            (ETH_GetITStatus(ETH_INT_RX_COMPLETE_FRAME)))
-    {
-        /* a frame has been received */
-        eth_device_ready(&(cme_eth_device.parent));
-
-        ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, FALSE);
-        ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, FALSE);
-        ETH_ClearITPendingBit(ETH_INT_RX_BUF_UNAVAI);
-        ETH_ClearITPendingBit(ETH_INT_RX_COMPLETE_FRAME);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-

bsp/CME_M7/drivers/uart.c

@@ -1,217 +0,0 @@
-#include <rthw.h>
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include <board.h>
-
-/* CME-M7 uart driver */
-struct CME_M7_uart
-{
-    UART0_Type* uart_device;
-    IRQn_Type irq;
-};
-
-#ifdef RT_USING_UART0
-struct CME_M7_uart uart0 =
-{
-    UART0,
-    UART0_INT_IRQn,
-};
-static struct rt_serial_device serial0;
-#endif /* RT_USING_UART0 */
-
-#ifdef RT_USING_UART2
-struct CME_M7_uart uart2 =
-{
-    UART2,
-    UART2_INT_IRQn,
-};
-static struct rt_serial_device serial2;
-#endif /* RT_USING_UART2 */
-
-static rt_err_t CME_M7_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct CME_M7_uart* uart;
-	UART_InitTypeDef init;
-
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(cfg != RT_NULL);
-
-    uart = (struct CME_M7_uart *)serial->parent.user_data;
-
-	init.UART_BaudRate = cfg->baud_rate;
-	init.UART_StopBits = UART_StopBits_1;
-    init.UART_Parity = UART_Parity_None;
-	init.UART_LoopBack = FALSE;
-	init.UART_RxEn = TRUE;
-	init.UART_CtsEn = FALSE;
-
-    UART_Init(uart->uart_device, &init);
-    uart->uart_device->RX_RESET = 1;
-	UART_Enable(uart->uart_device, TRUE);
-    uart->uart_device->RX_RESET = 0;
-
-    return RT_EOK;
-}
-
-static rt_err_t CME_M7_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct CME_M7_uart* uart;
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct CME_M7_uart *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        NVIC_InitStructure.NVIC_IRQChannel = uart->irq;
-		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-		NVIC_InitStructure.NVIC_IRQChannelCmd = FALSE;
-		NVIC_Init(&NVIC_InitStructure);
-
-		UART_EnableInt(uart->uart_device, UART_Int_RxNotEmpty, FALSE);
-        break;
-
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        NVIC_InitStructure.NVIC_IRQChannel = uart->irq;
-		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
-		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
-		NVIC_InitStructure.NVIC_IRQChannelCmd = TRUE;
-		NVIC_Init(&NVIC_InitStructure);
-
-		UART_ClearInt(uart->uart_device, UART_Int_RxNotEmpty);
-		UART_EnableInt(uart->uart_device, UART_Int_RxNotEmpty, TRUE);
-        break;
-    }
-
-    return RT_EOK;
-}
-
-static int CME_M7_putc(struct rt_serial_device *serial, char ch)
-{
-    struct CME_M7_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct CME_M7_uart *)serial->parent.user_data;
-
-    while(uart->uart_device->STATUS_b.TF); //waits for transmitter FIFO not full.
-    uart->uart_device->TX_BUF = ch;
-
-    return 1;
-}
-
-static int CME_M7_getc(struct rt_serial_device *serial)
-{
-    int ch;
-    struct CME_M7_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct CME_M7_uart *)serial->parent.user_data;
-
-    ch = -1;
-
-    if(uart->uart_device->STATUS_b.RNE)
-    {
-        ch = uart->uart_device->RX_BUF & 0x00FF; /* Get Data from UART RX  */
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops CME_M7_uart_ops =
-{
-    CME_M7_configure,
-    CME_M7_control,
-    CME_M7_putc,
-    CME_M7_getc,
-};
-
-int rt_hw_uart_init(void)
-{
-	struct CME_M7_uart* uart;
-	struct rt_serial_device *serial;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-#ifdef RT_USING_UART0
-    uart = &uart0;
-    serial = &serial0;
-
-    serial->ops    = &CME_M7_uart_ops;
-    serial->config = config;
-
-	/* register UART device */
-    rt_hw_serial_register(serial,
-                          "uart0",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-#endif /* RT_USING_UART0 */
-
-#ifdef RT_USING_UART2
-    uart = &uart2;
-    serial = &serial2;
-
-    serial->ops    = &CME_M7_uart_ops;
-    serial->config = config;
-
-	/* register UART device */
-    rt_hw_serial_register(serial,
-                          "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-#endif /* RT_USING_UART2 */
-
-	return RT_EOK;
-}
-INIT_BOARD_EXPORT(rt_hw_uart_init);
-
-static void CME_UART_IRQHandler(struct rt_serial_device *serial)
-{
-    struct CME_M7_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct CME_M7_uart *)serial->parent.user_data;
-
-    if(UART_GetIntStatus(uart->uart_device, UART_Int_RxNotEmpty))
-    {
-        UART_ClearInt(uart->uart_device, UART_Int_RxNotEmpty);
-        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
-    }
-
-    if(UART_GetIntStatus(uart->uart_device, UART_Int_RxThresholdReach))
-    {
-        UART_ClearInt(uart->uart_device, UART_Int_RxThresholdReach);
-    }
-
-    if(UART_GetIntStatus(uart->uart_device, UART_Int_OverrunError))
-    {
-        UART_ClearInt(uart->uart_device, UART_Int_OverrunError);
-    }
-
-    if(UART_GetIntStatus(uart->uart_device, UART_Int_FrameError))
-    {
-        UART_ClearInt(uart->uart_device, UART_Int_FrameError);
-    }
-
-    if(UART_GetIntStatus(uart->uart_device, UART_Int_ParityError))
-    {
-        UART_ClearInt(uart->uart_device, UART_Int_ParityError);
-    }
-}
-
-#ifdef RT_USING_UART0
-void UART0_IRQHandler(void)
-{
-    CME_UART_IRQHandler(&serial0);
-}
-#endif /* RT_USING_UART0 */
-
-#ifdef RT_USING_UART2
-void UART2_IRQHandler(void)
-{
-    CME_UART_IRQHandler(&serial2);
-}
-#endif /* RT_USING_UART2 */

bsp/CME_M7/project.uvopt

@@ -1,170 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rtthread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>10000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>0</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>1</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <tPdscDbg>1</tPdscDbg>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>17</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>CapitalMicro\BIN\cmagdi.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>Nu_Link</Key>
-          <Name>-S1 -B115200 -O0</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>1</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>Source Group 1</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-  </Group>
-
-</ProjectOpt>

bsp/CME_M7/rtconfig.h

@@ -1,129 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX		8
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-#define RT_USING_OVERFLOW_CHECK
-
-/* Using Hook */
-#define RT_USING_HOOK
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-#define RT_USING_EVENT
-
-/* Using MailBox */
-#define RT_USING_MAILBOX
-
-/* Using Message Queue */
-#define RT_USING_MESSAGEQUEUE
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using Small MM */
-#define RT_USING_SMALL_MEM
-
-#define RT_USING_COMPONENTS_INIT
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SERIAL
-
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-#define RT_CONSOLE_DEVICE_NAME	        "uart2"
-
-/* SECTION: finsh, a C-Express shell */
-#define RT_USING_FINSH
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_USING_MSH
-//#define FINSH_USING_MSH_ONLY
-
-#define RT_USING_LIBC
-
-/* SECTION: device filesystem */
-/* #define RT_USING_DFS */
-#define RT_USING_DFS_ELMFAT
-#define RT_DFS_ELM_REENTRANT
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_DRIVES			1
-#define RT_DFS_ELM_USE_LFN			2
-#define RT_DFS_ELM_MAX_LFN			255
-#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-
-/* SECTION: lwip, a lighwight TCP/IP protocol stack */
-#define RT_USING_LWIP
-/* Enable ICMP protocol*/
-#define RT_LWIP_ICMP
-/* Enable UDP protocol*/
-#define RT_LWIP_UDP
-/* Enable TCP protocol*/
-#define RT_LWIP_TCP
-/* Enable DNS */
-#define RT_LWIP_DNS
-/* Enable DHCP */
-// #define RT_LWIP_DHCP
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM		3
-
-/* ip address of target */
-#define RT_LWIP_IPADDR "192.168.1.30"
-
-/* gateway address of target */
-#define RT_LWIP_GWADDR  "192.168.1.1"
-
-/* mask address of target */
-#define RT_LWIP_MSKADDR  "255.255.255.0"
-
-/* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
-
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
-
-// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
-// #define RT_USING_CMSIS_OS
-// <bool name="RT_USING_RTT_CMSIS" description="Using CMSIS in RTT" default="true" />
-#define RT_USING_RTT_CMSIS
-
-#endif

bsp/CME_M7/rtconfig.py

@@ -1,124 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arm'
-CPU='cortex-m3'
-CROSS_TOOL='keil'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= r'C:\Program Files\GNU Tools ARM Embedded\4.8 2013q4\bin'
-elif CROSS_TOOL == 'keil':
-	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= 'C:/Keil'
-elif CROSS_TOOL == 'iar':
-	PLATFORM 	= 'iar'
-	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-BUILD = 'debug'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC = PREFIX + 'gcc'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-
-    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE + ' -g -Wall '
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles  -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T CME_M7.ld'
-
-    CPATH = ''
-    LPATH = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O3'
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --cortex-m3'
-    CFLAGS = DEVICE + ' --c99 --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter nuc472_flash.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' -D USE_STDPERIPH_DRIVER'
-
-    CFLAGS = DEVICE
-    CFLAGS += ' --diag_suppress Pa050'
-    CFLAGS += ' --no_cse' 
-    CFLAGS += ' --no_unroll' 
-    CFLAGS += ' --no_inline' 
-    CFLAGS += ' --no_code_motion' 
-    CFLAGS += ' --no_tbaa' 
-    CFLAGS += ' --no_clustering' 
-    CFLAGS += ' --no_scheduling' 
-    CFLAGS += ' --debug' 
-    CFLAGS += ' --endian=little' 
-    CFLAGS += ' --cpu=Cortex-M3' 
-    CFLAGS += ' -e' 
-    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
-    CFLAGS += ' -Ol'    
-        
-    AFLAGS = ''
-    AFLAGS += ' -s+' 
-    AFLAGS += ' -w+' 
-    AFLAGS += ' -r' 
-    AFLAGS += ' --cpu Cortex-M3' 
-    AFLAGS += ' --fpu None' 
-
-    LFLAGS = ' --config CME_M7.icf'
-    LFLAGS += ' --semihosting' 
-    LFLAGS += ' --entry __iar_program_start'    
-
-    EXEC_PATH = EXEC_PATH + '/arm/bin/'
-    POST_ACTION = ''

bsp/CME_M7/template.uvopt

@@ -1,170 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rtthread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>10000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>0</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>1</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <tPdscDbg>1</tPdscDbg>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>17</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>CapitalMicro\BIN\cmagdi.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>Nu_Link</Key>
-          <Name>-S1 -B115200 -O0</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>1</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>Source Group 1</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
-    <RteFlg>0</RteFlg>
-  </Group>
-
-</ProjectOpt>

bsp/CME_M7/template.uvproj

@@ -1,416 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rtthread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>ARMCM3</Device>
-          <Vendor>ARM</Vendor>
-          <PackID>ARM.CMSIS.4.1.0</PackID>
-          <PackURL>http://www.keil.com/pack/</PackURL>
-          <Cpu>CPUTYPE("Cortex-M3") CLOCK(10000000) ESEL ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll></FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>rtthread</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>1</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>0</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>1</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments> </SimDllArguments>
-          <SimDlgDll>DCM.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
-          <TargetDlgDll>TCM.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-            <RestoreSysVw>1</RestoreSysVw>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <RestoreTracepoints>1</RestoreTracepoints>
-            <RestoreSysVw>1</RestoreSysVw>
-            <UsePdscDebugDescription>1</UsePdscDebugDescription>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>17</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>CapitalMicro\BIN\cmagdi.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4097</DriverSelection>
-          </Flash1>
-          <bUseTDR>0</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M3"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>0</hadIROM>
-            <hadIRAM>0</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>0</StupSel>
-            <useUlib>0</useUlib>
-            <EndSel>1</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>0</RoSelD>
-            <RwSelD>0</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>0</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>0</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x10000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x80000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>2</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <useXO>0</useXO>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>0</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x00000000</TextAddressRange>
-            <DataAddressRange>0x00000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile>CME_M7.sct</ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>Source Group 1</GroupName>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>

bsp/K60Fxxxx/SConstruct

@@ -0,0 +1,37 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-k60.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# build program 
+env.Program(TARGET, objs)
+
+# end building 
+EndBuilding(TARGET)

bsp/K60Fxxxx/applications/application.c

@@ -0,0 +1,93 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+/**
+ * @addtogroup k60
+ */
+/*@{*/
+
+#include <stdio.h>
+
+#include "MK60F12.h"
+#include <board.h>
+#include <rtthread.h>
+
+#include "led.h"
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#include <lwip/api.h>
+#include <netif/ethernetif.h>
+#include "stm32_eth.h"
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+    /* nothing */
+}
+
+float f_var1;
+float f_var2;
+float f_var3;
+float f_var4;
+
+ALIGN(RT_ALIGN_SIZE)
+static char thread_led1_stack[1024];
+struct rt_thread thread_led1;
+static void rt_thread_entry_led1(void* parameter)
+{
+    int n = 0;
+    rt_hw_led_init();
+
+    while (1)
+    {
+        //rt_kprintf("LED\t%d\tis shining\r\n",n);
+
+        rt_hw_led_on(n);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+        rt_hw_led_off(n);
+        rt_thread_delay(RT_TICK_PER_SECOND/2);
+
+        n++;
+
+        if(n > LED_MAX-1)
+            n = 0;
+
+    }
+}
+
+int rt_application_init()
+{
+    rt_thread_t init_thread;
+
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
+
+    //------- init led1 thread
+    rt_thread_init(&thread_led1,
+                   "led_demo",
+                   rt_thread_entry_led1,
+                   RT_NULL,
+                   &thread_led1_stack[0],
+                   sizeof(thread_led1_stack),11,5);
+    rt_thread_startup(&thread_led1);
+
+    return 0;
+}
+
+/*@}*/

bsp/K60Fxxxx/applications/startup.c

@@ -0,0 +1,122 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <MK60F12.H>
+#include "board.h"
+
+/**
+ * @addtogroup k60
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define k60_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define k60_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define k60_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(rt_uint8_t* file, rt_uint32_t line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+    rt_system_heap_init((void*)k60_SRAM_BEGIN, (void*)k60_SRAM_END);
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device( FINSH_DEVICE_NAME );
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/

bsp/K60Fxxxx/drivers/SConscript

@@ -0,0 +1,12 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+src	+= Glob('*.s')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/K60Fxxxx/drivers/board.c

@@ -0,0 +1,88 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <MK60F12.H>
+#include "board.h"
+
+#include "drv_uart.h"
+
+
+/**
+ * @addtogroup K60
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    SystemCoreClockUpdate();              /* Update Core Clock Frequency        */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND); /* Generate interrupt each 1 ms       */
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial Tower board.
+ */
+void rt_hw_board_init()
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(CONSOLE_DEVICE);
+#endif
+}
+
+/*@}*/

bsp/K60Fxxxx/drivers/board.h

@@ -0,0 +1,58 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <MK60F12.H>
+
+
+/* board configuration */
+
+// <o> Internal SRAM memory size[Kbytes] <8-64>
+// <i>Default: 64
+#define k60_SRAM_SIZE         128
+#define k60_SRAM_END          (0x20000000 + (k60_SRAM_SIZE * 1024)/2)
+
+//#define RT_USING_UART1
+#define RT_USING_UART5
+//#define RT_USING_UART3
+
+// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
+// <i>Default: 1
+#define k60_CONSOLE_USART        5
+
+void rt_hw_board_init(void);
+
+#if k60_CONSOLE_USART == 0
+#define CONSOLE_DEVICE "no"
+#elif k60_CONSOLE_USART == 1
+#define CONSOLE_DEVICE "uart1"
+#elif k60_CONSOLE_USART == 2
+#define CONSOLE_DEVICE "uart2"
+#elif k60_CONSOLE_USART == 3
+#define CONSOLE_DEVICE "uart3"
+#elif k60_CONSOLE_USART == 4
+#define CONSOLE_DEVICE "uart4"
+#elif k60_CONSOLE_USART == 5
+#define CONSOLE_DEVICE "uart5"
+#endif
+
+#define FINSH_DEVICE_NAME   CONSOLE_DEVICE
+
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>

bsp/K60Fxxxx/drivers/drv_uart.c

@@ -0,0 +1,257 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+
+#include "drv_uart.h"
+
+static struct rt_serial_device _k60_serial;  //abstracted serial for RTT
+static struct serial_ringbuffer _k60_int_rx; //UART send buffer area
+
+struct k60_serial_device
+{
+    /* UART base address */
+    UART_Type *baseAddress;
+
+    /* UART IRQ Number */
+    int irq_num;
+
+    /* device config */
+    struct serial_configure config;
+};
+
+//hardware abstract device
+static struct k60_serial_device _k60_node =
+{
+    (UART_Type *)UART5,
+    k60_uasrt_irq_num,
+};
+
+static rt_err_t _configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    unsigned int reg_C1 = 0,reg_C3 = 0,reg_C4 = 0,reg_BDH = 0,reg_BDL = 0,reg_S2,reg_BRFA=0;
+    unsigned int cal_SBR = 0;
+    UART_Type *uart_reg;
+
+    /* ref : drivers\system_MK60F12.c Line 64 ,BusClock = 60MHz
+     * calculate baud_rate
+     */
+    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
+
+    /* calc SBR */
+    cal_SBR = 60000000 / (16 * cfg->baud_rate);
+
+    /* calc baud_rate */
+    reg_BDH = (cal_SBR & 0x1FFF) >> 8 & 0x00FF;
+    reg_BDL = cal_SBR & 0x00FF;
+
+    /* fractional divider */
+    reg_BRFA = ((60000*32000)/(cfg->baud_rate * 16)) - (cal_SBR * 32);
+
+    reg_C4 = (unsigned char)(reg_BRFA & 0x001F);
+
+    /*
+     * set bit order
+     */
+    if (cfg->bit_order == BIT_ORDER_LSB)
+        reg_S2 &= ~(UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT);
+    else if (cfg->bit_order == BIT_ORDER_MSB)
+        reg_S2 |= UART_S2_MSBF_MASK<<UART_S2_MSBF_SHIFT;
+
+    /*
+     * set data_bits
+     */
+    if (cfg->data_bits == DATA_BITS_8)
+        reg_C1 &= ~(UART_C1_M_MASK<<UART_C1_M_SHIFT);
+    else if (cfg->data_bits == DATA_BITS_9)
+        reg_C1 |= UART_C1_M_MASK<<UART_C1_M_SHIFT;
+
+    /*
+     * set parity
+     */
+    if (cfg->parity == PARITY_NONE)
+    {
+        reg_C1 &= ~(UART_C1_PE_MASK);
+    }
+    else
+    {
+        /* first ,set parity enable bit */
+        reg_C1 |= (UART_C1_PE_MASK);
+        
+        /* second ,determine parity odd or even*/
+        if (cfg->parity == PARITY_ODD)
+            reg_C1 |= UART_C1_PT_MASK;
+        if (cfg->parity == PARITY_EVEN)
+            reg_C1 &= ~(UART_C1_PT_MASK);
+    }
+
+    /*
+     * set stop bit
+     * not supported on Tower? need ur help!
+     */
+
+    /*
+     * set NZR mode
+     * not tested
+     */
+    if(cfg->invert != NRZ_NORMAL)
+    {
+        /* not in normal mode ,set inverted polarity */
+        reg_C3 |= UART_C3_TXINV_MASK;
+    }
+
+    switch( (int)uart_reg)
+    {
+    /* Tower board use UART5 for communication
+     * if you're using other board
+     * set clock and pin map for UARTx
+     */
+    case UART5_BASE:
+
+        //set UART5 clock
+        SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;//Enable UART gate clocking 
+        SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;//Enable PORTE gate clocking
+
+        //set UART5 pin
+        PORTE->PCR[ 8] = (3UL <<  8);      //Pin mux configured as ALT3
+        PORTE->PCR[ 9] = (3UL <<  8);      //Pin mux configured as ALT3
+        break;
+    default:
+        break;
+    }
+
+    uart_reg->BDH = reg_BDH;
+    uart_reg->BDL = reg_BDL;
+    uart_reg->C1 = reg_C1;
+    uart_reg->C4 = reg_C4;
+    uart_reg->S2 = reg_S2;
+
+    uart_reg->S2  =  0;
+    uart_reg->C3  =  0;
+
+    uart_reg->RWFIFO = UART_RWFIFO_RXWATER(1);
+    uart_reg->TWFIFO = UART_TWFIFO_TXWATER(0);
+
+    uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
+                     UART_C2_TE_MASK;     //Transmitter enable
+
+    return RT_EOK;
+}
+
+static rt_err_t _control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    UART_Type *uart_reg;
+    int uart_irq_num = 0;
+
+    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
+    uart_irq_num = ((struct k60_serial_device *)serial->parent.user_data)->irq_num;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        uart_reg->C2 &= ~UART_C2_RIE_MASK;
+        //disable NVIC
+        NVIC->ICER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        uart_reg->C2 |= UART_C2_RIE_MASK;
+        //enable NVIC,we are sure uart's NVIC vector is in NVICICPR1
+        NVIC->ICPR[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        NVIC->ISER[uart_irq_num / 32] = 1 << (uart_irq_num % 32);
+        break;
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        uart_reg->C2  &=  ~(UART_C2_RE_MASK |    //Receiver enable
+                            UART_C2_TE_MASK);     //Transmitter enable
+        break;
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        uart_reg->C2  =  UART_C2_RE_MASK |    //Receiver enable
+                         UART_C2_TE_MASK;     //Transmitter enable
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int _putc(struct rt_serial_device *serial, char c)
+{
+    UART_Type *uart_reg;
+    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
+
+    while (!(uart_reg->S1 & UART_S1_TDRE_MASK));
+    uart_reg->D = (c & 0xFF);
+    return 1;
+}
+
+static int _getc(struct rt_serial_device *serial)
+{
+    UART_Type *uart_reg;
+    uart_reg = ((struct k60_serial_device *)serial->parent.user_data)->baseAddress;
+
+    if (uart_reg->S1 & UART_S1_RDRF_MASK)
+        return (uart_reg->D);
+    else
+        return -1;
+}
+
+static const struct rt_uart_ops _k60_ops =
+{
+    _configure,
+    _control,
+    _putc,
+    _getc,
+};
+
+
+void UART5_RX_TX_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    rt_hw_serial_isr((struct rt_serial_device*)&_k60_serial);
+    rt_interrupt_leave();
+}
+
+
+void rt_hw_uart_init(void)
+{
+    struct serial_configure config;
+
+    /* fake configuration */
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+
+    _k60_serial.ops    = &_k60_ops;
+    _k60_serial.int_rx = &_k60_int_rx;
+    _k60_serial.config = config;
+
+    rt_hw_serial_register(&_k60_serial, "uart5",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          (void*)&_k60_node);
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while(*str != '\0')
+    {
+        if (*str == '\n')
+            _putc(&_k60_serial,'\r');
+        _putc(&_k60_serial,*str);
+        str++;
+    }
+}

bsp/K60Fxxxx/drivers/drv_uart.h

@@ -0,0 +1,34 @@
+/*
+ * File      : drv_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+#ifndef DRV_UART_H
+#define DRV_UART_H
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <MK60F12.H>
+
+#include <drivers/serial.h>
+
+
+#define k60_uasrt_irq_num   (55)
+
+void rt_hw_uart_init(void);
+
+//for kernel debug when console not registered
+void rt_hw_console_output(const char *str);
+
+#endif /* end of include guard: DRV_UART_H */

bsp/K60Fxxxx/drivers/led.c

@@ -0,0 +1,55 @@
+/*
+ * File      : led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+#include <MK60F12.H>
+#include "led.h"
+
+const rt_uint32_t led_mask[] = { 1 << 11, 1 << 28, 1 << 29, 1 << 10 };
+
+void rt_hw_led_init(void)
+{
+    SIM->SCGC5    |= (1UL <<  9);         //Enable Port A Clock
+    PORTA->PCR[10] = (1UL <<  8);         //PTA10 is GPIO pin  
+    PORTA->PCR[11] = (1UL <<  8);         //PTA11 is GPIO pin  
+    PORTA->PCR[28] = (1UL <<  8);         //PTA28 is GPIO pin  
+    PORTA->PCR[29] = (1UL <<  8);         //PTA29 is GPIO pin  
+
+    /* Switch LEDs off and enable output*/
+    PTA->PDOR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
+    PTA->PDDR = (led_mask[3] | led_mask[2] | led_mask[1] | led_mask[0]);
+}
+
+void rt_hw_led_uninit(void)
+{
+    PORTA->PCR[10] = 0;                   //PTA10 is at reset state
+    PORTA->PCR[11] = 0;                   //PTA11 is at reset state
+    PORTA->PCR[28] = 0;                   //PTA28 is at reset state
+    PORTA->PCR[29] = 0;                   //PTA29 is at reset state
+}
+
+void rt_hw_led_on(rt_uint32_t n)
+{
+    if (n < LED_MAX)
+    {
+        PTA->PCOR = led_mask[n];
+    }
+}
+
+
+void rt_hw_led_off(rt_uint32_t n)
+{
+    if (n < LED_MAX) {
+        PTA->PSOR = led_mask[n];
+    }
+}

bsp/K60Fxxxx/drivers/led.h

@@ -0,0 +1,27 @@
+/*
+ * File      : led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-11     reynolds     port to TWR-K60F120M
+ */
+
+#ifndef __LED_H__
+#define __LED_H__
+
+#include <rtthread.h>
+
+#define LED_MAX  4
+
+void rt_hw_led_init(void);
+void rt_hw_led_uninit(void);
+void rt_hw_led_on(rt_uint32_t n);
+void rt_hw_led_off(rt_uint32_t n);
+
+#endif /* end  of __LED_H__ */

bsp/K60Fxxxx/drivers/startup_MK60F12.s

@@ -0,0 +1,774 @@
+;/*****************************************************************************
+; * @file:    startup_MK60F12.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *           MK60F12
+; * @version: 1.1
+; * @date:    2011-11-3
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     HardFault_Handler  ; Hard Fault Handler
+                DCD     MemManage_Handler  ; MPU Fault Handler
+                DCD     BusFault_Handler  ; Bus Fault Handler
+                DCD     UsageFault_Handler  ; Usage Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     DebugMon_Handler  ; Debug Monitor Handler
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DMA0_DMA16_IRQHandler  ; DMA channel 0/16 transfer complete interrupt
+                DCD     DMA1_DMA17_IRQHandler  ; DMA channel 1/17 transfer complete interrupt
+                DCD     DMA2_DMA18_IRQHandler  ; DMA channel 2/18 transfer complete interrupt
+                DCD     DMA3_DMA19_IRQHandler  ; DMA channel 3/19 transfer complete interrupt
+                DCD     DMA4_DMA20_IRQHandler  ; DMA channel 4/20 transfer complete interrupt
+                DCD     DMA5_DMA21_IRQHandler  ; DMA channel 5/21 transfer complete interrupt
+                DCD     DMA6_DMA22_IRQHandler  ; DMA channel 6/22 transfer complete interrupt
+                DCD     DMA7_DMA23_IRQHandler  ; DMA channel 7/23 transfer complete interrupt
+                DCD     DMA8_DMA24_IRQHandler  ; DMA channel 8/24 transfer complete interrupt
+                DCD     DMA9_DMA25_IRQHandler  ; DMA channel 9/25 transfer complete interrupt
+                DCD     DMA10_DMA26_IRQHandler  ; DMA channel 10/26 transfer complete interrupt
+                DCD     DMA11_DMA27_IRQHandler  ; DMA channel 11/27 transfer complete interrupt
+                DCD     DMA12_DMA28_IRQHandler  ; DMA channel 12/28 transfer complete interrupt
+                DCD     DMA13_DMA29_IRQHandler  ; DMA channel 13/29 transfer complete interrupt
+                DCD     DMA14_DMA30_IRQHandler  ; DMA channel 14/30 transfer complete interrupt
+                DCD     DMA15_DMA31_IRQHandler  ; DMA channel 15/31 transfer complete interrupt
+                DCD     DMA_Error_IRQHandler  ; DMA error interrupt
+                DCD     MCM_IRQHandler  ; Normal interrupt
+                DCD     FTFE_IRQHandler  ; FTFE interrupt
+                DCD     Read_Collision_IRQHandler  ; Read collision interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
+                DCD     Watchdog_IRQHandler  ; WDOG interrupt
+                DCD     RNG_IRQHandler  ; RNGB interrupt
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     I2C1_IRQHandler  ; I2C1 interrupt
+                DCD     SPI0_IRQHandler  ; SPI0 interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 interrupt
+                DCD     SPI2_IRQHandler  ; SPI2 interrupt
+                DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd message buffers interrupt
+                DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 bus off interrupt
+                DCD     CAN0_Error_IRQHandler  ; CAN0 error interrupt
+                DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx warning interrupt
+                DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx warning interrupt
+                DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 wake up interrupt
+                DCD     I2S0_Tx_IRQHandler  ; I2S0 transmit interrupt
+                DCD     I2S0_Rx_IRQHandler  ; I2S0 receive interrupt
+                DCD     CAN1_ORed_Message_buffer_IRQHandler  ; CAN1 OR'd message buffers interrupt
+                DCD     CAN1_Bus_Off_IRQHandler  ; CAN1 bus off interrupt
+                DCD     CAN1_Error_IRQHandler  ; CAN1 error interrupt
+                DCD     CAN1_Tx_Warning_IRQHandler  ; CAN1 Tx warning interrupt
+                DCD     CAN1_Rx_Warning_IRQHandler  ; CAN1 Rx warning interrupt
+                DCD     CAN1_Wake_Up_IRQHandler  ; CAN1 wake up interrupt
+                DCD     Reserved59_IRQHandler  ; Reserved interrupt 59
+                DCD     UART0_LON_IRQHandler  ; UART0 LON interrupt
+                DCD     UART0_RX_TX_IRQHandler  ; UART0 receive/transmit interrupt
+                DCD     UART0_ERR_IRQHandler  ; UART0 error interrupt
+                DCD     UART1_RX_TX_IRQHandler  ; UART1 receive/transmit interrupt
+                DCD     UART1_ERR_IRQHandler  ; UART1 error interrupt
+                DCD     UART2_RX_TX_IRQHandler  ; UART2 receive/transmit interrupt
+                DCD     UART2_ERR_IRQHandler  ; UART2 error interrupt
+                DCD     UART3_RX_TX_IRQHandler  ; UART3 receive/transmit interrupt
+                DCD     UART3_ERR_IRQHandler  ; UART3 error interrupt
+                DCD     UART4_RX_TX_IRQHandler  ; UART4 receive/transmit interrupt
+                DCD     UART4_ERR_IRQHandler  ; UART4 error interrupt
+                DCD     UART5_RX_TX_IRQHandler  ; UART5 receive/transmit interrupt
+                DCD     UART5_ERR_IRQHandler  ; UART5 error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     ADC1_IRQHandler  ; ADC1 interrupt
+                DCD     CMP0_IRQHandler  ; CMP0 interrupt
+                DCD     CMP1_IRQHandler  ; CMP1 interrupt
+                DCD     CMP2_IRQHandler  ; CMP2 interrupt
+                DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
+                DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
+                DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
+                DCD     CMT_IRQHandler  ; CMT interrupt
+                DCD     RTC_IRQHandler  ; RTC interrupt
+                DCD     RTC_Seconds_IRQHandler  ; RTC seconds interrupt
+                DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
+                DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
+                DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
+                DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
+                DCD     PDB0_IRQHandler  ; PDB0 interrupt
+                DCD     USB0_IRQHandler  ; USB0 interrupt
+                DCD     USBDCD_IRQHandler  ; USBDCD interrupt
+                DCD     ENET_1588_Timer_IRQHandler  ; Ethernet MAC IEEE 1588 timer interrupt
+                DCD     ENET_Transmit_IRQHandler  ; Ethernet MAC transmit interrupt
+                DCD     ENET_Receive_IRQHandler  ; Ethernet MAC receive interrupt
+                DCD     ENET_Error_IRQHandler  ; Ethernet MAC error and miscelaneous interrupt
+                DCD     Reserved95_IRQHandler  ; Reserved interrupt 95
+                DCD     SDHC_IRQHandler  ; SDHC interrupt
+                DCD     DAC0_IRQHandler  ; DAC0 interrupt
+                DCD     DAC1_IRQHandler  ; DAC1 interrupt
+                DCD     TSI0_IRQHandler  ; TSI0 interrupt
+                DCD     MCG_IRQHandler  ; MCG interrupt
+                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
+                DCD     Reserved102_IRQHandler  ; Reserved interrupt 102
+                DCD     PORTA_IRQHandler  ; Port A interrupt
+                DCD     PORTB_IRQHandler  ; Port B interrupt
+                DCD     PORTC_IRQHandler  ; Port C interrupt
+                DCD     PORTD_IRQHandler  ; Port D interrupt
+                DCD     PORTE_IRQHandler  ; Port E interrupt
+                DCD     PORTF_IRQHandler  ; Port F interrupt
+                DCD     Reserved109_IRQHandler  ; Reserved interrupt 109
+                DCD     SWI_IRQHandler  ; Software interrupt
+                DCD     NFC_IRQHandler  ; NAND flash controller interrupt
+                DCD     USBHS_IRQHandler  ; USB high speed OTG interrupt
+                DCD     Reserved113_IRQHandler  ; Reserved interrupt 113
+                DCD     CMP3_IRQHandler  ; CMP3 interrupt
+                DCD     Reserved115_IRQHandler  ; Reserved interrupt 115
+                DCD     Reserved116_IRQHandler  ; Reserved interrupt 116
+                DCD     FTM3_IRQHandler  ; FTM3 fault, overflow and channels interrupt
+                DCD     ADC2_IRQHandler  ; ADC2 interrupt
+                DCD     ADC3_IRQHandler  ; ADC3 interrupt
+                DCD     I2S1_Tx_IRQHandler  ; I2S1 transmit interrupt
+                DCD     I2S1_Rx_IRQHandler  ; I2S1 receive interrupt
+                DCD     DefaultISR  ; 122
+                DCD     DefaultISR  ; 123
+                DCD     DefaultISR  ; 124
+                DCD     DefaultISR  ; 125
+                DCD     DefaultISR  ; 126
+                DCD     DefaultISR  ; 127
+                DCD     DefaultISR  ; 128
+                DCD     DefaultISR  ; 129
+                DCD     DefaultISR  ; 130
+                DCD     DefaultISR  ; 131
+                DCD     DefaultISR  ; 132
+                DCD     DefaultISR  ; 133
+                DCD     DefaultISR  ; 134
+                DCD     DefaultISR  ; 135
+                DCD     DefaultISR  ; 136
+                DCD     DefaultISR  ; 137
+                DCD     DefaultISR  ; 138
+                DCD     DefaultISR  ; 139
+                DCD     DefaultISR  ; 140
+                DCD     DefaultISR  ; 141
+                DCD     DefaultISR  ; 142
+                DCD     DefaultISR  ; 143
+                DCD     DefaultISR  ; 144
+                DCD     DefaultISR  ; 145
+                DCD     DefaultISR  ; 146
+                DCD     DefaultISR  ; 147
+                DCD     DefaultISR  ; 148
+                DCD     DefaultISR  ; 149
+                DCD     DefaultISR  ; 150
+                DCD     DefaultISR  ; 151
+                DCD     DefaultISR  ; 152
+                DCD     DefaultISR  ; 153
+                DCD     DefaultISR  ; 154
+                DCD     DefaultISR  ; 155
+                DCD     DefaultISR  ; 156
+                DCD     DefaultISR  ; 157
+                DCD     DefaultISR  ; 158
+                DCD     DefaultISR  ; 159
+                DCD     DefaultISR  ; 160
+                DCD     DefaultISR  ; 161
+                DCD     DefaultISR  ; 162
+                DCD     DefaultISR  ; 163
+                DCD     DefaultISR  ; 164
+                DCD     DefaultISR  ; 165
+                DCD     DefaultISR  ; 166
+                DCD     DefaultISR  ; 167
+                DCD     DefaultISR  ; 168
+                DCD     DefaultISR  ; 169
+                DCD     DefaultISR  ; 170
+                DCD     DefaultISR  ; 171
+                DCD     DefaultISR  ; 172
+                DCD     DefaultISR  ; 173
+                DCD     DefaultISR  ; 174
+                DCD     DefaultISR  ; 175
+                DCD     DefaultISR  ; 176
+                DCD     DefaultISR  ; 177
+                DCD     DefaultISR  ; 178
+                DCD     DefaultISR  ; 179
+                DCD     DefaultISR  ; 180
+                DCD     DefaultISR  ; 181
+                DCD     DefaultISR  ; 182
+                DCD     DefaultISR  ; 183
+                DCD     DefaultISR  ; 184
+                DCD     DefaultISR  ; 185
+                DCD     DefaultISR  ; 186
+                DCD     DefaultISR  ; 187
+                DCD     DefaultISR  ; 188
+                DCD     DefaultISR  ; 189
+                DCD     DefaultISR  ; 190
+                DCD     DefaultISR  ; 191
+                DCD     DefaultISR  ; 192
+                DCD     DefaultISR  ; 193
+                DCD     DefaultISR  ; 194
+                DCD     DefaultISR  ; 195
+                DCD     DefaultISR  ; 196
+                DCD     DefaultISR  ; 197
+                DCD     DefaultISR  ; 198
+                DCD     DefaultISR  ; 199
+                DCD     DefaultISR  ; 200
+                DCD     DefaultISR  ; 201
+                DCD     DefaultISR  ; 202
+                DCD     DefaultISR  ; 203
+                DCD     DefaultISR  ; 204
+                DCD     DefaultISR  ; 205
+                DCD     DefaultISR  ; 206
+                DCD     DefaultISR  ; 207
+                DCD     DefaultISR  ; 208
+                DCD     DefaultISR  ; 209
+                DCD     DefaultISR  ; 210
+                DCD     DefaultISR  ; 211
+                DCD     DefaultISR  ; 212
+                DCD     DefaultISR  ; 213
+                DCD     DefaultISR  ; 214
+                DCD     DefaultISR  ; 215
+                DCD     DefaultISR  ; 216
+                DCD     DefaultISR  ; 217
+                DCD     DefaultISR  ; 218
+                DCD     DefaultISR  ; 219
+                DCD     DefaultISR  ; 220
+                DCD     DefaultISR  ; 221
+                DCD     DefaultISR  ; 222
+                DCD     DefaultISR  ; 223
+                DCD     DefaultISR  ; 224
+                DCD     DefaultISR  ; 225
+                DCD     DefaultISR  ; 226
+                DCD     DefaultISR  ; 227
+                DCD     DefaultISR  ; 228
+                DCD     DefaultISR  ; 229
+                DCD     DefaultISR  ; 230
+                DCD     DefaultISR  ; 231
+                DCD     DefaultISR  ; 232
+                DCD     DefaultISR  ; 233
+                DCD     DefaultISR  ; 234
+                DCD     DefaultISR  ; 235
+                DCD     DefaultISR  ; 236
+                DCD     DefaultISR  ; 237
+                DCD     DefaultISR  ; 238
+                DCD     DefaultISR  ; 239
+                DCD     DefaultISR  ; 240
+                DCD     DefaultISR  ; 241
+                DCD     DefaultISR  ; 242
+                DCD     DefaultISR  ; 243
+                DCD     DefaultISR  ; 244
+                DCD     DefaultISR  ; 245
+                DCD     DefaultISR  ; 246
+                DCD     DefaultISR  ; 247
+                DCD     DefaultISR  ; 248
+                DCD     DefaultISR  ; 249
+                DCD     DefaultISR  ; 250
+                DCD     DefaultISR  ; 251
+                DCD     DefaultISR  ; 252
+                DCD     DefaultISR  ; 253
+                DCD     DefaultISR  ; 254
+                DCD     DefaultISR  ; 255
+__Vectors_End
+
+__Vectors_Size 	EQU     __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program flash protection bytes
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Data flash protection byte (FDPROT)
+;     <i> Each bit protects a 1/8 region of the data flash memory.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FDPROT.0
+;     <o.1>   FDPROT.1
+;     <o.2>   FDPROT.2
+;     <o.3>   FDPROT.3
+;     <o.4>   FDPROT.4
+;     <o.5>   FDPROT.5
+;     <o.6>   FDPROT.6
+;     <o.7>   FDPROT.7
+nFDPROT         EQU     0x00
+FDPROT          EQU     nFDPROT:EOR:0xFF
+;   </h>
+;   <h> EEPROM protection byte (FEPROT)
+;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FEPROT.0
+;     <o.1>   FEPROT.1
+;     <o.2>   FEPROT.2
+;     <o.3>   FEPROT.3
+;     <o.4>   FEPROT.4
+;     <o.5>   FEPROT.5
+;     <o.6>   FEPROT.6
+;     <o.7>   FEPROT.7
+nFEPROT         EQU     0x00
+FEPROT          EQU     nFEPROT:EOR:0xFF
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0>  LPBOOT
+;       <0=> Low-power boot
+;       <1=> normal boot
+;     <o.1>  EZPORT_DIS
+;       <0=> EzPort operation is enabled
+;       <1=> EzPort operation is disabled
+FOPT            EQU     0xFF
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;         <i> This bits define the security state of the MCU.
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;         <i> Mass Erase Enable Bits
+;         <i> Enables and disables mass erase capability of the FTFL module
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
+                DCB     FSEC,       FOPT,       FEPROT,     FDPROT
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  DMA0_DMA16_IRQHandler     [WEAK]
+                EXPORT  DMA1_DMA17_IRQHandler     [WEAK]
+                EXPORT  DMA2_DMA18_IRQHandler     [WEAK]
+                EXPORT  DMA3_DMA19_IRQHandler     [WEAK]
+                EXPORT  DMA4_DMA20_IRQHandler     [WEAK]
+                EXPORT  DMA5_DMA21_IRQHandler     [WEAK]
+                EXPORT  DMA6_DMA22_IRQHandler     [WEAK]
+                EXPORT  DMA7_DMA23_IRQHandler     [WEAK]
+                EXPORT  DMA8_DMA24_IRQHandler     [WEAK]
+                EXPORT  DMA9_DMA25_IRQHandler     [WEAK]
+                EXPORT  DMA10_DMA26_IRQHandler     [WEAK]
+                EXPORT  DMA11_DMA27_IRQHandler     [WEAK]
+                EXPORT  DMA12_DMA28_IRQHandler     [WEAK]
+                EXPORT  DMA13_DMA29_IRQHandler     [WEAK]
+                EXPORT  DMA14_DMA30_IRQHandler     [WEAK]
+                EXPORT  DMA15_DMA31_IRQHandler     [WEAK]
+                EXPORT  DMA_Error_IRQHandler     [WEAK]
+                EXPORT  MCM_IRQHandler     [WEAK]
+                EXPORT  FTFE_IRQHandler     [WEAK]
+                EXPORT  Read_Collision_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  LLW_IRQHandler     [WEAK]
+                EXPORT  Watchdog_IRQHandler     [WEAK]
+                EXPORT  RNG_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  I2C1_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  SPI2_IRQHandler     [WEAK]
+                EXPORT  CAN0_ORed_Message_buffer_IRQHandler     [WEAK]
+                EXPORT  CAN0_Bus_Off_IRQHandler     [WEAK]
+                EXPORT  CAN0_Error_IRQHandler     [WEAK]
+                EXPORT  CAN0_Tx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN0_Rx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN0_Wake_Up_IRQHandler     [WEAK]
+                EXPORT  I2S0_Tx_IRQHandler     [WEAK]
+                EXPORT  I2S0_Rx_IRQHandler     [WEAK]
+                EXPORT  CAN1_ORed_Message_buffer_IRQHandler     [WEAK]
+                EXPORT  CAN1_Bus_Off_IRQHandler     [WEAK]
+                EXPORT  CAN1_Error_IRQHandler     [WEAK]
+                EXPORT  CAN1_Tx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN1_Rx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN1_Wake_Up_IRQHandler     [WEAK]
+                EXPORT  Reserved59_IRQHandler     [WEAK]
+                EXPORT  UART0_LON_IRQHandler     [WEAK]
+                EXPORT  UART0_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART0_ERR_IRQHandler     [WEAK]
+                EXPORT  UART1_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART1_ERR_IRQHandler     [WEAK]
+                EXPORT  UART2_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART2_ERR_IRQHandler     [WEAK]
+                EXPORT  UART3_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART3_ERR_IRQHandler     [WEAK]
+                EXPORT  UART4_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART4_ERR_IRQHandler     [WEAK]
+                EXPORT  UART5_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART5_ERR_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  ADC1_IRQHandler     [WEAK]
+                EXPORT  CMP0_IRQHandler     [WEAK]
+                EXPORT  CMP1_IRQHandler     [WEAK]
+                EXPORT  CMP2_IRQHandler     [WEAK]
+                EXPORT  FTM0_IRQHandler     [WEAK]
+                EXPORT  FTM1_IRQHandler     [WEAK]
+                EXPORT  FTM2_IRQHandler     [WEAK]
+                EXPORT  CMT_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  RTC_Seconds_IRQHandler     [WEAK]
+                EXPORT  PIT0_IRQHandler     [WEAK]
+                EXPORT  PIT1_IRQHandler     [WEAK]
+                EXPORT  PIT2_IRQHandler     [WEAK]
+                EXPORT  PIT3_IRQHandler     [WEAK]
+                EXPORT  PDB0_IRQHandler     [WEAK]
+                EXPORT  USB0_IRQHandler     [WEAK]
+                EXPORT  USBDCD_IRQHandler     [WEAK]
+                EXPORT  ENET_1588_Timer_IRQHandler     [WEAK]
+                EXPORT  ENET_Transmit_IRQHandler     [WEAK]
+                EXPORT  ENET_Receive_IRQHandler     [WEAK]
+                EXPORT  ENET_Error_IRQHandler     [WEAK]
+                EXPORT  Reserved95_IRQHandler     [WEAK]
+                EXPORT  SDHC_IRQHandler     [WEAK]
+                EXPORT  DAC0_IRQHandler     [WEAK]
+                EXPORT  DAC1_IRQHandler     [WEAK]
+                EXPORT  TSI0_IRQHandler     [WEAK]
+                EXPORT  MCG_IRQHandler     [WEAK]
+                EXPORT  LPTimer_IRQHandler     [WEAK]
+                EXPORT  Reserved102_IRQHandler     [WEAK]
+                EXPORT  PORTA_IRQHandler     [WEAK]
+                EXPORT  PORTB_IRQHandler     [WEAK]
+                EXPORT  PORTC_IRQHandler     [WEAK]
+                EXPORT  PORTD_IRQHandler     [WEAK]
+                EXPORT  PORTE_IRQHandler     [WEAK]
+                EXPORT  PORTF_IRQHandler     [WEAK]
+                EXPORT  Reserved109_IRQHandler     [WEAK]
+                EXPORT  SWI_IRQHandler     [WEAK]
+                EXPORT  NFC_IRQHandler     [WEAK]
+                EXPORT  USBHS_IRQHandler     [WEAK]
+                EXPORT  Reserved113_IRQHandler     [WEAK]
+                EXPORT  CMP3_IRQHandler     [WEAK]
+                EXPORT  Reserved115_IRQHandler     [WEAK]
+                EXPORT  Reserved116_IRQHandler     [WEAK]
+                EXPORT  FTM3_IRQHandler     [WEAK]
+                EXPORT  ADC2_IRQHandler     [WEAK]
+                EXPORT  ADC3_IRQHandler     [WEAK]
+                EXPORT  I2S1_Tx_IRQHandler     [WEAK]
+                EXPORT  I2S1_Rx_IRQHandler     [WEAK]
+                EXPORT  DefaultISR                      [WEAK]
+
+DMA0_DMA16_IRQHandler
+DMA1_DMA17_IRQHandler
+DMA2_DMA18_IRQHandler
+DMA3_DMA19_IRQHandler
+DMA4_DMA20_IRQHandler
+DMA5_DMA21_IRQHandler
+DMA6_DMA22_IRQHandler
+DMA7_DMA23_IRQHandler
+DMA8_DMA24_IRQHandler
+DMA9_DMA25_IRQHandler
+DMA10_DMA26_IRQHandler
+DMA11_DMA27_IRQHandler
+DMA12_DMA28_IRQHandler
+DMA13_DMA29_IRQHandler
+DMA14_DMA30_IRQHandler
+DMA15_DMA31_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+RNG_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+CAN1_ORed_Message_buffer_IRQHandler
+CAN1_Bus_Off_IRQHandler
+CAN1_Error_IRQHandler
+CAN1_Tx_Warning_IRQHandler
+CAN1_Rx_Warning_IRQHandler
+CAN1_Wake_Up_IRQHandler
+Reserved59_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+ENET_1588_Timer_IRQHandler
+ENET_Transmit_IRQHandler
+ENET_Receive_IRQHandler
+ENET_Error_IRQHandler
+Reserved95_IRQHandler
+SDHC_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved102_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+PORTF_IRQHandler
+Reserved109_IRQHandler
+SWI_IRQHandler
+NFC_IRQHandler
+USBHS_IRQHandler
+Reserved113_IRQHandler
+CMP3_IRQHandler
+Reserved115_IRQHandler
+Reserved116_IRQHandler
+FTM3_IRQHandler
+ADC2_IRQHandler
+ADC3_IRQHandler
+I2S1_Tx_IRQHandler
+I2S1_Rx_IRQHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/K60Fxxxx/drivers/system_MK60F12.c

@@ -0,0 +1,366 @@
+/*
+** ###################################################################
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K60P144M150SF3RM, Rev. 2, Dec 2011
+**     Version:             rev. 1.3, 2012-04-13
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2011-08-24)
+**         Initial version
+**     - rev. 1.1 (2011-11-03)
+**         Registers updated according to the new reference manual revision - Rev. 1, Oct 2011
+**         Registers of the following modules have been updated - AXBS, CAN, I2S, MCG, MPU, NFC, RCM, RTC, SDHC, SIM, USBHS, WDOG
+**         The following modules have been removed - DDR, DRY
+**     - rev. 1.2 (2012-01-04)
+**         Registers updated according to the new reference manual revision - Rev. 2, Dec 2011
+**         EWM - INTEN bit in EWM_CTRL register has been added.
+**         PDB - register PDB_PO0EN renamed to PRB_POEN.
+**         PMC - BGEN bit in PMC_REGSC register has been removed.
+**         SIM - several changes in SCGC registers. Bit USBHS in SOPT2 register removed.
+**         UART - new bits RXOFE in regiter CFIFO and RXOF in register SFIFO.
+**     - rev. 1.3 (2012-04-13)
+**         Added new #define symbol MCU_MEM_MAP_VERSION_MINOR.
+**         Added new #define symbols <peripheralType>_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK60F12
+ * @version 1.3
+ * @date 2012-04-13
+ * @brief Device specific configuration file for MK60F12 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK60F12.h"
+
+#define DISABLE_WDOG    1
+
+
+#define CLOCK_SETUP     1
+/* Predefined clock setups
+   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+         Reference clock source for MCG module is the slow internal clock source 32.768kHz
+         Core clock = 41.94MHz, BusClock = 41.94MHz
+   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+         Reference clock source for MCG module is an external reference clock source 50MHz
+         Core clock = 120MHz, BusClock = 60MHz
+   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+         Core clock/Bus clock derived directly from an external reference clock source 50MHz with no multiplication
+         Core clock = 50MHz, BusClock = 50MHz
+*/
+
+/*----------------------------------------------------------------------------
+  Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
+    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
+    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
+    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
+    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            120000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+    #define CPU_XTAL0_CLK_HZ                50000000u /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 0 */
+    #define CPU_XTAL1_CLK_HZ                8000000u  /* Value of the external crystal or oscillator clock frequency in Hz connected to System Oscillator 1 */
+    #define CPU_XTAL32k_CLK_HZ              32768u    /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+    #define CPU_INT_SLOW_CLK_HZ             32768u    /* Value of the slow internal oscillator clock frequency in Hz  */
+    #define CPU_INT_FAST_CLK_HZ             4000000u  /* Value of the fast internal oscillator clock frequency in Hz  */
+    #define DEFAULT_SYSTEM_CLOCK            50000000u  /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+#if (DISABLE_WDOG)
+  /* Disable the WDOG module */
+  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
+  /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
+  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+
+  /* System clock initialization */
+#if (CLOCK_SETUP == 0)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
+  /* SIM_SOPT2: PLLFLLSEL=0 */
+  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
+  /* SIM_SOPT1: OSC32KSEL=0 */
+  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
+  /* SIM_SCGC1: OSC1=1 */
+  SIM->SCGC1 |= (uint32_t)0x20UL;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+  /* Switch to FEI Mode */
+  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x06U;
+  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x20U;
+  /* MCG_C4: DMX32=0,DRST_DRS=1 */
+  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC1->CR = (uint8_t)0x80U;
+  /* MCG_C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
+  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
+  MCG->C5 = (uint8_t)0x00U;
+  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x00U;             /* 3 */
+  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
+  MCG->C11 = (uint8_t)0x00U;            /* 3 */
+  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
+  MCG->C12 = (uint8_t)0x00U;            /* 3 */
+  while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
+  }
+#elif (CLOCK_SETUP == 1)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers */
+  /* SIM_SOPT2: PLLFLLSEL=1 */
+  SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
+  /* SIM_SOPT1: OSC32KSEL=0 */
+  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
+  /* SIM_SCGC1: OSC1=1 */
+  SIM->SCGC1 |= (uint32_t)0x20UL;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+  /* Switch to FBE Mode */
+  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC1->CR = (uint8_t)0x80U;
+  /* MCG_C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
+  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x20U;
+  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0xAAU;
+  /* MCG_C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
+  MCG->C5 = (uint8_t)0x04U;
+  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
+  MCG->C6 = (uint8_t)0x08U;
+  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
+  MCG->C11 = (uint8_t)0x00U;
+  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
+  MCG->C12 = (uint8_t)0x00U;
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to PBE Mode */
+  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
+  MCG->C6 = (uint8_t)0x48U;
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
+  }
+  /* Switch to PEE Mode */
+  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x2AU;
+  while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
+  }
+#elif (CLOCK_SETUP == 2)
+  /* SIM_SCGC5: PORTA=1 */
+  SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00110000UL; /* Update system prescalers */
+  /* SIM_SOPT2: PLLFLLSEL=0 */
+  SIM->SOPT2 &= (uint32_t)~0x00030000UL; /* Select FLL as a clock source for various peripherals */
+  /* SIM_SOPT1: OSC32KSEL=0 */
+  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals */
+  /* SIM_SCGC1: OSC1=1 */
+  SIM->SCGC1 |= (uint32_t)0x20UL;
+  /* PORTA_PCR18: ISF=0,MUX=0 */
+  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+  /* Switch to FBE Mode */
+  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC0->CR = (uint8_t)0x80U;
+  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC1->CR = (uint8_t)0x80U;
+  /* MCG_C7: OSCSEL=0 */
+  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;
+  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x20U;
+  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0xAAU;
+  /* MCG_C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=0 */
+  MCG->C5 = (uint8_t)0x00U;
+  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+  MCG->C6 = (uint8_t)0x00U;
+  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
+  MCG->C11 = (uint8_t)0x00U;
+  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
+  MCG->C12 = (uint8_t)0x00U;
+  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to BLPE Mode */
+  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
+  MCG->C2 = (uint8_t)0x22U;
+  while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
+  }
+#endif /* (CLOCK_SETUP == 2) */
+
+  /* Disable MPU */
+  MPU->CESR &= ~MPU_CESR_VLD_MASK;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
+  uint8_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+        /* External reference clock is selected */
+        if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+          MCGOUTClock = CPU_XTAL0_CLK_HZ;                                       /* System oscillator 0 drives MCG clock */
+        } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
+        } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
+        if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
+        } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x0u:
+          MCGOUTClock *= 640u;
+          break;
+        case 0x20u:
+          MCGOUTClock *= 1280u;
+          break;
+        case 0x40u:
+          MCGOUTClock *= 1920u;
+          break;
+        case 0x60u:
+          MCGOUTClock *= 2560u;
+          break;
+        case 0x80u:
+          MCGOUTClock *= 732u;
+          break;
+        case 0xA0u:
+          MCGOUTClock *= 1464u;
+          break;
+        case 0xC0u:
+          MCGOUTClock *= 2197u;
+          break;
+        case 0xE0u:
+          MCGOUTClock *= 2929u;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+      /* PLL is selected */
+      if ((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u) {
+        /* PLL1 output is selected */
+        if ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u) {
+          /* OSC1 clock source used as an external reference clock */
+          MCGOUTClock = CPU_XTAL1_CLK_HZ;
+        } else { /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
+          /* OSC0 clock source used as an external reference clock */
+          MCGOUTClock = CPU_XTAL0_CLK_HZ;
+        } /* (!((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) != 0x0u)) */
+        Divider = (1u + (MCG->C11 & MCG_C11_PRDIV1_MASK));
+        MCGOUTClock /= Divider;                                                  /* Calculate the PLL reference clock */
+        Divider = ((MCG->C12 & MCG_C12_VDIV1_MASK) + 16u);
+        MCGOUTClock = (MCGOUTClock * Divider) / 2u;                              /* Calculate the MCG output clock */
+      } else { /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
+        /* PLL0 output is selected */
+        if ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u) {
+          /* OSC1 clock source used as an external reference clock */
+          MCGOUTClock = CPU_XTAL1_CLK_HZ;
+        } else { /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
+          /* OSC0 clock source used as an external reference clock */
+          MCGOUTClock = CPU_XTAL0_CLK_HZ;
+        } /* (!((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) != 0x0u)) */
+        Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+        MCGOUTClock /= Divider;                                                  /* Calculate the PLL reference clock */
+        Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 16u);
+        MCGOUTClock = (MCGOUTClock * Divider) / 2u;                              /* Calculate the MCG output clock */
+      } /* (!((MCG->C11 & MCG_C11_PLLCS_MASK) != 0x0u)) */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+    /* External reference clock is selected */
+    if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+      MCGOUTClock = CPU_XTAL0_CLK_HZ;                                           /* System oscillator drives MCG clock */
+    } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
+    } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

bsp/K60Fxxxx/readme.txt

@@ -0,0 +1,8 @@
+board info:
+Freescale Tower TWR-K60F120M
+http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-K60F120M
+with:
+TWR-SER
+http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-SER
+and TWR-ELEV
+http://www.freescale.com/zh-Hans/webapp/sps/site/prod_summary.jsp?code=TWR-ELEV

bsp/K60Fxxxx/rtconfig.h

@@ -0,0 +1,156 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	8
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+#define IDLE_THREAD_STACK_SIZE     1024
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* "Using Device Driver Framework" default="true" */
+#define RT_USING_DEVICE
+/* Using IPC in Device Driver Framework" default="true" */
+#define RT_USING_DEVICE_IPC
+/* Using Serial Device Driver Framework" default="true" */
+#define RT_USING_SERIAL
+
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+//#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_WORD_ACCESS
+/* Reentrancy (thread safe) of the FatFs module.  */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES			2
+/* #define RT_DFS_ELM_USE_LFN			1 */
+#define RT_DFS_ELM_MAX_LFN			255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
+
+#define RT_USING_DFS_ROMFS
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	201
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+/* TCP sender buffer space */
+#define RT_LWIP_TCP_SND_BUF	8192
+/* TCP receive window. */
+#define RT_LWIP_TCP_WND		8192
+
+#define CHECKSUM_CHECK_TCP              0
+#define CHECKSUM_CHECK_IP               0
+#define CHECKSUM_CHECK_UDP              0
+
+#define CHECKSUM_GEN_TCP                0
+#define CHECKSUM_GEN_IP                 0
+#define CHECKSUM_GEN_UDP                0
+
+#endif

bsp/K60Fxxxx/rtconfig.py

@@ -0,0 +1,83 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+TOWER_TYPE = 'K60FN1M0'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE 
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T k60_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k60.map --scatter k60_rom.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

bsp/K60Fxxxx/template.uvproj

@@ -0,0 +1,394 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread_mk60f120m</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MK60FN1M0xxx12</Device>
+          <Vendor>Freescale Semiconductor</Vendor>
+          <Cpu>IRAM(0x1FFF0000-0x1FFFFFFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x0-0xFFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4")  FPU2 ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Freescale\Kinetis\startup_MK60F12.s" ("Freescale MK60Xxxxxxx12 Startup Code")</StartupFile>
+          <FlashDriverDll>ULP2CM3(-O2510 -S0 -C0 -FO15 -FD20000000 -FC4000 -FN1 -FF0MK_P1M0 -FS00 -FL0100000)</FlashDriverDll>
+          <DeviceId>6123</DeviceId>
+          <RegisterFile>MK60F12.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Freescale\Kinetis\MK60F12.sfr</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
+          <DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>thread-mk60f120m</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>12</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>PEMicro\Pemicro_ArmCortexInterface.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4103</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>PEMicro\Pemicro_ArmCortexInterface.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF0000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>

bsp/allwinner_tina/.config

@@ -1,265 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
-CONFIG_RT_DEBUG=y
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_DEBUG_INIT=0
-CONFIG_RT_DEBUG_THREAD=0
-CONFIG_RT_USING_HOOK=y
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
-# CONFIG_RT_USING_MODULE is not set
-CONFIG_ARCH_ARM=y
-CONFIG_ARCH_ARM_ARM9=y
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
-
-#
-# Device virtual file system
-#
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=4
-CONFIG_RT_USING_DFS_ELMFAT=y
-
-#
-# elm-chan's FatFs, Generic FAT Filesystem Module
-#
-CONFIG_RT_DFS_ELM_CODE_PAGE=437
-CONFIG_RT_DFS_ELM_WORD_ACCESS=y
-CONFIG_RT_DFS_ELM_USE_LFN_0=y
-# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
-# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
-CONFIG_RT_DFS_ELM_USE_LFN=0
-CONFIG_RT_DFS_ELM_MAX_LFN=255
-CONFIG_RT_DFS_ELM_DRIVES=2
-CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
-# CONFIG_RT_DFS_ELM_USE_ERASE is not set
-CONFIG_RT_DFS_ELM_REENTRANT=y
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_NET is not set
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
-# CONFIG_RT_USING_DFS_NFS is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_USING_SERIAL=y
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_WIFI is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
-
-#
-# Network stack
-#
-
-#
-# light weight TCP/IP stack
-#
-# CONFIG_RT_USING_LWIP is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
-#
-# RT-Thread UI Engine
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_LOGTRACE is not set
-# CONFIG_RT_USING_RYM is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_PERSIMMON is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_IPERF is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-
-#
-# example package: hello
-#
-# CONFIG_PKG_USING_HELLO is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-CONFIG_TINA_USING_UART0=y
-# CONFIG_TINA_USING_UART1 is not set
-CONFIG_TINA_USING_UART2=y
-CONFIG_RT_USING_CPU_FFS=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048

bsp/allwinner_tina/Kconfig

@@ -1,29 +0,0 @@
-mainmenu "RT-Thread Configuration"
-
-config $BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config $RTT_DIR
-    string
-    option env="RTT_ROOT"
-    default "../.."
-
-# you can change the RTT_ROOT default "../.." to your rtthread_root,
-# example : default "F:/git_repositories/rt-thread"
-
-config $PKGS_DIR
-    string
-    option env="PKGS_ROOT"
-    default "packages"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-config SOC_TINA
-    bool 
-    select ARCH_ARM_ARM9
-    default y
-
-source "$BSP_DIR/drivers/Kconfig"

bsp/allwinner_tina/README.md

@@ -1,131 +0,0 @@
-# Allwinner tina板级支持包
-
-## 1. 简介
-
-Allwinner tina 是由全志公司推出的ARM9内核的SOC
-包括如下硬件特性：
-
-| 硬件 | 描述 |
-| -- | -- |
-|芯片型号| tina系列 |
-|CPU| ARM9 |
-|主频| 408MHz |
-|片内DDR | 32MB |
-|板载SPI Nor Flash | 8/16MB|
-
-## 2. 编译说明
-
-| 环境 | 说明 |
-| --- | --- |
-|PC操作系统|Linux/MacOS|
-|编译器|arm-none-eabi-gcc version 6.3.1 20170620 (release)|
-|构建工具|scons|
-1) 下载源码
-
-```
-    git clone https://github.com/RT-Thread/rt-thread.git
-```
-2) 配置工程并准备env
-```
-    cd rt-thread/bsp/allwinner_tina
-    scons --menuconfig
-    source ~/.env/env.sh
-    pkgs --upgrade
-    
-```
-3) 编译安装下载工具
-```
-    pushd /tmp
-    git clone https://github.com/Icenowy/sunxi-tools.git
-    pushd sunxi-tools
-    git checkout -b f1c100s origin/f1c100s
-    make
-    sudo make install
-    popd
-    popd
-```
-4) 编译
-```
-    scons
-```
-如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
-
-## 3. 烧写及执行
-**烧写工具目前仅支持Linux/MacOS环境,请在Linux/MaxOS环境下进行烧写操作**
-当正确编译产生出rtthread.bin映像文件后可以使用下面的方式来烧写到设备中。
-
-1)编译初始化引导文件
-编译依赖 arm-eabi-gcc
-```
-    pushd ../../..
-    git clone https://github.com/uestczyh222/tina-spl.git
-    pushd tina-spl
-    make
-    cp output/f1c100s.bin ../rt-thread/bsp/tina/tina-spl.bin
-    popd
-    popd
-```
-2)下载并运行
-
-```
-1.短接flash 1、4脚(当flash中无可引导代码时无需此步骤)
-2.连接USB
-3.松开短接的引脚
-4.输入下列指令
-```
-
-```
-    sudo sunxi-fel -p write  0x00000000 tina-spl.bin
-    sudo sunxi-fel exec 0x00000000
-    sudo sunxi-fel -p write  0x80000000 rtthread.bin
-    sudo sunxi-fel exec 0x80000000
-```
-
-### 3.1 运行结果
-
-如果编译 & 烧写无误，会在串口0上看到RT-Thread的启动logo信息：
-
-```
- \ | /
-- RT -     Thread Operating System
- / | \     3.0.2 build Feb  8 2018
- 2006 - 2017 Copyright by rt-thread team
-periph_get_pll_clk:600000000
-cpu_get_clk:408000000
-ahb_get_clk:200000000
-apb_get_clk:100000000
-msh />
-```
-
-
-## 4. 驱动支持情况及计划
-
-| 驱动 | 支持情况  |  备注  |
-| ------ | :----:  | :------:  |
-| UART | 支持 | UART0/1/2 |
-| GPIO | 支持 | / |
-| clock | 支持 | / |
-| mmu | 支持 | / |
-
-
-### 4.1 IO在板级支持包中的映射情况
-
-| IO号 | 板级包中的定义 |
-| -- | -- |
-| PE8 | USART2 RX |
-| PE7 | USART2 TX |
-| PA3 | USART1 RX |
-| PA2 | USART1 TX |
-| PE1 | USART0 TX |
-| PE0 | USART0 RX |
-
-
-## 5. 联系人信息
-
-维护人:
-[uestczyh222][4] < [lymz@foxmail.com][5] >
-
-
-  [1]: https://www.rt-thread.org/page/download.html
-  [4]: https://github.com/uestczyh222
-  [5]: mailto:lymz@foxmail.com

bsp/allwinner_tina/SConscript

@@ -1,14 +0,0 @@
-# for module compiling
-import os
-from building import *
-
-cwd = GetCurrentDir()
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')

bsp/allwinner_tina/SConstruct

@@ -1,27 +0,0 @@
-import os
-import sys
-import rtconfig
-
-from rtconfig import RTT_ROOT
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CC, CXXFLAGS = rtconfig.CXXFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
-    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
-
-# make a building
-DoBuilding(TARGET, objs)

bsp/allwinner_tina/applications/SConscript

@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/allwinner_tina/applications/main.c

@@ -1,36 +0,0 @@
-/*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2017-5-30      Bernard      the first version
- */
-
-#include "rtthread.h"
-#include "drv_clock.h"
-
-int main(int argc, char **argv)
-{
-    rt_kprintf("periph_get_pll_clk:%d\n", periph_get_pll_clk());
-    rt_kprintf("cpu_get_clk:%d\n", cpu_get_clk());
-    rt_kprintf("ahb_get_clk:%d\n", ahb_get_clk());
-    rt_kprintf("apb_get_clk:%d\n", apb_get_clk());
-
-    return 0;
-}

bsp/allwinner_tina/drivers/Kconfig

@@ -1,37 +0,0 @@
-
-
-config TINA_USING_UART0
-    bool "Using UART0"
-    select RT_USING_SERIAL
-    default n
-
-config TINA_USING_UART1
-    bool "Using UART1"
-    select RT_USING_SERIAL
-    default y
-
-config TINA_USING_UART2
-    bool "Using UART2"
-    select RT_USING_SERIAL
-    default y
-
-config TINA_USING_SDIO0
-    bool "Using SDIO0"
-    select RT_USING_SDIO
-    default y
-
-config TINA_USING_SPI0
-    bool "Using spi0"
-    select RT_USING_SPI
-    default y
-
-config TINA_USING_SPI1
-    bool "Using spi1"
-    select RT_USING_SPI
-    default y
-
-config TINA_USING_SPI_FLASH
-    bool "Using flash"
-    select TINA_USING_SPI0
-    select RT_USING_SFUD
-    default y