Merge pull request #2289 from armink/lts-v3.1.x

Lts v3.1.x
Update the changelog.
2025-11-16 12:34:33 +00:00 · 2019-01-29 04:28:40 +08:00 · 2019-01-28 19:59:47 +08:00 · 2019-01-28 19:48:14 +08:00 · 2019-01-21 18:17:51 +08:00 · 2019-01-21 13:50:22 +08:00
4878 changed files with 3669614 additions and 719908 deletions
--- a/.github/PULL_REQUEST_TEMPLATE.md
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -0,0 +1,33 @@
+## 拉取/合并请求描述：(PR description)
+
+[
+这段方括号里的内容是您**必须填写并替换掉**的，否则PR不可能被合并。**方括号外面的内容不需要修改，但请仔细阅读。**
+The content in this square bracket must be filled in and replaced, otherwise PR can not be merged. The contents outside square brackets need not be changed, but please read them carefully.
+
+请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
+Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
+
+并确认并列出已经在什么情况或板卡上进行了测试。
+And confirm in which case or board have been tested.
+]
+
+以下的内容不应该在提交PR时的message修改，修改下述message，PR会被直接关闭。请在提交PR后，浏览器查看PR并对以下检查项逐项check，没问题后逐条在页面上打钩。
+The following content must not be changed in submitted PR message. Otherwise, the PR will be closed immediately. After submitted PR, please use web browser to visit PR, and check items one by one, and ticked them if no problem.
+
+### 当前拉取/合并请求的状态 Intent for your PR
+
+必须选择一项 Choose one (Mandatory):
+
+- [ ] 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
+- [ ] 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo
+
+### 代码质量 Code Quality：
+
+我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
+
+- [ ] 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
+- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other style
+- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
+- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
+- [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
+- [ ] 本拉取/合并请求代码是高质量的 Code in this PR is of high quality
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,7 +28,7 @@ env:
  - RTT_BSP='asm9260t' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='at91sam9260' RTT_TOOL_CHAIN='sourcery-arm'
  - RTT_BSP='allwinner_tina' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='imxrt1052-evk' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='imxrt/imxrt1050-evk' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
  - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 
@@ -74,13 +74,30 @@ env:
  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f411-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='stm32f429-armfly' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm' 
  - RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f446-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f746-st-disco' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f767-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32g071-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
 #  - RTT_BSP='upd70f3454' # iar
 #  - RTT_BSP='x86' # x86
--- a/ChangeLog.md
+++ b/ChangeLog.md
@@ -1,3 +1,103 @@
+# RT-Thread v3.1.2 Change Log
+
+## Kernel
+
+* nothing
+
+## Components
+
+* When formatting the file system, adds FM_SFD option to create a volume in SFD format for FatFs; (HubretXie)
+* Add file system handle pointer in `struct dfs_fd' structure;
+* Fix stdio fd issue when POSIX api is used; (gbcwbz)
+* Fix the `fd_is_open()` issue: when the sub-path is the same in different mounted filesystem. 
+* Change the critical lock/unlock to dfs_lock/unlock in `getcwd()` function of DFS (the critical lock/unlock is different in SMP environment);
+* Fix the `aio_result` issue, which is returned by `aio_read_work` in AIO; (fullhan)
+* Fix the mmap issue when the addr parameter is NULL; (fullhan)
+* Modify the `_sys_istty` function in armlibc to correctly handle STDIN/STDOUT/STDERR; (gbcwbz)
+* Modify the `_write_r` function in newlib to correctly handle stdout.
+* Fix the at_socket issue when socket is a null pointer; (thomas onegd)
+* Fix the select event issue in `at_recvfrom()` function in at_socket;
+* Divide SAL into `sal_socket_ops/sal_proto_ops` and sal_proto_ops is implemented with gethostbyname/getaddrinfo ops etc.
+* Add socket TLS layer in SAL, that is, upper application can be supported by encrypted transmission without considering lowlevel TLS at all.
+* Fix the length issue of `ulog_strcpy`, which should be not exceed `ULOG_LINE_BUF_SIZE`;
+* Add the macro definition of hexadecimal log output to ulog; (HubretXie)
+* Add uTest component. The uTest is a unit test framework on RT-Thread, and can also be used for automatic testing on board with external Python scripts.
+* Fix some compilation warnings and enumeration mismatches in drivers/audio;
+* Fix the `can_rx/can_tx` issue, which is not cleared to NULL when CAN device is closed in drivers/can; (xeonxu)
+* Fix drivers/hwtimer, time acquisition issue with counting down mode;
+* Add drivers/adc driver framework;
+* Fix the tick compensation issue when enable interrupt too early; (geniusgogo)
+* Add `RT_SERIAL_USING_DMA` option in drivers/serial;
+* Add QSPI support in drivers/spi framework;
+* Add QSPI support in SFUD (based on the QSPI peripheral of stm32); SFUD is upgraded to version 1.1.0;
+* Optimize SPI take/release function call in spi_msd;
+* Fix the `blk_size` issue in `rt_rbb_blk_alloc()`;
+* Fix the FS USB issue in `_get_descriptor` function;
+* Fix the empty password issue in AP mode of drivers/wlan;
+* Fix the return type issue in drivers/wlan;
+* Remove the duplicate opening file check when open a file;
+
+# BSP
+
+* Change the name parameter to `cosnt char *` in `rt_hw_interrupt_install` function; (liruncong)
+* Fix `$` warning issue in Kconfig files of each BSP;
+* Add the LPC54114-lite BSP, including GPIO, I2C, SDCard, SPI, SPI Flash, UART driver;
+* Add Nuvoton-M487 BSP, including UART, EMAC driver; (Bluebear 233)
+* Fix the CAN driver issue in STM32F4XX-HAL BSP; (xeonxu)
+* Fix UART DMA settings issue in STM32F10x/STM32F40x BSP; (zhouchuanfu)
+* Fix the HEAP_BEGIN definition issue in STM32H743-Nucleo BSP; (nongxiaoming)
+* Fix GPIO configuration issue in stm32f10x-HAL; (Wu Han)
+* Change stm32f107 BSP as main function entry; (whj4674672)
+* Fix the serial interrupt handling issue in stm32f10x BSP;
+* Add PWM, RTC and watchdog drivers to stm32f10x-HAL BSP; (XXXXzzzz000)
+* Fix the watchdog driver issue in stm32f4xx-HAL BSP; (XXXXzzzz000)
+* Use lwIP version 2.x in stm32f40x/stm32f107 BSP.
+* Fix the link issue when enable CmBacktrace package in stm32f4xx-HAL BSP; (xeonxu)
+* Support Audio and microphones features in stm32f429-apollo BSP;
+* Enable dlmodule support in x86 BSP; (SASANO Takayoshi)
+* Addd uTest section in the link script of qemu-vexpress-a9/stm32f429-atk-apollo BSP for automatic testing;
+* Change the license to Apache License v2.0 in Godson 1C BSP; (sundm75)
+* Add the new BSP framework for STM32 serial chip, such as STM32 G0/F0/L0/F1/F4/F7/H7. In new BSP framework, the SoC drivers is reused. And in same time, lots of STM32 boards are supportted with new BSP framework:
+  * STM32F091-Nucleo Development Board BSP
+  * STM32F411-Nucleo Development Board BSP
+  * STM32L432-Nucleo Development Board BSP; (sun_shine)
+  * STM32F407-Discovery Development Board BSP
+  * STM32F446-Nucleo Development Board BSP; (andeyqi)
+  * STM32F746-Discovery Development Board BSP; (jinsheng)
+  * STM32F767-Nucleo Development Board BSP; (e31207077)
+  * STM32G071-Nucleo Development Board BSP;
+  * ATK STM32F103 NANO Development Board BSP
+  * ATK STM32F407 Explorer Development Board BSP
+  * ATK STM32F429 Apollo Development Board BSP
+  * ATK STM32F767 Apollo Development Board BSP
+  * ATK STM32L475 Pandora IoT Development Board BSP
+  * Fire STM32F103 Arbitrary Development Board BSP
+  * Fire STM32F429 Challenger Development Board BSP
+  * Fire STM32F767 Challenger Development Board BSP; (Hao Zhu)
+  * ArmFly STM32F429-v6 Development Board BSP
+  * STM32F103 iBox development board BSP; (dingo1688)
+  * Dofly STM32F103 Development Board; (FindYGL)
+  * STM32F107 uC/Eval Development Board BSP; (whj4674672)
+  * and more, there are more developers involved for stm32 BSP framework, they are HubretXie, Hao Zhu, e190, etc. to improve the STM32 public driver.
+* Add SWM320 BSP of Synwit.cn, including GPIO, HW Timer, I2C, Watchdog, PWM, RTC, SPI, UART, etc.; (provided and maintained by Synwit)
+* Add TI TMS320F28379D BSP, the first DSP chip supported on RT-Thread; (xuzhuoyi)
+* Fix USB driver issue in X1000; (Zhou YanJie)
+
+# Tool
+
+* Provide more inforamtion when the tool chain does not exist;
+* Add a draft Segger Embedded Studio project file generation command. Note that the tool chain in SES is a special version not the newlib.
+* Fix the IAR library link command issue when use scons command line under;
+* Fix the BSP path issue in scons `str(Dir('#'))`;
+* Add `scons --pyconfig-silent` command to add some Kconfig configurations and to generate `.config` and `rtconfig.h` files;
+* Update the `scons --dist` command to adapt to the new BSP framework;
+* Modify the mkromfs.py script. Fix the corresponding C code generation When the romfs contains empty files or empty folders;
+* Fix the issue of version string comparison issue for GNU GCC version in utils.py;
+* ENV updated to V1.1.0
+  * Provide better prompt information to improve user experience;
+  * Add `system32` path to environment variables to avoid the `cmd` command cannot be found;
+  * Add `PYTHONHOME` variable to environment variables to avoid PYTHON environment issue;
+
 # RT-Thread v3.1.1 Change Log

 ## Kernel
@@ -462,7 +562,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 *  修正USB host代码的编译错误；
 *  修正sensor框架回调函数的问题；
 *  修正pin设备注册时的设备名称问题；
- 
+
 而v2.1.0 alpha这个技术预览版则沿着最初设定的roadmap技术路线进行，这其中主要包括：

 *  lwip更深度的集成：把它集成到RT-Thread的文件系统接口中，这样Linux/Unix下的一些socket网络应用能够更顺利的移植到RT-Thread上，也为以后可以应用到更多地方的select接口铺路。
@@ -475,7 +575,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 以下是自v2.0.0 RC版本以来的详细更改记录。后续我还会给出v2.0.0版本自v1.2.x版本的主要不同、看点，以及给出下一个版本的roadmap规划。

 ## 内核
- 
+
 *  console以RT_DEVICE_FLAG_STREAM参数打开字符设备；
 *  在rt_memheap_free中加入更多的断言检查；

@@ -495,7 +595,7 @@ RT-Thread v2.0.1是2.0这个系列的bug修正版，而v2.1.0 alpha则是当前
 *  添加VBUS组件用于Linux与RT-Thread系统之间，RT-Thread与RT-Thread系统之间通信（睿赛德服务公司捐赠）；
 *  增加lwIP/NAT组件，可以做多个网口间的地址转换（Hicard）；
 *  增加lwIP/DHCP服务端，用于向客户端分配IP地址（睿赛德服务公司提供）；
- 
+
 ## BSP

 *  修正LPC4357串口驱动初始化时过早打开中断的问题（nongxiaoming）；
@@ -606,7 +706,7 @@ v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持
 * 启动timer前，对timer进行强制移除；
 * 在执行soft timer超时函数时，打开调度器锁；
 * 新增块设备的自动刷新参数，RT_DEVICE_CTRL_BLK_AUTOREFRESH；
- 
+
 ## 工具

 * 修正scons命令编译时，选择keil mdk (armcc)编译器时，命令行太长编译失败的问题；
@@ -659,7 +759,7 @@ v2.0.0版本的开发相对活跃些，开源社区提供了强有力的支持
 # RT-Thread 2.0.0 Alpha更改说明

 发布时间:2014/4/8
-	
+	
 RT-Thread 2.0.0分支的第一个技术预览版本，仅用于展示2.0.0发展分支的演化动向(按照roadmap，2.0.0这个分支会有一部分RT-Thread和Linux互补性的技术，为Linux增加更好的实时性，为RT-Thread增加更多的功能性，这份技术预览版正是朝着这个目标而努力)，欢迎反馈建议和问题。

 ## 组件
@@ -695,7 +795,7 @@ insmod rtvmm.ko
 # RT-Thread 1.2.1更改说明

 发布时间: 2014/4/8
-	
+	
 在原有的1.2.0版本的bug修正版本，也是1.2.0系列的第一个修正版本，原则上不添加任何的新功能，我们尽量会按照每个季度一个修订版本的方式推进。大家在使用的过程中有什么问题还请反馈给我们，这些问题很可能会在下个版本中修正！

 以下是更改记录：
@@ -741,7 +841,7 @@ insmod rtvmm.ko
 发布时间: 2014/1/6 

 实现roadmap中提到的大部分内容
-	
+	
 1，文档方面已完成《RT-Thread编程手册》，同时还有论坛上jiezhi童鞋的《一起来学RT-Thread系列连载教程》
 2，BSP分支方面新增cortext-A8(beaglebone)，cortext-R4(rm48x50)，UNITY-2(SEP6200),lpc408x的移植
 3，组件方面：
@@ -828,7 +928,7 @@ insmod rtvmm.ko
 # RT-Thread 1.2.0RC更改说明

 发布时间: 2013/10/10/ 10:19
-	 
+	 
 主要说明: 该版本新增ARM Cortex-A8的支持(BeagleBone)，新增UNITY-2内核的支持(SEP6200)，新增Ymodem协议。

 变更履历
@@ -923,7 +1023,7 @@ insmod rtvmm.ko
 版本: RT-Thread 1.2.0 Beta 版本

 发布时间: 2013/6/30
-		
+		
 进过开发人员三个月的努力，RT-Thread 1.2.0 Beta 版本如期发布。
 该版本默认采用lwIP 1.4.1协议栈，USB device stack也进一步完善。加入 log_trace 子系统，加入组件初始化升级版本，加入 ARM Cortex-R 的移植。

@@ -970,7 +1070,7 @@ insmod rtvmm.ko
 版本: RT-Thread 1.2.0 Alpha版本

 发布时间: 2013/4/10
-	
+	
 遵循2013年RT-Thread roadmap，RT-Thread 1.2.0 Alpha版本发布，Alpha意味着此版本为技术预览版，仅用于展示RT-Thread 1.2.0未来的发展方向，并不适合于开发正式产品。RT-Thread 1.2.0版本是1.1.x系列的下一个分支，这个分支主要体现的是RT-Thread 1.x系列的文档情况。当然也有一些功能、代码方面的增强。

 伴随着新版本的到来，RT-Thread有几个重大的转变：
--- a/README.md
+++ b/README.md
@@ -53,10 +53,6 @@ RT-Thread is Open Source software under the Apache License 2.0 since RT-Thread v

 Since 9th of September 2018, PRs submitted by the community may be merged into the main line only after signing the Contributor License Agreement(CLA).

-NOTE:
-
-RT-Thread using the Apache license v2.0 is only launched after the release of v3.1.1, and is still in preparation right now.
-
 ## Usage ##

 RT-Thread RTOS uses [scons](http://www.scons.org) as building system. Therefore, please install scons and Python 2.7 firstly. 
--- a/bsp/CME_M7/rtconfig.h
+++ b/bsp/CME_M7/rtconfig.h
@@ -55,6 +55,7 @@
 #define RT_USING_DEVICE
 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA

 /* SECTION: Console options */
 #define RT_USING_CONSOLE
@@ -100,8 +101,14 @@
 /* Enable DHCP */
 // #define RT_LWIP_DHCP

-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM		3
+#define RT_MEMP_NUM_NETCONN     12
+#define RT_LWIP_PBUF_NUM        3
+#define RT_LWIP_RAW_PCB_NUM     2
+#define RT_LWIP_UDP_PCB_NUM     4
+#define RT_LWIP_TCP_PCB_NUM     8
+#define RT_LWIP_TCP_SEG_NUM     40
+#define RT_LWIP_TCP_SND_BUF     4380
+#define RT_LWIP_TCP_WND         4380

 /* ip address of target */
 #define RT_LWIP_IPADDR "192.168.1.30"
--- a/bsp/CME_M7/rtconfig.py
+++ b/bsp/CME_M7/rtconfig.py
@@ -15,8 +15,10 @@ elif CROSS_TOOL == 'keil':
 	PLATFORM 	= 'armcc'
 	EXEC_PATH 	= 'C:/Keil'
 elif CROSS_TOOL == 'iar':
-	PLATFORM 	= 'iar'
-	EXEC_PATH 	= 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'	
+	print('================ERROR============================')
+	print('Not support iar yet!')
+	print('=================================================')
+	exit(0)

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -64,15 +66,14 @@ elif PLATFORM == 'armcc':
    LINK = 'armlink'
    TARGET_EXT = 'axf'

-    DEVICE = ' --cortex-m3'
+    DEVICE = ' --cpu Cortex-M3'
    CFLAGS = DEVICE + ' --c99 --apcs=interwork'
    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter nuc472_flash.sct'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter CME_M7.sct'

-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)' 

-    EXEC_PATH += '/arm/bin40/'
+    EXEC_PATH += '/ARM/ARMCC/bin'

    if BUILD == 'debug':
        CFLAGS += ' -g -O0'
--- a/bsp/allwinner_tina/.config
+++ b/bsp/allwinner_tina/.config
@@ -120,6 +120,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/allwinner_tina/Kconfig
+++ b/bsp/allwinner_tina/Kconfig
@@ -1,11 +1,11 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."
@@ -13,7 +13,7 @@ config $RTT_DIR
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example : default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/allwinner_tina/libcpu/interrupt.c
+++ b/bsp/allwinner_tina/libcpu/interrupt.c
@@ -132,7 +132,7 @@ void rt_hw_interrupt_umask(int vector)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;
    rt_uint32_t pend_addr, en_addr, data;
--- a/bsp/allwinner_tina/libcpu/interrupt.h
+++ b/bsp/allwinner_tina/libcpu/interrupt.h
@@ -102,6 +102,6 @@ typedef struct tina_intc *tina_intc_t;
 void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int vector);
 void rt_hw_interrupt_umask(int vector);
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, char *name);
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);

 #endif /* __INTERRUPT_H__ */
--- a/bsp/allwinner_tina/libcpu/start_gcc.S
+++ b/bsp/allwinner_tina/libcpu/start_gcc.S
@@ -48,7 +48,7 @@ _vector_reset:
 _vector_undef:
    .word vector_undef
 _vector_swi:
-    .word vector_swi
+    .word SVC_Handler
 _vector_pabt:
    .word vector_pabt
 _vector_dabt:
@@ -314,7 +314,9 @@ rt_hw_context_switch_interrupt_do:
    str     lr, [r0, #14*4]
 .endm

-    .align  5
+    .align 5
+.weak SVC_Handler
+SVC_Handler:
 vector_swi:
    push_svc_reg
    bl      rt_hw_trap_swi
--- a/bsp/allwinner_tina/rtconfig.h
+++ b/bsp/allwinner_tina/rtconfig.h
@@ -111,6 +111,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 /* RT_USING_CAN is not set */
 /* RT_USING_HWTIMER is not set */
 /* RT_USING_CPUTIME is not set */
--- a/bsp/allwinner_tina/rtconfig.py
+++ b/bsp/allwinner_tina/rtconfig.py
@@ -2,7 +2,7 @@ import os

 # toolchains options
 ARCH        ='arm'
-CPU         ='R6'
+CPU         ='arm9'
 CROSS_TOOL  ='gcc'

 if os.getenv('RTT_ROOT'):
--- a/bsp/amebaz/.config
+++ b/bsp/amebaz/.config
@@ -106,6 +106,7 @@ CONFIG_FINSH_ARG_MAX=10
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/amebaz/Kconfig
+++ b/bsp/amebaz/Kconfig
@@ -1,11 +1,11 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."
@@ -13,12 +13,12 @@ config $RTT_DIR
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example : default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
    
-config $ENV_DIR
+config ENV_DIR
    string
    option env="ENV_ROOT"
    default "/"
--- a/bsp/amebaz/SConstruct
+++ b/bsp/amebaz/SConstruct
@@ -27,7 +27,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 if rtconfig.PLATFORM == 'iar':
    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')

 Export('RTT_ROOT')
 Export('rtconfig')
--- a/bsp/amebaz/drivers/wlan/drv_wifi.c
+++ b/bsp/amebaz/drivers/wlan/drv_wifi.c
@@ -91,10 +91,16 @@ int rthw_wifi_register(struct ameba_wifi *wifi)

    if ((wifi->flag & WIFI_INIT_FLAG) == 0)
    {
+        wlan = rt_malloc(sizeof(struct rt_wlan_device));
+        RT_ASSERT(wlan != RT_NULL);
        if (wifi->type == WIFI_TYPE_STA)
-            wlan = rt_wlan_dev_register(RT_WLAN_DEVICE_STA_NAME, &ops, 0, wifi);
+        {
+            rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_STA_NAME, &ops, 0, wifi);
+        }
        if (wifi->type == WIFI_TYPE_AP)
-            wlan = rt_wlan_dev_register(RT_WLAN_DEVICE_AP_NAME, &ops, 0, wifi);
+        {
+            rt_wlan_dev_register(wlan, RT_WLAN_DEVICE_AP_NAME, &ops, 0, wifi);
+        }
        wifi->flag |= WIFI_INIT_FLAG;
        wifi->wlan = wlan;
        LOG_D("F:%s L:%d wifi:0x%08x wlan:0x%08x\n", __FUNCTION__, __LINE__, wifi, wlan);
--- a/bsp/amebaz/rtconfig.h
+++ b/bsp/amebaz/rtconfig.h
@@ -75,6 +75,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA

 /* Using WiFi */

--- a/bsp/apollo2/rtconfig.h
+++ b/bsp/apollo2/rtconfig.h
@@ -99,6 +99,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 /* RT_USING_CAN is not set */
 /* RT_USING_HWTIMER is not set */
 #define RT_USING_I2C
--- a/bsp/apollo2/rtconfig.py
+++ b/bsp/apollo2/rtconfig.py
@@ -64,16 +64,14 @@ elif PLATFORM == 'armcc':
    LINK = 'armlink'
    TARGET_EXT = 'axf'

-    DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
+    DEVICE = ' --cpu Cortex-M4'
+    CFLAGS = DEVICE + ' --c99 --apcs=interwork'
    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread-apollo2.sct'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread.sct'

-    CFLAGS += ' --c99'
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)' 

-    EXEC_PATH += '/arm/bin40/'
+    EXEC_PATH += '/ARM/ARMCC/bin'

    if BUILD == 'debug':
        CFLAGS += ' -g -O0'
--- a/bsp/asm9260t/.config
+++ b/bsp/asm9260t/.config
@@ -83,6 +83,7 @@ CONFIG_FINSH_CMD_SIZE=80
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_I2C is not set
--- a/bsp/asm9260t/Kconfig
+++ b/bsp/asm9260t/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/asm9260t/platform/interrupt.c
+++ b/bsp/asm9260t/platform/interrupt.c
@@ -151,7 +151,7 @@ void rt_hw_interrupt_umask(int irq)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/asm9260t/rtconfig.h
+++ b/bsp/asm9260t/rtconfig.h
@@ -75,6 +75,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 /* RT_USING_CAN is not set */
 /* RT_USING_HWTIMER is not set */
 /* RT_USING_I2C is not set */
--- a/bsp/at91sam9260/.config
+++ b/bsp/at91sam9260/.config
@@ -0,0 +1,311 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_INTERRUPT_INFO=y
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu"
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_RT_USING_DBGU=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_RT_USING_UART1 is not set
+# CONFIG_RT_USING_UART2 is not set
+# CONFIG_RT_USING_UART3 is not set
+CONFIG_RT_USING_LED=y
--- a/bsp/at91sam9260/Kconfig
+++ b/bsp/at91sam9260/Kconfig
@@ -0,0 +1,46 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config RT_USING_DBGU
+    bool "Using RT_USING_DBGU"
+    default y    
+	
+config RT_USING_UART0
+    bool "Using RT_USING_UART0"
+    default n    
+	
+config RT_USING_UART1
+    bool "Using RT_USING_UART1"
+    default n    
+	
+config RT_USING_UART2
+    bool "Using RT_USING_UART2"
+    default n    
+	
+config RT_USING_UART3
+    bool "Using RT_USING_UART3"
+    default n    
+	
+config RT_USING_LED
+	bool "Using RT_USING_LED"
+	default y
+	help
+		led blink demo
+ 
--- a/bsp/at91sam9260/applications/application.c
+++ b/bsp/at91sam9260/applications/application.c
@@ -96,7 +96,10 @@ int main(void)
 #endif
 	}
 #endif
-
+	
+#ifdef RT_USING_LED
+	rt_led_app_init();
+#endif
 }

 #ifdef RT_USING_LED
@@ -121,7 +124,6 @@ void rt_led_thread_entry(void* parameter)
 			led_on(3);
 		else
 			led_off(3);
-			
 	}
 }
 #endif
--- a/bsp/at91sam9260/drivers/board.c
+++ b/bsp/at91sam9260/drivers/board.c
@@ -43,7 +43,7 @@ extern unsigned char __bss_end__;
 #define HEAP_BEGIN  (__section_end(".noinit"))
 #endif

-#define HEAP_END    (0x24000000)
+#define HEAP_END    (((rt_uint32_t)HEAP_BEGIN & (0xF0 << 24)) + (32 << 20))

 extern void rt_hw_interrupt_init(void);
 extern void rt_hw_clock_init(void);
@@ -57,8 +57,8 @@ static struct mem_desc at91_mem_desc[] = {
 	{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
 	{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
 	{ 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
-	{ 0x90000000, 0x90400000 - 1, 0x00200000, RW_NCNB }, /* 4K SRAM0 + 4k SRAM1 */
-	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }   /* 64M none-cached SDRAM memory */
+	{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
+	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
 };


--- a/bsp/at91sam9260/drivers/led.c
+++ b/bsp/at91sam9260/drivers/led.c
@@ -26,12 +26,27 @@
 #include <at91sam926x.h>
 #include "led.h"

+#if 1
+// GB9260 board
+#define PIO_LED		AT91_PIOB
+#define LED1		(1 << 25)	// LED_SYS
+#define LED2		(0)
+#define LED3		(1 << 23)	// LED_USR
+#define LED_ALL		(LED1 | LED2 | LED3)
+#else
+#define PIO_LED		AT91_PIOC
+#define LED1		(1 << 8)
+#define LED2		(1 << 11)
+#define LED3		(1 << 6)
+#define LED_ALL		(LED1 | LED2 | LED3)
+#endif
+
 void led_init(void)
 {
-	at91_sys_write(AT91_PIOC, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x10, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x64, (1<<8)|(1<<11)|(1<<6));
-	at91_sys_write(AT91_PIOC+0x30, (1<<8)|(1<<11)|(1<<6));
+	at91_sys_write(PIO_LED+0x00, LED_ALL);
+	at91_sys_write(PIO_LED+0x10, LED_ALL);
+	at91_sys_write(PIO_LED+0x64, LED_ALL);
+	at91_sys_write(PIO_LED+0x30, LED_ALL);
 }

 void led_on(int num)
@@ -39,18 +54,17 @@ void led_on(int num)
 	switch(num)
 	{
 		case 1:
-			at91_sys_write(AT91_PIOC+0x34, 1<<8);
+			at91_sys_write(PIO_LED+0x34, LED1);
 			break;
 		case 2:
-			at91_sys_write(AT91_PIOC+0x34, 1<<11);
+			at91_sys_write(PIO_LED+0x34, LED2);
 			break;
 		case 3:
-			at91_sys_write(AT91_PIOC+0x34, 1<<6);
+			at91_sys_write(PIO_LED+0x34, LED3);
 			break;
 		default:
 			break;
 	}
-	
 }

 void led_off(int num)
@@ -58,16 +72,15 @@ void led_off(int num)
 	switch(num)
 	{
 		case 1:
-			at91_sys_write(AT91_PIOC+0x30, 1<<8);
+			at91_sys_write(PIO_LED+0x30, LED1);
 			break;
 		case 2:
-			at91_sys_write(AT91_PIOC+0x30, 1<<11);
+			at91_sys_write(PIO_LED+0x30, LED2);
 			break;
 		case 3:
-			at91_sys_write(AT91_PIOC+0x30, 1<<6);
+			at91_sys_write(PIO_LED+0x30, LED3);
 			break;
 		default:
 			break;
 	}
-	//at91_sys_write(AT91_PIOC+0x30, 1<<8);
 }
--- a/bsp/at91sam9260/platform/interrupt.c
+++ b/bsp/at91sam9260/platform/interrupt.c
@@ -30,7 +30,7 @@
 extern rt_uint32_t rt_interrupt_nest;

 /* exception and interrupt handler table */
-struct rt_irq_desc irq_desc[MAX_HANDLERS]; 
+struct rt_irq_desc irq_desc[MAX_HANDLERS];

 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;
@@ -101,17 +101,17 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
    rt_uint32_t isr, pio, irq_n;
    void *parameter;

-    if (vector == AT91SAM9260_ID_PIOA) 
+    if (vector == AT91SAM9260_ID_PIOA)
    {
        pio = AT91_PIOA;
        irq_n = AIC_IRQS;
    }
-    else if (vector == AT91SAM9260_ID_PIOB) 
+    else if (vector == AT91SAM9260_ID_PIOB)
    {
        pio = AT91_PIOB;
        irq_n = AIC_IRQS + 32;
    }
-    else if (vector == AT91SAM9260_ID_PIOC) 
+    else if (vector == AT91SAM9260_ID_PIOC)
    {
        pio = AT91_PIOC;
        irq_n = AIC_IRQS + 32*2;
@@ -119,9 +119,9 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector, void *param)
    else
        return RT_NULL;
    isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
-    while (isr) 
+    while (isr)
    {
-        if (isr & 1) 
+        if (isr & 1)
        {
            parameter = irq_desc[irq_n].param;
            irq_desc[irq_n].handler(irq_n, parameter);
@@ -175,7 +175,7 @@ static void at91_gpio_irq_init()
 {
    int i, idx;
    char *name[] = {"PIOA", "PIOB", "PIOC"};
-    
+
    at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff);
    at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff);
    at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff);
@@ -183,11 +183,13 @@ static void at91_gpio_irq_init()
    idx = AT91SAM9260_ID_PIOA;
    for (i = 0; i < 3; i++)
    {
-        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
        irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
        irq_desc[idx].param = RT_NULL;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
        irq_desc[idx].counter = 0;
-        idx++;
+#endif
+		idx++;
    }

    rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
@@ -203,7 +205,7 @@ void rt_hw_interrupt_init(void)
 {
    register rt_uint32_t idx;
    rt_uint32_t *priority = at91sam9260_default_irq_priority;
-    
+
    at91_extern_irq = (1UL << AT91SAM9260_ID_IRQ0) | (1UL << AT91SAM9260_ID_IRQ1)
            | (1UL << AT91SAM9260_ID_IRQ2);

@@ -213,10 +215,12 @@ void rt_hw_interrupt_init(void)
    /* init exceptions table */
    for(idx=0; idx < MAX_HANDLERS; idx++)
    {
-        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
        irq_desc[idx].param = RT_NULL;
-		irq_desc[idx].counter = 0;
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+#endif
    }

    at91_gpio_irq_init();
@@ -234,15 +238,15 @@ static void at91_gpio_irq_mask(int irq)

    bank = (irq - AIC_IRQS)>>5;

-    if (bank == 0) 
+    if (bank == 0)
    {
        pio = AT91_PIOA;
    }
-    else if (bank == 1) 
+    else if (bank == 1)
    {
        pio = AT91_PIOB;
    }
-    else if (bank == 2) 
+    else if (bank == 2)
    {
        pio = AT91_PIOC;
    }
@@ -258,7 +262,7 @@ static void at91_gpio_irq_mask(int irq)
 */
 void rt_hw_interrupt_mask(int irq)
 {
-    if (irq >= AIC_IRQS) 
+    if (irq >= AIC_IRQS)
    {
        at91_gpio_irq_mask(irq);
    }
@@ -275,15 +279,15 @@ static void at91_gpio_irq_umask(int irq)

    bank = (irq - AIC_IRQS)>>5;

-    if (bank == 0) 
+    if (bank == 0)
    {
        pio = AT91_PIOA;
    }
-    else if (bank == 1) 
+    else if (bank == 1)
    {
        pio = AT91_PIOB;
    }
-    else if (bank == 2) 
+    else if (bank == 2)
    {
        pio = AT91_PIOC;
    }
@@ -299,7 +303,7 @@ static void at91_gpio_irq_umask(int irq)
 */
 void rt_hw_interrupt_umask(int irq)
 {
-    if (irq >= AIC_IRQS) 
+    if (irq >= AIC_IRQS)
    {
        at91_gpio_irq_umask(irq);
    }
@@ -319,7 +323,7 @@ void rt_hw_interrupt_umask(int irq)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-                                    void *param, char *name)
+                                    void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

@@ -328,10 +332,12 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
        old_handler = irq_desc[vector].handler;
        if (handler != RT_NULL)
        {
-            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
            irq_desc[vector].handler = (rt_isr_handler_t)handler;
            irq_desc[vector].param = param;
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
 			irq_desc[vector].counter = 0;
+#endif
        }
    }

@@ -353,15 +359,15 @@ static int at91_aic_set_type(unsigned irq, unsigned type)
        srctype = AT91_AIC_SRCTYPE_RISING;
        break;
    case IRQ_TYPE_LEVEL_LOW:
-        // only supported on external interrupts 
-        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))     
+        // only supported on external interrupts
+        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
            srctype = AT91_AIC_SRCTYPE_LOW;
        else
            return -1;
        break;
    case IRQ_TYPE_EDGE_FALLING:
-        // only supported on external interrupts 
-        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))     
+        // only supported on external interrupts
+        if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))
            srctype = AT91_AIC_SRCTYPE_FALLING;
        else
            return -1;
@@ -409,7 +415,7 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
 void list_irq(void)
 {
 	int irq;
-	
+
 	rt_kprintf("number\tcount\tname\n");
 	for (irq = 0; irq < MAX_HANDLERS; irq++)
 	{
--- a/bsp/at91sam9260/rtconfig.h
+++ b/bsp/at91sam9260/rtconfig.h
@@ -1,253 +1,160 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__

-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	32
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */

-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	256
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-//#define SCHEDULER_DEBUG
-/* #define RT_THREAD_DEBUG */
+/* RT-Thread Kernel */

+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
-
-#define RT_USING_INTERRUPT_INFO
-
-/* Using Hook */
 #define RT_USING_HOOK
+#define RT_IDEL_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_DEBUG

-/* Using Software Timer */
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO		8
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
+/* Inter-Thread communication */

-/* SECTION: IPC */
-/* Using Semaphore */
 #define RT_USING_SEMAPHORE
-
-/* Using Mutex */
 #define RT_USING_MUTEX
-
-/* Using Event */
 #define RT_USING_EVENT
-
-/* Using MailBox */
 #define RT_USING_MAILBOX
-
-/* Using Message Queue */
 #define RT_USING_MESSAGEQUEUE

-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
+/* Memory Management */

-/* Using Dynamic Heap Management */
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
 #define RT_USING_HEAP

-/* Using Small MM */
-/* #define RT_USING_SMALL_MEM */
+/* Kernel Device Object */

-/* Using SLAB Allocator */
-#define RT_USING_SLAB
-
-/* SECTION: the runtime libc library */
-/* the runtime libc library */
-#define RT_USING_LIBC
-#define RT_USING_PTHREADS
-
-/* Using Module System */
-#define RT_USING_MODULE
-
-/* SECTION: Device System */
-/* Using Device System */
 #define RT_USING_DEVICE
-
-#define RT_USING_DEVICE_IPC
-#define RT_USING_SERIAL
-
-/* SECTION: Console options */
+#define RT_USING_INTERRUPT_INFO
 #define RT_USING_CONSOLE
-/* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "dbgu"

-/* SECTION: finsh, a C-Express shell */
-/* Using FinSH as Shell*/
-#define RT_USING_FINSH
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-#define FINSH_THREAD_STACK_SIZE 4096
-#define FINSH_USING_MSH
-
-/* SECTION: C++ support */
-/* Using C++ support */
-/* #define RT_USING_CPLUSPLUS */
-
-/* SECTION: Device filesystem support */
-/* using DFS support */
-#define RT_USING_DFS
-#define RT_USING_DFS_ELMFAT
-/* use long file name feature */
-#define RT_DFS_ELM_USE_LFN			2
-#define RT_DFS_ELM_REENTRANT
-/* define OEM code page */
-#define RT_DFS_ELM_CODE_PAGE	936
-/* Using OEM code page file */
-// #define RT_DFS_ELM_CODE_PAGE_FILE
-/* the max number of file length */
-#define RT_DFS_ELM_MAX_LFN			128
-/* #define RT_USING_DFS_YAFFS2 */
-#define RT_USING_DFS_DEVFS
-
-#define RT_USING_DFS_NFS
-#define RT_NFS_HOST_EXPORT		"192.168.1.5:/"
-
-#define DFS_USING_WORKDIR
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX		4
-/* the max number of opened files */
-#define DFS_FD_MAX					16
-/* the max number of cached sector */
-#define DFS_CACHE_MAX_NUM   		4
-
-/* Enable freemodbus protocol stack*/
-/* #define RT_USING_MODBUS */
-
-//#define RT_USING_LED
-
-#define RT_USING_SDIO
-
-#define RT_USING_I2C
-#define RT_USING_I2C_BITOPS
-
-#define RT_USING_DBGU
-/* #define RT_USING_UART0 */
-/* #define RT_USING_UART1 */
-/* #define RT_USING_UART2 */
-/* #define RT_USING_UART3 */
-
-/* SECTION: lwip, a lightweight TCP/IP protocol stack */
-/* Using lightweight TCP/IP protocol stack */
-#define RT_USING_LWIP
-#define RT_LWIP_DNS
-
-/* Trace LwIP protocol */
-// #define RT_LWIP_DEBUG
-
-/* Enable ICMP protocol */
-#define RT_LWIP_ICMP
-
-/* Enable IGMP protocol */
-#define RT_LWIP_IGMP
-
-/* Enable UDP protocol */
-#define RT_LWIP_UDP
-
-/* Enable TCP protocol */
-#define RT_LWIP_TCP
-
-/* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
-
-/* TCP sender buffer space */
-#define RT_LWIP_TCP_SND_BUF	1024*10
-
-/* TCP receive window. */
-#define RT_LWIP_TCP_WND	1024*8
-
-/* Enable SNMP protocol */
-/* #define RT_LWIP_SNMP */
-
-/* Using DHCP */
-/* #define RT_LWIP_DHCP */
-
-/* ip address of target */
-#define RT_LWIP_IPADDR "192.168.1.30"
-
-/* gateway address of target */
-#define RT_LWIP_GWADDR  "192.168.1.1"
-
-/* mask address of target */
-#define RT_LWIP_MSKADDR  "255.255.255.0"
-
-/* the number of blocks for pbuf */
-#define RT_LWIP_PBUF_NUM	16
-
-/* the number of simultaneously queued TCP */
-#define RT_LWIP_TCP_SEG_NUM    40
-
-/* thread priority of tcpip thread */
-#define RT_LWIP_TCPTHREAD_PRIORITY	128
-
-/* mail box size of tcpip thread to wait for */
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	32
-
-/* thread stack size of tcpip thread */
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
-
-/* thread priority of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_PRIORITY	144
-
-/* mail box size of ethnetif thread to wait for */
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	32
-
-/* thread stack size of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_STACKSIZE	1024
-
-
-/* SECTION: RTGUI support */
-/* using RTGUI support */
-/* #define RT_USING_RTGUI */
-
-/* name length of RTGUI object */
-//#define RTGUI_NAME_MAX		16
-/* support 16 weight font */
-//#define RTGUI_USING_FONT16
-/* support 16 weight font */
-//#define RTGUI_USING_FONT12
-/* support Chinese font */
-//#define RTGUI_USING_FONTHZ
-/* use DFS as file interface */
-//#define RTGUI_USING_DFS_FILERW
-/* use font file as Chinese font */
-/* #define RTGUI_USING_HZ_FILE */
-/* use Chinese bitmap font */
-//#define RTGUI_USING_HZ_BMP
-/* use small size in RTGUI */
-/* #define RTGUI_USING_SMALL_SIZE */
-/* use mouse cursor */
-/* #define RTGUI_USING_MOUSE_CURSOR */
-
-/* SECTION: FTK support */
-/* using FTK support */
-/* #define RT_USING_FTK */
-
-/*
- * Note on FTK:
- *
- * FTK depends :
- * #define RT_USING_NEWLIB
- * #define DFS_USING_WORKDIR
- *
- * And the maximal length must great than 64
- * #define RT_DFS_ELM_MAX_LFN	128
- */
+/* RT-Thread Components */

 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* sample package */
+
+/* samples: kernel and components samples */
+
+
+/* example package: hello */
+
+#define RT_USING_DBGU
+#define RT_USING_LED

 #endif
--- a/bsp/at91sam9260/rtconfig.py
+++ b/bsp/at91sam9260/rtconfig.py
@@ -11,6 +11,12 @@ if os.getenv('RTT_CC'):
 if  CROSS_TOOL == 'gcc':
 	PLATFORM 	= 'gcc'
 	EXEC_PATH = r'D:\arm-2013.11\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'

 if os.getenv('RTT_EXEC_PATH'):
 	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
--- a/bsp/at91sam9260/template.ewp
+++ b/bsp/at91sam9260/template.ewp
--- a/bsp/stm32f411-nucleo/template.eww
+++ b/bsp/stm32f411-nucleo/template.eww
--- a/bsp/at91sam9260/template.uvopt
+++ b/bsp/at91sam9260/template.uvopt
@@ -0,0 +1,174 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>18432000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\Listings\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>16</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DS.PDF</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Summary</Title>
+          <Path>DATASHTS\ATMEL\AT91SAM9260_DC.PDF</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>0</tLdApp>
+        <tGomain>0</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>1</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>5</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile>.\jlink\at91sam9260.ini</tIfile>
+        <pMon>Segger\JLTAgdi.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JLTAgdi</Key>
+          <Name>-O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2ARM</Key>
+          <Name>-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>
--- a/bsp/at91sam9260/template.uvproj
+++ b/bsp/at91sam9260/template.uvproj
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>AT91SAM9260</Device>
+          <Vendor>Atmel</Vendor>
+          <Cpu>IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S)</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</FlashDriverDll>
+          <DeviceId>4210</DeviceId>
+          <RegisterFile>AT91SAM9260.H</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
+          <DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\Objects\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\Listings\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARM.DLL</SimDllName>
+          <SimDllArguments>-cAT91SAM9260</SimDllArguments>
+          <SimDlgDll>DARMATS9.DLL</SimDlgDll>
+          <SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
+          <TargetDllName>SARM.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+            <RestoreSysVw>1</RestoreSysVw>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>0</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+            <RestoreSysVw>1</RestoreSysVw>
+            <UsePdscDebugDescription>1</UsePdscDebugDescription>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>5</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile>.\jlink\at91sam9260.ini</InitializationFile>
+            <Driver>Segger\JLTAgdi.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2ARM.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4>.\jlink\at91sam9260.ini</Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>ARM926EJ-S</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>1</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>0</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>1</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x800000</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x100000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x20800000</StartAddress>
+                <Size>0x1800000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x300000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>RT_USING_INTERRUPT_INFO</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath>.\platform</IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x20000000</TextAddressRange>
+            <DataAddressRange>0x20800000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\link_scripts\at91sam9260_ram.scat</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>
--- a/bsp/beaglebone/.config
+++ b/bsp/beaglebone/.config
@@ -115,6 +115,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/beaglebone/Kconfig
+++ b/bsp/beaglebone/Kconfig
@@ -1,11 +1,11 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."
@@ -13,12 +13,12 @@ config $RTT_DIR
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example: default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
    
-config $ENV_DIR
+config ENV_DIR
    string
    option env="ENV_ROOT"
    default "/"
--- a/bsp/beaglebone/rtconfig.h
+++ b/bsp/beaglebone/rtconfig.h
@@ -77,6 +77,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN

 /* Using USB */
--- a/bsp/ck802/.config
+++ b/bsp/ck802/.config
@@ -97,6 +97,7 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/ck802/Kconfig
+++ b/bsp/ck802/Kconfig
@@ -1,11 +1,11 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."
@@ -13,7 +13,7 @@ config $RTT_DIR
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example : default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/ck802/rtconfig.h
+++ b/bsp/ck802/rtconfig.h
@@ -71,6 +71,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN

 /* Using USB */
--- a/bsp/dm365/.config
+++ b/bsp/dm365/.config
@@ -134,6 +134,7 @@ CONFIG_RT_NFS_HOST_EXPORT="192.168.1.5:/"
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/dm365/Kconfig
+++ b/bsp/dm365/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/dm365/platform/interrupt.c
+++ b/bsp/dm365/platform/interrupt.c
@@ -253,7 +253,7 @@ void rt_hw_interrupt_umask(int irq)
 */

 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, char *name)
+									void *param, const char *name)
 {
 	rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/dm365/rtconfig.h
+++ b/bsp/dm365/rtconfig.h
@@ -125,6 +125,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 /* RT_USING_CAN is not set */
 /* RT_USING_HWTIMER is not set */
 /* RT_USING_CPUTIME is not set */
--- a/bsp/fh8620/drivers/interrupt.c
+++ b/bsp/fh8620/drivers/interrupt.c
@@ -169,7 +169,7 @@ void rt_hw_interrupt_umask(int irq)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-                                    void *param, char *name)
+                                    void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/fh8620/drivers/interrupt.h
+++ b/bsp/fh8620/drivers/interrupt.h
@@ -35,6 +35,6 @@ void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int irq);
 void rt_hw_interrupt_umask(int irq);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-		void *param, char *name);
+		void *param, const char *name);

 #endif /* INTERRUPT_H_ */
--- a/bsp/fh8620/rtconfig.h
+++ b/bsp/fh8620/rtconfig.h
@@ -74,6 +74,7 @@
 #define RT_USING_DEVICE_IPC
 // <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 // <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
 #define RT_UART_RX_BUFFER_SIZE    64
 // </section>
--- a/bsp/frdm-k64f/MK64F.sct
+++ b/bsp/frdm-k64f/MK64F.sct
@@ -7,7 +7,7 @@ LR_IROM1 0x00000000 0x100000  {    ; load region size_region (1000k)
  }
  ; 8_byte_aligned(62 vect * 4 bytes) =  8_byte_aligned(0x194) = 0x198
  ; 0x40000 - 0x198 = 0x3FE68
-  RW_IRAM1 0x1FFF0198 0x3FE68 {
+  RW_IRAM2 0x20000000 0x30000 {
   .ANY (+RW +ZI)
  }
 }
--- a/bsp/frdm-k64f/rtconfig.h
+++ b/bsp/frdm-k64f/rtconfig.h
@@ -63,6 +63,7 @@
 #define RT_USING_DEVICE_IPC
 /* Using Serial Device Driver Framework" default="true" */
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA

 // <section name="RT_USING_COMPONENTS_INIT" description="Using components init" default="false" >
 #define RT_USING_COMPONENTS_INIT
--- a/bsp/frdm-k64f/rtconfig.py
+++ b/bsp/frdm-k64f/rtconfig.py
@@ -64,17 +64,16 @@ elif PLATFORM == 'armcc':
    TARGET_EXT = 'axf'

    DEVICE = ' --cpu Cortex-M4.fp '
-    CFLAGS = DEVICE + ' --apcs=interwork'
+    CFLAGS = DEVICE + ' --c99 --apcs=interwork'
    AFLAGS = DEVICE
    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k64f.map --scatter MK64F.sct'

-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)' 

-    EXEC_PATH += '/arm/bin40/'
+    EXEC_PATH += '/ARM/ARMCC/bin'

    if BUILD == 'debug':
-        CFLAGS += ' --c99 -g -O0'
+        CFLAGS += ' -g -O0'
        AFLAGS += ' -g'
    else:
        CFLAGS += ' -O2'
--- a/bsp/gd32303e-eval/.config
+++ b/bsp/gd32303e-eval/.config
@@ -120,6 +120,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/gd32303e-eval/Kconfig
+++ b/bsp/gd32303e-eval/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/gd32303e-eval/SConstruct
+++ b/bsp/gd32303e-eval/SConstruct
@@ -27,7 +27,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 if rtconfig.PLATFORM == 'iar':
    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')

 Export('RTT_ROOT')
 Export('rtconfig')
--- a/bsp/gd32303e-eval/rtconfig.h
+++ b/bsp/gd32303e-eval/rtconfig.h
@@ -87,6 +87,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_I2C
 #define RT_USING_PIN
 #define RT_USING_SPI
--- a/bsp/gd32450z-eval/.config
+++ b/bsp/gd32450z-eval/.config
@@ -131,6 +131,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/gd32450z-eval/Kconfig
+++ b/bsp/gd32450z-eval/Kconfig
@@ -1,19 +1,19 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
-    default: "../.."
+    default "../.."
    
 # you can change the RTT_ROOT default: "rt-thread"
 # example : default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/gd32450z-eval/SConstruct
+++ b/bsp/gd32450z-eval/SConstruct
@@ -27,7 +27,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 if rtconfig.PLATFORM == 'iar':
    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')

 Export('RTT_ROOT')
 Export('rtconfig')
--- a/bsp/gd32450z-eval/rtconfig.h
+++ b/bsp/gd32450z-eval/rtconfig.h
@@ -88,6 +88,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN

 /* Using USB */
--- a/bsp/gkipc/.config
+++ b/bsp/gkipc/.config
@@ -123,6 +123,7 @@ CONFIG_RT_NFS_HOST_EXPORT="192.168.10.82:/"
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/gkipc/Kconfig
+++ b/bsp/gkipc/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/gkipc/armv6/interrupt.c
+++ b/bsp/gkipc/armv6/interrupt.c
@@ -97,7 +97,7 @@ void rt_hw_interrupt_umask(int irq)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                    void *param, char *name)
+                                    void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/gkipc/rtconfig.h
+++ b/bsp/gkipc/rtconfig.h
@@ -114,6 +114,7 @@

 #define RT_USING_DEVICE_IPC
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 /* RT_USING_CAN is not set */
 /* RT_USING_HWTIMER is not set */
 /* RT_USING_CPUTIME is not set */
--- a/bsp/hifive1/Kconfig
+++ b/bsp/hifive1/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/hifive1/drivers/interrupt.c
+++ b/bsp/hifive1/drivers/interrupt.c
@@ -110,7 +110,7 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
 * @return old handler
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/hifive1/drivers/interrupt.h
+++ b/bsp/hifive1/drivers/interrupt.h
@@ -32,6 +32,6 @@ void rt_hw_interrupt_init(void);
 rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
 void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name);
+        void *param, const char *name);
        
 #endif
--- a/bsp/imx6sx/cortex-a9/.config
+++ b/bsp/imx6sx/cortex-a9/.config
@@ -116,6 +116,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
--- a/bsp/imx6sx/cortex-a9/Kconfig
+++ b/bsp/imx6sx/cortex-a9/Kconfig
@@ -1,11 +1,11 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../../.."
@@ -13,12 +13,12 @@ config $RTT_DIR
 # you can change the RTT_ROOT default "../.." to your rtthread_root,
 # example: default "F:/git_repositories/rt-thread"

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
    
-config $ENV_DIR
+config ENV_DIR
    string
    option env="ENV_ROOT"
    default "/"
--- a/bsp/imx6sx/cortex-a9/cpu/interrupt.c
+++ b/bsp/imx6sx/cortex-a9/cpu/interrupt.c
@@ -110,7 +110,7 @@ void rt_hw_interrupt_umask(int vector)
 * @param old_handler the old interrupt service routine
 */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
    rt_isr_handler_t old_handler = RT_NULL;

--- a/bsp/imx6sx/cortex-a9/rtconfig.h
+++ b/bsp/imx6sx/cortex-a9/rtconfig.h
@@ -77,6 +77,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN

 /* Using USB */
--- a/bsp/imx6ul/Kconfig
+++ b/bsp/imx6ul/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
--- a/bsp/imx6ul/rtconfig.h
+++ b/bsp/imx6ul/rtconfig.h
@@ -72,6 +72,7 @@
 #define RT_USING_DEVICE_IPC
 // <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 // <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
 #define RT_UART_RX_BUFFER_SIZE    64
 // <bool name="RT_USING_INTERRUPT_INFO" description="Using interrupt information description" default="true" />
--- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c
+++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.c
@@ -33,7 +33,6 @@
 */

 #include "fsl_flexspi.h"
-
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.flexspi"
@@ -113,21 +112,21 @@ static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
 #endif

 /*! @brief Pointers to flexspi bases for each instance. */
-static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
+static FLEXSPI_Type *const s_flexspiBases[] SECTION("itcm") = FLEXSPI_BASE_PTRS;

 /*! @brief Pointers to flexspi IRQ number for each instance. */
-static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS;
+static const IRQn_Type s_flexspiIrqs[] SECTION("itcm") = FLEXSPI_IRQS;

 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /* Clock name array */
-static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS;
+static const clock_ip_name_t s_flexspiClock[] SECTION("itcm") = FLEXSPI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

 /*******************************************************************************
 * Code
 ******************************************************************************/

-uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
+SECTION("itcm") uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
 {
    uint32_t instance;

@@ -145,7 +144,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base)
    return instance;
 }

-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
+SECTION("itcm") static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config)
 {
    bool isUnifiedConfig = true;
    uint32_t flexspiDllValue;
@@ -199,7 +198,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
    return flexspiDllValue;
 }

-status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
+SECTION("itcm") status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
 {
    status_t result = kStatus_Success;

@@ -236,7 +235,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
    return result;
 }

-void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 {
    uint32_t configValue = 0;
    uint8_t i = 0;
@@ -309,7 +308,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
    base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
 }

-void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
+SECTION("itcm") void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
 {
    config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
    config->enableSckFreeRunning = false;
@@ -339,13 +338,13 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
    config->ahbConfig.enableAHBCachable = false;
 }

-void FLEXSPI_Deinit(FLEXSPI_Type *base)
+SECTION("itcm") void FLEXSPI_Deinit(FLEXSPI_Type *base) 
 {
    /* Reset peripheral. */
    FLEXSPI_SoftwareReset(base);
 }

-void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
+SECTION("itcm") void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)
 {
    uint32_t configValue = 0;
    uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */
@@ -416,7 +415,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
    base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
 }

-void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
+SECTION("itcm") void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
 {
    assert(index < 64U);

@@ -443,7 +442,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
    base->LUTCR = 0x01;
 }

-status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
    uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1;
    uint32_t status;
@@ -491,7 +490,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
    return result;
 }

-status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
+SECTION("itcm") status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
 {
    uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1;
    uint32_t status;
@@ -561,7 +560,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
    return result;
 }

-status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
 {
    uint32_t configValue = 0;
    status_t result = kStatus_Success;
@@ -618,7 +617,7 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
    return result;
 }

-void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
+SECTION("itcm") void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
                                  flexspi_handle_t *handle,
                                  flexspi_transfer_callback_t callback,
                                  void *userData)
@@ -643,7 +642,7 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
    EnableIRQ(s_flexspiIrqs[instance]);
 }

-status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
+SECTION("itcm") status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer)
 {
    uint32_t configValue = 0;
    status_t result = kStatus_Success;
@@ -709,7 +708,7 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
    return result;
 }

-status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
+SECTION("itcm") status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count)
 {
    assert(handle);

@@ -727,7 +726,7 @@ status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle,
    return result;
 }

-void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
    assert(handle);

@@ -735,7 +734,7 @@ void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle)
    handle->state = kFLEXSPI_Idle;
 }

-void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
+SECTION("itcm") void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
 {
    uint8_t status;
    status_t result;
@@ -832,7 +831,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)

 #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
 #if defined(FLEXSPI)
-void FLEXSPI_DriverIRQHandler(void)
+SECTION("itcm") void FLEXSPI_DriverIRQHandler(void)
 {
    FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -844,7 +843,7 @@ void FLEXSPI_DriverIRQHandler(void)
 #endif

 #if defined(FLEXSPI0)
-void FLEXSPI0_DriverIRQHandler(void)
+void FLEXSPI0_DriverIRQHandler(void) SECTION("itcm")
 {
    FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -855,7 +854,7 @@ void FLEXSPI0_DriverIRQHandler(void)
 }
 #endif
 #if defined(FLEXSPI1)
-void FLEXSPI1_DriverIRQHandler(void)
+void FLEXSPI1_DriverIRQHandler(void) SECTION("itcm")
 {
    FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
--- a/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h
+++ b/bsp/imxrt/Libraries/imxrt1050/devices/MIMXRT1052/drivers/fsl_flexspi.h
@@ -34,7 +34,7 @@

 #ifndef __FSL_FLEXSPI_H_
 #define __FSL_FLEXSPI_H_
-
+#include <rtthread.h>
 #include <stddef.h>
 #include "fsl_device_registers.h"
 #include "fsl_common.h"
@@ -401,7 +401,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
 *
 * @param base FLEXSPI peripheral base address.
 */
-static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+static SECTION("itcm") inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
 {
    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
    while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
@@ -415,7 +415,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
 * @param base FLEXSPI peripheral base address.
 * @param enable True means enable FLEXSPI, false means disable.
 */
-static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
 {
    if (enable)
    {
@@ -439,7 +439,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
 * @param base FLEXSPI peripheral base address.
 * @param mask FLEXSPI interrupt source.
 */
-static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
    base->INTEN |= mask;
 }
@@ -450,7 +450,7 @@ static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 * @param base FLEXSPI peripheral base address.
 * @param mask FLEXSPI interrupt source.
 */
-static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 {
    base->INTEN &= ~mask;
 }
@@ -466,7 +466,7 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
 * @param base FLEXSPI peripheral base address.
 * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
 */
-static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
 {
    if (enable)
    {
@@ -484,7 +484,7 @@ static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
 * @param base FLEXSPI peripheral base address.
 * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
 */
-static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
 {
    if (enable)
    {
@@ -502,7 +502,7 @@ static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
 * @param base FLEXSPI peripheral base address.
 * @retval The tx fifo address.
 */
-static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
 {
    return (uint32_t)&base->TFDR[0];
 }
@@ -513,7 +513,7 @@ static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
 * @param base FLEXSPI peripheral base address.
 * @retval The rx fifo address.
 */
-static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
 {
    return (uint32_t)&base->RFDR[0];
 }
@@ -529,7 +529,7 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
 * @param txFifo Pass true to reset TX FIFO.
 * @param rxFifo Pass true to reset RX FIFO.
 */
-static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
+static SECTION("itcm") inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
 {
    if (txFifo)
    {
@@ -550,7 +550,7 @@ static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFi
 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
 *      Pass NULL if this value is not required.
 */
-static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
+static SECTION("itcm") inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
 {
    if (txCount)
    {
@@ -574,7 +574,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si
 * @param base FLEXSPI peripheral base address.
 * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
 */
-static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
+static SECTION("itcm") inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
 {
    return base->INTR;
 }
@@ -585,7 +585,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
 * @param base FLEXSPI peripheral base address.
 * @param interrupt status flag.
 */
-static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+static SECTION("itcm") inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
 {
    base->INTR |= mask;
 }
@@ -616,7 +616,7 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
 * @param base FLEXSPI peripheral base address.
 * @retval trigger source of current command sequence.
 */
-static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
+static SECTION("itcm") inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
 {
    return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
 }
@@ -627,7 +627,7 @@ static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FL
 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
 * @retval error code when IP command error detected.
 */
-static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
    *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
    return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
@@ -639,7 +639,7 @@ static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type
 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
 * @retval error code when AHB command error detected.
 */
-static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
+static SECTION("itcm") inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
 {
    *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
    return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
@@ -652,7 +652,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
 * @retval true Bus is idle.
 * @retval false Bus is busy.
 */
-static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+static SECTION("itcm") inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
 {
    return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
 }
@@ -668,7 +668,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
 * @param base FLEXSPI peripheral base address.
 * @param enable True means enable parallel mode, false means disable parallel mode.
 */
-static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
 {
    if (enable)
    {
@@ -685,7 +685,7 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
 * @param base FLEXSPI peripheral base address.
 * @param enable True means enable parallel mode, false means disable parallel mode.
 */
-static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
+static SECTION("itcm") inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
 {
    if (enable)
    {
@@ -715,7 +715,7 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
 * @param data The data bytes to send
 * @param fifoIndex Destination fifo index.
 */
-static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
+static SECTION("itcm") inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
 {
    base->TFDR[fifoIndex] = data;
 }
@@ -727,7 +727,7 @@ static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t
 * @param fifoIndex Source fifo index.
 * @return The data in the FIFO.
 */
-static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
+static SECTION("itcm") inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
 {
    return base->RFDR[fifoIndex];
 }
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/SConscript
@@ -11,7 +11,13 @@ drv_cache.c
 CPPPATH = [cwd]
 CPPDEFINES = []

-# add sdram driver code
+if GetDepend('BOARD_USING_QSPIFLASH'):
+    src += ['drv_flexspi_nor.c'] 
+
+if GetDepend('BOARD_USING_HYPERFLASH'):
+    src += ['drv_flexspi_hyper.c'] 
+    
+# add sdram driver code 
 if GetDepend('RT_USING_SDRAM'):
    src = src + ['drv_sdram.c'] 

@@ -21,7 +27,7 @@ if GetDepend('RT_USING_PIN'):

 # add rtc driver code
 if GetDepend('RT_USING_RTC_HP'):
-    src = src + ['drv_rtc.c'] 
+    src += ['drv_rtc.c'] 

 # add spibus driver code
 if GetDepend('RT_USING_SPI'):
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_hyper.c
@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[Hyper]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
+#define CUSTOM_LUT_LENGTH 48
+
+static flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */
+    .isSck2Enabled = false,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 0,
+    .CSSetupTime = 3,
+    .dataValidTime = 1,
+    .columnspace = 3,
+    .enableWordAddress = true,
+    .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
+    .AWRSeqNumber = 1,
+    .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 20,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+        /* Read Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+        /* Write Data */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
+        /* Read Status */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+        /* Write Enable */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+
+        /* Erase Sector  */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+        /* program page */
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
+            FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+        [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
+            kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
+};
+
+
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperbus_write(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    flashXfer.deviceAddress = addr * 2;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
+    flashXfer.data = buffer;
+    flashXfer.dataSize = bytes;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr) 
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base) 
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 2;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (readValue & 0x8000)
+        {
+            isBusy = false;
+        }
+        else
+        {
+            isBusy = true;
+        }
+
+        if (readValue & 0x3200)
+        {
+            status = kStatus_Fail;
+            break;
+        }
+
+    } while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address) 
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write enable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 4;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLEXSPI_NOR_SECTOR_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+ SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 2;
+    flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE,(void *)(FLEXSPI_AMBA_BASE+address),FLASH_PAGE_SIZE);
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base)
+{
+    /*
+     * Read ID-CFI Parameters
+     */
+    // CFI Entry
+    status_t status;
+    uint32_t buffer[2];
+    uint32_t data = 0x9800;
+    status = flexspi_nor_hyperbus_write(base, 0x555, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    // ID-CFI Read
+    // Read Query Unique ASCII String
+    status = flexspi_nor_hyperbus_read(base, 0x10, &buffer[0], sizeof(buffer));
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    buffer[1] &= 0xFFFF;
+    // Check that the data read out is  unicode "QRY" in big-endian order
+    if ((buffer[0] != 0x52005100) || (buffer[1] != 0x5900))
+    {
+        status = kStatus_Fail;
+        return status;
+    }
+    // ASO Exit
+    data = 0xF000;
+    status = flexspi_nor_hyperbus_write(base, 0x0, &data, 2);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    return status;
+}
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    // Set flexspi root clock to 166MHZ.
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26);   /* Set PLL3 PFD0 clock 332MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);   /* flexspi clock 83M, DDR mode, internal clock 42M. */
+
+    
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    /*Allow AHB read start address do not follow the alignment requirement. */
+    config.ahbConfig.enableReadAddressOpt = true;
+    /* enable diff clock and DQS */
+    config.enableSckBDiffOpt = true;
+    config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+    config.enableCombination = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+    
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+    
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    status = flexspi_nor_hyperflash_cfi(FLEXSPI);
+    /* Get vendor ID. */
+    if (status != kStatus_Success)
+    {
+        FLEXSPI_Enable(FLEXSPI, false);
+        CLOCK_DisableClock(FLEXSPI_CLOCK);
+        CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+        CLOCK_EnableClock(FLEXSPI_CLOCK);
+        FLEXSPI_Enable(FLEXSPI, true);
+        FLEXSPI_SoftwareReset(FLEXSPI);
+        rt_hw_interrupt_enable(level);
+        return status;
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+    CLOCK_DisableClock(FLEXSPI_CLOCK);
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); /* flexspi clock 332M, DDR mode, internal clock 166M. */
+    CLOCK_EnableClock(FLEXSPI_CLOCK);
+    FLEXSPI_Enable(FLEXSPI, true);
+    FLEXSPI_SoftwareReset(FLEXSPI);
+    rt_hw_interrupt_enable(level);
+    return 0;
+}
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_flexspi_nor.c
@@ -0,0 +1,373 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-07-05     ZYH    the first version
+ */
+#include <rtthread.h>
+#define PRINTF rt_kprintf
+#include "board.h"
+#include <rthw.h>
+#include "drv_flexspi.h"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME  "[FLEXSPI]"
+#define DBG_LEVEL         DBG_LOG
+#define DBG_COLOR
+#include <rtdbg.h>
+
+#define FLEXSPI_CLOCK kCLOCK_FlexSpi
+#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 1
+#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 3
+#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
+#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
+#define NOR_CMD_LUT_SEQ_IDX_READID 8
+#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
+#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
+#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
+#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
+#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 13
+#define CUSTOM_LUT_LENGTH 60
+#define FLASH_BUSY_STATUS_POL 1
+#define FLASH_BUSY_STATUS_OFFSET 0
+
+static flexspi_device_config_t deviceconfig =
+{
+    .flexspiRootClk = 100000000,
+    .flashSize = FLASH_SIZE,
+    .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval = 2,
+    .CSHoldTime = 3,
+    .CSSetupTime = 3,
+    .dataValidTime = 0,
+    .columnspace = 0,
+    .enableWordAddress = 0,
+    .AWRSeqIndex = 0,
+    .AWRSeqNumber = 0,
+    .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD,
+    .ARDSeqNumber = 1,
+    .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 0,
+};
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] =
+{
+    /* Normal read mode -SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Fast read mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Fast read quad mode - SDR */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x6B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
+
+    /* Read extend parameters */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Write Enable */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Erase Sector  */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+
+    /* Page Program - single mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Page Program - quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read ID */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xAB, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x18),
+    [4 * NOR_CMD_LUT_SEQ_IDX_READID + 1] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Enable Quad mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Enter QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x38, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Exit QPI mode */
+    [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xFF, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+
+    /* Read status register */
+    [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
+
+    /* Erase Chip */
+    [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
+    FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
+};
+
+
+
+SECTION("itcm") static status_t flexspi_nor_write_enable(FLEXSPI_Type *base, uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+
+    /* Write neable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_wait_bus_busy(FLEXSPI_Type *base)
+{
+    /* Wait status ready. */
+    bool isBusy;
+    uint32_t readValue;
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG;
+    flashXfer.data = &readValue;
+    flashXfer.dataSize = 1;
+
+    do
+    {
+        status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+        if (status != kStatus_Success)
+        {
+            return status;
+        }
+        if (FLASH_BUSY_STATUS_POL)
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = true;
+            }
+            else
+            {
+                isBusy = false;
+            }
+        }
+        else
+        {
+            if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET))
+            {
+                isBusy = false;
+            }
+            else
+            {
+                isBusy = true;
+            }
+        }
+
+    }
+    while (isBusy);
+
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_enable_quad_mode(FLEXSPI_Type *base)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status;
+    uint32_t writeValue = 0x40;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, 0);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Enable quad mode. */
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG;
+    flashXfer.data = &writeValue;
+    flashXfer.dataSize = 1;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write enable */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Command;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "flexspi tranfer error\n");
+        dbg_here
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src)
+{
+    status_t status;
+    flexspi_transfer_t flashXfer;
+
+    /* Write neable */
+    status = flexspi_nor_write_enable(base, address);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    /* Prepare page program command */
+    flashXfer.deviceAddress = address;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Write;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD;
+    flashXfer.data = (uint32_t *)src;
+    flashXfer.dataSize = FLASH_PAGE_SIZE;
+    status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy(base);
+    rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)(FLEXSPI_AMBA_BASE + address), FLEXSPI_NOR_SECTOR_SIZE);
+    return status;
+}
+
+SECTION("itcm") static status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId)
+{
+    uint32_t temp;
+    flexspi_transfer_t flashXfer;
+    flashXfer.deviceAddress = 0;
+    flashXfer.port = kFLEXSPI_PortA1;
+    flashXfer.cmdType = kFLEXSPI_Read;
+    flashXfer.SeqNumber = 1;
+    flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READID;
+    flashXfer.data = &temp;
+    flashXfer.dataSize = 1;
+
+    status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
+
+    *vendorId = temp;
+
+    return status;
+}
+
+SECTION("itcm") int rt_hw_flexspi_init(void)
+{
+    flexspi_config_t config;
+    status_t status;
+    uint8_t vendorID = 0;
+
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24);   /* Set PLL3 PFD0 clock 360MHZ. */
+    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
+    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);   /* flexspi clock 120M. */
+
+    dbg_log(DBG_INFO, "NorFlash Init\r\n");
+
+    FLEXSPI_GetDefaultConfig(&config);
+
+    config.ahbConfig.enableAHBPrefetch = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    status = flexspi_nor_get_vendor_id(FLEXSPI, &vendorID);
+    if (status != kStatus_Success)
+    {
+        return status;
+    }
+    dbg_log(DBG_INFO, "Vendor ID: 0x%x\r\n", vendorID);
+
+    status = flexspi_nor_enable_quad_mode(FLEXSPI);
+    if (status != kStatus_Success)
+    {
+        dbg_log(DBG_ERROR, "Entry Quad mode failed\r\n");
+        return status;
+    }
+    dbg_log(DBG_INFO, "NorFlash Init Done\r\n");
+    rt_hw_interrupt_enable(level);
+    return 0;
+}
--- a/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c
+++ b/bsp/imxrt/Libraries/imxrt1050/drivers/drv_pin.c
@@ -8,41 +8,41 @@
 * 2018-03-13     Liuguang     the first version.
 * 2018-03-19     Liuguang     add GPIO interrupt mode support.
 */
-#include "drv_pin.h" 
+#include "drv_pin.h"

-#include "fsl_common.h" 
-#include "fsl_iomuxc.h" 
-#include "fsl_gpio.h" 
+#include "fsl_common.h"
+#include "fsl_iomuxc.h"
+#include "fsl_gpio.h"

 #ifdef RT_USING_PIN

 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
-    #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif

 struct rt1052_pin
 {
-    rt_uint16_t   pin; 
-    GPIO_Type    *gpio; 
-    rt_uint32_t   gpio_pin; 
-}; 
+    rt_uint16_t   pin;
+    GPIO_Type    *gpio;
+    rt_uint32_t   gpio_pin;
+};

 struct rt1052_irq
 {
-    rt_uint16_t           enable; 
-    struct rt_pin_irq_hdr irq_info; 
+    rt_uint16_t           enable;
+    struct rt_pin_irq_hdr irq_info;
 };

-#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) 
-#define __RT1052_PIN_DEFAULT {0, 0, 0} 
-#define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN} 
+#define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0]))
+#define __RT1052_PIN_DEFAULT {0, 0, 0}
+#define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN}

-static struct rt_pin_ops rt1052_pin_ops; 
+static struct rt_pin_ops rt1052_pin_ops;

-static struct rt1052_pin rt1052_pin_map[] = 
+static struct rt1052_pin rt1052_pin_map[] =
 {
-    __RT1052_PIN_DEFAULT, 
-    
+    __RT1052_PIN_DEFAULT,
+
    /* GPIO4 */
    __RT1052_PIN( 1, GPIO4,  0),    /* GPIO_EMC_00 */
    __RT1052_PIN( 2, GPIO4,  1),    /* GPIO_EMC_01 */
@@ -76,7 +76,7 @@ static struct rt1052_pin rt1052_pin_map[] =
    __RT1052_PIN(30, GPIO4, 29),    /* GPIO_EMC_29 */
    __RT1052_PIN(31, GPIO4, 30),    /* GPIO_EMC_30 */
    __RT1052_PIN(32, GPIO4, 31),    /* GPIO_EMC_31 */
-    
+
    __RT1052_PIN(33, GPIO3, 18),    /* GPIO_EMC_32 */
    __RT1052_PIN(34, GPIO3, 19),    /* GPIO_EMC_33 */
    __RT1052_PIN(35, GPIO3, 20),    /* GPIO_EMC_34 */
@@ -86,10 +86,10 @@ static struct rt1052_pin rt1052_pin_map[] =
    __RT1052_PIN(39, GPIO3, 24),    /* GPIO_EMC_38 */
    __RT1052_PIN(40, GPIO3, 25),    /* GPIO_EMC_39 */
    __RT1052_PIN(41, GPIO3, 26),    /* GPIO_EMC_40 */
-    __RT1052_PIN(42, GPIO3, 27),    /* GPIO_EMC_41 */ 
-    
+    __RT1052_PIN(42, GPIO3, 27),    /* GPIO_EMC_41 */
+
    /* GPIO1 */
-    __RT1052_PIN(43, GPIO1,  0),    /* GPIO_AD_B0_00 */ 
+    __RT1052_PIN(43, GPIO1,  0),    /* GPIO_AD_B0_00 */
    __RT1052_PIN(44, GPIO1,  1),    /* GPIO_AD_B0_01 */
    __RT1052_PIN(45, GPIO1,  2),    /* GPIO_AD_B0_02 */
    __RT1052_PIN(46, GPIO1,  3),    /* GPIO_AD_B0_03 */
@@ -155,7 +155,7 @@ static struct rt1052_pin rt1052_pin_map[] =
    __RT1052_PIN(104, GPIO2, 29),    /* GPIO_B1_13 */
    __RT1052_PIN(105, GPIO2, 30),    /* GPIO_B1_14 */
    __RT1052_PIN(106, GPIO2, 31),    /* GPIO_B1_15 */
-    
+
    /* GPIO3 */
    __RT1052_PIN(107, GPIO3,  0),    /* GPIO_SD_B1_00 */
    __RT1052_PIN(108, GPIO3,  1),    /* GPIO_SD_B1_01 */
@@ -180,9 +180,9 @@ static struct rt1052_pin rt1052_pin_map[] =
    __RT1052_PIN(125, GPIO5,  0),    /* WAKEUP */
    __RT1052_PIN(126, GPIO5,  1),    /* PMIC_ON_REQ */
    __RT1052_PIN(127, GPIO5,  2)     /* PMIC_STBY_REQ */
-}; 
+};

-static struct rt1052_irq rt1052_irq_map[] = 
+static struct rt1052_irq rt1052_irq_map[] =
 {
    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
@@ -216,15 +216,15 @@ static struct rt1052_irq rt1052_irq_map[] =
    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
-}; 
+};

-void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
+void gpio_isr(GPIO_Type *base, rt_uint32_t gpio_pin)
 {
-    if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
+    if ((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
    {
-        GPIO_PortClearInterruptFlags(base, gpio_pin); 
-        
-        if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
+        GPIO_PortClearInterruptFlags(base, (1 << gpio_pin));
+
+        if (rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
        {
            rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args);
        }
@@ -233,124 +233,124 @@ void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)

 void GPIO1_Combined_0_15_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
    {
-        gpio_isr(GPIO1, gpio_pin); 
+        gpio_isr(GPIO1, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO1_Combined_16_31_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
    {
-        gpio_isr(GPIO1, gpio_pin); 
+        gpio_isr(GPIO1, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO2_Combined_0_15_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
    {
-        gpio_isr(GPIO2, gpio_pin); 
+        gpio_isr(GPIO2, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO2_Combined_16_31_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
    {
-        gpio_isr(GPIO2, gpio_pin); 
+        gpio_isr(GPIO2, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

-void GPIO3_Combined_0_15_IRQHandler(void) 
+void GPIO3_Combined_0_15_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
    {
-        gpio_isr(GPIO3, gpio_pin); 
+        gpio_isr(GPIO3, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO3_Combined_16_31_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
    {
-        gpio_isr(GPIO3, gpio_pin); 
+        gpio_isr(GPIO3, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO4_Combined_0_15_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    for (gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
    {
-        gpio_isr(GPIO4, gpio_pin); 
+        gpio_isr(GPIO4, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }
 void GPIO4_Combined_16_31_IRQHandler(void)
 {
-    rt_uint8_t gpio_pin; 
-    
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    for (gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
    {
-        gpio_isr(GPIO4, gpio_pin); 
+        gpio_isr(GPIO4, gpio_pin);
    }
-    
+
    rt_interrupt_leave();
 }

 void GPIO5_Combined_0_15_IRQHandler(void)
-{ 
-    rt_uint8_t gpio_pin; 
-    
+{
+    rt_uint8_t gpio_pin;
+
    rt_interrupt_enter();

-    for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
+    for (gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
    {
-        gpio_isr(GPIO5, gpio_pin); 
+        gpio_isr(GPIO5, gpio_pin);
    }

    rt_interrupt_leave();
@@ -359,143 +359,143 @@ void GPIO5_Combined_0_15_IRQHandler(void)
 static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
 {
    IRQn_Type irq_num = NotAvail_IRQn;  /* Invalid interrupt number */
-    
-    if(gpio == GPIO1)
+
+    if (gpio == GPIO1)
    {
-        if(gpio_pin <= 15)
+        if (gpio_pin <= 15)
        {
-            irq_num = GPIO1_Combined_0_15_IRQn; 
+            irq_num = GPIO1_Combined_0_15_IRQn;
        }
        else
        {
-            irq_num = GPIO1_Combined_16_31_IRQn; 
+            irq_num = GPIO1_Combined_16_31_IRQn;
        }
    }
-    else if(gpio == GPIO2)
+    else if (gpio == GPIO2)
    {
-        if(gpio_pin <= 15)
+        if (gpio_pin <= 15)
        {
-            irq_num = GPIO2_Combined_0_15_IRQn; 
+            irq_num = GPIO2_Combined_0_15_IRQn;
        }
        else
        {
-            irq_num = GPIO2_Combined_16_31_IRQn; 
+            irq_num = GPIO2_Combined_16_31_IRQn;
        }
    }
-    else if(gpio == GPIO3)
+    else if (gpio == GPIO3)
    {
-        if(gpio_pin <= 15)
+        if (gpio_pin <= 15)
        {
-            irq_num = GPIO3_Combined_0_15_IRQn; 
+            irq_num = GPIO3_Combined_0_15_IRQn;
        }
        else
        {
-            irq_num = GPIO3_Combined_16_31_IRQn; 
+            irq_num = GPIO3_Combined_16_31_IRQn;
        }
    }
-    else if(gpio == GPIO4)
+    else if (gpio == GPIO4)
    {
-        if(gpio_pin <= 15)
+        if (gpio_pin <= 15)
        {
-            irq_num = GPIO4_Combined_0_15_IRQn; 
+            irq_num = GPIO4_Combined_0_15_IRQn;
        }
        else
        {
-            irq_num = GPIO4_Combined_16_31_IRQn; 
+            irq_num = GPIO4_Combined_16_31_IRQn;
        }
    }
-    else if(gpio == GPIO5)
+    else if (gpio == GPIO5)
    {
-        if(gpio_pin <= 15)
+        if (gpio_pin <= 15)
        {
-            irq_num = GPIO5_Combined_0_15_IRQn; 
+            irq_num = GPIO5_Combined_0_15_IRQn;
        }
        else
        {
-            irq_num = GPIO5_Combined_16_31_IRQn; 
+            irq_num = GPIO5_Combined_16_31_IRQn;
        }
    }
-    
-    return irq_num; 
+
+    return irq_num;
 }

 static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
-    gpio_pin_config_t gpio; 
-    rt_uint32_t config_value = 0; 
-    
-    if((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0))
+    gpio_pin_config_t gpio;
+    rt_uint32_t config_value = 0;
+
+    if ((pin > __ARRAY_LEN(rt1052_pin_map)) || (pin == 0))
    {
-        return; 
-    }
-    
-    if(rt1052_pin_map[pin].gpio != GPIO5)
-    {
-        CLOCK_EnableClock(kCLOCK_Iomuxc); 
-        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1); 
-    }
-    else
-    {
-        CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
-        IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1); 
-    }
-    
-    gpio.outputLogic = 0; 
-    gpio.interruptMode = kGPIO_NoIntmode; 
-    
-    switch(mode)
-    {
-        case PIN_MODE_OUTPUT:
-        {
-            config_value = 0x1030U;
-            gpio.direction = kGPIO_DigitalOutput; 
-        }
-        break; 
-        
-        case PIN_MODE_INPUT:
-        {
-            config_value = 0x1030U;
-            gpio.direction = kGPIO_DigitalInput; 
-        }
-        break;
-        
-        case PIN_MODE_INPUT_PULLDOWN:
-        {
-            config_value = 0x1030U;
-            gpio.direction = kGPIO_DigitalInput; 
-        }
-        break; 
-        
-        case PIN_MODE_INPUT_PULLUP:
-        {
-            config_value = 0x5030U;
-            gpio.direction = kGPIO_DigitalInput; 
-        }
-        break;
-        
-        case PIN_MODE_OUTPUT_OD:
-        {
-            config_value = 0x1830U;
-            gpio.direction = kGPIO_DigitalOutput; 
-        }
-        break;
+        return;
    }

-    if(rt1052_pin_map[pin].gpio != GPIO5)
+    if (rt1052_pin_map[pin].gpio != GPIO5)
    {
-        IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); 
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+        IOMUXC_SetPinMux(0x401F8010U + pin * 4, 0x5U, 0, 0, 0, 1);
    }
    else
    {
-        IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); 
+        CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+        IOMUXC_SetPinMux(0x400A8000U + (pin - 125) * 4, 0x5U, 0, 0, 0, 1);
    }
-    
-    GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); 
+
+    gpio.outputLogic = 0;
+    gpio.interruptMode = kGPIO_NoIntmode;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+    {
+        config_value = 0x0030U;/* Drive Strength R0/6 */
+        gpio.direction = kGPIO_DigitalOutput;
+    }
+    break;
+
+    case PIN_MODE_INPUT:
+    {
+        config_value = 0x0830U;/* Open Drain Enable */
+        gpio.direction = kGPIO_DigitalInput;
+    }
+    break;
+
+    case PIN_MODE_INPUT_PULLDOWN:
+    {
+        config_value = 0x3030U;/* 100K Ohm Pull Down */
+        gpio.direction = kGPIO_DigitalInput;
+    }
+    break;
+
+    case PIN_MODE_INPUT_PULLUP:
+    {
+        config_value = 0xB030U;/* 100K Ohm Pull Up */
+        gpio.direction = kGPIO_DigitalInput;
+    }
+    break;
+
+    case PIN_MODE_OUTPUT_OD:
+    {
+        config_value = 0x0830U;/* Open Drain Enable */
+        gpio.direction = kGPIO_DigitalOutput;
+    }
+    break;
+    }
+
+    if (rt1052_pin_map[pin].gpio != GPIO5)
+    {
+        IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin * 4, config_value);
+    }
+    else
+    {
+        IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin - 125) * 4, config_value);
+    }
+
+    GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
 }

 static int rt1052_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
+    return GPIO_PinReadPadStatus(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
 }

 static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
@@ -504,188 +504,192 @@ static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 }

 static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
-    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+                                      rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
-    struct rt1052_pin* pin_map = RT_NULL; 
-    struct rt1052_irq* irq_map = RT_NULL; 
-    
-    pin_map = &rt1052_pin_map[pin]; 
-    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
-    
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    struct rt1052_pin *pin_map = RT_NULL;
+    struct rt1052_irq *irq_map = RT_NULL;
+
+    pin_map = &rt1052_pin_map[pin];
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
+
+    if (pin_map == RT_NULL || irq_map == RT_NULL)
    {
-        return RT_ENOSYS; 
+        return RT_ENOSYS;
    }
-    
-    if(irq_map->enable == PIN_IRQ_ENABLE)
+
+    if (irq_map->enable == PIN_IRQ_ENABLE)
    {
-        return RT_EBUSY; 
+        return RT_EBUSY;
    }
-    
-    irq_map->irq_info.pin  = pin; 
-    irq_map->irq_info.hdr  = hdr; 
-    irq_map->irq_info.mode = mode; 
-    irq_map->irq_info.args = args; 
-    
+
+    irq_map->irq_info.pin  = pin;
+    irq_map->irq_info.hdr  = hdr;
+    irq_map->irq_info.mode = mode;
+    irq_map->irq_info.args = args;
+
    return RT_EOK;
 }

 static rt_err_t rt1052_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
-    struct rt1052_pin* pin_map = RT_NULL; 
-    struct rt1052_irq* irq_map = RT_NULL; 
-    
-    pin_map = &rt1052_pin_map[pin]; 
-    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
-    
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    struct rt1052_pin *pin_map = RT_NULL;
+    struct rt1052_irq *irq_map = RT_NULL;
+
+    pin_map = &rt1052_pin_map[pin];
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
+
+    if (pin_map == RT_NULL || irq_map == RT_NULL)
    {
-        return RT_ENOSYS; 
+        return RT_ENOSYS;
    }
-    
-    if(irq_map->enable == PIN_IRQ_DISABLE)
+
+    if (irq_map->enable == PIN_IRQ_DISABLE)
    {
-        return RT_EOK; 
+        return RT_EOK;
    }
-    
-    irq_map->irq_info.pin  = PIN_IRQ_PIN_NONE; 
-    irq_map->irq_info.hdr  = RT_NULL; 
-    irq_map->irq_info.mode = PIN_IRQ_MODE_RISING; 
-    irq_map->irq_info.args = RT_NULL; 
-    
+
+    irq_map->irq_info.pin  = PIN_IRQ_PIN_NONE;
+    irq_map->irq_info.hdr  = RT_NULL;
+    irq_map->irq_info.mode = PIN_IRQ_MODE_RISING;
+    irq_map->irq_info.args = RT_NULL;
+
    return RT_EOK;
 }

 static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
 {
-    gpio_pin_config_t gpio; 
+    gpio_pin_config_t gpio;
    IRQn_Type irq_num;
-    rt_uint32_t config_value = 0x1b0a0; 
-    
-    struct rt1052_pin* pin_map = RT_NULL; 
-    struct rt1052_irq* irq_map = RT_NULL; 
-    
-    pin_map = &rt1052_pin_map[pin]; 
-    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
-    
-    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    rt_uint32_t config_value = 0;
+    struct rt1052_pin *pin_map = RT_NULL;
+    struct rt1052_irq *irq_map = RT_NULL;
+
+    pin_map = &rt1052_pin_map[pin];
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin];
+
+    if (pin_map == RT_NULL || irq_map == RT_NULL)
    {
-        return RT_ENOSYS; 
+        return RT_ENOSYS;
    }
-    
-    if(enabled == PIN_IRQ_ENABLE) 
+
+    if (enabled == PIN_IRQ_ENABLE)
    {
-        if(irq_map->enable == PIN_IRQ_ENABLE)
+        if (irq_map->enable == PIN_IRQ_ENABLE)
        {
-            return RT_EBUSY; 
+            return RT_EBUSY;
        }
-        
-        if(irq_map->irq_info.pin != pin)
+
+        if (irq_map->irq_info.pin != pin)
        {
-            return RT_EIO; 
+            return RT_EIO;
        }
-        
-        irq_map->enable = PIN_IRQ_ENABLE; 
-        
-        if(rt1052_pin_map[pin].gpio != GPIO5)
+
+        irq_map->enable = PIN_IRQ_ENABLE;
+
+        if (rt1052_pin_map[pin].gpio != GPIO5)
        {
-            CLOCK_EnableClock(kCLOCK_Iomuxc); 
-            IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
+            CLOCK_EnableClock(kCLOCK_Iomuxc);
+            IOMUXC_SetPinMux(0x401F8010U + pin * 4, 0x5U, 0, 0, 0, 1);
        }
        else
        {
-            CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
-            IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); 
+            CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+            IOMUXC_SetPinMux(0x400A8000U + (pin - 125) * 4, 0x5U, 0, 0, 0, 1);
        }
-        
-        gpio.direction     = kGPIO_DigitalInput; 
-        gpio.outputLogic   = 0; 
-        
-        switch(irq_map->irq_info.mode)
+
+        gpio.direction     = kGPIO_DigitalInput;
+        gpio.outputLogic   = 0;
+
+        switch (irq_map->irq_info.mode)
        {
-            case PIN_IRQ_MODE_RISING:
-            {
-                gpio.interruptMode = kGPIO_IntRisingEdge; 
-            }
-            break;
-            
-            case PIN_IRQ_MODE_FALLING:
-            {
-                gpio.interruptMode = kGPIO_IntFallingEdge; 
-            }
-            break;
-            
-            case PIN_IRQ_MODE_RISING_FALLING:
-            {
-                gpio.interruptMode = kGPIO_IntRisingOrFallingEdge; 
-            }
-            break;
-            
-            case PIN_IRQ_MODE_HIGH_LEVEL:
-            {
-                gpio.interruptMode = kGPIO_IntHighLevel; 
-            }
-            break;
-            
-            case PIN_IRQ_MODE_LOW_LEVEL:
-            {
-                gpio.interruptMode = kGPIO_IntLowLevel; 
-            }
-            break;
+        case PIN_IRQ_MODE_RISING:
+        {
+            config_value = 0x3030U;/* 100K Ohm Pull Down */
+            gpio.interruptMode = kGPIO_IntRisingEdge;
        }
-        
-        if(rt1052_pin_map[pin].gpio != GPIO5)
+        break;
+
+        case PIN_IRQ_MODE_FALLING:
        {
-            IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); 
+            config_value = 0xB030U;/* 100K Ohm Pull Up */
+            gpio.interruptMode = kGPIO_IntFallingEdge;
+        }
+        break;
+
+        case PIN_IRQ_MODE_RISING_FALLING:
+        {
+            config_value = 0x0830U;/* Open Drain Enable */
+            gpio.interruptMode = kGPIO_IntRisingOrFallingEdge;
+        }
+        break;
+
+        case PIN_IRQ_MODE_HIGH_LEVEL:
+        {
+            config_value = 0x3030U;/* 100K Ohm Pull Down */
+            gpio.interruptMode = kGPIO_IntHighLevel;
+        }
+        break;
+
+        case PIN_IRQ_MODE_LOW_LEVEL:
+        {
+            config_value = 0xB030U;/* 100K Ohm Pull Up */
+            gpio.interruptMode = kGPIO_IntLowLevel;
+        }
+        break;
+        }
+
+        if (rt1052_pin_map[pin].gpio != GPIO5)
+        {
+            IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin * 4, config_value);
        }
        else
        {
-            IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value); 
+            IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin - 125) * 4, config_value);
        }
-        
-        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
-        
+
+        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
+
        NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
        EnableIRQ(irq_num);
-        
-        GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); 
-        GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin); 
+
+        GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio);
+        GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin);
    }
-    else if(enabled == PIN_IRQ_DISABLE)
+    else if (enabled == PIN_IRQ_DISABLE)
    {
-        if(irq_map->enable == PIN_IRQ_DISABLE)
+        if (irq_map->enable == PIN_IRQ_DISABLE)
        {
-            return RT_EOK; 
+            return RT_EOK;
        }
-        
+
        irq_map->enable = PIN_IRQ_DISABLE;
-        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
-        
+        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
+
        NVIC_DisableIRQ(irq_num);
    }
    else
    {
-        return RT_EINVAL; 
+        return RT_EINVAL;
    }
-    
+
    return RT_EOK;
 }

 int rt_hw_pin_init(void)
 {
-    int ret = RT_EOK; 
-    
-    rt1052_pin_ops.pin_mode        = rt1052_pin_mode; 
-    rt1052_pin_ops.pin_read        = rt1052_pin_read; 
-    rt1052_pin_ops.pin_write       = rt1052_pin_write; 
-    rt1052_pin_ops.pin_attach_irq  = rt1052_pin_attach_irq; 
+    int ret = RT_EOK;
+
+    rt1052_pin_ops.pin_mode        = rt1052_pin_mode;
+    rt1052_pin_ops.pin_read        = rt1052_pin_read;
+    rt1052_pin_ops.pin_write       = rt1052_pin_write;
+    rt1052_pin_ops.pin_attach_irq  = rt1052_pin_attach_irq;
    rt1052_pin_ops.pin_detach_irq  = rt1052_pin_detach_irq;
-    rt1052_pin_ops.pin_irq_enable  = rt1052_pin_irq_enable; 
-    
+    rt1052_pin_ops.pin_irq_enable  = rt1052_pin_irq_enable;
+
    ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL);
-    
+
    return ret;
 }
-INIT_BOARD_EXPORT(rt_hw_pin_init); 
+INIT_BOARD_EXPORT(rt_hw_pin_init);

 #endif /*RT_USING_PIN */
--- a/bsp/imxrt/imxrt1050-ArchMix/.config
+++ b/bsp/imxrt/imxrt1050-ArchMix/.config
@@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=100
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -60,10 +61,12 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x30102
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_FPU=y
 CONFIG_ARCH_ARM_CORTEX_M7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set

 #
 # RT-Thread Components
@@ -102,8 +105,8 @@ CONFIG_FINSH_ARG_MAX=10
 #
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
 CONFIG_DFS_FD_MAX=16
 # CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_RT_USING_DFS_ELMFAT=y
@@ -135,6 +138,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 CONFIG_RT_USING_CPUTIME=y
@@ -142,13 +146,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y
 CONFIG_RT_USING_I2C=y
 CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
-# CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
 CONFIG_RT_SDIO_STACK_SIZE=512
 CONFIG_RT_SDIO_THREAD_PRIORITY=15
@@ -157,6 +162,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
 CONFIG_RT_MMCSD_MAX_PARTITION=16
 # CONFIG_RT_SDIO_DEBUG is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 # CONFIG_RT_USING_SFUD is not set
 # CONFIG_RT_USING_W25QXX is not set
@@ -219,6 +225,8 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set

 #
 # ARM CMSIS
@@ -235,6 +243,7 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
@@ -269,6 +278,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set

 #
 # security packages
@@ -289,7 +299,6 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
-# CONFIG_PKG_USING_BEEPPLAYER is not set

 #
 # tools packages
@@ -299,6 +308,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
 # CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set

 #
 # system packages
@@ -315,6 +326,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set

 #
 # peripheral libraries and drivers
@@ -326,6 +338,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set

 #
 # miscellaneous packages
@@ -339,10 +355,8 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set

 #
 # samples: kernel and components samples
@@ -351,14 +365,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
 CONFIG_SOC_IMXRT1052=y
 CONFIG_BOARD_RT1050_ArchMix=y
-# CONFIG_BOARD_USING_HYPERFLASH is not set
 CONFIG_BOARD_USING_QSPIFLASH=y

 #
--- a/bsp/imxrt/imxrt1050-ArchMix/Kconfig
+++ b/bsp/imxrt/imxrt1050-ArchMix/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
@@ -284,6 +284,7 @@ endmenu
    config RT_USING_RTC_HP
        bool "Using hp rtc"
        select RT_USING_RTC
+        select RT_USING_LIBC
        default n 
 #endmenu

--- a/bsp/imxrt/imxrt1050-ArchMix/SConstruct
+++ b/bsp/imxrt/imxrt1050-ArchMix/SConstruct
@@ -35,7 +35,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 if rtconfig.PLATFORM == 'iar':
    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')

 Export('RTT_ROOT')
 Export('rtconfig')
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/SConscript
@@ -5,11 +5,23 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 board.c
+drv_flexspi.c
 """)

 CPPPATH = [cwd]
 CPPDEFINES = []

+if GetDepend('PKG_USING_EASYFLASH'):
+    src += ['ports/ef_fal_port.c'] 
+
+if GetDepend('PKG_USING_FAL'):
+    src += ['ports/fal_flexspi_nor_flash_port.c'] 
+
+if GetDepend('PKG_USING_FAL') and GetDepend('PKG_USING_EASYFLASH'):
+    src += ['ports/fal_flash_init.c', 'ports/ef_update.c'] 
+
+CPPPATH += [cwd + '/ports']
+
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)

 Return('group')
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <rtthread.h>
+#include <drv_flexspi.h>
+
+INIT_PREV_EXPORT(rt_hw_flexspi_init);
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/drv_flexspi.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#ifndef __DRV_FLEXSPI_H__
+#define __DRV_FLEXSPI_H__
+#include "fsl_flexspi.h"
+#include "fsl_common.h"
+#ifdef BOARD_USING_QSPIFLASH
+#define FLASH_SIZE 0x2000 /* 64Mb/KByte */
+#define FLASH_PAGE_SIZE 256
+#define FLEXSPI_NOR_SECTOR_SIZE 0x1000 /* 4K */
+#elif defined(BOARD_USING_HYPERFLASH)
+#define FLASH_SIZE 0x10000 /* 512Mb/KByte */
+#define FLASH_PAGE_SIZE 512
+#define FLEXSPI_NOR_SECTOR_SIZE 0x40000 /* 256K */
+#endif
+#define FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
+extern int      rt_hw_flexspi_init(void);
+extern status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address);
+extern status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src);
+#endif
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_fal_port.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-19     armink       the first version
+ */
+
+#include <easyflash.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include <fal.h>
+
+/* EasyFlash partition name on FAL partition table */
+#define FAL_EF_PART_NAME               "env"
+
+/* default ENV set for user */
+static const ef_env default_env_set[] = {
+        {"stay_in_bootloader","0"},
+        {"check_upgrade","0"},
+        {"bootdelay","1"},
+};
+
+static char log_buf[RT_CONSOLEBUF_SIZE];
+static struct rt_semaphore env_cache_lock;
+static const struct fal_partition *part = NULL;
+
+/**
+ * Flash port for hardware initialize.
+ *
+ * @param default_env default ENV set for user
+ * @param default_env_size default ENV size
+ *
+ * @return result
+ */
+EfErrCode ef_port_init(ef_env const **default_env, size_t *default_env_size) {
+    EfErrCode result = EF_NO_ERR;
+
+    *default_env = default_env_set;
+    *default_env_size = sizeof(default_env_set) / sizeof(default_env_set[0]);
+
+    rt_sem_init(&env_cache_lock, "env lock", 1, RT_IPC_FLAG_PRIO);
+
+    part = fal_partition_find(FAL_EF_PART_NAME);
+    EF_ASSERT(part);
+
+    return result;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_read(uint32_t addr, uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    EF_ASSERT(size % 4 == 0);
+
+    fal_partition_read(part, addr, (uint8_t *)buf, size);
+
+    return result;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_erase(uint32_t addr, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    /* make sure the start address is a multiple of FLASH_ERASE_MIN_SIZE */
+    EF_ASSERT(addr % EF_ERASE_MIN_SIZE == 0);
+
+    if (fal_partition_erase(part, addr, size) < 0)
+    {
+        result = EF_ERASE_ERR;
+    }
+
+    return result;
+}
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+EfErrCode ef_port_write(uint32_t addr, const uint32_t *buf, size_t size) {
+    EfErrCode result = EF_NO_ERR;
+
+    EF_ASSERT(size % 4 == 0);
+
+    if (fal_partition_write(part, addr, (uint8_t *)buf, size) < 0)
+    {
+        result = EF_WRITE_ERR;
+    }
+
+    return result;
+}
+
+/**
+ * lock the ENV ram cache
+ */
+void ef_port_env_lock(void) {
+    rt_sem_take(&env_cache_lock, RT_WAITING_FOREVER);
+}
+
+/**
+ * unlock the ENV ram cache
+ */
+void ef_port_env_unlock(void) {
+    rt_sem_release(&env_cache_lock);
+}
+
+/**
+ * This function is print flash debug info.
+ *
+ * @param file the file which has call this function
+ * @param line the line number which has call this function
+ * @param format output format
+ * @param ... args
+ *
+ */
+void ef_log_debug(const char *file, const long line, const char *format, ...) {
+
+#ifdef PRINT_DEBUG
+
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] (%s:%ld) ", file, line);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+
+#endif
+
+}
+
+/**
+ * This function is print flash routine info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_log_info(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    ef_print("[Flash] ");
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    ef_print("%s", log_buf);
+    va_end(args);
+}
+/**
+ * This function is print flash non-package info.
+ *
+ * @param format output format
+ * @param ... args
+ */
+void ef_print(const char *format, ...) {
+    va_list args;
+
+    /* args point to the first variable parameter */
+    va_start(args, format);
+    /* must use vprintf to print */
+    rt_vsprintf(log_buf, format, args);
+    rt_kprintf("%s", log_buf);
+    va_end(args);
+}
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/ef_update.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <easyflash.h>
+#include <rtthread.h>
+#include <fsl_wdog.h>
+
+void reset(void)
+{
+    SCB->AIRCR = 0x05fa0000 | 0x04UL;
+    while (1)
+    {
+    }
+}
+MSH_CMD_EXPORT(reset, reset system.);
+
+#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) && defined(EF_USING_ENV)
+#include <finsh.h>
+#if defined(EF_USING_ENV)
+
+static void update(uint8_t argc, char **argv)
+{
+    ef_set_env("check_upgrade", "1");
+    ef_save_env();
+    reset();
+}
+MSH_CMD_EXPORT(update, reset and check update.);
+
+#endif /* defined(EF_USING_ENV) */
+#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_cfg.h
@@ -0,0 +1,52 @@
+/*
+ * File      : fal_cfg.h
+ * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-17     armink       the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+#define RT_FAL_BL_PART_LEN              (256*1024)
+#define RT_FAL_ENV_PART_LEN             (1*1024)
+#define RT_FAL_PT_PART_LEN              (1*1024)
+#define RT_FAL_APP_PART_LEN             (1*1024*1024)
+#define RT_FAL_DL_PART_LEN              (1*1024*1024)
+
+#define RT_FAL_FLASH_BASE               0
+#define RT_FAL_BL_PART_OFFSET           RT_FAL_FLASH_BASE
+#define RT_FAL_ENV_PART_OFFSET          (RT_FAL_BL_PART_OFFSET  + RT_FAL_BL_PART_LEN)
+#define RT_FAL_PT_PART_OFFSET           (RT_FAL_ENV_PART_OFFSET + RT_FAL_ENV_PART_LEN)
+#define RT_FAL_APP_PART_OFFSET          (RT_FAL_PT_PART_OFFSET  + RT_FAL_PT_PART_LEN)
+#define RT_FAL_DL_PART_OFFSET           (RT_FAL_APP_PART_OFFSET + RT_FAL_APP_PART_LEN)
+#define RT_FAL_FS_PART_OFFSET           (RT_FAL_DL_PART_OFFSET  + RT_FAL_DL_PART_LEN)
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                          \
+{                                                                               \
+    {FAL_PART_MAGIC_WROD,       "bl",   "norflash0",  RT_FAL_BL_PART_OFFSET,   RT_FAL_BL_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,      "env",   "norflash0", RT_FAL_ENV_PART_OFFSET,  RT_FAL_ENV_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,       "pt",   "norflash0",  RT_FAL_PT_PART_OFFSET,   RT_FAL_PT_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,      "app",   "norflash0", RT_FAL_APP_PART_OFFSET,  RT_FAL_APP_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD, "download",   "norflash0",  RT_FAL_DL_PART_OFFSET,   RT_FAL_DL_PART_LEN, 0}, \
+    {FAL_PART_MAGIC_WROD,       "fs",   "norflash0",  RT_FAL_FS_PART_OFFSET,                    0, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flash_init.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-29     flybreak     first implementation
+ */
+
+#include <rtthread.h>
+#include <fal.h>
+#include <easyflash.h>
+
+#define FAL_FS_PART_NAME               "fs"
+#define FAL_DOWNLOAD_PART_NAME         "download"
+
+int rt_fal_flash_init(void)
+{
+    fal_init();
+    easyflash_init();
+
+    fal_blk_device_create(FAL_FS_PART_NAME);
+    fal_char_device_create(FAL_DOWNLOAD_PART_NAME);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_fal_flash_init);
--- a/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c
+++ b/bsp/imxrt/imxrt1050-ArchMix/drivers/ports/fal_flexspi_nor_flash_port.c
@@ -0,0 +1,75 @@
+/*
+ * File      : rt_ota_flash_sfud_port.c
+ * COPYRIGHT (C) 2012-2018, Shanghai Real-Thread Technology Co., Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-26     armink       the first version
+ */
+
+#include <rtthread.h>
+#include <fal.h>
+#include <drv_flexspi.h>
+#include <rthw.h>
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    memcpy(buf,(const void *)(FLEXSPI_AMBA_BASE+offset),size);
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    static char write_buffer[FLASH_PAGE_SIZE];
+    size_t writen_size = 0;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    while(size)
+    {
+        if(size >= FLASH_PAGE_SIZE)
+        {
+            flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)buf);
+            size -= FLASH_PAGE_SIZE;
+            writen_size += FLASH_PAGE_SIZE;
+        }
+        else
+        {
+            memcpy(write_buffer,(const void *)(FLEXSPI_AMBA_BASE+offset),FLASH_PAGE_SIZE);
+            memcpy(write_buffer,buf,size);
+            flexspi_nor_flash_page_program(FLEXSPI,offset,(const unsigned int *)write_buffer);
+            writen_size += size;
+            size = 0;
+        }
+        offset += FLASH_PAGE_SIZE;
+        buf += FLASH_PAGE_SIZE;
+    }
+    rt_hw_interrupt_enable(level);
+    return writen_size;
+}
+
+static int erase(long offset, size_t size)
+{
+    size_t erase_size = size;
+    rt_uint32_t level;
+    level = rt_hw_interrupt_disable();
+    size = offset;
+    offset = (offset/FLEXSPI_NOR_SECTOR_SIZE)*FLEXSPI_NOR_SECTOR_SIZE;
+    size = erase_size + size - offset;
+    while(size)
+    {
+        flexspi_nor_flash_erase_sector(FLEXSPI,offset);
+        if(size >= FLEXSPI_NOR_SECTOR_SIZE)
+        {
+            size -= FLEXSPI_NOR_SECTOR_SIZE;
+        }
+        else
+        {
+            size = 0;
+        }
+        offset += FLEXSPI_NOR_SECTOR_SIZE;
+    }
+    rt_hw_interrupt_enable(level);
+    return erase_size;
+}
+struct fal_flash_dev nor_flash0 = { "norflash0", 0, FLASH_SIZE*1024, FLEXSPI_NOR_SECTOR_SIZE, {NULL, read, write, erase} };
+
--- a/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf
+++ b/bsp/imxrt/imxrt1050-ArchMix/flexspi_nor.scf
@@ -122,4 +122,13 @@ LR_IROM1 m_text_start m_text_size
        * (NonCacheable.init)
        * (NonCacheable)
    }
+  ITCM 0x400 0xFBFF {
+		;drv_flexspi_hyper.o(+RO)
+		;fsl_flexspi.o(+RO)
+		* (*CLOCK_DisableClock)
+		* (*CLOCK_ControlGate)
+		* (*CLOCK_EnableClock)
+		* (*CLOCK_SetDiv)
+		* (itcm)
+	}
 }
--- a/bsp/imxrt/imxrt1050-ArchMix/project.ewp
+++ b/bsp/imxrt/imxrt1050-ArchMix/project.ewp
--- a/bsp/imxrt/imxrt1050-ArchMix/project.eww
+++ b/bsp/imxrt/imxrt1050-ArchMix/project.eww
@@ -1,10 +1,10 @@
-<?xml version="1.0" encoding="iso-8859-1"?>
-
-<workspace>
-  <project>
-    <path>$WS_DIR$\project.ewp</path>
-  </project>
-  <batchBuild/>
-</workspace>
-
-
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+
--- a/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx
+++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvoptx
--- a/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx
+++ b/bsp/imxrt/imxrt1050-ArchMix/project.uvprojx
--- a/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h
+++ b/bsp/imxrt/imxrt1050-ArchMix/rtconfig.h
@@ -13,6 +13,7 @@
 #define RT_TICK_PER_SECOND 100
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 #define RT_DEBUG
@@ -38,6 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x30102
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_FPU
@@ -73,8 +75,8 @@

 #define RT_USING_DFS
 #define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
 #define DFS_FD_MAX 16
 #define RT_USING_DFS_ELMFAT

@@ -95,6 +97,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_CPUTIME
 #define RT_USING_CPUTIME_CORTEXM
 #define RT_USING_I2C
@@ -179,13 +182,8 @@
 /* miscellaneous packages */


-/* sample package */
-
 /* samples: kernel and components samples */

-
-/* example package: hello */
-
 #define SOC_IMXRT1052
 #define BOARD_RT1050_ArchMix
 #define BOARD_USING_QSPIFLASH
--- a/bsp/imxrt/imxrt1050-evk/.config
+++ b/bsp/imxrt/imxrt1050-evk/.config
@@ -15,6 +15,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=100
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -60,10 +61,12 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x30102
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_FPU=y
 CONFIG_ARCH_ARM_CORTEX_M7=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set

 #
 # RT-Thread Components
@@ -136,6 +139,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 CONFIG_RT_USING_CPUTIME=y
@@ -143,13 +147,14 @@ CONFIG_RT_USING_CPUTIME_CORTEXM=y
 CONFIG_RT_USING_I2C=y
 CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_SOFT_RTC is not set
-# CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
 CONFIG_RT_SDIO_STACK_SIZE=512
 CONFIG_RT_SDIO_THREAD_PRIORITY=15
@@ -158,6 +163,7 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
 CONFIG_RT_MMCSD_MAX_PARTITION=16
 # CONFIG_RT_SDIO_DEBUG is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 # CONFIG_RT_USING_SFUD is not set
 # CONFIG_RT_USING_W25QXX is not set
@@ -204,6 +210,7 @@ CONFIG_RT_USING_POSIX=y
 CONFIG_RT_USING_LWIP=y
 # CONFIG_RT_USING_LWIP141 is not set
 CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP210 is not set
 # CONFIG_RT_USING_LWIP_IPV6 is not set
 # CONFIG_RT_LWIP_IGMP is not set
 CONFIG_RT_LWIP_ICMP=y
@@ -271,6 +278,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set

 #
 # ARM CMSIS
@@ -287,6 +296,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # CONFIG_PKG_USING_PAHOMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
@@ -312,6 +322,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set

 #
 # IoT Cloud
@@ -320,6 +331,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set

 #
 # security packages
@@ -348,6 +360,9 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set

 #
 # system packages
@@ -363,9 +378,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
-# CONFIG_PKG_USING_CMSIS_LATEST_VERSION is not set
-# CONFIG_PKG_USING_CMSIS_V500 is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set

 #
 # peripheral libraries and drivers
@@ -376,6 +390,11 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_AP3216C is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set

 #
 # miscellaneous packages
@@ -389,10 +408,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set

 #
 # samples: kernel and components samples
@@ -401,11 +418,8 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
 CONFIG_SOC_IMXRT1052=y
 CONFIG_BOARD_USING_HYPERFLASH=y
 # CONFIG_BOARD_USING_QSPIFLASH is not set
--- a/bsp/imxrt/imxrt1050-evk/Kconfig
+++ b/bsp/imxrt/imxrt1050-evk/Kconfig
@@ -1,16 +1,16 @@
 mainmenu "RT-Thread Configuration"

-config $BSP_DIR
+config BSP_DIR
    string
    option env="BSP_ROOT"
    default "."

-config $RTT_DIR
+config RTT_DIR
    string
    option env="RTT_ROOT"
    default "../../.."

-config $PKGS_DIR
+config PKGS_DIR
    string
    option env="PKGS_ROOT"
    default "packages"
@@ -445,6 +445,7 @@ endmenu
    config RT_USING_RTC_HP
        bool "Using hp rtc"
        select RT_USING_RTC
+        select RT_USING_LIBC
        default n 
 #endmenu

--- a/bsp/imxrt/imxrt1050-evk/SConstruct
+++ b/bsp/imxrt/imxrt1050-evk/SConstruct
@@ -35,7 +35,7 @@ env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 if rtconfig.PLATFORM == 'iar':
    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
    env.Replace(ARFLAGS = [''])
-    env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')

 Export('RTT_ROOT')
 Export('rtconfig')
--- a/bsp/imxrt/imxrt1050-evk/drivers/SConscript
+++ b/bsp/imxrt/imxrt1050-evk/drivers/SConscript
@@ -5,6 +5,7 @@ cwd = GetCurrentDir()
 # add the general drivers.
 src = Split("""
 board.c
+drv_flexspi.c
 """)

 CPPPATH = [cwd]
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Bernard Xiong	b2c2958964	Merge pull request #2289 from armink/lts-v3.1.x Lts v3.1.x	2019-01-29 04:28:40 +08:00
armink	8ff9b7795f	Update the changelog.	2019-01-28 19:59:47 +08:00
armink	991c919dea	Sync from master (`aa1e41d04f`)	2019-01-28 19:48:14 +08:00
Bernard Xiong	dfebb30c91	Merge pull request #2238 from armink/lts-v3.1.x Sync from master latest version.	2019-01-21 18:17:51 +08:00
armink	b7996af186	Sync from master (`99bef01983`).	2019-01-21 13:50:22 +08:00
armink	0e977c00c4	Sync from master (`0889bafda8`).	2019-01-19 18:09:18 +08:00
Bernard Xiong	3dd0ebe6e7	Merge pull request #2158 from armink/lts-v3.1.x Lts v3.1.x	2019-01-07 18:05:42 +08:00
armink	18dfb50e9b	[bsp] Remove the at91sam9g45 bsp.	2019-01-07 09:12:31 +08:00
armink	56075ce8a3	[bsp] sync to master version(`366e28f476`), not contain stm32 new BSP.	2019-01-05 17:54:17 +08:00
armink	c0f15a59bb	[component] Sync to master (`366e28f476`).	2019-01-05 16:33:36 +08:00
Bernard Xiong	d113eb07f5	Merge pull request #2145 from armink/lts-v3.1.x Lts v3.1.x	2019-01-03 07:25:25 +08:00
armink	1805aadbbb	[component] Sync to latest version.	2019-01-02 16:49:57 +08:00
armink	ebc14b09d5	[example] Sync to latest version.	2019-01-02 16:06:03 +08:00
Bernard Xiong	af33226fab	Merge pull request #2135 from armink/lts-v3.1.x Sync the code to v3.1.2	2018-12-29 13:38:56 +08:00
armink	77623e8119	[bsp] Update tm4c19x and fix the warning in lwip-1.4.1	2018-12-29 12:04:28 +08:00
armink	715360de74	Update the rt_hw_interrupt_install input param to 'const char *name'.	2018-12-28 20:41:36 +08:00
armink	1bc7b8e61b	[libcpu] Sync to latest version.	2018-12-28 19:22:33 +08:00
armink	62a7c59c7a	[Tools] Sync to latest version.	2018-12-28 18:41:48 +08:00
armink	7a6a1e1107	[Kernel] Sync to latest version.	2018-12-28 18:41:03 +08:00
armink	506866e849	Update the version number to v3.1.2 .	2018-12-28 16:40:21 +08:00