[libcpu][cortex-a] Replace FPU init loop with rt_memset

Co-authored-by: BernardXiong <1241087+BernardXiong@users.noreply.github.com>

.github/ALL_BSP_COMPILE.json

@@ -195,6 +195,7 @@
         "stm32/stm32h563-st-nucleo",
         "stm32/stm32h503-st-nucleo",
         "stm32/stm32h723-st-nucleo",
+        "stm32/stm32h723-lxb-disco",
         "stm32/stm32h730-esphosted-evb",
         "stm32/stm32h743-armfly-v7",
         "stm32/stm32h743-atk-apollo",

.github/workflows/bsp_buildings.yml

@@ -293,15 +293,15 @@ jobs:
           name: 00_all_bsp_output_${{ github.sha }}  
           path: output/
 
-  # Post CI status to PR comment
-  post-ci-status:
-    needs: build
-    if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
-    uses: ./.github/workflows/post_ci_status.yml
-    with:
-      workflow_name: "RT-Thread BSP Static Build Check"
-      workflow_status: ${{ needs.build.result }}
-      pr_number: ${{ github.event.pull_request.number }}
-    permissions:
-      pull-requests: write
-      issues: write
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: build
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "RT-Thread BSP Static Build Check"
+  #     workflow_status: ${{ needs.build.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/ci_results_comment.yml

@@ -9,17 +9,17 @@
 
 name: CI Results Comment
 
-on:
-  workflow_run:
-    workflows:
-      - "RT-Thread BSP Static Build Check"
-      - "Static code analysis"
-      - "Check File Format and License"
-      - "utest_auto_run"
-      - "ToolsCI"
-      - "pkgs_test"
-    types:
-      - completed
+# on:
+#   workflow_run:
+#     workflows:
+#       - "RT-Thread BSP Static Build Check"
+#       - "Static code analysis"
+#       - "Check File Format and License"
+#       - "utest_auto_run"
+#       - "ToolsCI"
+#       - "pkgs_test"
+#     types:
+#       - completed
 
 permissions:
   pull-requests: write

.github/workflows/format_check.yml

@@ -31,15 +31,15 @@ jobs:
           pip install click chardet PyYaml
           python tools/ci/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'
 
-  # Post CI status to PR comment
-  post-ci-status:
-    needs: scancode_job
-    if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
-    uses: ./.github/workflows/post_ci_status.yml
-    with:
-      workflow_name: "Check File Format and License"
-      workflow_status: ${{ needs.scancode_job.result }}
-      pr_number: ${{ github.event.pull_request.number }}
-    permissions:
-      pull-requests: write
-      issues: write
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: scancode_job
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "Check File Format and License"
+  #     workflow_status: ${{ needs.scancode_job.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/post_ci_status.yml

@@ -9,21 +9,21 @@
 
 name: Post CI Status Comment
 
-on:
-  workflow_call:
-    inputs:
-      workflow_name:
-        description: 'Name of the workflow'
-        required: true
-        type: string
-      workflow_status:
-        description: 'Status of the workflow (success/failure)'
-        required: true
-        type: string
-      pr_number:
-        description: 'Pull request number'
-        required: true
-        type: number
+# on:
+#   workflow_call:
+#     inputs:
+#       workflow_name:
+#         description: 'Name of the workflow'
+#         required: true
+#         type: string
+#       workflow_status:
+#         description: 'Status of the workflow (success/failure)'
+#         required: true
+#         type: string
+#       pr_number:
+#         description: 'Pull request number'
+#         required: true
+#         type: number
 
 permissions:
   pull-requests: write

.github/workflows/static_code_analysis.yml

@@ -56,15 +56,15 @@ jobs:
           cd ..
           python tools/ci/cpp_check.py check
 
-  # Post CI status to PR comment
-  post-ci-status:
-    needs: scancode_job
-    if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
-    uses: ./.github/workflows/post_ci_status.yml
-    with:
-      workflow_name: "Static code analysis"
-      workflow_status: ${{ needs.scancode_job.result }}
-      pr_number: ${{ github.event.pull_request.number }}
-    permissions:
-      pull-requests: write
-      issues: write
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: scancode_job
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "Static code analysis"
+  #     workflow_status: ${{ needs.scancode_job.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/utest_auto_run.yml

@@ -305,15 +305,15 @@ jobs:
               break
             fi
           done
-  # Post CI status to PR comment
-  post-ci-status:
-    needs: test
-    if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
-    uses: ./.github/workflows/post_ci_status.yml
-    with:
-      workflow_name: "utest_auto_run"
-      workflow_status: ${{ needs.test.result }}
-      pr_number: ${{ github.event.pull_request.number }}
-    permissions:
-      pull-requests: write
-      issues: write
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: test
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "utest_auto_run"
+  #     workflow_status: ${{ needs.test.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

bsp/airm2m/air105/board/board.h

@@ -28,6 +28,5 @@ extern int __bss_end;
 #define HEAP_END    (void*)(0x20000000 + 0xA0000)
 
 void rt_hw_board_init(void);
-int rt_vbus_do_init(void);
 
 #endif

bsp/gd32/arm/gd32527I-eval/board/Kconfig

@@ -34,55 +34,63 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART0_RX_USING_DMA
                 bool "Enable UART0 RX DMA"
-                depends on BSP_USING_UART0
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART0_TX_USING_DMA
                 bool "Enable UART0 TX DMA"
-                depends on BSP_USING_UART0
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART0_DMA_PING_BUFSIZE
+                int "Set UART0 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA
+                default 64
+
             config BSP_UART0_RX_BUFSIZE
                 int "Set UART0 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART0_TX_BUFSIZE
                 int "Set UART0 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART1
                 bool "Enable UART1"
-                default n
+                default y
 
             config BSP_UART1_RX_USING_DMA
                 bool "Enable UART1 RX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART1_TX_USING_DMA
                 bool "Enable UART1 TX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART1_DMA_PING_BUFSIZE
+                int "Set UART1 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA
+                default 64
+
             config BSP_UART1_RX_BUFSIZE
                 int "Set UART1 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART1_TX_BUFSIZE
                 int "Set UART1 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART2
                 bool "Enable UART2"
@@ -90,27 +98,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART2_RX_USING_DMA
                 bool "Enable UART2 RX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART2_TX_USING_DMA
                 bool "Enable UART2 TX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
-            
+
+            config BSP_UART2_DMA_PING_BUFSIZE
+                int "Set UART2 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA
+                default 64
+
             config BSP_UART2_RX_BUFSIZE
                 int "Set UART2 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART2_TX_BUFSIZE
                 int "Set UART2 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART3
                 bool "Enable UART3"
@@ -118,27 +130,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART3_RX_USING_DMA
                 bool "Enable UART3 RX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART3_TX_USING_DMA
                 bool "Enable UART3 TX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART3_DMA_PING_BUFSIZE
+                int "Set UART3 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA
+                default 64
+
             config BSP_UART3_RX_BUFSIZE
                 int "Set UART3 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART3_TX_BUFSIZE
                 int "Set UART3 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART4
                 bool "Enable UART4"
@@ -146,27 +162,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART4_RX_USING_DMA
                 bool "Enable UART4 RX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART4_TX_USING_DMA
                 bool "Enable UART4 TX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART4_DMA_PING_BUFSIZE
+                int "Set UART4 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA
+                default 64
+
             config BSP_UART4_RX_BUFSIZE
                 int "Set UART4 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART4_TX_BUFSIZE
                 int "Set UART4 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART5
                 bool "Enable UART5"
@@ -174,27 +194,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART5_RX_USING_DMA
                 bool "Enable UART5 RX DMA"
-                depends on BSP_USING_UART5
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART5_TX_USING_DMA
                 bool "Enable UART5 TX DMA"
-                depends on BSP_USING_UART5
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART5_DMA_PING_BUFSIZE
+                int "Set UART5 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA
+                default 64
+
             config BSP_UART5_RX_BUFSIZE
                 int "Set UART5 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART5_TX_BUFSIZE
                 int "Set UART5 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART6
                 bool "Enable UART6"
@@ -202,55 +226,63 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART6_RX_USING_DMA
                 bool "Enable UART6 RX DMA"
-                depends on BSP_USING_UART6
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART6_TX_USING_DMA
                 bool "Enable UART6 TX DMA"
-                depends on BSP_USING_UART6
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART6_DMA_PING_BUFSIZE
+                int "Set UART6 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA
+                default 64
+
             config BSP_UART6_RX_BUFSIZE
                 int "Set UART6 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART6_TX_BUFSIZE
                 int "Set UART6 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
-            config BSP_USING_UART7
+                config BSP_USING_UART7
                 bool "Enable UART7"
                 default n
 
             config BSP_UART7_RX_USING_DMA
                 bool "Enable UART7 RX DMA"
-                depends on BSP_USING_UART7
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART7_TX_USING_DMA
                 bool "Enable UART7 TX DMA"
-                depends on BSP_USING_UART7
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART7_DMA_PING_BUFSIZE
+                int "Set UART7 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA
+                default 64
+
             config BSP_UART7_RX_BUFSIZE
                 int "Set UART7 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART7_TX_BUFSIZE
                 int "Set UART7 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
-                default 0
+                default 128
         endif
 
     menuconfig BSP_USING_SPI

bsp/gd32/arm/libraries/gd32_drivers/drv_usart_v2.c

@@ -263,7 +263,6 @@ static void dma_recv_isr (struct rt_serial_device *serial)
     RT_ASSERT(serial != RT_NULL);
     uart = rt_container_of(serial, struct gd32_uart, serial);
 
-    recv_len = 0;
     level = rt_hw_interrupt_disable();
     #if defined SOC_SERIES_GD32E23x
     counter = dma_transfer_number_get(uart->dma.rx.channel);
@@ -297,21 +296,14 @@ static void usart_isr (struct rt_serial_device *serial)
 
     if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_RBNE) != RESET)
     {
-        struct rt_serial_rx_fifo *rx_fifo;
-        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
-        RT_ASSERT(rx_fifo != RT_NULL);
-
-        char chr = usart_data_receive(uart->periph);
-        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
+        rt_uint8_t chr = usart_data_receive(uart->periph);
+        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, (void *)&chr);
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-
-        /* Clear RXNE interrupt flag */
-        usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_RBNE);
     }
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TBE) != RESET)
     {
         rt_uint8_t put_char = 0;
-        if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
+        if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, (void *)&put_char) == RT_EOK)
         {
             usart_data_transmit(uart->periph, put_char);
         }
@@ -320,7 +312,6 @@ static void usart_isr (struct rt_serial_device *serial)
             usart_interrupt_disable(uart->periph, USART_INT_TBE);
             usart_interrupt_enable(uart->periph, USART_INT_TC);
         }
-        usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_TBE);
     }
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TC) != RESET)
     {
@@ -334,10 +325,9 @@ static void usart_isr (struct rt_serial_device *serial)
 #ifdef RT_SERIAL_USING_DMA
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_IDLE) != RESET)
     {
-        volatile uint8_t data = (uint8_t)usart_data_receive(uart->periph);
-
+        volatile uint8_t idle_clear_dummy = (uint8_t)usart_data_receive(uart->periph);
+        RT_UNUSED(idle_clear_dummy);
         dma_recv_isr(serial);
-
         usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_IDLE);
     }
 #endif
@@ -595,8 +585,8 @@ void UART7_IRQHandler (void)
 }
 
 #endif /* BSP_USING_UART7 */
-#if define SOC_SERIES_GD32E23x
-#if define BSP_UART0_RX_USING_DMA || define BSP_UART0_TX_USING_DMA
+#if defined SOC_SERIES_GD32E23x
+#if defined BSP_UART0_RX_USING_DMA || defined BSP_UART0_TX_USING_DMA
 void DMA_Channel1_2_IRQHandler(void)
 {
     /* enter interrupt */
@@ -906,6 +896,9 @@ static void _uart_dma_receive (struct gd32_uart *uart, rt_uint8_t *buffer, rt_ui
     dma_interrupt_enable(uart->dma.rx.channel, DMA_CHXCTL_HTFIE);
     dma_interrupt_enable(uart->dma.rx.channel, DMA_CHXCTL_FTFIE);
 
+    /* enable circular mode */
+    dma_circulation_enable(uart->dma.rx.channel);
+
     /* enable dma channel */
     dma_channel_enable(uart->dma.rx.channel);
 
@@ -953,7 +946,11 @@ static void _uart_dma_receive (struct gd32_uart *uart, rt_uint8_t *buffer, rt_ui
     usart_interrupt_enable(uart->periph, USART_INT_IDLE);
 
     /* enable dma receive */
+#if defined SOC_SERIES_GD32F5xx
+    usart_dma_receive_config(uart->periph, USART_DENR_ENABLE);
+#else
     usart_dma_receive_config(uart->periph, USART_RECEIVE_DMA_ENABLE);
+#endif
     #endif
 }
 
@@ -972,7 +969,11 @@ static void _uart_dma_transmit (struct gd32_uart *uart, rt_uint8_t *buffer, rt_u
     DMA_CHCNT(uart->dma.tx.periph, uart->dma.tx.channel) = size;
 
     /* enable dma transmit */
+#if defined SOC_SERIES_GD32F5xx
+    usart_dma_transmit_config(uart->periph, USART_DENT_ENABLE);
+#else
     usart_dma_transmit_config(uart->periph, USART_TRANSMIT_DMA_ENABLE);
+#endif
 
     /* enable dma channel */
     dma_channel_enable(uart->dma.tx.periph, uart->dma.tx.channel);
@@ -1057,7 +1058,7 @@ static void gd32_dma_config (struct rt_serial_device *serial, rt_ubase_t flag)
     if (flag == RT_DEVICE_FLAG_DMA_RX)
     {
         rt_uint8_t *ptr = NULL;
-        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
+        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ptr);
 
         /* start dma transfer */
         _uart_dma_receive(uart, ptr, serial->config.dma_ping_bufsz);

bsp/gd32/arm/libraries/gd32_drivers/drv_usart_v2.h

@@ -32,12 +32,12 @@ struct gd32_uart
     rcu_periph_enum tx_gpio_clk;
     rcu_periph_enum rx_gpio_clk;
     uint32_t tx_port;
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32F5xx
     uint16_t tx_af;
 #endif
     uint16_t tx_pin;
     uint32_t rx_port;
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32F5xx
     uint16_t rx_af;
 #endif
     uint16_t rx_pin;

bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/.clang-format-ignore

@@ -0,0 +1,10 @@
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+# NXP imxrt1060-nxp-evk library
+/board/MCUX_Config/
+/xip/

bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- board/board.c
-- board/MCUX_Config
-- xip

bsp/nxp/imx/imxrt/libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MIMXRT1060

bsp/nxp/lpc/lpc43xx/M0/applications/application.c

@@ -18,10 +18,6 @@
 #include <shell.h>
 #endif
 
-#ifdef RT_USING_VBUS
-#include <vbus.h>
-#endif
-
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
@@ -32,10 +28,6 @@ void rt_init_thread_entry(void *parameter)
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 #endif
-
-#ifdef RT_USING_VBUS
-    rt_vbus_do_init();
-#endif
 }
 
 /*the led thread*/
@@ -45,8 +37,6 @@ static struct rt_thread led_thread;
 static void led_thread_entry(void *parameter)
 {
     rt_device_t led_dev;
-    rt_device_t vbus_dev;
-    rt_err_t err;
 
     rt_led_hw_init();
 
@@ -57,32 +47,14 @@ static void led_thread_entry(void *parameter)
         return;
     }
 
-    vbus_dev = rt_device_find("vecho");
-    if (vbus_dev == RT_NULL)
-    {
-        rt_kprintf("can not find the vbus device\n");
-        return;
-    }
-
-    err = rt_device_open(vbus_dev, RT_DEVICE_OFLAG_RDWR);
-    if (err != RT_EOK)
-    {
-        rt_kprintf("open vbus failed: %d\n", err);
-        return;
-    }
-
     while (1)
     {
-        rt_uint8_t led_value;
-        int len;
-
-        len = rt_device_read(vbus_dev, 0, &led_value, sizeof(led_value));
-        if (len <= 0)
-        {
-            rt_kprintf("vbus read err: %d, %d\n", len, rt_get_errno());
-        }
-
+        rt_uint8_t led_value = 1;
         led_dev->write(led_dev, 1, &led_value, sizeof(led_value));
+        rt_thread_delay(500);
+        led_value = 0;
+        led_dev->write(led_dev, 1, &led_value, sizeof(led_value));
+        rt_thread_delay(500);
     }
 }
 

bsp/nxp/lpc/lpc43xx/M0/applications/board.h

@@ -50,6 +50,5 @@ extern int __bss_end;
 
 void rt_hw_board_init(void);
 int  rt_hw_board_heap_init(void);
-int rt_vbus_do_init(void);
 
 #endif

bsp/nxp/lpc/lpc43xx/M0/applications/vbus_conf.h

@@ -1,13 +0,0 @@
-#ifndef __VBUS_CONF_H__
-#define __VBUS_CONF_H__
-
-/* Number of blocks in VBus. The total size of VBus is
- * RT_VMM_RB_BLK_NR * 64byte * 2. */
-#define RT_VMM_RB_BLK_NR     20
-
-/* We don't use the IRQ number to trigger IRQ in this BSP. */
-#define RT_VBUS_GUEST_VIRQ    0
-#define RT_VBUS_HOST_VIRQ     0
-
-#endif /* end of include guard: __VBUS_CONF_H__ */
-

bsp/nxp/lpc/lpc43xx/M0/applications/vbus_drv.c

@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-01-07     Grissiom     add comment
- */
-
-#include <rtthread.h>
-
-#ifdef RT_USING_VBUS
-#include <rtdevice.h>
-#include <vbus.h>
-#include <board.h>
-
-struct rt_vbus_ring rt_vbus_rings[2] rt_section("vbus_ring");
-
-int rt_vbus_do_init(void)
-{
-    return rt_vbus_init(&rt_vbus_rings[1], &rt_vbus_rings[0]);
-}
-INIT_COMPONENT_EXPORT(rt_vbus_do_init);
-
-int rt_vbus_hw_init(void)
-{
-    NVIC_ClearPendingIRQ(M0_M4CORE_IRQn);
-    NVIC_EnableIRQ(M0_M4CORE_IRQn);
-    return 0;
-}
-
-void M4CORE_IRQHandler(void)
-{
-    LPC_CREG->M4TXEVENT = 0;
-    rt_vbus_isr(M0_M4CORE_IRQn, RT_NULL);
-}
-
-int rt_vbus_hw_eoi(int irqnr, void *param)
-{
-    /* Nothing to do here as we cleared the interrupt in IRQHandler. */
-    return 0;
-}
-
-struct rt_vbus_dev rt_vbus_chn_devx[] = {
-    {
-        .req =
-        {
-            .prio = 30,
-            .name = "vecho",
-            .is_server = 0,
-            .recv_wm.low = RT_VMM_RB_BLK_NR / 3,
-            .recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
-            .post_wm.low = RT_VMM_RB_BLK_NR / 3,
-            .post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
-        }
-    },
-    {
-        .req =
-        {
-            .name = RT_NULL,
-        }
-    },
-};
-
-#endif /* RT_USING_VBUS */
-

bsp/nxp/lpc/lpc43xx/M0/applications/vbus_hw.h

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-01-07     Grissiom     init commit
- */
-
-#ifndef __VBUS_HW_H__
-#define __VBUS_HW_H__
-
-#include <rtthread.h>
-#include <board.h>
-
-rt_inline void rt_vbus_tick(unsigned int target_cpu, unsigned int irqnr)
-{
-    __SEV();
-}
-
-/* Read memory barrier. */
-rt_inline void rt_vbus_smp_rmb(void)
-{
-    __DMB();
-}
-
-/* Write memory barrier. */
-rt_inline void rt_vbus_smp_wmb(void)
-{
-    __DSB();
-}
-
-/* General memory barrier. */
-rt_inline void rt_vbus_smp_mb(void)
-{
-    __DSB();
-}
-
-#endif /* __VBUS_HW_H__ */

bsp/nxp/lpc/lpc43xx/M0/rtconfig.h

@@ -220,9 +220,6 @@
 #define RT_LWIP_MSKADDR3 0
 // </section>
 
-#define RT_USING_VBUS
-#define _RT_VBUS_RING_SZ 64
-#define RT_VBUS_GUEST_VIRQ 0
 // </RDTConfigurator>
 
 

bsp/nxp/lpc/lpc43xx/M0/vbus_local_conf.h

@@ -1,8 +0,0 @@
-#ifndef __VBUS_LOCAL_CONF_H__
-#define __VBUS_LOCAL_CONF_H__
-
-#define RT_VBUS_USING_FLOW_CONTROL
-
-#define RT_VBUS_USING_TESTS
-
-#endif /* end of include guard: __VBUS_LOCAL_CONF_H__ */

bsp/nxp/lpc/lpc43xx/M4/applications/application.c

@@ -18,10 +18,6 @@
 #include <shell.h>
 #endif
 
-#ifdef RT_USING_VBUS
-#include <vbus.h>
-#endif
-
 static const unsigned char _M0_CODE[] rt_section("M0_CODE") = {
 // #include "M0_CODE.h"
 };
@@ -64,10 +60,6 @@ void rt_init_thread_entry(void *parameter)
 #endif
 #endif
 
-#ifdef RT_USING_VBUS
-    rt_vbus_do_init();
-#endif
-
     _boot_M0();
 }
 
@@ -79,8 +71,6 @@ static void led_thread_entry(void *parameter)
 {
     rt_uint8_t led_value;
     rt_device_t led_dev;
-    rt_device_t vbus_dev;
-    rt_err_t err;
 
     rt_led_hw_init();
 
@@ -91,34 +81,11 @@ static void led_thread_entry(void *parameter)
         return;
     }
 
-    vbus_dev = rt_device_find("vecho");
-    if (vbus_dev == RT_NULL)
-    {
-        rt_kprintf("can not find the vbus device\n");
-        return;
-    }
-
-    err = rt_device_open(vbus_dev, RT_DEVICE_OFLAG_RDWR);
-    if (err != RT_EOK)
-    {
-        rt_kprintf("open vbus failed: %d\n", err);
-        return;
-    }
-
     led_value = 0;
     while (1)
     {
-        int len;
-
         led_dev->write(led_dev, 0, &led_value, sizeof(led_value));
-
         led_value = !led_value;
-        len = rt_device_write(vbus_dev, 0, &led_value, sizeof(led_value));
-        if (len <= 0)
-        {
-            rt_kprintf("vbus write err: %d, %d\n", len, rt_get_errno());
-        }
-
         rt_thread_delay(1000);
     }
 }

bsp/nxp/lpc/lpc43xx/M4/applications/board.h

@@ -50,6 +50,5 @@ extern int __bss_end;
 
 void rt_hw_board_init(void);
 int  rt_hw_board_heap_init(void);
-int rt_vbus_do_init(void);
 
 #endif

bsp/nxp/lpc/lpc43xx/M4/applications/vbus_conf.h

@@ -1,13 +0,0 @@
-#ifndef __VBUS_CONF_H__
-#define __VBUS_CONF_H__
-
-/* Number of blocks in VBus. The total size of VBus is
- * RT_VMM_RB_BLK_NR * 64byte * 2. */
-#define RT_VMM_RB_BLK_NR     20
-
-/* We don't use the IRQ number to trigger IRQ in this BSP. */
-#define RT_VBUS_GUEST_VIRQ    0
-#define RT_VBUS_HOST_VIRQ     0
-
-#endif /* end of include guard: __VBUS_CONF_H__ */
-

bsp/nxp/lpc/lpc43xx/M4/applications/vbus_drv.c

@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-01-07     Grissiom     add comment
- */
-
-#include <rtthread.h>
-
-#ifdef RT_USING_VBUS
-#include <rtdevice.h>
-#include <vbus.h>
-#include <board.h>
-
-struct rt_vbus_ring rt_vbus_rings[2] rt_section("vbus_ring");
-
-int rt_vbus_do_init(void)
-{
-    return rt_vbus_init(&rt_vbus_rings[0], &rt_vbus_rings[1]);
-}
-INIT_COMPONENT_EXPORT(rt_vbus_do_init);
-
-int rt_vbus_hw_init(void)
-{
-    NVIC_ClearPendingIRQ(M0CORE_IRQn);
-    NVIC_EnableIRQ(M0CORE_IRQn);
-    return 0;
-}
-
-void M0CORE_IRQHandler(void)
-{
-    LPC_CREG->M0TXEVENT = 0;
-    rt_vbus_isr(M0CORE_IRQn, RT_NULL);
-}
-
-int rt_vbus_hw_eoi(int irqnr, void *param)
-{
-    /* Nothing to do here as we cleared the interrupt in IRQHandler. */
-    return 0;
-}
-
-struct rt_vbus_dev rt_vbus_chn_devx[] = {
-    {
-        .req =
-        {
-            .prio = 30,
-            .name = "vecho",
-            .is_server = 1,
-            .recv_wm.low = RT_VMM_RB_BLK_NR / 3,
-            .recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
-            .post_wm.low = RT_VMM_RB_BLK_NR / 3,
-            .post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
-        }
-    },
-    {
-        .req =
-        {
-            .name = RT_NULL,
-        }
-    },
-};
-
-#endif /* RT_USING_VBUS */
-

bsp/nxp/lpc/lpc43xx/M4/applications/vbus_hw.h

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-01-07     Grissiom     init commit
- */
-
-#ifndef __VBUS_HW_H__
-#define __VBUS_HW_H__
-
-#include <rtthread.h>
-#include <board.h>
-
-rt_inline void rt_vbus_tick(unsigned int target_cpu, unsigned int irqnr)
-{
-    __SEV();
-}
-
-/* Read memory barrier. */
-rt_inline void rt_vbus_smp_rmb(void)
-{
-    __DMB();
-}
-
-/* Write memory barrier. */
-rt_inline void rt_vbus_smp_wmb(void)
-{
-    __DSB();
-}
-
-/* General memory barrier. */
-rt_inline void rt_vbus_smp_mb(void)
-{
-    __DSB();
-}
-
-#endif /* __VBUS_HW_H__ */

bsp/nxp/lpc/lpc43xx/M4/rtconfig.h

@@ -222,10 +222,6 @@
 #define RT_LWIP_MSKADDR3 0
 // </section>
 
-#define RT_USING_VBUS
-
-#define RT_VBUS_GUEST_VIRQ 0
-#define _RT_VBUS_RING_SZ 64
 // </RDTConfigurator>
 #define RT_CPUS_NR 1
 #define RT_BACKTRACE_LEVEL_MAX_NR 32

bsp/nxp/lpc/lpc43xx/M4/vbus_local_conf.h

@@ -1,8 +0,0 @@
-#ifndef __VBUS_LOCAL_CONF_H__
-#define __VBUS_LOCAL_CONF_H__
-
-#define RT_VBUS_USING_FLOW_CONTROL
-
-#define RT_VBUS_USING_TESTS
-
-#endif /* end of include guard: __VBUS_LOCAL_CONF_H__ */

bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml

@@ -1,8 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- LPC55S6X
-- LPC55S06
-- LPC5502
-- LPC55S28
-- LPC55S36

bsp/nxp/mcx/mcxa/Libraries/.clang-format-ignore

@@ -0,0 +1,9 @@
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+# NXP MCXA library
+/MCXA153/

bsp/nxp/mcx/mcxa/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXA153

bsp/nxp/mcx/mcxc/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXC444

bsp/nxp/mcx/mcxn/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXN947

bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h

@@ -145,6 +145,17 @@ extern "C" {
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
 
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "hlpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#endif /* BSP_USING_LPUART1 */
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c

@@ -500,7 +500,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  *
  * @return `RT_EOK` on success, or an error code on failure.
  */
-static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
 {
     CAN_HandleTypeDef *hcan;
     hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
@@ -649,7 +649,7 @@ static rt_ssize_t _can_sendmsg_nonblocking(struct rt_can_device *can, const void
     return RT_EOK;
 }
 
-static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
 {
     HAL_StatusTypeDef status;
     CAN_HandleTypeDef *hcan;

bsp/stm32/stm32h723-lxb-disco/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/stm32/stm32h723-lxb-disco/Kconfig

@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+config SOC_STM32H723ZG
+    bool
+    select SOC_SERIES_STM32H7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "board/Kconfig"
+endif

bsp/stm32/stm32h723-lxb-disco/README.md

@@ -0,0 +1,127 @@
+# LXB723ZG-P1 Development Board BSP Instructions
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides the BSP (Board Support Package) instructions for the LXB723ZG-P1 development board developed by Pcb-yun based on STM32H723.
+
+The main content includes:
+
+- Development board resources introduction
+- BSP quick start guide
+- Advanced usage methods
+
+By reading the quick start section, developers can quickly get started with this BSP and run RT-Thread on the development board. In the advanced usage guide section, more advanced features will be introduced to help developers use RT-Thread to drive more on-board resources.
+
+## Development Board Introduction
+
+LXB723ZG-P1 is a development board launched by LXB (鹿小班) based on the ARM Cortex-M7 core, with a maximum frequency of 550MHz.
+The development board integrates resources including: W25Q64 8MB OSPI Flash (available for user's own use), SPI screen and 8-bit DCMI camera FPC socket (corresponding accessories need to be purchased separately), self-ejecting TF card socket, Type-C interface, 108 extended IO interfaces, reset button and BOOT button (no custom buttons).
+
+The appearance of the development board is shown in the figure below:
+
+![board](figures/board.png)
+
+The commonly used **on-board resources** of this development board are as follows:
+
+- MCU: STM32H723ZGT6, frequency 550MHz, 1MB FLASH, 564K RAM
+- External FLASH: W25Q64, 8MB
+- Common peripherals
+  - LED: 1, DS0 (blue, PG7)
+- Common interfaces: Type-C interface, TF card interface, 8-bit DCMI camera interface (FPC), SPI screen interface (FPC)
+- Debugging interface: Standard SWD interface
+
+For more detailed information about the development board, please refer to [LXB723ZG-P1 Core Board](https://item.taobao.com/item.htm?abbucket=17&id=831139393305&mi_id=0000Hr_7YuvNzXkf9ukTHb3zeHF5wgFLDumgDHyYZNYGbIs&ns=1&priceTId=2150419217612182188817937e1045&skuId=5739335367823&spm=a21n57.sem.item.1.47ef3a43Uq2LAX&utparam=%7B%22aplus_abtest%22%3A%229add53b62022488d347cf05287760183%22%7D&xxc=taobaoSearch).
+
+## Peripheral Support
+
+The current support status of peripherals for this BSP is as follows:
+
+| **On-board Peripherals** | **Support Status** | **Notes**                            |
+| :---------------------- | :---------------- | :----------------------------------- |
+| OSPI Flash              | Not supported     | OSPI1                                |
+| TF card                 | Not supported     | SDMMC1                               |
+| SPI screen              | Not supported     | SPI6                                 |
+| DCMI camera             | Not supported     |                                      |
+
+| **On-chip Peripherals**  | **Support Status** | **Notes**                            |
+| :---------------------- | :---------------- | :----------------------------------- |
+| GPIO                    | Supported         |                                      |
+| UART                    | Supported         |                                      |
+
+## Usage Instructions
+
+Usage instructions are divided into the following two chapters:
+
+- Quick Start
+
+    This chapter is a usage guide prepared for beginners who are new to RT-Thread. Following simple steps, you can run the RT-Thread operating system on this development board and see the experimental results.
+
+- Advanced Usage
+
+    This chapter is prepared for developers who need to use more development board resources on the RT-Thread operating system. By configuring the BSP using the ENV tool, you can enable more on-board resources and implement more advanced functions.
+
+### Quick Start
+
+This BSP provides an MDK5 project for developers and supports the GCC development environment. The following takes the MDK5 development environment as an example to introduce how to run the system.
+
+**Please note!!!**
+
+Before performing the compilation work, please open the ENV tool in the BSP directory and execute the following command (this command is used to pull the necessary HAL library and CMSIS library, otherwise compilation cannot pass):
+
+```bash
+pkgs --update
+```
+
+#### Hardware Connection
+
+The development board has separate debugging interfaces (SWD, LPUART1). Connect to the debugger as needed.
+
+#### Compilation and Download
+
+Double-click the project.uvprojx file to open the MDK5 project, compile and download the program to the development board.
+
+> The project is configured to use CMSIS_DAP emulator to download the program by default. On the basis of connecting the development board through CMSIS_DAP, click the download button to download the program to the development board.
+
+#### Running Results
+
+After successfully downloading the program, the system will run automatically, and the LED will blink.
+
+Connect the corresponding serial port of the development board to the PC, open the corresponding serial port (115200-8-1-N) in the terminal tool, and after resetting the device, you can see the output information of RT-Thread:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Oct 23 2025 18:41:53
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+
+### Advanced Usage
+
+This BSP only enables the functions of GPIO and UART1 by default. If you need to use more advanced functions, you need to use the ENV tool to configure the BSP. The steps are as follows:
+
+1. Open the env tool under the bsp directory.
+
+2. Enter the `menuconfig` command to configure the project, save and exit after configuration.
+
+3. Enter the `pkgs --update` command to update the software package.
+
+4. Enter the `scons --target=mdk5` command to regenerate the project.
+
+For more detailed introduction in this chapter, please refer to [STM32 Series BSP Peripheral Driver Usage Tutorial](../docs/STM32系列BSP外设驱动使用教程.md).
+
+## Notes
+
+- Debugging serial port is low-power UART1 mapping description
+
+    PA9     ------> LPUART1_TX
+
+    PA10    ------> LPUART1_RX
+
+## Contact Information
+
+Maintainer:
+
+- [Pcb-yun](https://github.com/Pcb-yun)

bsp/stm32/stm32h723-lxb-disco/README_zh.md

@@ -0,0 +1,126 @@
+# 鹿小班STM32H723 开发板 BSP 说明
+
+## 简介
+
+本文档为 Pcb-yun为 鹿小班STM32H723（LXB723ZG-P1） 开发板提供的的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+LXB723ZG-P1 是 鹿小班 推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为550MHz。
+开发板集成资源包括：W25Q64 8MB OSPI Flash（可供用户自行使用）、SPI屏幕与8位DCMI摄像头FPC底座（需自行购买相应配件）、自弹式TF卡座、Type-C接口、108个引出IO接口、复位按键和BOOT按键（无自定义按键）。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32H723ZGT6，主频 550MHz，1MB FLASH ，564K RAM
+- 外部 FLASH：W25Q64，8MB
+- 常用外设
+  - LED：1个，DS0（蓝色，PG7）
+- 常用接口：Type-C接口、TF卡接口、8位DCMI摄像头接口（FPC）、SPI屏幕接口（FPC）
+- 调试接口：标准SWD接口
+
+开发板更多详细信息请参考 [鹿小班STM32H723ZGT6核心板](https://item.taobao.com/item.htm?abbucket=17&id=831139393305&mi_id=0000Hr_7YuvNzXkf9ukTHb3zeHF5wgFLDumgDHyYZNYGbIs&ns=1&priceTId=2150419217612182188817937e1045&skuId=5739335367823&spm=a21n57.sem.item.1.47ef3a43Uq2LAX&utparam=%7B%22aplus_abtest%22%3A%229add53b62022488d347cf05287760183%22%7D&xxc=taobaoSearch)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**        | **支持情况** | **备注**                               |
+| :----------------- | :----------: | :------------------------------------- |
+| OSPI Flash         |   暂不支持    | OSPI1                                  |
+| TF卡               |   暂不支持    | SDMMC1                                 |
+| SPI屏幕            |   暂不支持    | SPI6                                   |
+| DCMI摄像头         |   暂不支持    |                                        |
+
+| **片上外设**       | **支持情况**  | **备注**                               |
+| :----------------- | :----------: | :------------------------------------- |
+| GPIO               |     支持     |                                        |
+| UART               |     支持     |                                        |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+**请注意！！！**
+
+在执行编译工作前请先在BSP目录下打开ENV工具，执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
+
+```bash
+pkgs --update
+```
+
+#### 硬件连接
+
+开发板将调试接口单独引出（SWD、LPUART1），根据需要连接到调试器即可。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 CMSIS_DAP 仿真器下载程序，在通过 CMSIS_DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Oct 23 2025 18:41:53
+ 2006 - 2024 Copyright by RT-Thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 调试串口为 低功耗串口1 映射说明
+
+    PA9     ------> LPUART1_TX
+
+    PA10    ------> LPUART1_RX
+
+## 联系人信息
+
+维护人:
+
+-  [Pcb-yun](https://github.com/Pcb-yun)

bsp/stm32/stm32h723-lxb-disco/SConscript

@@ -0,0 +1,20 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('env')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+# STM32H743xx || STM32H750xx || STM32F753xx || STM32H723xx
+# You can select chips from the list above
+env.Append(CPPDEFINES = ['STM32H723xx'])
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32h723-lxb-disco/SConstruct

@@ -0,0 +1,74 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+
+    check_paths = [
+        os.path.join("packages", "CMSIS-Core-latest"),
+        os.path.join("packages", "stm32h7_cmsis_driver-latest"),
+        os.path.join("packages", "stm32h7_hal_driver-latest")
+    ]
+
+    need_update = not all(os.path.exists(p) for p in check_paths)
+
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('env')
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/stm32/stm32h723-lxb-disco/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/stm32/stm32h723-lxb-disco/applications/main.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-05     whj4674672   first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+/* defined the LED0 pin: PG7 */
+#define LED0_PIN    GET_PIN(G, 7)
+
+int main(void)
+{
+    int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}

bsp/stm32/stm32h723-lxb-disco/board/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- CubeMX_Config

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,219 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+LPUART1.BaudRate=115200
+LPUART1.IPParameters=BaudRate
+MMTAppReg1.MEMORYMAP.AppRegionName=DTCMRAM
+MMTAppReg1.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg1.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg1.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name
+MMTAppReg1.MEMORYMAP.Name=DTCMRAM
+MMTAppReg1.MEMORYMAP.Size=131072
+MMTAppReg1.MEMORYMAP.StartAddress=0x20000000
+MMTAppReg2.MEMORYMAP.AppRegionName=RAM
+MMTAppReg2.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg2.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg2.MEMORYMAP.DefaultDataRegion=true
+MMTAppReg2.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,DefaultDataRegion
+MMTAppReg2.MEMORYMAP.Name=RAM
+MMTAppReg2.MEMORYMAP.Size=327680
+MMTAppReg2.MEMORYMAP.StartAddress=0x24000000
+MMTAppReg3.MEMORYMAP.AppRegionName=RAM_D2
+MMTAppReg3.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg3.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg3.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name
+MMTAppReg3.MEMORYMAP.Name=RAM_D2
+MMTAppReg3.MEMORYMAP.Size=32768
+MMTAppReg3.MEMORYMAP.StartAddress=0x30000000
+MMTAppReg4.MEMORYMAP.AppRegionName=RAM_D3
+MMTAppReg4.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg4.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg4.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name
+MMTAppReg4.MEMORYMAP.Name=RAM_D3
+MMTAppReg4.MEMORYMAP.Size=16384
+MMTAppReg4.MEMORYMAP.StartAddress=0x38000000
+MMTAppReg5.MEMORYMAP.AppRegionName=ITCMRAM
+MMTAppReg5.MEMORYMAP.Cacheability=WTRA
+MMTAppReg5.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg5.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg5.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,ContextName,Name,Cacheability
+MMTAppReg5.MEMORYMAP.Name=ITCMRAM
+MMTAppReg5.MEMORYMAP.Size=65536
+MMTAppReg5.MEMORYMAP.StartAddress=0x00000000
+MMTAppReg6.MEMORYMAP.AP=RO_priv_only
+MMTAppReg6.MEMORYMAP.AppRegionName=FLASH
+MMTAppReg6.MEMORYMAP.Cacheability=WTRA
+MMTAppReg6.MEMORYMAP.ContextName=Cortex-M7NS
+MMTAppReg6.MEMORYMAP.CoreName=Arm Cortex-M7
+MMTAppReg6.MEMORYMAP.DefaultCodeRegion=true
+MMTAppReg6.MEMORYMAP.IPParameters=StartAddress,Size,CoreName,MemType,ContextName,Name,AP,Cacheability,DefaultCodeRegion,ISRRegion,RootBootRegion
+MMTAppReg6.MEMORYMAP.ISRRegion=true
+MMTAppReg6.MEMORYMAP.MemType=ROM
+MMTAppReg6.MEMORYMAP.Name=FLASH
+MMTAppReg6.MEMORYMAP.RootBootRegion=true
+MMTAppReg6.MEMORYMAP.Size=1048576
+MMTAppReg6.MEMORYMAP.StartAddress=0x08000000
+MMTAppRegionsCount=6
+MMTConfigApplied=false
+Mcu.CPN=STM32H723ZGT6
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=DEBUG
+Mcu.IP2=LPUART1
+Mcu.IP3=MEMORYMAP
+Mcu.IP4=NVIC
+Mcu.IP5=RCC
+Mcu.IP6=SYS
+Mcu.IPNb=7
+Mcu.Name=STM32H723ZGTx
+Mcu.Package=LQFP144
+Mcu.Pin0=PH0-OSC_IN
+Mcu.Pin1=PH1-OSC_OUT
+Mcu.Pin2=PG7
+Mcu.Pin3=PA9
+Mcu.Pin4=PA10
+Mcu.Pin5=PA13(JTMS/SWDIO)
+Mcu.Pin6=PA14(JTCK/SWCLK)
+Mcu.Pin7=VP_SYS_VS_Systick
+Mcu.Pin8=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.PinsNb=9
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H723ZGTx
+MxCube.Version=6.15.0
+MxDb.Version=DB.6.0.150
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA10.Mode=Asynchronous
+PA10.Signal=LPUART1_RX
+PA13(JTMS/SWDIO).Mode=Serial_Wire
+PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14(JTCK/SWCLK).Mode=Serial_Wire
+PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
+PA9.Mode=Asynchronous
+PA9.Signal=LPUART1_TX
+PG7.GPIOParameters=PinState,GPIO_Label
+PG7.GPIO_Label=LED
+PG7.Locked=true
+PG7.PinState=GPIO_PIN_SET
+PG7.Signal=GPIO_Output
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerLinker=GCC
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H723ZGTx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.12.1
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5.32
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=129000000
+RCC.AHB12Freq_Value=64000000
+RCC.AHB4Freq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB3Freq_Value=32000000
+RCC.APB4Freq_Value=64000000
+RCC.AXIClockFreq_Value=64000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=64000000
+RCC.CpuClockFreq_Value=64000000
+RCC.D1CPREFreq_Value=64000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.DFSDMACLkFreq_Value=129000000
+RCC.DFSDMFreq_Value=64000000
+RCC.DIVP1Freq_Value=129000000
+RCC.DIVP2Freq_Value=129000000
+RCC.DIVP3Freq_Value=129000000
+RCC.DIVQ1Freq_Value=129000000
+RCC.DIVQ2Freq_Value=129000000
+RCC.DIVQ3Freq_Value=129000000
+RCC.DIVR1Freq_Value=129000000
+RCC.DIVR2Freq_Value=129000000
+RCC.DIVR3Freq_Value=129000000
+RCC.FDCANFreq_Value=129000000
+RCC.FMCFreq_Value=64000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.I2C123Freq_Value=64000000
+RCC.I2C4Freq_Value=64000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPTIM345Freq_Value=64000000
+RCC.LPUART1Freq_Value=32000000
+RCC.LTDCFreq_Value=129000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=64000000
+RCC.QSPIFreq_Value=64000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=129000000
+RCC.SAI4AFreq_Value=129000000
+RCC.SAI4BFreq_Value=129000000
+RCC.SDMMCFreq_Value=129000000
+RCC.SPDIFRXFreq_Value=129000000
+RCC.SPI123Freq_Value=129000000
+RCC.SPI45Freq_Value=64000000
+RCC.SPI6Freq_Value=64000000
+RCC.SWPMI1Freq_Value=64000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.Tim1OutputFreq_Value=64000000
+RCC.Tim2OutputFreq_Value=64000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=64000000
+RCC.USART234578Freq_Value=64000000
+RCC.USBFreq_Value=129000000
+RCC.VCO1OutputFreq_Value=258000000
+RCC.VCO2OutputFreq_Value=258000000
+RCC.VCO3OutputFreq_Value=258000000
+RCC.VCOInput1Freq_Value=2000000
+RCC.VCOInput2Freq_Value=2000000
+RCC.VCOInput3Freq_Value=2000000
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Inc/main.h

@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define LED_Pin GPIO_PIN_7
+#define LED_GPIO_Port GPIOG
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Inc/stm32h7xx_hal_conf.h

@@ -0,0 +1,514 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CONF_H
+#define STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_FMAC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CORDIC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RAMECC_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    (100UL)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    (64000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    (5000UL)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  (32000UL)              /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000UL /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    (3300UL) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            (15UL) /*!< tick interrupt priority */
+#define  USE_RTOS                     0
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+#define  USE_SPI_CRC	              0U               /*!< use CRC in SPI */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CORDIC_REGISTER_CALLBACKS  0U /* CORDIC register callback disabled  */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_FMAC_REGISTER_CALLBACKS    0U /* FMAC register callback disabled  */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4U  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4U  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    (0x02UL)
+#define ETH_MAC_ADDR1    (0x00UL)
+#define ETH_MAC_ADDR2    (0x00UL)
+#define ETH_MAC_ADDR3    (0x00UL)
+#define ETH_MAC_ADDR4    (0x00UL)
+#define ETH_MAC_ADDR5    (0x00UL)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_RAMECC_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t *file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_CONF_H */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Inc/stm32h7xx_it.h

@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_IT_H
+#define __STM32H7xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_IT_H */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Src/main.c

@@ -0,0 +1,271 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+UART_HandleTypeDef hlpuart1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_LPUART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_LPUART1_UART_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = 64;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief LPUART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LPUART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN LPUART1_Init 0 */
+
+  /* USER CODE END LPUART1_Init 0 */
+
+  /* USER CODE BEGIN LPUART1_Init 1 */
+
+  /* USER CODE END LPUART1_Init 1 */
+  hlpuart1.Instance = LPUART1;
+  hlpuart1.Init.BaudRate = 115200;
+  hlpuart1.Init.WordLength = UART_WORDLENGTH_8B;
+  hlpuart1.Init.StopBits = UART_STOPBITS_1;
+  hlpuart1.Init.Parity = UART_PARITY_NONE;
+  hlpuart1.Init.Mode = UART_MODE_TX_RX;
+  hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  hlpuart1.FifoMode = UART_FIFOMODE_DISABLE;
+  if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LPUART1_Init 2 */
+
+  /* USER CODE END LPUART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  /* USER CODE BEGIN MX_GPIO_Init_1 */
+
+  /* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin : LED_Pin */
+  GPIO_InitStruct.Pin = LED_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN MX_GPIO_Init_2 */
+
+  /* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+#ifdef USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Src/stm32h7xx_hal_msp.c

@@ -0,0 +1,158 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32h7xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+#include <drv_common.h>
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+  * @brief UART MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+  if(huart->Instance==LPUART1)
+  {
+    /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+    /* USER CODE END LPUART1_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_LPUART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**LPUART1 GPIO Configuration
+    PA9     ------> LPUART1_TX
+    PA10     ------> LPUART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF3_LPUART;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+    /* USER CODE END LPUART1_MspInit 1 */
+
+  }
+
+}
+
+/**
+  * @brief UART MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==LPUART1)
+  {
+    /* USER CODE BEGIN LPUART1_MspDeInit 0 */
+
+    /* USER CODE END LPUART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LPUART1_CLK_DISABLE();
+
+    /**LPUART1 GPIO Configuration
+    PA9     ------> LPUART1_TX
+    PA10     ------> LPUART1_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+    /* USER CODE BEGIN LPUART1_MspDeInit 1 */
+
+    /* USER CODE END LPUART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Src/stm32h7xx_it.c

@@ -0,0 +1,203 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+   while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32h7xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

bsp/stm32/stm32h723-lxb-disco/board/CubeMX_Config/Src/system_stm32h7xx.c

@@ -0,0 +1,556 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - ExitRun0Mode(): Specifies the Power Supply source. This function is
+  *                        called at startup just after reset and before the call
+  *                        of SystemInit(). This call is made inside
+  *                        the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   D2_AXISRAM_BASE   /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BANK2_BASE  /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   D1_AXISRAM_BASE   /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BANK1_BASE  /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+
+   /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+  }
+
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+
+   /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+  }
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x02020200;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x01FF0000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif /* STM32H7_DEV_ID */
+
+#if defined(DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#else
+  if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
+  {
+    /* Enable the FMC interface clock */
+    SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+    /*
+     * Disable the FMC bank1 (enabled after reset).
+     * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+     * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+     */
+    FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+    /* Disable the FMC interface clock */
+    CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+  }
+
+  /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
+#endif /* USER_VECT_TAB_ADDRESS */
+
+#endif /*DUAL_CORE && CORE_CM4*/
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+          pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+/**
+  * @brief  Exit Run* mode and Configure the system Power Supply
+  *
+  * @note   This function exits the Run* mode and configures the system power supply
+  *         according to the definition to be used at compilation preprocessing level.
+  *         The application shall set one of the following configuration option:
+  *           - PWR_LDO_SUPPLY
+  *           - PWR_DIRECT_SMPS_SUPPLY
+  *           - PWR_EXTERNAL_SOURCE_SUPPLY
+  *           - PWR_SMPS_1V8_SUPPLIES_LDO
+  *           - PWR_SMPS_2V5_SUPPLIES_LDO
+  *           - PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
+  *           - PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
+  *           - PWR_SMPS_1V8_SUPPLIES_EXT
+  *           - PWR_SMPS_2V5_SUPPLIES_EXT
+  *
+  * @note   The function modifies the PWR->CR3 register to enable or disable specific
+  *         power supply modes and waits until the voltage level flag is set, indicating
+  *         that the power supply configuration is stable.
+  *
+  * @param  None
+  * @retval None
+  */
+void ExitRun0Mode(void)
+{
+#if defined(USE_PWR_LDO_SUPPLY)
+  #if defined(SMPS)
+    /* Exit Run* mode by disabling SMPS and enabling LDO */
+    PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
+  #else
+    /* Enable LDO mode */
+    PWR->CR3 |= PWR_CR3_LDOEN;
+  #endif /* SMPS */
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
+  #if defined(SMPS)
+    /* Exit Run* mode */
+    PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
+  #else
+    PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
+  #endif /* SMPS */
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 &= ~(PWR_CR3_LDOEN);
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
+  /* Exit Run* mode */
+  PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
+  /* Wait till voltage level flag is set */
+  while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
+  {}
+#else
+  /* No system power supply configuration is selected at exit Run* mode */
+#endif /* USE_PWR_LDO_SUPPLY */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

bsp/stm32/stm32h723-lxb-disco/board/Kconfig

@@ -0,0 +1,36 @@
+menu "Hardware Drivers Config"
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+
+            if BSP_USING_UART
+                config BSP_STM32_UART_V1_TX_TIMEOUT
+                    int "UART TX timeout"
+                    default 1000
+                    depends on RT_USING_SERIAL_V1
+
+                config BSP_USING_LPUART1
+                    bool "Enable LPUART1"
+                    default y
+
+            endif
+        source "$(BSP_DIR)/../libraries/HAL_Drivers/drivers/Kconfig"
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+    endmenu
+
+endmenu

bsp/stm32/stm32h723-lxb-disco/board/SConscript

@@ -0,0 +1,21 @@
+import os
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Glob('board.c')
+src += Glob('CubeMX_Config/Src/stm32h7xx_hal_msp.c')
+
+path = [cwd]
+path += [cwd + '/CubeMX_Config/Inc']
+
+CPPDEFINES = ['STM32H723xx']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/stm32/stm32h723-lxb-disco/board/board.c

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#include "board.h"
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
+  RCC_OscInitStruct.HSICalibrationValue = 64;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}

bsp/stm32/stm32h723-lxb-disco/board/board.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2006-2024 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-5      SummerGift   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32h7xx.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (1024 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+#define STM32_SRAM_SIZE           (320)
+#define STM32_SRAM_END            (0x24000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__ARMCC_VERSION)
+extern int Image$$AXI_SRAM$$ZI$$Limit;
+#define HEAP_BEGIN      (&Image$$AXI_SRAM$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      (&__bss_end)
+#endif
+
+#define HEAP_END        STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32h723-lxb-disco/board/linker_scripts/link.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF; /* 1MB FLASH */
+define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF; /* 320KB AXI SRAM */
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+/* Commented memory regions for reference */
+/* define symbol __ICFEDIT_region_ITCM_start__ = 0x00000000; */
+/* define symbol __ICFEDIT_region_ITCM_end__   = 0x0000FFFF; /\* 64KB ITCM *\/ */
+/* define symbol __ICFEDIT_region_DTCM_start__ = 0x20000000; */
+/* define symbol __ICFEDIT_region_DTCM_end__   = 0x2001FFFF; /\* 128KB DTCM *\/ */
+/* define symbol __ICFEDIT_region_SRAM2_start__ = 0x30000000; */
+/* define symbol __ICFEDIT_region_SRAM2_end__   = 0x30007FFF; /\* 32KB AHB SRAM D2 *\/ */
+/* define symbol __ICFEDIT_region_SRAM3_start__ = 0x38000000; */
+/* define symbol __ICFEDIT_region_SRAM3_end__   = 0x38003FFF; /\* 16KB AHB SRAM D3 *\/ */
+/* define symbol __ICFEDIT_region_BSRAM_start__ = 0x38800000; */
+/* define symbol __ICFEDIT_region_BSRAM_end__   = 0x38800FFF; /\* 4KB BACKUP SRAM D3 *\/ */
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/stm32/stm32h723-lxb-disco/board/linker_scripts/link.lds

@@ -0,0 +1,162 @@
+/*
+ * linker script for STM32F4xx with GNU ld
+ * bernard.xiong 2009-10-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024k /* 1024KB flash */
+    RAM (rw) : ORIGIN = 0x24000000, LENGTH =  320k /* 320K AXI SRAM */
+    /* ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 64k  /\* 64KB ITCM SRAM *\/ */
+    /* DTCM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /\* 128KB DTCM SRAM *\/ */
+    /* SRAM2 (rw): ORIGIN = 0x30000000, LENGTH = 32k  /\* 32KB AHB SRAM D2 *\/ */
+    /* SRAM3 (rw): ORIGIN = 0x38000000, LENGTH = 16k  /\* 16KB AHB SRAM D3 *\/ */
+    /* BSRAM (rw): ORIGIN = 0x38800000, LENGTH = 4k   /\* 4KB BACKUP SRAM D3 *\/ */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x400;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack :
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/stm32/stm32h723-lxb-disco/board/linker_scripts/link.sct

@@ -0,0 +1,35 @@
+; *********************************************************************************
+; *** Scatter-Loading Description File generated by STM32CubeMX/LinkerGenerator ***
+; *********************************************************************************;
+
+ON_CHIP 0x08000000 0x00100000  {  ; load_region size_region
+  FLASH 0x08000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  AXI_SRAM 0x24000000 0x00050000  {  ; load address = execution address
+   .ANY (+RW +ZI)
+  ;  *(.sram1)
+  }
+;***region***;
+  ; ITCM 0x00000000 0x00010000  {  ; load address = execution address
+  ;  *(.itcm)
+  ; }
+  ; DTCM 0x20000000 0x00020000  {  ; load address = execution address
+  ;  *(.dtcm)
+  ; }
+  ; AHB_SRAM_D2 0x30000000 0x00008000  {  ; load address = execution address
+  ;  *(.sram2)
+  ; }
+  ; AHB_SRAM_D3 0x38000000 0x00004000  {  ; load address = execution address
+  ;  *(.sram3)
+  ; }
+  ; BACKUP_SRAM_D3 0x38800000 0x00001000  {  ; load address = execution address
+  ;  *(.bsram)
+  ; }
+;***endregion***;
+}
+
+/*-Start of  regions- Auto-generated By STM32CubeMX-*/

bsp/stm32/stm32h723-lxb-disco/rtconfig.h

@@ -0,0 +1,429 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+#define SOC_STM32H723ZG
+
+/* RT-Thread Kernel */
+
+/* klibc options */
+
+/* rt_vsnprintf options */
+
+/* end of rt_vsnprintf options */
+
+/* rt_vsscanf options */
+
+/* end of rt_vsscanf options */
+
+/* rt_memset options */
+
+/* end of rt_memset options */
+
+/* rt_memcpy options */
+
+/* end of rt_memcpy options */
+
+/* rt_memmove options */
+
+/* end of rt_memmove options */
+
+/* rt_memcmp options */
+
+/* end of rt_memcmp options */
+
+/* rt_strstr options */
+
+/* end of rt_strstr options */
+
+/* rt_strcasecmp options */
+
+/* end of rt_strcasecmp options */
+
+/* rt_strncpy options */
+
+/* end of rt_strncpy options */
+
+/* rt_strcpy options */
+
+/* end of rt_strcpy options */
+
+/* rt_strncmp options */
+
+/* end of rt_strncmp options */
+
+/* rt_strcmp options */
+
+/* end of rt_strcmp options */
+
+/* rt_strlen options */
+
+/* end of rt_strlen options */
+
+/* rt_strnlen options */
+
+/* end of rt_strnlen options */
+/* end of klibc options */
+#define RT_NAME_MAX 9
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice options */
+
+/* end of kservice options */
+#define RT_USING_DEBUG
+#define RT_DEBUGING_ASSERT
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "hlpuart1"
+#define RT_VER_NUM 0x50201
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+/* end of RT-Thread Kernel */
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M7
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+/* end of DFS: device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+/* end of Device Drivers */
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+/* end of Timezone and Daylight Saving Time */
+/* end of ISO-ANSI C layer */
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+/* end of Interprocess Communication (IPC) */
+/* end of POSIX (Portable Operating System Interface) layer */
+/* end of C/C++ and POSIX layer */
+
+/* Network */
+
+/* end of Network */
+
+/* Memory protection */
+
+/* end of Memory protection */
+
+/* Utilities */
+
+/* end of Utilities */
+
+/* Using USB legacy version */
+
+/* end of Using USB legacy version */
+/* end of RT-Thread Components */
+
+/* RT-Thread Utestcases */
+
+/* end of RT-Thread Utestcases */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* end of Marvell WiFi */
+
+/* Wiced WiFi */
+
+/* end of Wiced WiFi */
+
+/* CYW43012 WiFi */
+
+/* end of CYW43012 WiFi */
+
+/* BL808 WiFi */
+
+/* end of BL808 WiFi */
+
+/* CYW43439 WiFi */
+
+/* end of CYW43439 WiFi */
+/* end of Wi-Fi */
+
+/* IoT Cloud */
+
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
+
+/* security packages */
+
+/* end of security packages */
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+/* XML: Extensible Markup Language */
+
+/* end of XML: Extensible Markup Language */
+/* end of language packages */
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+/* end of LVGL: powerful and easy-to-use embedded GUI library */
+
+/* u8g2: a monochrome graphic library */
+
+/* end of u8g2: a monochrome graphic library */
+/* end of multimedia packages */
+
+/* tools packages */
+
+/* end of tools packages */
+
+/* system packages */
+
+/* enhanced kernel services */
+
+/* end of enhanced kernel services */
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+/* end of acceleration: Assembly language or algorithmic acceleration packages */
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+#define PKG_USING_CMSIS_CORE
+#define PKG_USING_CMSIS_CORE_LATEST_VERSION
+/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+/* end of Micrium: Micrium software products porting for RT-Thread */
+/* end of system packages */
+
+/* peripheral libraries and drivers */
+
+/* HAL & SDK Drivers */
+
+/* STM32 HAL & SDK Drivers */
+
+#define PKG_USING_STM32H7_HAL_DRIVER
+#define PKG_USING_STM32H7_HAL_DRIVER_LATEST_VERSION
+#define PKG_USING_STM32H7_CMSIS_DRIVER
+#define PKG_USING_STM32H7_CMSIS_DRIVER_LATEST_VERSION
+/* end of STM32 HAL & SDK Drivers */
+
+/* Infineon HAL Packages */
+
+/* end of Infineon HAL Packages */
+
+/* Kendryte SDK */
+
+/* end of Kendryte SDK */
+
+/* WCH HAL & SDK Drivers */
+
+/* end of WCH HAL & SDK Drivers */
+
+/* AT32 HAL & SDK Drivers */
+
+/* end of AT32 HAL & SDK Drivers */
+
+/* HC32 DDL Drivers */
+
+/* end of HC32 DDL Drivers */
+
+/* NXP HAL & SDK Drivers */
+
+/* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
+
+/* HPMicro SDK */
+
+/* end of HPMicro SDK */
+/* end of HAL & SDK Drivers */
+
+/* sensors drivers */
+
+/* end of sensors drivers */
+
+/* touch drivers */
+
+/* end of touch drivers */
+/* end of peripheral libraries and drivers */
+
+/* AI packages */
+
+/* end of AI packages */
+
+/* Signal Processing and Control Algorithm Packages */
+
+/* end of Signal Processing and Control Algorithm Packages */
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* end of project laboratory */
+
+/* samples: kernel and components samples */
+
+/* end of samples: kernel and components samples */
+
+/* entertainment: terminal games and other interesting software packages */
+
+/* end of entertainment: terminal games and other interesting software packages */
+/* end of miscellaneous packages */
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+/* end of Projects and Demos */
+
+/* Sensors */
+
+/* end of Sensors */
+
+/* Display */
+
+/* end of Display */
+
+/* Timing */
+
+/* end of Timing */
+
+/* Data Processing */
+
+/* end of Data Processing */
+
+/* Data Storage */
+
+/* Communication */
+
+/* end of Communication */
+
+/* Device Control */
+
+/* end of Device Control */
+
+/* Other */
+
+/* end of Other */
+
+/* Signal IO */
+
+/* end of Signal IO */
+
+/* Uncategorized */
+
+/* end of Arduino libraries */
+/* end of RT-Thread online packages */
+#define SOC_FAMILY_STM32
+#define SOC_SERIES_STM32H7
+
+/* Hardware Drivers Config */
+
+#define SCO_STM32H723ZGT6
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_STM32_UART_V1_TX_TIMEOUT 1000
+#define BSP_USING_LPUART1
+/* end of On-chip Peripheral Drivers */
+
+/* Board extended module Drivers */
+
+/* end of Hardware Drivers Config */
+
+#endif

bsp/stm32/stm32h723-lxb-disco/rtconfig.py

@@ -0,0 +1,185 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m7'
+CROSS_TOOL='keil'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armclang'
+    EXEC_PATH   = r'E:\Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M7.fp.sp'
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'armclang':
+    # toolchains
+    CC = 'armclang'
+    CXX = 'armclang'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M7.fp.sp '
+    CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M7 '
+    CFLAGS += ' -mcpu=cortex-M7 -mfpu=fpv4-sp-d16 '
+    CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
+    CFLAGS += ' -gdwarf-3 -ffunction-sections '
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
+    LFLAGS += ' --list rt-thread.map '
+    LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
+
+    EXEC_PATH += '/ARM/ARMCLANG/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O1' # armclang recommend
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M7'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv5_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M7'
+    AFLAGS += ' --fpu VFPv5_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/stm32/stm32h723-lxb-disco/template.uvoptx

@@ -0,0 +1,187 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp; *.cc; *.cxx</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>0</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H72x-73x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32H723ZGTx$CMSIS\Flash\STM32H72x-73x_1024.FLM))</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group 1</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+  </Group>
+
+</ProjectOpt>

bsp/stm32/stm32h723-lxb-disco/template.uvprojx

@@ -0,0 +1,397 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6230000::V6.23::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32H723ZGTx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32H7xx_DFP.4.1.2</PackID>
+          <PackURL>https://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x24000000,0x00050000) IROM(0x08000000,0x00100000) XRAM(0x30000000,0x00008000) XRAM2(0x38000000,0x00004000) CPUTYPE("Cortex-M7") FPU3(DFPU) DSP CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H72x-73x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32H723ZGTx$CMSIS\Flash\STM32H72x-73x_1024.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32H723ZGTx$CMSIS\SVD\STM32H723.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>1</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <nBranchProt>0</nBranchProt>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>0</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x8000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x38000000</StartAddress>
+                <Size>0x4000</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x24000000</StartAddress>
+                <Size>0x50000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>3</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group 1</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

components/Kconfig

@@ -37,7 +37,6 @@ rsource "libc/Kconfig"
 rsource "net/Kconfig"
 rsource "mprotect/Kconfig"
 rsource "utilities/Kconfig"
-rsource "vbus/Kconfig"
 endif
 
 if ARCH_MM_MMU

components/dfs/dfs_v1/src/dfs_file.c

@@ -830,11 +830,11 @@ void ls(const char *pathname)
                     rt_kprintf("%-20s", dirent.d_name);
                     if (S_ISDIR(stat.st_mode))
                     {
-                        rt_kprintf("%-25s\n", "<DIR>");
+                        rt_kprintf(" %-25s\n", "<DIR>");
                     }
                     else
                     {
-                        rt_kprintf("%-25lu\n", (unsigned long)stat.st_size);
+                        rt_kprintf(" %-25lu\n", (unsigned long)stat.st_size);
                     }
                 }
                 else

components/dfs/dfs_v2/src/dfs_file.c

@@ -2597,7 +2597,7 @@ void ls(const char *pathname)
                         if (S_ISDIR(stat.st_mode))
                         {
                             rt_kprintf(_COLOR_BLUE "%-20s" _COLOR_NORMAL, dirent.d_name);
-                            rt_kprintf("%-25s\n", "<DIR>");
+                            rt_kprintf(" %-25s\n", "<DIR>");
                         }
                         else if (S_ISLNK(stat.st_mode))
                         {
@@ -2655,17 +2655,17 @@ void ls(const char *pathname)
                         else if (stat.st_mode & (S_IXUSR | S_IXGRP | S_IXOTH))
                         {
                             rt_kprintf(_COLOR_GREEN "%-20s" _COLOR_NORMAL, dirent.d_name);
-                            rt_kprintf("%-25lu\n", (unsigned long)stat.st_size);
+                            rt_kprintf(" %-25lu\n", (unsigned long)stat.st_size);
                         }
                         else if (S_ISCHR(stat.st_mode))
                         {
                             rt_kprintf(_COLOR_YELLOW "%-20s" _COLOR_NORMAL, dirent.d_name);
-                            rt_kprintf("%-25s\n", "<CHR>");
+                            rt_kprintf(" %-25s\n", "<CHR>");
                         }
                         else
                         {
                             rt_kprintf("%-20s", dirent.d_name);
-                            rt_kprintf("%-25lu\n", (unsigned long)stat.st_size);
+                            rt_kprintf(" %-25lu\n", (unsigned long)stat.st_size);
                         }
                     }
                     else

components/drivers/can/dev_can.c

@@ -186,6 +186,7 @@ rt_inline int _can_int_tx(struct rt_can_device *can, const struct rt_can_msg *da
         no = ((rt_ubase_t)tx_tosnd - (rt_ubase_t)tx_fifo->buffer) / sizeof(struct rt_can_sndbxinx_list);
         tx_tosnd->result = RT_CAN_SND_RESULT_WAIT;
         rt_completion_init(&tx_tosnd->completion);
+        can->status.sndchange |= 1<<no;
         if (can->ops->sendmsg(can, data, no) != RT_EOK)
         {
             /* send failed. */
@@ -196,7 +197,6 @@ rt_inline int _can_int_tx(struct rt_can_device *can, const struct rt_can_msg *da
             goto err_ret;
         }
 
-        can->status.sndchange |= 1<<no;
         if (rt_completion_wait(&(tx_tosnd->completion), RT_CANSND_MSG_TIMEOUT) != RT_EOK)
         {
             level = rt_hw_local_irq_disable();
@@ -286,11 +286,12 @@ rt_inline int _can_int_tx_priv(struct rt_can_device *can, const struct rt_can_ms
         tx_fifo->buffer[no].result = RT_CAN_SND_RESULT_WAIT;
         rt_hw_local_irq_enable(level);
 
+        can->status.sndchange |= 1<<no;
         if (can->ops->sendmsg(can, data, no) != RT_EOK)
         {
             continue;
         }
-        can->status.sndchange |= 1<<no;
+
         if (rt_completion_wait(&(tx_fifo->buffer[no].completion), RT_CANSND_MSG_TIMEOUT) != RT_EOK)
         {
             can->status.sndchange &= ~ (1<<no);

components/drivers/include/drivers/dev_can.h

@@ -68,6 +68,9 @@ enum CANBAUD
 #define RT_CAN_MODE_PRIV                0x01
 #define RT_CAN_MODE_NOPRIV              0x00
 
+#define RT_CAN_MODE_MASK                0x00
+#define RT_CAN_MODE_LIST                0x01
+
 /**
  * @defgroup    group_drivers_can CAN Driver
  * @brief       CAN driver api

components/drivers/serial/dev_serial_v2.c

@@ -441,7 +441,7 @@ rt_ssize_t _serial_poll_tx(struct rt_device *dev,
 
     while (size)
     {
-        if (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM)
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM || (dev == rt_console_get_device()))
         {
             /* If open_flag satisfies RT_DEVICE_FLAG_STREAM and the received character is '\n',
              * inserts '\r' character before '\n' character for the effect of carriage return newline */
@@ -579,7 +579,7 @@ static rt_ssize_t _serial_fifo_tx_blocking_nbuf(struct rt_device *dev,
     tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx;
     RT_ASSERT(tx_fifo != RT_NULL);
 
-    if (rt_thread_self() == RT_NULL || (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM))
+    if (rt_thread_self() == RT_NULL || (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM) || (dev == rt_console_get_device()))
     {
         /* using poll tx when the scheduler not startup or in stream mode */
         return _serial_poll_tx(dev, pos, buffer, size);
@@ -651,7 +651,7 @@ static rt_ssize_t _serial_fifo_tx_blocking_buf(struct rt_device *dev,
     tx_fifo = (struct rt_serial_tx_fifo *)serial->serial_tx;
     RT_ASSERT(tx_fifo != RT_NULL);
 
-    if (rt_thread_self() == RT_NULL || (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM))
+    if (rt_thread_self() == RT_NULL || (serial->parent.open_flag & RT_DEVICE_FLAG_STREAM) || (dev == rt_console_get_device()))
     {
         /* using poll tx when the scheduler not startup or in stream mode */
         return _serial_poll_tx(dev, pos, buffer, size);

components/finsh/cmd.c

@@ -262,7 +262,7 @@ long list_thread(void)
 #else
                     ptr = (rt_uint8_t *)thread->stack_addr;
                     while (*ptr == '#') ptr ++;
-                    rt_kprintf(" 0x%08x 0x%08x    %02d%%   0x%08x %s %p",
+                    rt_kprintf(" 0x%08x 0x%08x    %3d%%   0x%08x %s %p",
                                thread->stack_size + ((rt_ubase_t)thread->stack_addr - (rt_ubase_t)thread->sp),
                                thread->stack_size,
                                (thread->stack_size - ((rt_ubase_t) ptr - (rt_ubase_t) thread->stack_addr)) * 100

components/libc/compilers/armlibc/syscall_mem.c

@@ -27,6 +27,21 @@
     #pragma import(__use_no_heap)
 #endif /* __CC_ARM */
 
+/**
+ * @brief Allocate memory block
+ *
+ * Allocates a block of size bytes of memory, returning a pointer to the
+ * beginning of the block. The content of the newly allocated block of
+ * memory is not initialized, remaining with indeterminate values.
+ *
+ * @param[in] n the size of the memory block, in bytes.
+ *
+ * @return On success, a pointer to the memory block allocated by the function.
+ *         If the system is configured without heap (RT_USING_HEAP is not defined),
+ *         the function will assert and return RT_NULL.
+ *
+ * @note The returned pointer is always suitably aligned for any built-in type.
+ */
 void *malloc(size_t n)
 {
 #ifdef RT_USING_HEAP
@@ -38,6 +53,28 @@ void *malloc(size_t n)
 }
 RTM_EXPORT(malloc);
 
+/**
+ * @brief Reallocate memory block
+ *
+ * Changes the size of the memory block pointed to by rmem.
+ * The function may move the memory block to a new location
+ * (whose address is returned by the function).
+ * The content of the memory block is preserved up to the
+ * lesser of the new and old sizes, even if the block is
+ * moved to a new location. If the new size is larger,
+ * the value of the newly allocated portion is indeterminate.
+ *
+ * @param[in,out] rmem pointer to a memory block previously allocated with
+ *             malloc, calloc or realloc to be reallocated.
+ *             If this is RT_NULL, a new block is allocated and
+ *             a pointer to it is returned by the function.
+ * @param[in] newsize new size for the memory block, in bytes.
+ *
+ * @return A pointer to the reallocated memory block, which may be either
+ *         the same as the rmem pointer or a new location.
+ *         If the system is configured without heap (RT_USING_HEAP is not defined),
+ *         the function will assert and return RT_NULL.
+ */
 void *realloc(void *rmem, size_t newsize)
 {
 #ifdef RT_USING_HEAP
@@ -49,6 +86,21 @@ void *realloc(void *rmem, size_t newsize)
 }
 RTM_EXPORT(realloc);
 
+/**
+ * @brief Allocate and zero-initialize array
+ *
+ * Allocates a block of memory for an array of nelem elements, each of them
+ * elsize bytes long, and initializes all its bits to zero.
+ * The effective result is the allocation of a zero-initialized memory block
+ * of (nelem*elsize) bytes.
+ *
+ * @param[in] nelem number of elements to allocate.
+ * @param[in] elsize size of each element.
+ *
+ * @return On success, a pointer to the memory block allocated by the function.
+ *         If the system is configured without heap (RT_USING_HEAP is not defined),
+ *         the function will assert and return RT_NULL.
+ */
 void *calloc(size_t nelem, size_t elsize)
 {
 #ifdef RT_USING_HEAP
@@ -60,6 +112,19 @@ void *calloc(size_t nelem, size_t elsize)
 }
 RTM_EXPORT(calloc);
 
+/**
+ * @brief Deallocate memory block
+ *
+ * A block of memory previously allocated by a call to malloc, calloc or realloc
+ * is deallocated, making it available again for further allocations.
+ *
+ * @param[in] rmem pointer to a memory block previously allocated with malloc,
+ *             calloc or realloc to be deallocated. If a null pointer is
+ *             passed as argument, no action occurs.
+ *
+ * @note If the system is configured without heap (RT_USING_HEAP is not defined),
+ *       the function will assert.
+ */
 void free(void *rmem)
 {
 #ifdef RT_USING_HEAP

components/libc/compilers/armlibc/syscalls.c

@@ -27,23 +27,23 @@
 #endif /* RT_USING_POSIX_STDIO */
 #include <posix/stdlib.h>
 
-#define DBG_TAG    "armlibc.syscalls"
-#define DBG_LVL    DBG_INFO
+#define DBG_TAG "armlibc.syscalls"
+#define DBG_LVL DBG_INFO
 #include <rtdbg.h>
 
 #ifdef __clang__
-    __asm(".global __use_no_semihosting\n\t");
+__asm(".global __use_no_semihosting\n\t");
 #else
-    #pragma import(__use_no_semihosting_swi)
+#pragma import(__use_no_semihosting_swi)
 #endif
 
 /* Standard IO device handles. */
-#define STDIN       0
-#define STDOUT      1
-#define STDERR      2
+#define STDIN  0
+#define STDOUT 1
+#define STDERR 2
 
 /* Standard IO device name defines. */
-const char __stdin_name[]  = "STDIN";
+const char __stdin_name[] = "STDIN";
 const char __stdout_name[] = "STDOUT";
 const char __stderr_name[] = "STDERR";
 
@@ -314,7 +314,8 @@ void _ttywrch(int ch)
 rt_weak void _sys_exit(int return_code)
 {
     __rt_libc_exit(return_code);
-    while (1);
+    while (1)
+        ;
 }
 
 /**
@@ -339,6 +340,12 @@ long _sys_flen(FILEHANDLE fh)
 #endif /* DFS_USING_POSIX */
 }
 
+/**
+ * check whether the file is a terminal device.
+ *
+ * @param fh - file handle
+ * @return 1 if is a terminal device, 0 if not
+ */
 int _sys_istty(FILEHANDLE fh)
 {
     if ((STDIN <= fh) && (fh <= STDERR))
@@ -347,6 +354,12 @@ int _sys_istty(FILEHANDLE fh)
         return 0;
 }
 
+/**
+ * remove a file
+ *
+ * @param filename - file name with path
+ * @return 0 on success, -1 on failed
+ */
 int remove(const char *filename)
 {
 #ifdef DFS_USING_POSIX
@@ -360,6 +373,13 @@ int remove(const char *filename)
 #ifdef __MICROLIB
 #include <stdio.h>
 
+/**
+ * write a character to file
+ *
+ * @param c - character to write
+ * @param fh - file handle
+ * @return 1 on success, 0 on failed
+ */
 int fputc(int c, FILE *f)
 {
 #ifdef RT_USING_CONSOLE
@@ -370,6 +390,12 @@ int fputc(int c, FILE *f)
 #endif /* RT_USING_CONSOLE */
 }
 
+/**
+ * get a character from file
+ *
+ * @param fh - file handle
+ * @return character read, or -1 on failed
+ */
 int fgetc(FILE *f)
 {
 #ifdef RT_USING_POSIX_STDIO

components/utilities/Kconfig

@@ -192,6 +192,14 @@ menuconfig RT_USING_ULOG
                 It will enable the log filter.
                 Such as level filter, log tag filter, log kw filter and tag's level filter.
 
+        config ULOG_USING_FINSH_CMD
+            bool "Enable ulog finsh/msh commands"
+            depends on ULOG_USING_FILTER && RT_USING_FINSH
+            default y
+            help
+                Enable this option to use ulog commands in finsh/msh,
+                such as ulog_lvl, ulog_tag, ulog_kw and so on.
+
         config ULOG_USING_SYSLOG
             bool "Enable syslog format log and API."
             select ULOG_OUTPUT_TIME

components/utilities/ulog/ulog.c

@@ -1084,7 +1084,7 @@ const char *ulog_global_filter_kw_get(void)
     return ulog.filter.keyword;
 }
 
-#ifdef RT_USING_FINSH
+#if defined(RT_USING_FINSH) && defined(ULOG_USING_FINSH_CMD)
 #include <finsh.h>
 
 static void _print_lvl_info(void)
@@ -1259,7 +1259,7 @@ static void ulog_filter(uint8_t argc, char **argv)
     }
 }
 MSH_CMD_EXPORT(ulog_filter, Show ulog filter settings);
-#endif /* RT_USING_FINSH */
+#endif /* RT_USING_FINSH && ULOG_USING_FINSH_CMD */
 #endif /* ULOG_USING_FILTER */
 
 /**

components/vbus/Kconfig

@@ -1,56 +0,0 @@
-menuconfig RT_USING_VBUS
-    bool "VBus: virtual software bus"
-    default n
-
-if RT_USING_VBUS
-    config RT_USING_VBUS_RFS
-        bool "Enable Remote File System on VBus"
-        default n
-        help
-            When enable remote file system, the application can visit the remote file system
-            through VBus with POSIX file I/O.
-
-    config RT_USING_VBUS_RSHELL
-        bool "Enable Remote Shell on VBus"
-        default n
-        help
-            When enable remote shell, the finsh/msh of RT-Thread can be operated from another
-            Operating System.
-
-    config RT_VBUS_USING_TESTS
-        bool "Enable tests on VBus"
-        default n
-
-    config _RT_VBUS_RING_BASE
-        hex "VBus address"
-        help
-            VBus ring buffer physical address.
-
-    config _RT_VBUS_RING_SZ
-        int "VBus ring size"
-        help
-            VBus size of the ring buffer.
-
-    config RT_VBUS_GUEST_VIRQ
-        int "RT_VBUS_GUEST_VIRQ"
-        help
-            The interrupt number used to notify the client on a particular system.
-
-    config RT_VBUS_HOST_VIRQ
-        int "RT_VBUS_HOST_VIRQ"
-        help
-            The interrupt be triggered on a particular system when the client notify the host.
-
-    config RT_VBUS_SHELL_DEV_NAME
-        string "RT_VBUS_SHELL_DEV_NAME"
-        default "vbser0"
-        help
-            The name of the UBUS shell device.
-
-    config RT_VBUS_RFS_DEV_NAME
-        string "RT_VBUS_RFS_DEV_NAME"
-        default "rfs"
-        help
-            The name of the UBUS rfs device.
-
-endif

components/vbus/SConscript

@@ -1,23 +0,0 @@
-# RT-Thread building script for component
-
-import SCons, os
-from building import *
-
-group = []
-if not GetDepend(['RT_USING_VBUS']):
-    Return('group')
-
-cwd = GetCurrentDir()
-src = Glob('*.c')
-
-for c, f in [['RT_USING_VBUS_RFS', 'utilities/rfs.c'],
-             ['RT_USING_VBUS_RSHELL', 'utilities/rshell.c'],
-             ]:
-    if GetDepend(c):
-        src += Glob(f)
-
-CPPPATH = [cwd, os.path.join(cwd, 'share_hdr')]
-
-group = DefineGroup('VBus', src, depend = ['RT_USING_VBUS'], CPPPATH = CPPPATH)
-
-Return('group')

components/vbus/prio_queue.c

@@ -1,256 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-04     Grissiom     add comment
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "prio_queue.h"
-
-struct rt_prio_queue_item {
-    struct rt_prio_queue_item *next;
-    /* data follows */
-};
-
-static void _do_push(struct rt_prio_queue *que,
-                     rt_uint8_t prio,
-                     struct rt_prio_queue_item *item)
-{
-    if (que->head[prio] == RT_NULL)
-    {
-        que->head[prio] = item;
-        que->bitmap |= 1 << prio;
-    }
-    else
-    {
-        RT_ASSERT(que->tail[prio]);
-        que->tail[prio]->next = item;
-    }
-    que->tail[prio] = item;
-}
-
-static struct rt_prio_queue_item* _do_pop(struct rt_prio_queue *que)
-{
-    int ffs;
-    struct rt_prio_queue_item *item;
-
-    ffs = __rt_ffs(que->bitmap);
-    if (ffs == 0)
-        return RT_NULL;
-    ffs--;
-
-    item = que->head[ffs];
-    RT_ASSERT(item);
-
-    que->head[ffs] = item->next;
-    if (que->head[ffs] == RT_NULL)
-    {
-        que->bitmap &= ~(1 << ffs);
-    }
-
-    return item;
-}
-
-rt_err_t rt_prio_queue_init(struct rt_prio_queue *que,
-                            const char *name,
-                            void *buf,
-                            rt_size_t bufsz,
-                            rt_size_t itemsz)
-{
-    RT_ASSERT(que);
-
-    rt_memset(que, 0, sizeof(*que));
-
-    rt_list_init(&(que->suspended_pop_list));
-
-    rt_mp_init(&que->pool, name, buf, bufsz,
-               sizeof(struct rt_prio_queue_item) + itemsz);
-
-    que->item_sz = itemsz;
-
-    return RT_EOK;
-}
-
-void rt_prio_queue_detach(struct rt_prio_queue *que)
-{
-    /* wake up all suspended pop threads, push thread is suspended on mempool.
-     */
-    while (!rt_list_isempty(&(que->suspended_pop_list)))
-    {
-        rt_thread_t thread;
-
-        /* disable interrupt */
-        rt_base_t level = rt_hw_interrupt_disable();
-
-        /* get next suspend thread */
-        thread = RT_THREAD_LIST_NODE_ENTRY(que->suspended_pop_list.next);
-        /* set error code to -RT_ERROR */
-        thread->error = -RT_ERROR;
-
-        rt_thread_resume(thread);
-
-        /* enable interrupt */
-        rt_hw_interrupt_enable(level);
-    }
-    rt_mp_detach(&que->pool);
-}
-
-#ifdef RT_USING_HEAP
-struct rt_prio_queue* rt_prio_queue_create(const char *name,
-                                           rt_size_t item_nr,
-                                           rt_size_t item_sz)
-{
-    struct rt_prio_queue *que;
-    rt_size_t bufsz;
-
-    bufsz = item_nr * (sizeof(struct rt_prio_queue_item)
-                       + item_sz
-                       + sizeof(void*));
-
-    RT_ASSERT(item_nr);
-
-    que = rt_malloc(sizeof(*que) + bufsz);
-    if (!que)
-        return RT_NULL;
-
-    rt_prio_queue_init(que, name, que+1, bufsz, item_sz);
-
-    return que;
-}
-
-void rt_prio_queue_delete(struct rt_prio_queue *que)
-{
-    rt_prio_queue_detach(que);
-    rt_free(que);
-}
-#endif
-
-rt_err_t rt_prio_queue_push(struct rt_prio_queue *que,
-                            rt_uint8_t prio,
-                            void *data,
-                            rt_int32_t timeout)
-{
-    rt_base_t level;
-    struct rt_prio_queue_item *item;
-
-    RT_ASSERT(que);
-
-    if (prio >= RT_PRIO_QUEUE_PRIO_MAX)
-        return -RT_ERROR;
-
-    item = rt_mp_alloc(&que->pool, timeout);
-    if (item == RT_NULL)
-        return -RT_ENOMEM;
-
-    rt_memcpy(item+1, data, que->item_sz);
-    item->next = RT_NULL;
-
-    level = rt_hw_interrupt_disable();
-
-    _do_push(que, prio, item);
-
-    if (!rt_list_isempty(&(que->suspended_pop_list)))
-    {
-        rt_thread_t thread;
-
-        /* get thread entry */
-        thread = RT_THREAD_LIST_NODE_ENTRY(que->suspended_pop_list.next);
-        /* resume it */
-        rt_thread_resume(thread);
-        rt_hw_interrupt_enable(level);
-
-        /* perform a schedule */
-        rt_schedule();
-
-        return RT_EOK;
-    }
-
-    rt_hw_interrupt_enable(level);
-
-    return RT_EOK;
-}
-
-rt_err_t rt_prio_queue_pop(struct rt_prio_queue *que,
-                           void *data,
-                           rt_int32_t timeout)
-{
-    rt_base_t level;
-    struct rt_prio_queue_item *item;
-
-    RT_ASSERT(que);
-    RT_ASSERT(data);
-
-    level = rt_hw_interrupt_disable();
-    for (item = _do_pop(que);
-         item == RT_NULL;
-         item = _do_pop(que))
-    {
-        rt_thread_t thread;
-
-        if (timeout == 0)
-        {
-            rt_hw_interrupt_enable(level);
-            return -RT_ETIMEOUT;
-        }
-
-        RT_DEBUG_NOT_IN_INTERRUPT;
-
-        thread = rt_thread_self();
-        thread->error = RT_EOK;
-        rt_thread_suspend(thread);
-
-        rt_list_insert_before(&(que->suspended_pop_list), &RT_THREAD_LIST_NODE(thread));
-
-        if (timeout > 0)
-        {
-            rt_tick_t timeout_tick = timeout;
-            rt_timer_control(&(thread->thread_timer),
-                             RT_TIMER_CTRL_SET_TIME,
-                             &timeout_tick);
-            rt_timer_start(&(thread->thread_timer));
-        }
-
-        rt_hw_interrupt_enable(level);
-
-        rt_schedule();
-
-        /* thread is waked up */
-        if (thread->error != RT_EOK)
-            return thread->error;
-        level = rt_hw_interrupt_disable();
-    }
-
-    rt_hw_interrupt_enable(level);
-
-    rt_memcpy(data, item+1, que->item_sz);
-    rt_mp_free(item);
-
-    return RT_EOK;
-}
-
-void rt_prio_queue_dump(struct rt_prio_queue *que)
-{
-    int level = 0;
-
-    rt_kprintf("bitmap: %08x\n", que->bitmap);
-    for (level = 0; level < RT_PRIO_QUEUE_PRIO_MAX; level++)
-    {
-        struct rt_prio_queue_item *item;
-
-        rt_kprintf("%2d: ", level);
-        for (item = que->head[level];
-             item;
-             item = item->next)
-        {
-            rt_kprintf("%p, ", item);
-        }
-        rt_kprintf("\n");
-    }
-}
-

components/vbus/prio_queue.h

@@ -1,54 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-04     Grissiom     add comment
- */
-
-#ifndef __PRIO_QUEUE_H__
-#define __PRIO_QUEUE_H__
-
-#include <rtthread.h>
-
-#define RT_PRIO_QUEUE_PRIO_MAX  32
-
-struct rt_prio_queue_item;
-
-struct rt_prio_queue {
-    rt_uint32_t bitmap;
-    struct rt_prio_queue_item *head[RT_PRIO_QUEUE_PRIO_MAX];
-    struct rt_prio_queue_item *tail[RT_PRIO_QUEUE_PRIO_MAX];
-    /* push thread suspend on the mempool, not queue */
-    rt_list_t suspended_pop_list;
-    rt_size_t item_sz;
-
-    struct rt_mempool pool;
-};
-
-rt_err_t rt_prio_queue_init(struct rt_prio_queue *que,
-                            const char *name,
-                            void *buf,
-                            rt_size_t bufsz,
-                            rt_size_t itemsz);
-void rt_prio_queue_detach(struct rt_prio_queue *que);
-
-rt_err_t rt_prio_queue_push(struct rt_prio_queue *que,
-                            rt_uint8_t prio,
-                            void *data,
-                            rt_int32_t timeout);
-rt_err_t rt_prio_queue_pop(struct rt_prio_queue *que,
-                           void *data,
-                           rt_int32_t timeout);
-#ifdef RT_USING_HEAP
-struct rt_prio_queue* rt_prio_queue_create(const char *name,
-                                           rt_size_t item_nr,
-                                           rt_size_t item_sz);
-void rt_prio_queue_delete(struct rt_prio_queue *que);
-#endif
-
-void rt_prio_queue_dump(struct rt_prio_queue *que);
-
-#endif /* end of include guard: __PRIO_QUEUE_H__ */

components/vbus/share_hdr/vbus_api.h

@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __VBUS_API_H__
-#define __VBUS_API_H__
-
-#define RT_VBUS_USING_FLOW_CONTROL
-
-#define RT_VBUS_CHANNEL_NR   32
-
-#define RT_VBUS_BLK_HEAD_SZ  4
-#define RT_VBUS_MAX_PKT_SZ   (256 - RT_VBUS_BLK_HEAD_SZ)
-
-#define RT_VMM_RB_BLK_NR (_RT_VBUS_RING_SZ / 64 - 1)
-
-#ifndef __ASSEMBLY__
-#include <stddef.h> /* For size_t */
-
-struct rt_vbus_blk
-{
-    unsigned char id;
-    unsigned char qos;
-    unsigned char len;
-    unsigned char reserved;
-    unsigned char data[60];
-} __attribute__((packed));
-
-struct rt_vbus_ring
-{
-    volatile size_t put_idx;
-    volatile size_t get_idx;
-    /* whether the writer is blocked on this ring. For RTT, it means the
-     * central writer thread is waiting. For Linux, it means there are some
-     * threads waiting for space to write.
-     *
-     * Note that we don't record whether there are reading thread blocked. When
-     * there is new data, the other side will always be waked up. */
-    volatile unsigned int blocked;
-    struct rt_vbus_blk blks[RT_VMM_RB_BLK_NR];
-};
-
-enum
-{
-    RT_VBUS_CHN0_CMD_ENABLE,
-    RT_VBUS_CHN0_CMD_DISABLE,
-    RT_VBUS_CHN0_CMD_SET,
-    RT_VBUS_CHN0_CMD_ACK,
-    RT_VBUS_CHN0_CMD_NAK,
-    /* If the recieving side reached high water mark. It has the right to
-     * suspend the channel. All the server/client should know about this
-     * command but the one that does not implement flow control could ignore
-     * this command. */
-    RT_VBUS_CHN0_CMD_SUSPEND,
-    RT_VBUS_CHN0_CMD_RESUME,
-    RT_VBUS_CHN0_CMD_MAX,
-};
-
-enum rt_vbus_chn_status
-{
-    /* initial state, available for reuse */
-    RT_VBUS_CHN_ST_AVAILABLE,
-    /* ACK DISABLE send(CS) or received(CS), but not ready for reuse.(the
-     * channel is not closed by this end) */
-    RT_VBUS_CHN_ST_CLOSED,
-    /* ENABLE send(client) or received(server) */
-    RT_VBUS_CHN_ST_ESTABLISHING,
-    /* ACK SET send(C) or received(S) */
-    RT_VBUS_CHN_ST_ESTABLISHED,
-    /* Channel suspended by flow control. */
-    RT_VBUS_CHN_ST_SUSPEND,
-    /* DISABLE received(CS) */
-    RT_VBUS_CHN_ST_CLOSING,
-};
-#endif
-
-#undef BUILD_ASSERT
-/* borrowed from http://lxr.linux.no/linux+v2.6.26.5/include/linux/kernel.h#L494 */
-#define BUILD_ASSERT(condition) ((void)sizeof(char[1 - 2*!(condition)]))
-
-/* max length of a channel name, including the \0 */
-#define RT_VBUS_CHN_NAME_MAX   16
-
-#endif /* end of include guard: __VBUS_API_H__ */
-

components/vbus/vbus.h

@@ -1,177 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-06-09     Grissiom     version 2.0.2; add comment
- * 2015-01-06     Grissiom     version 2.0.3; API change, no functional changes
- */
-#ifndef __VBUS_H__
-#define __VBUS_H__
-
-#include <vbus_api.h>
-
-int rt_vbus_init(void *outr, void *inr);
-
-void rt_vbus_resume_out_thread(void);
-
-/** Post data on channel.
- *
- * @param chnr the channel number
- * @param prio the priority of the data
- * @param datap pointer to the actual data
- * @param size number of byte of the data
- * @param timeout the value used in the blocking API
- *
- * Note: rt_vbus_post is an asynchronous function that when it returns, the
- * @datap and @size is recorded in the post queue at least but there is no
- * guarantee that the data is copied into the ring buffer. To avoid data
- * corruption, you need to wait on the RT_VBUS_EVENT_ID_TX event.
- *
- * However, if you just post static data such as static string, there is no
- * need to wait.
- *
- * @sa rt_vbus_register_listener .
- */
-rt_err_t rt_vbus_post(rt_uint8_t chnr,
-                      rt_uint8_t prio,
-                      const void *datap,
-                      rt_size_t size,
-                      rt_int32_t timeout);
-
-struct rt_vbus_data {
-    /* Number of bytes in current data package. */
-    unsigned char size;
-    /* Used internally in VBus. Don't modify this field as it may corrupt the
-     * receive queue. */
-    struct rt_vbus_data *next;
-    /* Data follows the struct */
-};
-
-struct rt_vbus_wm_cfg {
-    unsigned int low, high;
-};
-
-struct rt_vbus_request {
-    unsigned char prio;
-    const char *name;
-    int is_server;
-    struct rt_vbus_wm_cfg recv_wm, post_wm;
-};
-
-/** Request a channel.
- *
- * @return channel number. Negative if error happened.
- */
-int rt_vbus_request_chn(struct rt_vbus_request *req, int timeout);
-
-/** Close channel @chnr */
-void rt_vbus_close_chn(unsigned char chnr);
-
-/** Set the water mark level for posting into the channel @chnr. */
-void rt_vbus_set_post_wm(unsigned char chnr, unsigned int low, unsigned int high);
-/** Set the water mark level for receiving from the channel @chnr. */
-void rt_vbus_set_recv_wm(unsigned char chnr, unsigned int low, unsigned int high);
-
-typedef void (*rt_vbus_event_listener)(void *ctx);
-
-enum rt_vbus_event_id {
-    /* On a packet received in channel. */
-    RT_VBUS_EVENT_ID_RX,
-    /* On the data of rt_vbus_post has been written to the ring buffer. */
-    RT_VBUS_EVENT_ID_TX,
-    /* On the channel has been closed. */
-    RT_VBUS_EVENT_ID_DISCONN,
-    RT_VBUS_EVENT_ID_MAX,
-};
-
-/** Register callback @indi on the event @eve on the @chnr.
- *
- * @ctx will passed to @indi on calling the @indi.
- */
-void rt_vbus_register_listener(unsigned char chnr,
-                               enum rt_vbus_event_id eve,
-                               rt_vbus_event_listener indi,
-                               void *ctx);
-
-/** Listen on any events happen on the @chnr for @timeout ticks.
- *
- * This function blocks until events occur or timeout happened.
- */
-rt_err_t rt_vbus_listen_on(rt_uint8_t chnr,
-                           rt_int32_t timeout);
-
-/** Push a data package into the receive queue of the channel @chnr. */
-void rt_vbus_data_push(unsigned int chnr,
-                       struct rt_vbus_data *data);
-/** Pop a data package from the receive queue of the channel @chnr.
- *
- * The actual data is following the struct rt_vbus_data. After using it, it
- * should be freed by rt_free.
- */
-struct rt_vbus_data* rt_vbus_data_pop(unsigned int chnr);
-
-struct rt_vbus_dev
-{
-    /* Runtime infomations. */
-    rt_uint8_t chnr;
-    struct rt_vbus_data *act;
-    rt_size_t pos;
-
-    /* There will be a request for each channel. So no need to seperate them so
-     * clearly. */
-    struct rt_vbus_request req;
-};
-
-rt_err_t rt_vbus_chnx_init(void);
-/** Get the corresponding channel number from the VBus device @dev. */
-rt_uint8_t rt_vbus_get_chnnr(rt_device_t dev);
-/** Register a call back on the other side disconnect the channel.
- *
- * @sa rt_vbus_register_listener .
- */
-void rt_vbus_chnx_register_disconn(rt_device_t dev,
-                                   rt_vbus_event_listener indi,
-                                   void *ctx);
-
-/* Commands for the device control interface. */
-#define VBUS_IOCRECV_WM      0xD1
-#define VBUS_IOCPOST_WM      0xD2
-/** Configure event listener */
-#define VBUS_IOC_LISCFG      0xD3
-
-struct rt_vbus_dev_liscfg
-{
-    enum rt_vbus_event_id event;
-    rt_vbus_event_listener listener;
-    void *ctx;
-};
-
-int rt_vbus_shell_start(void);
-#ifdef RT_USING_VBUS_RFS
-int dfs_rfs_init(void);
-#endif
-
-/** VBus hardware init function.
- *
- * BSP should implement this function to initialize the interrupts etc.
- */
-int rt_vbus_hw_init(void);
-
-/** VBus ISR function.
- *
- * BSP should call this function when the interrupt from other core is
- * triggered. @param is not used by VBus and will pass to rt_vbus_hw_eoi.
- */
-void rt_vbus_isr(int irqnr, void *param);
-
-/** VBus End Of Interrupt function.
- *
- * This function will be called when VBus finished the ISR handling. BSP should
- * define this function to clear the interrupt flag etc.
- */
-int rt_vbus_hw_eoi(int irqnr, void *param);
-
-#endif /* end of include guard: __VBUS_H__ */

components/vbus/vbus_chnx.c

@@ -1,269 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-04     Grissiom     add comment
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include "vbus.h"
-
-static void _rx_indicate(void *ctx)
-{
-    rt_device_t dev = ctx;
-
-    if (dev->rx_indicate)
-        dev->rx_indicate(dev, 0);
-}
-
-static void _tx_complete(void *ctx)
-{
-    rt_device_t dev = ctx;
-
-    if (dev->tx_complete)
-        dev->tx_complete(dev, 0);
-}
-
-static rt_err_t _open(rt_device_t dev, rt_uint16_t oflag)
-{
-    int chnr;
-    struct rt_vbus_dev *vdev = dev->user_data;
-
-    if (vdev->chnr)
-        return RT_EOK;
-
-    /* FIXME: request the same name for twice will crash */
-    chnr = rt_vbus_request_chn(&vdev->req, RT_WAITING_FOREVER);
-    if (chnr < 0)
-        return chnr;
-
-    vdev->chnr = chnr;
-    rt_vbus_register_listener(chnr, RT_VBUS_EVENT_ID_RX, _rx_indicate, dev);
-    rt_vbus_register_listener(chnr, RT_VBUS_EVENT_ID_TX, _tx_complete, dev);
-
-    return RT_EOK;
-}
-
-static rt_err_t _close(rt_device_t dev)
-{
-    struct rt_vbus_dev *vdev = dev->user_data;
-
-    RT_ASSERT(vdev->chnr != 0);
-
-    rt_vbus_close_chn(vdev->chnr);
-    vdev->chnr = 0;
-
-    return RT_EOK;
-}
-
-static rt_ssize_t _read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
-{
-    rt_size_t outsz = 0;
-    struct rt_vbus_dev *vdev = dev->user_data;
-
-    RT_ASSERT(vdev->chnr != 0);
-
-    if (vdev->act == RT_NULL)
-    {
-        vdev->act = rt_vbus_data_pop(vdev->chnr);
-        vdev->pos = 0;
-    }
-
-    while (1)
-    {
-        rt_err_t err;
-
-        while (vdev->act)
-        {
-            rt_size_t cpysz;
-
-            if (size - outsz > vdev->act->size - vdev->pos)
-                cpysz = vdev->act->size - vdev->pos;
-            else
-                cpysz = size - outsz;
-
-            rt_memcpy((char*)buffer + outsz, ((char*)(vdev->act+1)) + vdev->pos, cpysz);
-            vdev->pos += cpysz;
-
-            outsz += cpysz;
-            if (outsz == size)
-            {
-                return outsz;
-            }
-            else if (outsz > size)
-                RT_ASSERT(0);
-
-            /* free old and get new */
-            rt_free(vdev->act);
-            vdev->act = rt_vbus_data_pop(vdev->chnr);
-            vdev->pos = 0;
-        }
-
-        /* TODO: We don't want to touch the rx_indicate here. But this lead to
-         * some duplication. Maybe we should find a better way to handle this.
-         */
-        if (rt_interrupt_get_nest() == 0)
-        {
-            err = rt_vbus_listen_on(vdev->chnr, RT_WAITING_FOREVER);
-        }
-        else
-        {
-            err = rt_vbus_listen_on(vdev->chnr, 0);
-        }
-        if (err != RT_EOK)
-        {
-            rt_set_errno(err);
-            return outsz;
-        }
-        vdev->act = rt_vbus_data_pop(vdev->chnr);
-        vdev->pos = 0;
-    }
-}
-
-static rt_ssize_t _write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
-{
-    rt_err_t err;
-    struct rt_vbus_dev *vdev = dev->user_data;
-
-    RT_ASSERT(vdev->chnr != 0);
-
-    if (rt_interrupt_get_nest() == 0)
-    {
-        /* Thread context. */
-        err = rt_vbus_post(vdev->chnr, vdev->req.prio,
-                           buffer, size, RT_WAITING_FOREVER);
-    }
-    else
-    {
-        /* Interrupt context. */
-        err = rt_vbus_post(vdev->chnr, vdev->req.prio,
-                           buffer, size, 0);
-    }
-
-    if (err)
-    {
-        rt_set_errno(err);
-        return 0;
-    }
-
-    return size;
-}
-
-rt_err_t  _control(rt_device_t dev, int cmd, void *args)
-{
-    RT_ASSERT(dev);
-
-    switch (cmd) {
-    case VBUS_IOC_LISCFG: {
-        struct rt_vbus_dev *vdev = dev->user_data;
-        struct rt_vbus_dev_liscfg *liscfg = args;
-
-        RT_ASSERT(vdev->chnr != 0);
-        if (!liscfg)
-            return -RT_ERROR;
-
-        rt_vbus_register_listener(vdev->chnr, liscfg->event,
-                                  liscfg->listener, liscfg->ctx);
-        return RT_EOK;
-    }
-        break;
-#ifdef RT_VBUS_USING_FLOW_CONTROL
-    case VBUS_IOCRECV_WM: {
-        struct rt_vbus_dev *vdev = dev->user_data;
-        struct rt_vbus_wm_cfg *cfg;
-
-        RT_ASSERT(vdev->chnr != 0);
-
-        if (!args)
-            return -RT_ERROR;
-
-        cfg = (struct rt_vbus_wm_cfg*)args;
-        if (cfg->low > cfg->high)
-            return -RT_ERROR;
-
-        rt_vbus_set_recv_wm(vdev->chnr, cfg->low, cfg->high);
-        return RT_EOK;
-    }
-        break;
-    case VBUS_IOCPOST_WM: {
-        struct rt_vbus_dev *vdev = dev->user_data;
-        struct rt_vbus_wm_cfg *cfg;
-
-        RT_ASSERT(vdev->chnr != 0);
-
-        if (!args)
-            return -RT_ERROR;
-
-        cfg = (struct rt_vbus_wm_cfg*)args;
-        if (cfg->low > cfg->high)
-            return -RT_ERROR;
-
-        rt_vbus_set_post_wm(vdev->chnr, cfg->low, cfg->high);
-        return RT_EOK;
-    }
-        break;
-#endif
-    default:
-        break;
-    };
-
-    return -RT_ENOSYS;
-}
-
-rt_uint8_t rt_vbus_get_chnnr(rt_device_t dev)
-{
-    struct rt_vbus_dev *vdev;
-
-    RT_ASSERT(dev);
-
-    vdev = dev->user_data;
-
-    return vdev->chnr;
-}
-
-void rt_vbus_chnx_register_disconn(rt_device_t dev,
-                                   rt_vbus_event_listener indi,
-                                   void *ctx)
-{
-    if (dev && dev->user_data)
-    {
-        struct rt_vbus_dev *vdev = dev->user_data;
-        RT_ASSERT(vdev->chnr != 0);
-
-        rt_vbus_register_listener(vdev->chnr, RT_VBUS_EVENT_ID_DISCONN,
-                                  indi, ctx);
-    }
-}
-
-#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
-
-extern struct rt_vbus_dev rt_vbus_chn_devx[];
-static struct rt_device _devx[32];
-
-rt_err_t rt_vbus_chnx_init(void)
-{
-    int i;
-    struct rt_vbus_dev *p;
-
-    for (i = 0,                   p = rt_vbus_chn_devx;
-         i < ARRAY_SIZE(_devx) && p->req.name;
-         i++,                     p++)
-    {
-        _devx[i].type      = RT_Device_Class_Char;
-        _devx[i].open      = _open;
-        _devx[i].close     = _close;
-        _devx[i].read      = _read;
-        _devx[i].write     = _write;
-        _devx[i].control   = _control;
-        _devx[i].user_data = p;
-        rt_device_register(&_devx[i], p->req.name, RT_DEVICE_FLAG_RDWR);
-    }
-
-    return RT_EOK;
-}

components/vbus/watermark_queue.c

@@ -1,50 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-04-16     Grissiom     first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "watermark_queue.h"
-
-void rt_wm_que_set_mark(struct rt_watermark_queue *wg,
-                             unsigned int low, unsigned int high)
-{
-    RT_ASSERT(low <= high);
-
-    wg->high_mark = high;
-    wg->low_mark = low;
-}
-
-void rt_wm_que_init(struct rt_watermark_queue *wg,
-                         unsigned int low, unsigned int high)
-{
-    rt_wm_que_set_mark(wg, low, high);
-    rt_list_init(&wg->suspended_threads);
-    wg->level = 0;
-}
-
-void rt_wm_que_dump(struct rt_watermark_queue *wg)
-{
-    struct rt_list_node *node;
-
-    rt_kprintf("wg %p: low: %d, high: %d, cur: %d\n",
-               wg, wg->low_mark, wg->high_mark, wg->level);
-    rt_kprintf("thread suspend:");
-    for (node = wg->suspended_threads.next;
-         node != &wg->suspended_threads;
-         node = node->next)
-    {
-        rt_thread_t thread;
-
-        thread = RT_THREAD_LIST_NODE_ENTRY(wg->suspended_threads.next);
-        rt_kprintf(" %.*s", RT_NAME_MAX, thread->parent.name);
-    }
-    rt_kprintf("\n");
-}

components/vbus/watermark_queue.h

@@ -1,129 +0,0 @@
-/*
- * COPYRIGHT (C) 2011-2021, Real-Thread Information Technology Ltd
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2014-04-16     Grissiom     first version
- */
-
-struct rt_watermark_queue
-{
-    /* Current water level. */
-    unsigned int level;
-    unsigned int high_mark;
-    unsigned int low_mark;
-    rt_list_t suspended_threads;
-};
-
-/** Init the struct rt_watermark_queue.
- */
-void rt_wm_que_init(struct rt_watermark_queue *wg,
-                    unsigned int low, unsigned int high);
-void rt_wm_que_set_mark(struct rt_watermark_queue *wg,
-                        unsigned int low, unsigned int high);
-void rt_wm_que_dump(struct rt_watermark_queue *wg);
-
-/* Water marks are often used in performance critical places. Benchmark shows
- * inlining functions will have 10% performance gain in some situation(for
- * example, VBus). So keep the inc/dec compact and inline. */
-
-/** Increase the water level.
- *
- * It should be called in the thread that want to raise the water level. If the
- * current level is above the high mark, the thread will be suspended up to
- * @timeout ticks.
- *
- * @return RT_EOK if water level increased successfully. -RT_EFULL on @timeout
- * is zero and the level is above water mark. -RT_ETIMEOUT if timeout occurred.
- */
-rt_inline rt_err_t rt_wm_que_inc(struct rt_watermark_queue *wg,
-                                 int timeout)
-{
-    rt_base_t level;
-
-    /* Assert as early as possible. */
-    if (timeout != 0)
-    {
-        RT_DEBUG_IN_THREAD_CONTEXT;
-    }
-
-    level = rt_hw_interrupt_disable();
-
-    while (wg->level > wg->high_mark)
-    {
-        rt_thread_t thread;
-
-        if (timeout == 0)
-        {
-            rt_hw_interrupt_enable(level);
-            return -RT_EFULL;
-        }
-
-        thread = rt_thread_self();
-        thread->error = RT_EOK;
-        rt_thread_suspend(thread);
-        rt_list_insert_after(&wg->suspended_threads, &RT_THREAD_LIST_NODE(thread));
-        if (timeout > 0)
-        {
-            rt_tick_t timeout_tick = timeout;
-            rt_timer_control(&(thread->thread_timer),
-                             RT_TIMER_CTRL_SET_TIME,
-                             &timeout_tick);
-            rt_timer_start(&(thread->thread_timer));
-        }
-        rt_hw_interrupt_enable(level);
-        rt_schedule();
-        if (thread->error != RT_EOK)
-            return thread->error;
-
-        level = rt_hw_interrupt_disable();
-    }
-
-    wg->level++;
-
-    if (wg->level == 0)
-    {
-        wg->level = ~0;
-    }
-
-    rt_hw_interrupt_enable(level);
-
-    return RT_EOK;
-}
-
-/** Decrease the water level.
- *
- * It should be called by the consumer that drain the water out. If the water
- * level reached low mark, all the thread suspended in this queue will be waken
- * up. It's safe to call this function in interrupt context.
- */
-rt_inline void rt_wm_que_dec(struct rt_watermark_queue *wg)
-{
-    int need_sched = 0;
-    rt_base_t level;
-
-    if (wg->level == 0)
-        return;
-
-    level = rt_hw_interrupt_disable();
-    wg->level--;
-    if (wg->level == wg->low_mark)
-    {
-        /* There should be spaces between the low mark and high mark, so it's
-         * safe to resume all the threads. */
-        while (!rt_list_isempty(&wg->suspended_threads))
-        {
-            rt_thread_t thread;
-
-            thread = RT_THREAD_LIST_NODE_ENTRY(wg->suspended_threads.next);
-            rt_thread_resume(thread);
-            need_sched = 1;
-        }
-    }
-    rt_hw_interrupt_enable(level);
-
-    if (need_sched)
-        rt_schedule();
-}

documentation/Doxyfile.1.9.1

@@ -924,7 +924,8 @@ RECURSIVE              = YES
 EXCLUDE                = ./0.doxygen/mainpage.h \
                          ./2.quick-start/quick_start_qemu \
                          ./env/env-vscode.md \
-                         ./7.contribution/coding_style_cn.md
+                         ./7.contribution/coding_style_cn.md \
+                         ../src/utest/perf/README.md
 
 # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
 # directories that are symbolic links (a Unix file system feature) are excluded

documentation/Doxyfile.1.9.8

@@ -1014,7 +1014,8 @@ RECURSIVE              = YES
 EXCLUDE                = ./0.doxygen/mainpage.h \
                          ./2.quick-start/quick_start_qemu \
                          ./env/env-vscode.md \
-                         ./7.contribution/coding_style_cn.md
+                         ./7.contribution/coding_style_cn.md \
+                         ../src/utest/perf/README.md
 
 # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
 # directories that are symbolic links (a Unix file system feature) are excluded

include/klibc/kstdio.h

@@ -19,9 +19,9 @@ extern "C" {
 #endif
 
 int rt_vsprintf(char *dest, const char *format, va_list arg_ptr);
-int rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list args);
+int rt_vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
 int rt_sprintf(char *buf, const char *format, ...);
-int rt_snprintf(char *buf, rt_size_t size, const char *format, ...);
+int rt_snprintf(char *buf, size_t size, const char *format, ...);
 int rt_vsscanf(const char *buffer, const char *format, va_list ap);
 int rt_sscanf(const char *str, const char *format, ...);
 

include/klibc/kstring.h

@@ -17,20 +17,20 @@
 extern "C" {
 #endif
 
-void *rt_memset(void *src, int c, rt_ubase_t n);
-void *rt_memcpy(void *dest, const void *src, rt_ubase_t n);
-void *rt_memmove(void *dest, const void *src, rt_size_t n);
-rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_size_t count);
+void *rt_memset(void *s, int c, size_t n);
+void *rt_memcpy(void *dest, const void *src, size_t n);
+void *rt_memmove(void *dest, const void *src, size_t n);
+int rt_memcmp(const void *cs, const void *ct, size_t count);
 
 char *rt_strdup(const char *s);
-rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen);
+size_t rt_strnlen(const char *s, size_t maxlen);
 char *rt_strstr(const char *str1, const char *str2);
-rt_int32_t rt_strcasecmp(const char *a, const char *b);
+int rt_strcasecmp(const char *a, const char *b);
 char *rt_strcpy(char *dst, const char *src);
-char *rt_strncpy(char *dest, const char *src, rt_size_t n);
-rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_size_t count);
-rt_int32_t rt_strcmp(const char *cs, const char *ct);
-rt_size_t rt_strlen(const char *src);
+char *rt_strncpy(char *dest, const char *src, size_t n);
+int rt_strncmp(const char *cs, const char *ct, size_t count);
+int rt_strcmp(const char *cs, const char *ct);
+size_t rt_strlen(const char *src);
 
 #ifdef __cplusplus
 }

include/rtdef.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2025 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -60,6 +60,7 @@
  * 2024-01-18     Shell        Seperate basical types to a rttypes.h
  *                             Seperate the compiler portings to rtcompiler.h
  * 2024-03-30     Meco Man     update version number to v5.2.0
+ * 2025-11-10     Rbb666       update version number to v5.3.0
  */
 
 #ifndef __RT_DEF_H__
@@ -82,8 +83,8 @@ extern "C" {
 
 /* RT-Thread version information */
 #define RT_VERSION_MAJOR                5               /**< Major version number (X.x.x) */
-#define RT_VERSION_MINOR                2               /**< Minor version number (x.X.x) */
-#define RT_VERSION_PATCH                2               /**< Patch version number (x.x.X) */
+#define RT_VERSION_MINOR                3               /**< Minor version number (x.X.x) */
+#define RT_VERSION_PATCH                0               /**< Patch version number (x.x.X) */
 
 /* e.g. #if (RTTHREAD_VERSION >= RT_VERSION_CHECK(4, 1, 0) */
 #define RT_VERSION_CHECK(major, minor, revise)          ((major * 10000U) + (minor * 100U) + revise)

libcpu/arm/cortex-a/cpuport.h

@@ -72,6 +72,11 @@ struct rt_hw_stack
 #define E_Bit       (1<<9)
 #define J_Bit       (1<<24)
 
+/* VFP/NEON register count for FPU context */
+#ifndef VFP_DATA_NR
+#define VFP_DATA_NR 64  /* 32 double-precision registers = 64 words */
+#endif
+
 #ifdef RT_USING_SMP
 typedef union {
     unsigned long slock;

libcpu/arm/cortex-a/stack.c

@@ -61,7 +61,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0;       /* user sp*/
 #endif
 #ifdef RT_USING_FPU
-    *(--stk) = 0;       /* not use fpu*/
+    /* FPU context initialization matches context_gcc.S restore order:
+     * Stack layout (high to low): FPEXC -> FPSCR -> D16-D31 -> D0-D15
+     */
+    stk -= VFP_DATA_NR;
+    rt_memset(stk, 0, VFP_DATA_NR * sizeof(rt_uint32_t));  /* Initialize D0-D31 (64 words for 32 double regs) */
+    *(--stk) = 0;       /* FPSCR: Floating-Point Status and Control Register */
+    *(--stk) = 0x40000000;  /* FPEXC: Enable FPU (bit 30 = EN) */
 #endif
 
     /* return task's current stack address */

libcpu/arm/realview-a8-vmm/SConscript

@@ -1,23 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd]
-
-if rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += Glob('*_rvds.S')
-
-if rtconfig.PLATFORM in ['gcc']:
-    src += Glob('*_init.S')
-    src += Glob('*_gcc.S')
-
-if rtconfig.PLATFORM in ['iccarm']:
-    src += Glob('*_iar.S')
-
-group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

libcpu/arm/realview-a8-vmm/armv7.h

@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __ARMV7_H__
-#define __ARMV7_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long sp;
-    unsigned long lr;
-    unsigned long pc;
-    unsigned long cpsr;
-};
-
-struct rt_hw_stack
-{
-    unsigned long cpsr;
-    unsigned long r0;
-    unsigned long r1;
-    unsigned long r2;
-    unsigned long r3;
-    unsigned long r4;
-    unsigned long r5;
-    unsigned long r6;
-    unsigned long r7;
-    unsigned long r8;
-    unsigned long r9;
-    unsigned long r10;
-    unsigned long fp;
-    unsigned long ip;
-    unsigned long lr;
-    unsigned long pc;
-};
-
-#define USERMODE    0x10
-#define FIQMODE     0x11
-#define IRQMODE     0x12
-#define SVCMODE     0x13
-#define MONITORMODE 0x16
-#define ABORTMODE   0x17
-#define HYPMODE     0x1b
-#define UNDEFMODE   0x1b
-#define MODEMASK    0x1f
-#define NOINT       0xc0
-
-#define T_Bit       (1<<5)
-#define F_Bit       (1<<6)
-#define I_Bit       (1<<7)
-#define A_Bit       (1<<8)
-#define E_Bit       (1<<9)
-#define J_Bit       (1<<24)
-
-#endif

libcpu/arm/realview-a8-vmm/context_gcc.S

@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-07-05     Bernard      the first version
- */
-
-#include <rtconfig.h>
-
-.section .text, "ax"
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mrs r0, cpsr
-    cpsid i
-    bx  lr
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    msr cpsr, r0
-    bx  lr
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    ldr sp, [r0]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task spsr
-    msr spsr_cxsf, r4
-
-    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
-
-.section .bss.share.isr
-_guest_switch_lvl:
-    .word 0
-
-.globl vmm_virq_update
-
-.section .text.isr, "ax"
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
-    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
-
-    mrs r4, cpsr
-    tst lr, #0x01
-    orrne r4, r4, #0x20     @ it's thumb code
-
-    stmfd sp!, {r4}         @ push cpsr
-
-    str sp, [r0]            @ store sp in preempted tasks TCB
-    ldr sp, [r1]            @ get new task stack pointer
-
-    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
-    msr spsr_cxsf, r4
-    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    ldr r2, =rt_thread_switch_interrupt_flag
-    ldr r3, [r2]
-    cmp r3, #1
-    beq _reswitch
-    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
-    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
-    str r0, [ip]
-    str r3, [r2]
-_reswitch:
-    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
-    str r1, [r2]
-    bx  lr

libcpu/arm/realview-a8-vmm/cp15.h

@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __CP15_H__
-#define __CP15_H__
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_vector_set_base(unsigned int addr);
-
-#endif