[docs][utest]:Add standardized utest documentation block for slab_tc

Signed-off-by: Ze-Hou <yingkezhou@qq.com>

.github/ALL_BSP_COMPILE.json

@@ -160,6 +160,7 @@
         "stm32/stm32f407-atk-explorer",
         "stm32/stm32f407-robomaster-c",
         "stm32/stm32f407-st-discovery",
+        "stm32/stm32f407-micu",
         "stm32/stm32f410-st-nucleo",
         "stm32/stm32f411-st-nucleo",
         "stm32/stm32f411-atk-nano",
@@ -195,6 +196,7 @@
         "stm32/stm32h563-st-nucleo",
         "stm32/stm32h503-st-nucleo",
         "stm32/stm32h723-st-nucleo",
+        "stm32/stm32h723-lxb-disco",
         "stm32/stm32h730-esphosted-evb",
         "stm32/stm32h743-armfly-v7",
         "stm32/stm32h743-atk-apollo",
@@ -482,6 +484,7 @@
       "RTT_BSP": "xuantie",
       "RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib",
       "SUB_RTT_BSP": [
+        "xuantie/smartl/e901",
         "xuantie/smartl/e902",
         "xuantie/smartl/e906",
         "xuantie/smartl/e907",

.github/workflows/README_CI_RESULTS.md

@@ -0,0 +1,139 @@
+# CI Results Comment Workflow
+
+## Overview / 概述
+
+This feature automatically posts CI test results as comments on Pull Requests, making it easier for contributors and reviewers to see the status of all CI checks at a glance.
+
+此功能自动将 CI 测试结果作为评论发布到 Pull Request 中，使贡献者和审阅者更容易一目了然地看到所有 CI 检查的状态。
+
+## Implementation / 实现方式
+
+The feature uses **two complementary approaches** to ensure CI results are always visible:
+该功能使用**两种互补方法**来确保 CI 结果始终可见：
+
+### 1. Direct Workflow Integration (Immediate) / 直接工作流集成（立即生效）
+
+Each main CI workflow includes a `post-ci-status` job that:
+每个主要 CI 工作流都包含一个 `post-ci-status` 作业，它：
+
+- ✅ Works immediately on PR branches (no merge required) / 立即在 PR 分支上生效（无需合并）
+- 📝 Updates a single comment with workflow status / 使用工作流状态更新单个评论
+- 🔄 Runs after each workflow completes / 在每个工作流完成后运行
+
+**Modified Workflows:**
+- `bsp_buildings.yml`
+- `static_code_analysis.yml`
+- `format_check.yml`
+- `utest_auto_run.yml`
+
+### 2. Workflow Run Trigger (After Merge) / 工作流运行触发器（合并后）
+
+The `ci_results_comment.yml` workflow:
+`ci_results_comment.yml` 工作流：
+
+- ⏰ Triggers when CI workflows complete / 在 CI 工作流完成时触发
+- 📊 Provides comprehensive summary of all workflows / 提供所有工作流的全面摘要
+- 🔍 Shows detailed job-level information / 显示详细的作业级信息
+- ⚠️ **Only works after merged to master** / **仅在合并到 master 后才有效**
+
+## Features / 功能特性
+
+1. **Automatic Updates / 自动更新**: The comment is automatically created when CI workflows complete and updated as new workflows finish.
+   / 当 CI 工作流完成时自动创建评论，并在新工作流完成时更新。
+
+2. **Comprehensive Summary / 全面总结**: Shows the status of all major CI workflows including:
+   / 显示所有主要 CI 工作流的状态，包括：
+   - RT-Thread BSP Static Build Check / BSP 静态构建检查
+   - Static code analysis / 静态代码分析
+   - Check File Format and License / 文件格式和许可证检查
+   - utest_auto_run / 单元测试自动运行
+
+3. **Status Indicators / 状态指示器**:
+   - ✅ Success / 成功
+   - ❌ Failure / 失败
+   - 🟠 Queued / 排队中
+   - 🟡 In Progress / 进行中
+   - ⏭️ Skipped / 已跳过
+
+4. **Detailed Information / 详细信息**: Expandable sections show individual job results within each workflow.
+   / 可展开的部分显示每个工作流中的各个作业结果。
+
+## How It Works / 工作原理
+
+1. The workflow is triggered when any of the monitored CI workflows complete.
+   / 当任何受监控的 CI 工作流完成时，将触发此工作流。
+
+2. It collects the status of all workflows and jobs for the associated Pull Request.
+   / 它收集关联 Pull Request 的所有工作流和作业的状态。
+
+3. A formatted comment is posted (or updated if one already exists) with the current CI status.
+   / 发布（或更新已存在的）格式化评论，显示当前 CI 状态。
+
+## Comment Format / 评论格式
+
+The comment includes:
+评论包括：
+
+- **Overall Summary / 总体摘要**: Quick statistics showing count of passed, failed, queued, in-progress, and skipped workflows.
+  / 快速统计数据，显示通过、失败、排队、进行中和跳过的工作流数量。
+
+- **Detailed Results / 详细结果**: Collapsible sections for each workflow with links to individual jobs.
+  / 每个工作流的可折叠部分，包含指向各个作业的链接。
+
+## Benefits / 优势
+
+1. **Visibility / 可见性**: Contributors can immediately see which CI checks have passed or failed without navigating to the Actions tab.
+   / 贡献者无需导航到 Actions 选项卡即可立即查看哪些 CI 检查通过或失败。
+
+2. **Efficiency / 效率**: Reviewers can quickly assess the CI status before reviewing the code.
+   / 审阅者可以在审查代码之前快速评估 CI 状态。
+
+3. **Transparency / 透明度**: All stakeholders have a clear view of the PR's CI status.
+   / 所有利益相关者都可以清楚地了解 PR 的 CI 状态。
+
+## Permissions Required / 所需权限
+
+The workflow requires the following permissions:
+工作流需要以下权限：
+
+- `pull-requests: write` - To create and update comments / 创建和更新评论
+- `issues: write` - To post comments on PR issues / 在 PR 问题上发布评论
+- `actions: read` - To read workflow run status / 读取工作流运行状态
+- `checks: read` - To read check run status / 读取检查运行状态
+
+## Configuration / 配置
+
+The workflow monitors the following workflows by default:
+工作流默认监控以下工作流：
+
+```yaml
+workflows:
+  - "RT-Thread BSP Static Build Check"
+  - "Static code analysis"
+  - "Check File Format and License"
+  - "utest_auto_run"
+```
+
+To add more workflows to monitor, edit the `.github/workflows/ci_results_comment.yml` file and add workflow names to the `workflows` list.
+
+要监控更多工作流，请编辑 `.github/workflows/ci_results_comment.yml` 文件并将工作流名称添加到 `workflows` 列表中。
+
+## Troubleshooting / 故障排除
+
+### Comment not appearing / 评论未出现
+
+1. Ensure the workflow has the required permissions / 确保工作流具有所需权限
+2. Check that the PR is from a branch in the repository (not a fork) / 检查 PR 是否来自存储库中的分支（而非分支）
+3. Verify the workflow is enabled in the repository settings / 验证工作流在存储库设置中已启用
+
+### Comment not updating / 评论未更新
+
+1. The comment updates when a monitored workflow completes / 当受监控的工作流完成时，评论会更新
+2. Check the Actions tab to see if the workflow is running / 检查 Actions 选项卡以查看工作流是否正在运行
+3. Look for errors in the workflow logs / 在工作流日志中查找错误
+
+## Contributing / 贡献
+
+Contributions to improve this workflow are welcome! Please follow the standard contribution process outlined in the CONTRIBUTING.md file.
+
+欢迎改进此工作流的贡献！请遵循 CONTRIBUTING.md 文件中概述的标准贡献流程。

.github/workflows/bsp_buildings.yml

@@ -13,9 +13,6 @@ name: RT-Thread BSP Static Build Check
 # Controls when the action will run. Triggers the workflow on push or pull request
 # events but only for the RT-Thread organization master branch
 on:
-  # Runs at 16:00 UTC (BeiJing 00:00) every day
-  schedule:
-    - cron:  '0 16 * * *'
   push:
     branches:
       - master
@@ -46,6 +43,12 @@ on:
     types:
       - online-pkgs-static-building-trigger-event
   workflow_dispatch:
+    inputs:
+      trigger_type:
+        description: '触发类型'
+        required: false
+        default: 'manual'
+        type: string
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
@@ -177,10 +180,10 @@ jobs:
       - name: Install Xuantie-900-gcc-elf-newlib Tools
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-Xuantie-900-gcc-elf-newlib' && success() }}
         run: |
-          wget -q https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1744884010580/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2-20250410.tar.gz
-          sudo tar -zxvf Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2-20250410.tar.gz -C /opt
-          /opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2/bin/riscv64-unknown-elf-gcc --version
-          echo "RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2/bin" >> $GITHUB_ENV
+          wget -q https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1751370399722/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz
+          sudo tar -zxvf Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz -C /opt
+          /opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin/riscv64-unknown-elf-gcc --version
+          echo "RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin" >> $GITHUB_ENV
 
       - name: Install Xuantie-900-gcc-linux-musl Tools
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-Xuantie-900-gcc-linux-musl' && success() }}
@@ -289,3 +292,16 @@ jobs:
         with:
           name: 00_all_bsp_output_${{ github.sha }}  
           path: output/
+
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: build
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "RT-Thread BSP Static Build Check"
+  #     workflow_status: ${{ needs.build.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/ci_results_comment.yml

@@ -0,0 +1,303 @@
+#
+# Copyright (c) 2025, RT-Thread Development Team
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Change Logs:
+# Date           Author       Notes
+# 2025-10-27     GitHub Copilot  Post CI results to PR comments
+
+name: CI Results Comment
+
+# on:
+#   workflow_run:
+#     workflows:
+#       - "RT-Thread BSP Static Build Check"
+#       - "Static code analysis"
+#       - "Check File Format and License"
+#       - "utest_auto_run"
+#       - "ToolsCI"
+#       - "pkgs_test"
+#     types:
+#       - completed
+
+permissions:
+  pull-requests: write
+  issues: write
+  actions: read
+  checks: read
+
+jobs:
+  comment-ci-results:
+    runs-on: ubuntu-22.04
+    if: github.event.workflow_run.event == 'pull_request' && github.repository_owner == 'RT-Thread'
+    steps:
+      - name: Get PR number
+        id: get-pr
+        uses: actions/github-script@v7
+        with:
+          script: |
+            // Get PR number from workflow_run
+            const prNumber = context.payload.workflow_run.pull_requests[0]?.number;
+            if (!prNumber) {
+              console.log('No PR found in workflow_run');
+              // Fallback: search for PR by branch
+              const pulls = await github.rest.pulls.list({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                state: 'open',
+                head: `${context.repo.owner}:${context.payload.workflow_run.head_branch}`
+              });
+              
+              if (pulls.data.length === 0) {
+                console.log('No open PR found for this branch');
+                return null;
+              }
+              
+              const pr = pulls.data[0];
+              console.log(`Found PR #${pr.number}`);
+              return pr.number;
+            }
+            
+            console.log(`Found PR #${prNumber}`);
+            return prNumber;
+
+      - name: Get workflow run details
+        if: steps.get-pr.outputs.result != 'null'
+        id: workflow-details
+        uses: actions/github-script@v7
+        with:
+          script: |
+            const prNumber = ${{ steps.get-pr.outputs.result }};
+            if (!prNumber) {
+              return { success: false, message: 'No PR found' };
+            }
+
+            // Get all workflow runs for this PR
+            const workflowRuns = await github.rest.actions.listWorkflowRunsForRepo({
+              owner: context.repo.owner,
+              repo: context.repo.repo,
+              event: 'pull_request',
+              per_page: 100
+            });
+
+            // Filter runs for this specific PR
+            const prRuns = workflowRuns.data.workflow_runs.filter(run => {
+              return run.pull_requests.some(pr => pr.number === prNumber);
+            });
+
+            // Get the latest run for each workflow
+            const workflowMap = new Map();
+            for (const run of prRuns) {
+              const existing = workflowMap.get(run.name);
+              if (!existing || new Date(run.created_at) > new Date(existing.created_at)) {
+                workflowMap.set(run.name, run);
+              }
+            }
+
+            // Prepare results summary
+            const results = [];
+            for (const [name, run] of workflowMap) {
+              let status = '🟡';
+              let statusText = 'In Progress';
+              
+              if (run.status === 'completed') {
+                if (run.conclusion === 'success') {
+                  status = '✅';
+                  statusText = 'Success';
+                } else if (run.conclusion === 'failure') {
+                  status = '❌';
+                  statusText = 'Failure';
+                } else if (run.conclusion === 'cancelled') {
+                  status = '⏭️';
+                  statusText = 'Cancelled';
+                } else if (run.conclusion === 'skipped') {
+                  status = '⏭️';
+                  statusText = 'Skipped';
+                }
+              } else if (run.status === 'queued') {
+                status = '🟠';
+                statusText = 'Queued';
+              }
+              
+              results.push({
+                name: name,
+                status: status,
+                statusText: statusText,
+                url: run.html_url,
+                conclusion: run.conclusion,
+                runId: run.id
+              });
+            }
+
+            return { 
+              success: true, 
+              results: results,
+              prNumber: prNumber
+            };
+
+      - name: Get job details
+        if: steps.get-pr.outputs.result != 'null'
+        id: job-details
+        uses: actions/github-script@v7
+        with:
+          script: |
+            const workflowDetails = ${{ steps.workflow-details.outputs.result }};
+            if (!workflowDetails || !workflowDetails.success) {
+              return { jobs: [] };
+            }
+
+            const allJobs = [];
+            
+            for (const result of workflowDetails.results) {
+              try {
+                const jobs = await github.rest.actions.listJobsForWorkflowRun({
+                  owner: context.repo.owner,
+                  repo: context.repo.repo,
+                  run_id: result.runId,
+                  per_page: 100
+                });
+
+                for (const job of jobs.data.jobs) {
+                  let jobStatus = '⌛';
+                  if (job.status === 'completed') {
+                    if (job.conclusion === 'success') {
+                      jobStatus = '✅';
+                    } else if (job.conclusion === 'failure') {
+                      jobStatus = '❌';
+                    } else if (job.conclusion === 'skipped') {
+                      jobStatus = '⏭️';
+                    }
+                  } else if (job.status === 'in_progress') {
+                    jobStatus = '🔄';
+                  } else if (job.status === 'queued') {
+                    jobStatus = '🟠';
+                  }
+
+                  allJobs.push({
+                    workflow: result.name,
+                    name: job.name,
+                    status: jobStatus,
+                    conclusion: job.conclusion || job.status,
+                    url: job.html_url
+                  });
+                }
+              } catch (error) {
+                console.log(`Error getting jobs for workflow ${result.name}: ${error.message}`);
+              }
+            }
+
+            return { jobs: allJobs };
+
+      - name: Post or update comment
+        if: steps.get-pr.outputs.result != 'null'
+        uses: actions/github-script@v7
+        with:
+          script: |
+            const prNumber = ${{ steps.get-pr.outputs.result }};
+            const workflowDetails = ${{ steps.workflow-details.outputs.result }};
+            const jobDetails = ${{ steps.job-details.outputs.result }};
+            
+            if (!workflowDetails || !workflowDetails.success) {
+              console.log('No workflow details available');
+              return;
+            }
+
+            // Prepare comment body
+            const now = new Date();
+            const timestamp = now.toISOString();
+            const results = workflowDetails.results;
+            const jobs = jobDetails.jobs || [];
+
+            let commentBody = '<!-- CI Results Comment -->\n';
+            commentBody += '## 🤖 CI Test Results\n\n';
+            commentBody += `**Last Updated:** ${timestamp}\n\n`;
+            commentBody += '### Test Spec & Results:\n\n';
+            commentBody += '✅ Success | ❌ Failure | 🟠 Queued | 🟡 Progress | ⏭️ Skipped | ⚠️ Quarantine\n\n';
+            
+            // Group jobs by workflow
+            const jobsByWorkflow = new Map();
+            for (const job of jobs) {
+              if (!jobsByWorkflow.has(job.workflow)) {
+                jobsByWorkflow.set(job.workflow, []);
+              }
+              jobsByWorkflow.get(job.workflow).push(job);
+            }
+
+            // Calculate overall statistics
+            let totalSuccess = 0;
+            let totalFailure = 0;
+            let totalQueued = 0;
+            let totalProgress = 0;
+            let totalSkipped = 0;
+
+            for (const result of results) {
+              if (result.conclusion === 'success') totalSuccess++;
+              else if (result.conclusion === 'failure') totalFailure++;
+              else if (result.statusText === 'Queued') totalQueued++;
+              else if (result.statusText === 'In Progress') totalProgress++;
+              else if (result.conclusion === 'skipped' || result.conclusion === 'cancelled') totalSkipped++;
+            }
+
+            // Summary line
+            commentBody += '#### Overall Summary\n\n';
+            commentBody += `- ✅ **Success:** ${totalSuccess}\n`;
+            commentBody += `- ❌ **Failure:** ${totalFailure}\n`;
+            commentBody += `- 🟠 **Queued:** ${totalQueued}\n`;
+            commentBody += `- 🟡 **In Progress:** ${totalProgress}\n`;
+            commentBody += `- ⏭️ **Skipped:** ${totalSkipped}\n\n`;
+
+            commentBody += '---\n\n';
+            commentBody += '### Detailed Results\n\n';
+
+            // Build detailed results
+            for (const result of results) {
+              commentBody += `<details>\n`;
+              commentBody += `<summary>${result.status} <strong>${result.name}</strong> - ${result.statusText}</summary>\n\n`;
+              commentBody += `**Workflow:** [${result.name}](${result.url})\n\n`;
+              
+              // Show jobs for this workflow
+              const workflowJobs = jobsByWorkflow.get(result.name) || [];
+              if (workflowJobs.length > 0) {
+                commentBody += '**Jobs:**\n\n';
+                for (const job of workflowJobs) {
+                  commentBody += `- ${job.status} [${job.name}](${job.url})\n`;
+                }
+              }
+              commentBody += '\n</details>\n\n';
+            }
+
+            commentBody += '\n---\n';
+            commentBody += '*🤖 This comment is automatically generated and updated by the CI system.*\n';
+
+            // Check if comment already exists
+            const comments = await github.rest.issues.listComments({
+              owner: context.repo.owner,
+              repo: context.repo.repo,
+              issue_number: prNumber
+            });
+
+            const existingComment = comments.data.find(comment => 
+              comment.user.login === 'github-actions[bot]' && 
+              comment.body.includes('<!-- CI Results Comment -->')
+            );
+
+            if (existingComment) {
+              // Update existing comment
+              await github.rest.issues.updateComment({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                comment_id: existingComment.id,
+                body: commentBody
+              });
+              console.log(`Updated comment ${existingComment.id} on PR #${prNumber}`);
+            } else {
+              // Create new comment
+              await github.rest.issues.createComment({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                issue_number: prNumber,
+                body: commentBody
+              });
+              console.log(`Created new comment on PR #${prNumber}`);
+            }

.github/workflows/format_check.yml

@@ -30,3 +30,16 @@ jobs:
         run: |
           pip install click chardet PyYaml
           python tools/ci/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master'
+
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: scancode_job
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "Check File Format and License"
+  #     workflow_status: ${{ needs.scancode_job.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/post_ci_status.yml

@@ -0,0 +1,110 @@
+#
+# Copyright (c) 2025, RT-Thread Development Team
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Change Logs:
+# Date           Author       Notes
+# 2025-10-27     GitHub Copilot  Reusable workflow to post CI status
+
+name: Post CI Status Comment
+
+# on:
+#   workflow_call:
+#     inputs:
+#       workflow_name:
+#         description: 'Name of the workflow'
+#         required: true
+#         type: string
+#       workflow_status:
+#         description: 'Status of the workflow (success/failure)'
+#         required: true
+#         type: string
+#       pr_number:
+#         description: 'Pull request number'
+#         required: true
+#         type: number
+
+permissions:
+  pull-requests: write
+  issues: write
+
+jobs:
+  post-comment:
+    runs-on: ubuntu-22.04
+    if: github.repository_owner == 'RT-Thread'
+    steps:
+      - name: Post or update CI status comment
+        uses: actions/github-script@v7
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          script: |
+            const prNumber = ${{ inputs.pr_number }};
+            const workflowName = '${{ inputs.workflow_name }}';
+            const workflowStatus = '${{ inputs.workflow_status }}';
+            
+            // Status emoji mapping
+            const statusEmoji = workflowStatus === 'success' ? '✅' : '❌';
+            const timestamp = new Date().toISOString();
+            
+            // Try to find existing comment
+            const comments = await github.rest.issues.listComments({
+              owner: context.repo.owner,
+              repo: context.repo.repo,
+              issue_number: prNumber
+            });
+            
+            const botComment = comments.data.find(comment => 
+              comment.user.login === 'github-actions[bot]' && 
+              comment.body.includes('<!-- CI Status Comment -->')
+            );
+            
+            // Get all workflow runs for this PR to build comprehensive status
+            let allStatuses = {};
+            
+            if (botComment) {
+              // Parse existing statuses from comment
+              const statusRegex = /- (✅|❌|🟡) \*\*(.+?)\*\*/g;
+              let match;
+              while ((match = statusRegex.exec(botComment.body)) !== null) {
+                allStatuses[match[2]] = match[1];
+              }
+            }
+            
+            // Update current workflow status
+            allStatuses[workflowName] = statusEmoji;
+            
+            // Build comment body
+            let commentBody = '<!-- CI Status Comment -->\n';
+            commentBody += '## 🤖 CI Test Results\n\n';
+            commentBody += `**Last Updated:** ${timestamp}\n\n`;
+            commentBody += '### Workflow Status:\n\n';
+            
+            for (const [name, emoji] of Object.entries(allStatuses)) {
+              commentBody += `- ${emoji} **${name}**\n`;
+            }
+            
+            commentBody += '\n---\n';
+            commentBody += '✅ Success | ❌ Failure | 🟡 In Progress\n\n';
+            commentBody += '*This comment is automatically updated as CI workflows complete.*\n';
+            
+            if (botComment) {
+              // Update existing comment
+              await github.rest.issues.updateComment({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                comment_id: botComment.id,
+                body: commentBody
+              });
+              console.log(`Updated comment ${botComment.id} on PR #${prNumber}`);
+            } else {
+              // Create new comment
+              await github.rest.issues.createComment({
+                owner: context.repo.owner,
+                repo: context.repo.repo,
+                issue_number: prNumber,
+                body: commentBody
+              });
+              console.log(`Created new comment on PR #${prNumber}`);
+            }

.github/workflows/scheduled-ci-trigger.yml

@@ -0,0 +1,200 @@
+name: Weekly CI Scheduler
+
+on:
+  # Runs at 08:00 Beijing time every day
+  schedule:
+    - cron: '0 0 * * *'
+  workflow_dispatch:
+    inputs:
+      debug:
+        description: 'Debug mode'
+        required: false
+        default: 'false'
+
+env:
+  TARGET_WORKFLOWS: '["RT-Thread BSP Static Build Check", "utest_auto_run"]'
+  DISCUSSION_CATEGORY: "Github Action Exception Reports"
+
+jobs:
+  trigger-and-monitor:
+    name: Trigger and Monitor CIs
+    runs-on: ubuntu-latest
+    outputs:
+      failed_workflows: ${{ steps.collect-results.outputs.failed_workflows }}
+      total_workflows: ${{ steps.collect-results.outputs.total_workflows }}
+      has_results: ${{ steps.collect-results.outputs.has_results }}
+    
+    steps:
+    - name: Checkout repository
+      uses: actions/checkout@v4
+
+    - name: Install Python dependencies
+      run: |
+        python -m pip install --upgrade pip
+        pip install requests
+
+    - name: Record start time
+      id: start-time
+      run: |
+        echo "start_time=$(date -u +'%Y-%m-%dT%H:%M:%SZ')" >> $GITHUB_OUTPUT
+        echo "Start time: $(date -u +'%Y-%m-%dT%H:%M:%SZ')"
+
+    - name: Trigger CI workflows directly
+      id: trigger-ci
+      run: |
+        python tools/ci/scheduled-ci-trigger/trigger_workflows_direct.py
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        TARGET_WORKFLOWS: ${{ env.TARGET_WORKFLOWS }}
+
+    - name: Wait for workflows to appear
+      id: wait-for-workflows
+      run: |
+        echo "Waiting for workflows to appear in API..."
+        python tools/ci/scheduled-ci-trigger/wait_for_workflows.py "${{ steps.start-time.outputs.start_time }}"
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        TARGET_WORKFLOWS: ${{ env.TARGET_WORKFLOWS }}
+
+    - name: Monitor CI workflows
+      id: monitor-ci
+      run: |
+        python tools/ci/scheduled-ci-trigger/monitor_workflows.py "${{ steps.start-time.outputs.start_time }}"
+      env:
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        TARGET_WORKFLOWS: ${{ env.TARGET_WORKFLOWS }}
+
+    - name: Collect monitoring results
+      id: collect-results
+      run: |
+        echo "Checking for monitoring results..."
+        if [ -f "monitoring_results.json" ]; then
+          echo "monitoring_results.json found"
+          FAILED_COUNT=$(python -c "import json; data=json.load(open('monitoring_results.json')); print(len([w for w in data if w.get('conclusion') == 'failure']))")
+          TOTAL_COUNT=$(python -c "import json; data=json.load(open('monitoring_results.json')); print(len(data))")
+          echo "failed_workflows=$FAILED_COUNT" >> $GITHUB_OUTPUT
+          echo "total_workflows=$TOTAL_COUNT" >> $GITHUB_OUTPUT
+          echo "has_results=true" >> $GITHUB_OUTPUT
+          echo "Results: $FAILED_COUNT failed out of $TOTAL_COUNT total"
+        else
+          echo "monitoring_results.json not found"
+          echo "failed_workflows=0" >> $GITHUB_OUTPUT
+          echo "total_workflows=0" >> $GITHUB_OUTPUT
+          echo "has_results=false" >> $GITHUB_OUTPUT
+        fi
+
+    - name: Generate detailed report
+      if: steps.collect-results.outputs.has_results == 'true' && steps.collect-results.outputs.failed_workflows != '0'
+      id: generate-report
+      run: |
+        echo "Generating detailed report..."
+        python tools/ci/scheduled-ci-trigger/generate_report.py
+        echo "Report generation completed"
+
+    - name: Upload report artifact
+      if: steps.collect-results.outputs.has_results == 'true' && steps.collect-results.outputs.failed_workflows != '0'
+      uses: actions/upload-artifact@v4
+      with:
+        name: ci-failure-report
+        path: |
+          monitoring_results.json
+          failure_details.md
+        retention-days: 7
+
+  create-discussion:
+    name: Create Discussion Report
+    needs: trigger-and-monitor
+    if: needs.trigger-and-monitor.outputs.has_results == 'true' && needs.trigger-and-monitor.outputs.failed_workflows != '0'
+    runs-on: ubuntu-latest
+    
+    steps:
+    - name: Checkout repository
+      uses: actions/checkout@v4
+
+    - name: Download report artifact
+      uses: actions/download-artifact@v4
+      with:
+        name: ci-failure-report
+
+    - name: Create Discussion
+      uses: actions/github-script@v6
+      env:
+        DISCUSSION_CATEGORY: ${{ env.DISCUSSION_CATEGORY }}
+      with:
+        script: |
+          const fs = require('fs');
+          
+          const reportPath = './failure_details.md';
+          
+          let reportContent = fs.readFileSync(reportPath, 'utf8');
+          
+          // 提取日期从第一行: # YYYYMMDD_ci_integration-failed-report
+          const lines = reportContent.split('\n');
+          const firstLine = lines[0].trim();
+          const dateMatch = firstLine.match(/# (\d{8})_ci_integration-failed-report/);
+          
+          if (!dateMatch) {
+            console.error('Failed to extract date from first line:', firstLine);
+            process.exit(1);
+          }
+          
+          const dateString = dateMatch[1];
+          const discussionTitle = `${dateString}_ci_integration-failed-report`;
+          
+          // === 关键修复：移除第一行（用于提取的隐藏行） ===
+          reportContent = lines.slice(1).join('\n').trim();
+          
+          // 获取仓库ID和分类ID
+          const getRepoQuery = `
+            query($owner: String!, $repo: String!) {
+              repository(owner: $owner, name: $repo) {
+                id
+                discussionCategories(first: 20) {
+                  nodes {
+                    id
+                    name
+                  }
+                }
+              }
+            }
+          `;
+          
+          const repoData = await github.graphql(getRepoQuery, {
+            owner: context.repo.owner,
+            repo: context.repo.repo
+          });
+          
+          const repositoryId = repoData.repository.id;
+          const categories = repoData.repository.discussionCategories.nodes;
+          const targetCategory = categories.find(cat => cat.name === process.env.DISCUSSION_CATEGORY);
+          
+          if (!targetCategory) {
+            console.error('Category not found:', process.env.DISCUSSION_CATEGORY);
+            process.exit(1);
+          }
+          
+          const createDiscussionMutation = `
+            mutation($repositoryId: ID!, $categoryId: ID!, $title: String!, $body: String!) {
+              createDiscussion(input: {
+                repositoryId: $repositoryId
+                categoryId: $categoryId
+                title: $title
+                body: $body
+              }) {
+                discussion {
+                  id
+                  title
+                  url
+                }
+              }
+            }
+          `;
+          
+          const result = await github.graphql(createDiscussionMutation, {
+            repositoryId: repositoryId,
+            categoryId: targetCategory.id,
+            title: discussionTitle,
+            body: reportContent  // 使用清理后的内容（无第一行）
+          });
+          
+          console.log('Discussion created successfully:', result.createDiscussion.discussion.url);

.github/workflows/static_code_analysis.yml

@@ -55,3 +55,16 @@ jobs:
           cppcheck --version
           cd ..
           python tools/ci/cpp_check.py check
+
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: scancode_job
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "Static code analysis"
+  #     workflow_status: ${{ needs.scancode_job.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

.github/workflows/utest_auto_run.yml

@@ -18,6 +18,13 @@ on:
       - documentation/**
       - '**/README.md'
       - '**/README_zh.md'
+  workflow_dispatch:
+    inputs:
+      trigger_type:
+        description: '触发类型'
+        required: false
+        default: 'manual'
+        type: string
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
@@ -298,3 +305,15 @@ jobs:
               break
             fi
           done
+  # # Post CI status to PR comment
+  # post-ci-status:
+  #   needs: test
+  #   if: always() && github.event_name == 'pull_request' && github.repository_owner == 'RT-Thread'
+  #   uses: ./.github/workflows/post_ci_status.yml
+  #   with:
+  #     workflow_name: "utest_auto_run"
+  #     workflow_status: ${{ needs.test.result }}
+  #     pr_number: ${{ github.event.pull_request.number }}
+  #   permissions:
+  #     pull-requests: write
+  #     issues: write

ChangeLog.md

@@ -1,3 +1,184 @@
+# RT-Thread v5.2.2 Released
+
+Change Log Since v5.2.1 Release.
+
+## Kernel
+
+* Fix scheduling exception caused by interrupt preemption in rt_schedule.[(#10715)](https://github.com/RT-Thread/rt-thread/pull/10715)
+* Fix the legacy issue related to the length of the object name version.[(#10537)](https://github.com/RT-Thread/rt-thread/pull/10537)
+* Fixed buffer overflow vulnerability in object.[(#10523)](https://github.com/RT-Thread/rt-thread/pull/10523)
+* Add up scheduler critical switch flag.[(#10581)](https://github.com/RT-Thread/rt-thread/pull/10581)
+* Update the default value of RT_NAME_MAX to 12.[(#10839)](https://github.com/RT-Thread/rt-thread/pull/10839)
+* Feat the rt_scheduler lock nest uses atomic operations.[(#10621)](https://github.com/RT-Thread/rt-thread/pull/10621)
+
+## Components
+
+* **Drivers**
+  * **Serial:** 
+    * serial_v1
+      * Fix correct data loss logic when RX ring buffer is full.
+    * serial_v2
+      * Fix the bug of RX flush under DMA.
+      * Add serial V2 buffer configuration via Kconfig.
+      * Feat optimize serial v2. [(#10603)](https://github.com/RT-Thread/rt-thread/pull/10603)
+      * Feat modify the default configuration of the RT_SERIAL_CONFIG_DEFAULT structure to support parameters in the absence of DMA configuration.
+  * **RTC:** 
+    * Add the alarm using local time for calculation.
+  * **CAN:** 
+    * Fixed the issue where the thread calling CAN int TX was suspended when CAN at the bottom layer failed to work.
+    * Feat: Implement non-blocking send mechanism and enhance CAN driver functionality.
+  * **SPI:** 
+    * Add SPI device detach function.[(#10733)](https://github.com/RT-Thread/rt-thread/pull/10733)
+    * Update and fix up the SPI.
+  * **ADC:** 
+    * Fixed cppcheck error.
+    * Remove build warnings.
+  * **ktime:**
+    * Remove unused rt_ktime_hrtimer_getcnt for hrtimer.
+  * **wlan:**
+    * Update SECURITY_UNKNOWN value.
+* **LWP**
+  * Fix potential signal handler infinite loop for riscv.
+  * Feat: Restore TP register in arch_thread_signal_enter to fix user-mode memory access.
+* **Libc**
+  * Add comments for some pthread functions.
+  * pthreads: Fix pthread_cond_timedwait lacks timeout wakeup.
+  * ensure compatibility with newlib <3.4.0 by handling removed __sdidinit. [(#10791)](https://github.com/RT-Thread/rt-thread/pull/10791)
+* **DFS**
+  * **DFS v2**:
+    * Fix bugs for function _get_parent_path(). [(#10539)](https://github.com/RT-Thread/rt-thread/pull/10539)
+* **Net**
+  * **SAL/Socket:** 
+    * Fixed CI compilation failure in sal/src/sal_socket.c.
+    * Fix memory leak when sal_socket failed.
+    * improve the error return of sal.
+  * **Netdev:**
+    * Fixed compilation errors when enabling IPv6 and IPv4 dual-stack support.
+    * Fixed netdev_unregister missing correct return value. [(#10693)](https://github.com/RT-Thread/rt-thread/pull/10693)
+    * Expose netdev_set_dns and netdev_set_if. [(#10128)](https://github.com/RT-Thread/rt-thread/pull/10128)
+  * **AT:**
+    * at_client add deInit port. [(#10598)](https://github.com/RT-Thread/rt-thread/pull/10598)
+* **Finsh:**
+
+  * Fixed clear out the useless copy operations. [(#10699)](https://github.com/RT-Thread/rt-thread/pull/10699)
+  * Feat add support for the Home, Insert, Delete and End keys, and improve input mode processing.[(#10595)](https://github.com/RT-Thread/rt-thread/pull/10595)
+  * Feat: Add new features (delete by word, switch cursor, etc.).
+* **USB:**
+  * Update (cherryusb): update to v1.5.1.
+  * Fixed several issues related to cherryusb.[(#10844)](https://github.com/RT-Thread/rt-thread/pull/10844)
+* **Ulog:**
+  * Fix:filter should not be associated with ULOG_USING_COLOR and ULOG_USING_SYSLOG configurations.
+* **IPC:**
+  * Pass rt_tick_t for RT_TIMER_CTRL_SET_TIME and RT_TIMER_CTRL_GET_TIME.[(#10717)](https://github.com/RT-Thread/rt-thread/pull/10717)
+
+## DM
+
+* NVME: fix up the QUEUE alloc error no check.
+* Thermal: Fix up the C99, 6.8.1 Labeled statements p4; Fix up the PWM-FAN remove handle data ptr.
+* PCI: Add SoC PCI Kconfig import; Multiple PCI-related fixes; Fix and optimize interrupt-related issues.
+* WDT: Support related to Intel 6300ESB/Synopsys Watchdog, etc.
+
+## Libcpu
+
+* **AArch64:** 
+  * Fix up MMU and linker warning. 
+  * Fix rt_aspace_init error when KERNEL_VADDR_START >= 0x80000000.
+  * Add the configuration of libcpu/aarch64 KERNEL ASPACE START.
+  * Update Hypercall API.
+  * Remove unused rt_hw_set_gtimer_frq.
+* **Cortex-M33:**
+  * Fix the M33 assembly syntax errors and fix the compilation error of BSP.
+  * Added HardFault_Handler to save floating point registers.
+* **Cortex-M4:**
+  * Fixed compilation error. 
+  * Added HardFault_Handler to save floating point registers.
+
+* **Cortex-M3:**
+  * The parameter passed to the unified rt_exception_hook is exception_stack. [(#10619)](https://github.com/RT-Thread/rt-thread/pull/10619)
+* **RISC-V:** 
+  * Fix type mismatch of `_query`.
+  * Fix the support for RV32E. RV32E does not support the s2 register. Modify it to the s1 register.
+  * Use volatile RW for claim and complete.
+  * Add spaces to fix `Wliteral-suffix`.
+  * Add comment for the round down of symb_pc.
+  * Remove `rt_hw_cpu_id` in `cpuport.h` to fix error.
+
+## Tools
+
+* Add support for package.json, refactor BuildPackage function to handle new format.
+* Add documents for tools script; Add NG for tools. [(#10572)](https://github.com/RT-Thread/rt-thread/pull/10572)
+* Add workspace generation for RT-Thread root directory.
+* Add vsc_workspace target in scons.
+* Add DTC (Devicetree Compiler) tools.
+* Add clang-format formatting script for CI. 
+* Optimize the file opening method.
+* Clang format ignore migration.
+* Improve[clang-format]: optimize the formatting logic for RT-Thread coding standard.
+
+## Action
+
+* Fixed CI: ARDUINO_ADAFRUIT_SENSORLAB compilation failure issue.
+* Fixed CI compilation failure in sal/src/sal_socket.c.[(#10854)](https://github.com/RT-Thread/rt-thread/pull/10854)
+* Merge same tag with different paths, remove Path display from CI comment.
+* Add Copilot review title keywords.
+* Add concurrency control to GitHub Actions. [(#10761)](https://github.com/RT-Thread/rt-thread/pull/10761)
+* integrate utest run ci. [(#10748)](https://github.com/RT-Thread/rt-thread/pull/10748)
+* Improve the comment instructions for the PR format bot.[(#10747)](https://github.com/RT-Thread/rt-thread/pull/10747)
+
+## Documents
+
+* **Doxygen:**
+  * Fix some document issues.
+  * Update naming rule for utest-case.
+  * Update doc for env to latest.
+  * Update some document content.
+  * Group name all in lowercase. [(#10530)](https://github.com/RT-Thread/rt-thread/pull/10530)
+  * Grouping and page optimization related to device driver.
+  * use layout to control the HTML display.
+  * Add doxygen comments for scheduler. [(#10366)](https://github.com/RT-Thread/rt-thread/pull/10366) and lwp
+  * update doxygen version to v1.9.8 .
+
+## Utest
+
+* Add netdev/lwip/filesystem/memory pool/SAL/system performance API test case.
+* Support autocomplete of utest cases for `utest_run`. [(#10701)](https://github.com/RT-Thread/rt-thread/pull/10701)
+* Feat:reorganize utest menu.
+* Feat:rename files and update naming according to new rule.
+* Feat:reorganize utest framework structure (initial version).
+* Feat:unify config name. [(#10808)](https://github.com/RT-Thread/rt-thread/pull/10808)
+* Feat:integrate test cases into utest framework. [(#10665)](https://github.com/RT-Thread/rt-thread/pull/10665)
+* Move driver-related test cases under `drivers`.
+* Move and enhance C++ test cases.
+
+## BSP
+
+* Some driver issues have been resolved and some driver support has been added.
+
+* **Added/Updated BSPs:**
+
+  * **xuantie：**
+    * E901
+
+  * **Renesas:** 
+    * ek-ra6e2
+    * ek-ra4e2
+    * ek-ra2a1
+    * ek-ra2e2
+    * ek-ra4m1
+  * **GD32:** 
+    * gd32h759i-eval
+    * gd32470i-eval
+    * gd32e230-lckfb
+  * **NXP:** 
+    * MCX E247
+    * FRDM-MCXE247
+    * FRDM-MCXA346
+  * **HPMicro:** 
+    * hpm6p00evk 
+    * hpm5e00evk
+  * **Phytium**
+  * **Raspberry RP2350**
+
 # RT-Thread v5.2.1 Released
 
 Change Log Since v5.2.0 Release

MAINTAINERS

@@ -147,6 +147,10 @@ tag: bsp_stm32f429-atk-apollo
 path: bsp/stm32/stm32f429-atk-apollo
 owners: lizhen9880(lizhen9880)<lizhen9880@126.com>
 
+tag: bsp_stm32f407-micu
+path: bsp/stm32/stm32f407-micu
+owners: DaiLingxiang(Dailingxiang1)<3070269033@qq.com>
+
 tag: bsp_stm32h723-st-nucleo
 path: bsp/stm32/stm32h723-st-nucleo
 owners: 下里巴人(hywing)<hywing.sir@qq.com>

bsp/Vango/.clang-format-ignore

@@ -0,0 +1,9 @@
+
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+# 从 .ignore_format.yml 迁移的规则
+
+/v85xx*/Libraries/CMSIS/
+/v85xx*/Libraries/VangoV85xx*_standard_peripheral/

bsp/gd32/arm/gd32527I-eval/board/Kconfig

@@ -34,55 +34,63 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART0_RX_USING_DMA
                 bool "Enable UART0 RX DMA"
-                depends on BSP_USING_UART0
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART0_TX_USING_DMA
                 bool "Enable UART0 TX DMA"
-                depends on BSP_USING_UART0
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART0_DMA_PING_BUFSIZE
+                int "Set UART0 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART0 && RT_USING_SERIAL_V2 && BSP_UART0_RX_USING_DMA
+                default 64
+
             config BSP_UART0_RX_BUFSIZE
                 int "Set UART0 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART0_TX_BUFSIZE
                 int "Set UART0 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART0 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART1
                 bool "Enable UART1"
-                default n
+                default y
 
             config BSP_UART1_RX_USING_DMA
                 bool "Enable UART1 RX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART1_TX_USING_DMA
                 bool "Enable UART1 TX DMA"
-                depends on BSP_USING_UART1
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART1_DMA_PING_BUFSIZE
+                int "Set UART1 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART1 && RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA
+                default 64
+
             config BSP_UART1_RX_BUFSIZE
                 int "Set UART1 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART1_TX_BUFSIZE
                 int "Set UART1 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART1 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART2
                 bool "Enable UART2"
@@ -90,27 +98,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART2_RX_USING_DMA
                 bool "Enable UART2 RX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART2_TX_USING_DMA
                 bool "Enable UART2 TX DMA"
-                depends on BSP_USING_UART2
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART2_DMA_PING_BUFSIZE
+                int "Set UART2 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART2 && RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA
+                default 64
+
             config BSP_UART2_RX_BUFSIZE
                 int "Set UART2 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART2_TX_BUFSIZE
                 int "Set UART2 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART2 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART3
                 bool "Enable UART3"
@@ -118,27 +130,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART3_RX_USING_DMA
                 bool "Enable UART3 RX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART3_TX_USING_DMA
                 bool "Enable UART3 TX DMA"
-                depends on BSP_USING_UART3
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART3_DMA_PING_BUFSIZE
+                int "Set UART3 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART3 && RT_USING_SERIAL_V2 && BSP_UART3_RX_USING_DMA
+                default 64
+
             config BSP_UART3_RX_BUFSIZE
                 int "Set UART3 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART3_TX_BUFSIZE
                 int "Set UART3 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART3 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART4
                 bool "Enable UART4"
@@ -146,27 +162,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART4_RX_USING_DMA
                 bool "Enable UART4 RX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART4_TX_USING_DMA
                 bool "Enable UART4 TX DMA"
-                depends on BSP_USING_UART4
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART4_DMA_PING_BUFSIZE
+                int "Set UART4 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART4 && RT_USING_SERIAL_V2 && BSP_UART4_RX_USING_DMA
+                default 64
+
             config BSP_UART4_RX_BUFSIZE
                 int "Set UART4 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART4_TX_BUFSIZE
                 int "Set UART4 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART4 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART5
                 bool "Enable UART5"
@@ -174,27 +194,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART5_RX_USING_DMA
                 bool "Enable UART5 RX DMA"
-                depends on BSP_USING_UART5
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART5_TX_USING_DMA
                 bool "Enable UART5 TX DMA"
-                depends on BSP_USING_UART5
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART5_DMA_PING_BUFSIZE
+                int "Set UART5 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART5 && RT_USING_SERIAL_V2 && BSP_UART5_RX_USING_DMA
+                default 64
+
             config BSP_UART5_RX_BUFSIZE
                 int "Set UART5 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART5_TX_BUFSIZE
                 int "Set UART5 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART5 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
             config BSP_USING_UART6
                 bool "Enable UART6"
@@ -202,27 +226,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART6_RX_USING_DMA
                 bool "Enable UART6 RX DMA"
-                depends on BSP_USING_UART6
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART6_TX_USING_DMA
                 bool "Enable UART6 TX DMA"
-                depends on BSP_USING_UART6
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART6_DMA_PING_BUFSIZE
+                int "Set UART6 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART6 && RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA
+                default 64
+
             config BSP_UART6_RX_BUFSIZE
                 int "Set UART6 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART6_TX_BUFSIZE
                 int "Set UART6 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART6 && RT_USING_SERIAL_V2
-                default 0
+                default 128
 
                 config BSP_USING_UART7
                 bool "Enable UART7"
@@ -230,27 +258,31 @@ menu "On-chip Peripheral Drivers"
 
             config BSP_UART7_RX_USING_DMA
                 bool "Enable UART7 RX DMA"
-                depends on BSP_USING_UART7
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
             config BSP_UART7_TX_USING_DMA
                 bool "Enable UART7 TX DMA"
-                depends on BSP_USING_UART7
-                select RT_SERIAL_USING_DMA
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && RT_SERIAL_USING_DMA
                 default n
 
+            config BSP_UART7_DMA_PING_BUFSIZE
+                int "Set UART7 RX DMA ping-pong buffer size"
+                range 16 65535
+                depends on BSP_USING_UART7 && RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA
+                default 64
+
             config BSP_UART7_RX_BUFSIZE
                 int "Set UART7 RX buffer size"
                 range 64 65535
                 depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
-                default 64
+                default 128
 
             config BSP_UART7_TX_BUFSIZE
                 int "Set UART7 TX buffer size"
                 range 0 65535
                 depends on BSP_USING_UART7 && RT_USING_SERIAL_V2
-                default 0
+                default 128
         endif
 
     menuconfig BSP_USING_SPI

bsp/gd32/arm/libraries/gd32_drivers/drv_usart_v2.c

@@ -263,7 +263,6 @@ static void dma_recv_isr (struct rt_serial_device *serial)
     RT_ASSERT(serial != RT_NULL);
     uart = rt_container_of(serial, struct gd32_uart, serial);
 
-    recv_len = 0;
     level = rt_hw_interrupt_disable();
     #if defined SOC_SERIES_GD32E23x
     counter = dma_transfer_number_get(uart->dma.rx.channel);
@@ -297,21 +296,14 @@ static void usart_isr (struct rt_serial_device *serial)
 
     if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_RBNE) != RESET)
     {
-        struct rt_serial_rx_fifo *rx_fifo;
-        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
-        RT_ASSERT(rx_fifo != RT_NULL);
-
-        char chr = usart_data_receive(uart->periph);
-        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
+        rt_uint8_t chr = usart_data_receive(uart->periph);
+        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, (void *)&chr);
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-
-        /* Clear RXNE interrupt flag */
-        usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_RBNE);
     }
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TBE) != RESET)
     {
         rt_uint8_t put_char = 0;
-        if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
+        if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, (void *)&put_char) == RT_EOK)
         {
             usart_data_transmit(uart->periph, put_char);
         }
@@ -320,7 +312,6 @@ static void usart_isr (struct rt_serial_device *serial)
             usart_interrupt_disable(uart->periph, USART_INT_TBE);
             usart_interrupt_enable(uart->periph, USART_INT_TC);
         }
-        usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_TBE);
     }
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_TC) != RESET)
     {
@@ -334,10 +325,9 @@ static void usart_isr (struct rt_serial_device *serial)
 #ifdef RT_SERIAL_USING_DMA
     else if (usart_interrupt_flag_get(uart->periph, USART_INT_FLAG_IDLE) != RESET)
     {
-        volatile uint8_t data = (uint8_t)usart_data_receive(uart->periph);
-
+        volatile uint8_t idle_clear_dummy = (uint8_t)usart_data_receive(uart->periph);
+        RT_UNUSED(idle_clear_dummy);
         dma_recv_isr(serial);
-
         usart_interrupt_flag_clear(uart->periph, USART_INT_FLAG_IDLE);
     }
 #endif
@@ -595,8 +585,8 @@ void UART7_IRQHandler (void)
 }
 
 #endif /* BSP_USING_UART7 */
-#if define SOC_SERIES_GD32E23x
-#if define BSP_UART0_RX_USING_DMA || define BSP_UART0_TX_USING_DMA
+#if defined SOC_SERIES_GD32E23x
+#if defined BSP_UART0_RX_USING_DMA || defined BSP_UART0_TX_USING_DMA
 void DMA_Channel1_2_IRQHandler(void)
 {
     /* enter interrupt */
@@ -906,6 +896,9 @@ static void _uart_dma_receive (struct gd32_uart *uart, rt_uint8_t *buffer, rt_ui
     dma_interrupt_enable(uart->dma.rx.channel, DMA_CHXCTL_HTFIE);
     dma_interrupt_enable(uart->dma.rx.channel, DMA_CHXCTL_FTFIE);
 
+    /* enable circular mode */
+    dma_circulation_enable(uart->dma.rx.channel);
+
     /* enable dma channel */
     dma_channel_enable(uart->dma.rx.channel);
 
@@ -953,7 +946,11 @@ static void _uart_dma_receive (struct gd32_uart *uart, rt_uint8_t *buffer, rt_ui
     usart_interrupt_enable(uart->periph, USART_INT_IDLE);
 
     /* enable dma receive */
+#if defined SOC_SERIES_GD32F5xx
+    usart_dma_receive_config(uart->periph, USART_DENR_ENABLE);
+#else
     usart_dma_receive_config(uart->periph, USART_RECEIVE_DMA_ENABLE);
+#endif
     #endif
 }
 
@@ -972,7 +969,11 @@ static void _uart_dma_transmit (struct gd32_uart *uart, rt_uint8_t *buffer, rt_u
     DMA_CHCNT(uart->dma.tx.periph, uart->dma.tx.channel) = size;
 
     /* enable dma transmit */
+#if defined SOC_SERIES_GD32F5xx
+    usart_dma_transmit_config(uart->periph, USART_DENT_ENABLE);
+#else
     usart_dma_transmit_config(uart->periph, USART_TRANSMIT_DMA_ENABLE);
+#endif
 
     /* enable dma channel */
     dma_channel_enable(uart->dma.tx.periph, uart->dma.tx.channel);
@@ -1057,7 +1058,7 @@ static void gd32_dma_config (struct rt_serial_device *serial, rt_ubase_t flag)
     if (flag == RT_DEVICE_FLAG_DMA_RX)
     {
         rt_uint8_t *ptr = NULL;
-        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
+        rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, (void *)&ptr);
 
         /* start dma transfer */
         _uart_dma_receive(uart, ptr, serial->config.dma_ping_bufsz);

bsp/gd32/arm/libraries/gd32_drivers/drv_usart_v2.h

@@ -32,12 +32,12 @@ struct gd32_uart
     rcu_periph_enum tx_gpio_clk;
     rcu_periph_enum rx_gpio_clk;
     uint32_t tx_port;
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32F5xx
     uint16_t tx_af;
 #endif
     uint16_t tx_pin;
     uint32_t rx_port;
-#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x
+#if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32F5xx
     uint16_t rx_af;
 #endif
     uint16_t rx_pin;

bsp/k230/.ci/attachconfig/ci.attachconfig.yml

@@ -0,0 +1,48 @@
+scons.args: &scons
+    scons_arg:
+      - '--strict'
+devices.i2c:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_I2C=y
+      - CONFIG_BSP_USING_I2C=y
+      - CONFIG_BSP_USING_I2C0=y
+devices.adc:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_ADC=y
+      - CONFIG_BSP_USING_ADC=y
+devices.hwtimer:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_HWTIMER=y
+      - CONFIG_BSP_USING_TIMERS=y
+      - CONFIG_BSP_USING_TIMER0=y
+devices.pdma:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_PDMA=y
+      - CONFIG_BSP_USING_PDMA=y
+      - CONFIG_BSP_USING_PDMA_CHANNEL0=y
+devices.pwm:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_PWM=y
+      - CONFIG_BSP_USING_PWM=y
+      - CONFIG_BSP_USING_PWM0=y
+devices.rtc:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_RTC=y
+      - CONFIG_BSP_USING_RTC=y
+devices.ts:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_TS=y
+      - CONFIG_BSP_USING_TS=y
+devices.wdt:
+    <<: *scons
+    kconfig:
+      - CONFIG_RT_USING_WDT=y
+      - CONFIG_BSP_USING_WDT=y
+      - CONFIG_BSP_USING_WDT0=y

bsp/k230/.config

@@ -227,6 +227,7 @@ CONFIG_FINSH_THREAD_STACK_SIZE=8192
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
 # CONFIG_FINSH_USING_WORD_OPERATION is not set
+# CONFIG_FINSH_USING_FUNC_EXT is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -425,6 +426,7 @@ CONFIG_RT_USING_POSIX_TIMER=y
 #
 CONFIG_RT_USING_SAL=y
 CONFIG_SAL_INTERNET_CHECK=y
+CONFIG_SOCKET_TABLE_STEP_LEN=4
 
 #
 # Docking with protocol stacks
@@ -1617,6 +1619,7 @@ CONFIG_PKG_ZLIB_VER="latest"
 #
 # Drivers Configuration
 #
+# CONFIG_BSP_USING_I2C is not set
 # CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_TS is not set

bsp/k230/board/Kconfig

@@ -1,4 +1,31 @@
 menu "Drivers Configuration"
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        select RT_USING_I2C
+        default n
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+
+            config BSP_USING_I2C2
+                bool "Enable I2C2"
+                default n
+
+            config BSP_USING_I2C3
+                bool "Enable I2C3"
+                default n
+
+            config BSP_USING_I2C4
+                bool "Enable I2C4"
+                default n
+
+        endif
 
     config BSP_USING_RTC
         bool "Enable RTC"

bsp/k230/drivers/interdrv/i2c/SConscript

@@ -0,0 +1,11 @@
+# RT-Thread building script for I2C component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('I2C', src, depend = ['BSP_USING_I2C'], CPPPATH = CPPPATH)
+
+Return('group')

bsp/k230/drivers/interdrv/i2c/drv_i2c.c

@@ -0,0 +1,528 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 2006-2025 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <riscv_io.h>
+#include <ioremap.h>
+#include "board.h"
+#include "drv_i2c.h"
+#include "sysctl_clk.h"
+
+#undef DBG_TAG
+#undef DBG_LVL
+#define DBG_TAG     "drv_i2c"
+#define DBG_LVL     DBG_INFO
+#include <rtdbg.h>
+
+struct _i2c_speed_cfg
+{
+    rt_uint16_t hcnt;
+    rt_uint16_t lcnt;
+    rt_uint16_t spklen;
+};
+
+struct k230_i2c_dev
+{
+    struct rt_i2c_bus_device dev;
+    const char *name;
+    rt_ubase_t base;
+    size_t size;
+    int vector;
+    rt_uint32_t clock;
+    struct rt_i2c_msg *msg;
+    struct _i2c_speed_cfg speed_cfg;
+};
+
+static rt_size_t k230_i2c_get_timer(rt_size_t base)
+{
+    return rt_tick_get() - base ;
+}
+
+static void k230_i2c_enable(struct k230_i2c_dev *dev, rt_bool_t enable)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_uint32_t en_value = enable ? 1 : 0;
+    int timeout = 100;
+
+    do
+    {
+        i2c->enable.enable = en_value;
+        if(i2c->enable_status.en == en_value)
+        {
+            return;
+        }
+
+        /*
+         * Wait 10 times the signaling period of the highest I2C
+         * transfer supported by the driver (for 400KHz this is
+         * 25us) as described in the DesignWare I2C databook.
+         */
+        rt_hw_us_delay(25);
+    }while(timeout--);
+
+    LOG_E("timeout in %s i2c\n", enable ? "enable" : "disable");
+}
+
+static void k230_i2c_set_bus_timeout(struct k230_i2c_dev *dev, rt_uint32_t timeout)
+{
+    float tick = 0;
+
+    tick = RT_TICK_PER_SECOND / 1000.0f; /* ms to tick */
+    dev->dev.timeout = (rt_uint32_t)(timeout * tick);
+}
+
+static int k230_i2c_set_bus_speed(struct k230_i2c_dev *dev, rt_uint32_t speed)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_uint32_t i2c_spd, period, spklen, ft;
+
+    /*
+     * Calculate clock counts for I2C speed
+     * hcnt + lcnt + spklen + 7 + 1 + fall_time * clk = clk / speed
+     * fall_time = 10ns
+     * spklen = 0~50ns
+     */
+
+    spklen = dev->clock * 10 / 1e9;
+    ft = dev->clock * 10 / 1e9;
+    period = dev->clock / speed;
+    period = period - spklen - 7 - 1 - ft;
+    dev->speed_cfg.lcnt = period / 2;
+    dev->speed_cfg.hcnt = period - dev->speed_cfg.lcnt;
+    dev->speed_cfg.spklen = spklen;
+
+    if(speed <= I2C_STANDARD_SPEED_UP)
+    {
+        i2c_spd = I2C_SPEED_MODE_STANDARD;
+    }
+    else if(speed <= I2C_FAST_SPEED_UP)
+    {
+        i2c_spd = I2C_SPEED_MODE_FAST;
+    }
+    else if(speed <= I2C_MAX_SPEED_UP)
+    {
+        i2c_spd = I2C_SPEED_MODE_MAX;
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    /* to set speed cltr must be disabled */
+    k230_i2c_enable(dev, RT_FALSE);
+
+    switch(i2c_spd)
+    {
+        case I2C_SPEED_MODE_STANDARD:
+            i2c->ss_ufm_scl_hcnt.cnt = dev->speed_cfg.hcnt;
+            i2c->ss_ufm_scl_lcnt.cnt = dev->speed_cfg.lcnt;
+            i2c->fs_ufm_spklen.spklen = dev->speed_cfg.spklen;
+            break;
+
+        case I2C_SPEED_MODE_FAST:
+            i2c->fs_scl_hcnt_ufm_tbuf_cnt.cnt = dev->speed_cfg.hcnt;
+            i2c->fs_scl_lcnt.cnt = dev->speed_cfg.lcnt;
+            i2c->fs_ufm_spklen.spklen = dev->speed_cfg.spklen;
+            break;
+
+        case I2C_SPEED_MODE_MAX:
+            i2c->hs_scl_hcnt.cnt = dev->speed_cfg.hcnt;
+            i2c->hs_scl_lcnt.cnt = dev->speed_cfg.lcnt;
+            i2c->hs_spklen.spklen = dev->speed_cfg.spklen;
+            break;
+
+        default: break;
+    }
+
+    i2c->con.speed = i2c_spd;
+
+    /* Enable back i2c now speed set */
+    k230_i2c_enable(dev, RT_TRUE);
+
+    return RT_EOK;
+}
+
+static void k230_i2c_set_addr(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_uint16_t i2c_addr = dev->msg->addr;
+
+    /* Disable i2c */
+    k230_i2c_enable(dev, RT_FALSE);
+
+    if(dev->msg->flags & RT_I2C_ADDR_10BIT || dev->dev.flags & RT_I2C_ADDR_10BIT)
+    {
+        i2c->tar.master_10bit_addr = 1;
+        i2c_addr &= 0x3FF;
+    }
+    else
+    {
+        i2c->tar.master_10bit_addr = 0;
+        i2c_addr &= 0x7F;
+    }
+
+    i2c->tar.tar = i2c_addr;
+
+    /* Enable i2c */
+    k230_i2c_enable(dev, RT_TRUE);
+}
+
+static void k230_i2c_flush_rxfifo(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+
+    while(i2c->status.rfne)
+    {
+        readl(&i2c->data_cmd);
+    }
+}
+
+static int k230_i2c_wait_for_bus_busy(struct k230_i2c_dev *dev)
+{
+    rt_size_t start_time = k230_i2c_get_timer(0);
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+
+    while((i2c->status.mst_activity) || !(i2c->status.tfe))
+    {
+        /* Evaluate timeout */
+        if(k230_i2c_get_timer(start_time) > (rt_size_t)dev->dev.timeout * I2C_TX_FIFO_SIZE)
+        {
+            return -RT_ETIMEOUT;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static int k230_i2c_xfer_init(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_uint8_t addr = 0;
+
+    if(k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
+    {
+        return -RT_EBUSY;
+    }
+
+    k230_i2c_set_addr(dev);
+
+    return RT_EOK;
+}
+
+static int k230_i2c_xfer_finish(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_uint32_t start_stop_det = k230_i2c_get_timer(0);
+
+    while (1)
+    {
+        if(i2c->raw_intr_stat.stop_det)
+        {
+            readl(&i2c->clr_stop_det);
+            break;
+        }
+
+        else if (k230_i2c_get_timer(start_stop_det) > dev->dev.timeout)
+        {
+            break;
+        }
+    }
+
+    if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
+    {
+        return -RT_EBUSY;
+    }
+
+    k230_i2c_flush_rxfifo(dev);
+
+    return RT_EOK;
+}
+
+static int _k230_i2c_read(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_size_t start_time_rx = 0;
+    rt_uint32_t recv_len = dev->msg->len;
+    rt_uint32_t tran_len = dev->msg->len;
+    rt_uint8_t *buffer = dev->msg->buf;
+    rt_uint32_t cmd = 0;
+
+    /* If no start condition is sent before reading, then send a repeated start. */
+    if(dev->msg->flags & RT_I2C_NO_START)
+    {
+        cmd |= I2C_DATA_CMD_RESTART;
+    }
+    else
+    {
+        if(k230_i2c_xfer_init(dev) != RT_EOK)
+        {
+            return -RT_EBUSY;
+        }
+    }
+
+    start_time_rx = k230_i2c_get_timer(0);
+    while(recv_len || tran_len)
+    {
+        if (tran_len)
+        {
+            while(i2c->status.tfnf == 0);
+            /* Write stop when the last byte */
+            cmd = tran_len == 1 ? cmd | I2C_DATA_CMD_STOP : cmd;
+            /* Write to data cmd register to trigger i2c */
+            writel(cmd | I2C_DATA_CMD_READ, &i2c->data_cmd);
+            cmd = 0;
+            tran_len--;
+        }
+
+        if(i2c->status.rfne)
+        {
+            *buffer++ = i2c->data_cmd.dat;
+            recv_len--;
+            start_time_rx = k230_i2c_get_timer(0);
+        }
+        else if(k230_i2c_get_timer(start_time_rx) > dev->dev.timeout)
+        {
+            return -RT_ETIMEOUT;
+        }
+    }
+    return k230_i2c_xfer_finish(dev);
+}
+
+static int _k230_i2c_write(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+    rt_size_t start_time_tx = 0;
+    rt_uint32_t tran_len = dev->msg->len;
+    rt_uint8_t *buffer = dev->msg->buf;
+    rt_uint32_t cmd = 0;
+    rt_uint32_t cut = 0;
+
+    if (k230_i2c_xfer_init(dev) != RT_EOK)
+    {
+        return -RT_EBUSY;
+    }
+
+    start_time_tx = k230_i2c_get_timer(0);
+    while(tran_len)
+    {
+        if(i2c->status.tfnf)
+        {
+            /* If there is no stop flag, the stop condition will not be sent at the last byte. */
+            if(tran_len == 1 && !(dev->msg->flags & RT_I2C_NO_STOP))
+            {
+                cmd |= I2C_DATA_CMD_STOP;
+            }
+            else
+            {
+                cmd &= ~I2C_DATA_CMD_STOP;
+            }
+            cmd |= *buffer++;
+            writel(cmd, &i2c->data_cmd);
+            cmd = 0;
+            tran_len--;
+            start_time_tx = k230_i2c_get_timer(0);
+        }
+        else if(k230_i2c_get_timer(start_time_tx) > dev->dev.timeout)
+        {
+            return -RT_ETIMEOUT;
+        }
+    }
+
+    if (dev->msg->flags & RT_I2C_NO_STOP)
+    {
+        return RT_EOK;
+    }
+
+    if (k230_i2c_wait_for_bus_busy(dev) != RT_EOK)
+    {
+        return -RT_EBUSY;
+    }
+
+    return RT_EOK;
+}
+
+static rt_ssize_t k230_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
+{
+    struct k230_i2c_dev *i2c_dev = rt_container_of(bus, struct k230_i2c_dev, dev);
+    volatile i2c_t *i2c = (i2c_t *)i2c_dev->base;
+    int ret;
+    rt_ssize_t send_mesgs = num;
+
+    for (; num > 0; num--, msgs++)
+    {
+        i2c_dev->msg = msgs;
+
+        if(msgs->flags & RT_I2C_RD)
+        {
+            ret = _k230_i2c_read(i2c_dev);
+        }
+        else
+        {
+            ret = _k230_i2c_write(i2c_dev);
+        }
+        if (ret != RT_EOK)
+        {
+            return -RT_EIO;
+        }
+    }
+
+    return send_mesgs;
+}
+
+static rt_err_t k230_i2c_control(struct rt_i2c_bus_device *bus, int cmd, void *args)
+{
+    struct k230_i2c_dev *i2c_dev = rt_container_of(bus, struct k230_i2c_dev, dev);
+    rt_uint32_t arg = *(rt_uint32_t *)args;
+    rt_err_t ret;
+
+    RT_ASSERT(bus != RT_NULL);
+
+    switch (cmd)
+    {
+        /* set 10-bit addr mode */
+        case RT_I2C_DEV_CTRL_10BIT:
+            if(arg & RT_I2C_ADDR_10BIT)
+            {
+                i2c_dev->dev.flags |= RT_I2C_ADDR_10BIT;
+            }
+            else
+            {
+                i2c_dev->dev.flags &= ~RT_I2C_ADDR_10BIT;
+            }
+            break;
+
+        case RT_I2C_DEV_CTRL_TIMEOUT:
+            k230_i2c_set_bus_timeout(i2c_dev, arg);
+            break;
+
+        case RT_I2C_DEV_CTRL_CLK:
+            ret = k230_i2c_set_bus_speed(i2c_dev, arg);
+            if (ret != RT_EOK)
+            {
+                return -RT_EIO;
+            }
+            break;
+
+        default: break;
+    }
+
+    return RT_EOK;
+}
+
+static void k230_i2c_master_init(struct k230_i2c_dev *dev)
+{
+    volatile i2c_t *i2c = (i2c_t *)dev->base;
+
+    /* Disable i2c */
+    k230_i2c_enable(dev, RT_FALSE);
+
+    i2c->con.slave_disable = 1;
+    i2c->con.restart_en = 1;
+    i2c->con.master_mode = 1;
+    i2c->tx_tl.tl = I2C_TX_TL;
+    i2c->rx_tl.tl = I2C_RX_TL;
+    i2c->intr_mask.m_stop_det = 1;
+
+    /* Enable i2c */
+    k230_i2c_enable(dev, RT_TRUE);
+}
+
+static const struct rt_i2c_bus_device_ops k230_i2c_ops =
+{
+    .master_xfer = k230_i2c_xfer,
+    .i2c_bus_control = k230_i2c_control,
+};
+
+static struct k230_i2c_dev k230_i2c_devs[] =
+{
+#ifdef BSP_USING_I2C0
+    {
+        .name = "i2c0",
+        .base = I2C0_BASE_ADDR,
+        .size = I2C0_IO_SIZE,
+        .vector = K230_IRQ_I2C0,
+    },
+#endif
+#ifdef BSP_USING_I2C1
+    {
+        .name = "i2c1",
+        .base = I2C1_BASE_ADDR,
+        .size = I2C1_IO_SIZE,
+        .vector = K230_IRQ_I2C1,
+    },
+#endif
+#ifdef BSP_USING_I2C2
+    {
+        .name = "i2c2",
+        .base = I2C2_BASE_ADDR,
+        .size = I2C2_IO_SIZE,
+        .vector = K230_IRQ_I2C2,
+    },
+#endif
+#ifdef BSP_USING_I2C3
+    {
+        .name = "i2c3",
+        .base = I2C3_BASE_ADDR,
+        .size = I2C3_IO_SIZE,
+        .vector = K230_IRQ_I2C3,
+    },
+#endif
+#ifdef BSP_USING_I2C4
+    {
+        .name = "i2c4",
+        .base = I2C4_BASE_ADDR,
+        .size = I2C4_IO_SIZE,
+        .vector = K230_IRQ_I2C4,
+    },
+#endif
+};
+
+int rt_hw_i2c_init(void)
+{
+    int i;
+
+    for (i = 0; i < sizeof(k230_i2c_devs) / sizeof(k230_i2c_devs[0]); i++)
+    {
+        k230_i2c_devs[i].base = (rt_ubase_t)rt_ioremap((void *)k230_i2c_devs[i].base, k230_i2c_devs[i].size);
+        k230_i2c_devs[i].dev.ops = &k230_i2c_ops;
+        k230_i2c_devs[i].clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_I2C0_CORE + i);
+
+        k230_i2c_master_init(&k230_i2c_devs[i]);
+        k230_i2c_set_bus_timeout(&k230_i2c_devs[i], I2C_DEFAULT_TIMEOUT);
+        k230_i2c_set_bus_speed(&k230_i2c_devs[i], I2C_DEFAULT_SPEED);
+        rt_i2c_bus_device_register(&k230_i2c_devs[i].dev, k230_i2c_devs[i].name);
+        LOG_I("i2c%d master mode, i2c%d clock=%dHz\n", i, i, k230_i2c_devs[i].clock);
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);

bsp/k230/drivers/interdrv/i2c/drv_i2c.h

@@ -0,0 +1,704 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 2006-2025 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+#include <stdint.h>
+
+#define BIT(x)              (1<<(x))
+
+/* Speed Selection */
+#define I2C_SPEED_MODE_STANDARD      1
+#define I2C_SPEED_MODE_FAST          2
+#define I2C_SPEED_MODE_MAX           3
+
+#define I2C_MAX_SPEED_UP            3400000
+#define I2C_FAST_SPEED_UP           1000000
+#define I2C_STANDARD_SPEED_UP       100000
+#define I2C_DEFAULT_SPEED           400000
+#define I2C_DEFAULT_TIMEOUT         8       /* 8ms */
+
+/* i2c data cmd definition */
+#define I2C_DATA_CMD_READ            BIT(8)
+#define I2C_DATA_CMD_STOP            BIT(9)
+#define I2C_DATA_CMD_RESTART         BIT(10)
+#define I2C_DATA_CMD_FIRST_DATA_BYTE BIT(11)
+
+/* i2c fifo size */
+#define I2C_TX_FIFO_SIZE    32       /* 32 * 32bit */
+#define I2C_RX_FIFO_SIZE    32       /* 64 * 8bit */
+
+/* fifo threshold register definitions */
+#define I2C_TL0          0x00
+#define I2C_TL1          0x01
+#define I2C_TL2          0x02
+#define I2C_TL3          0x03
+#define I2C_TL4          0x04
+#define I2C_TL5          0x05
+#define I2C_TL6          0x06
+#define I2C_TL7          0x07
+#define I2C_RX_TL        I2C_TL0
+#define I2C_TX_TL        I2C_TL0
+
+/* i2c control register(offset address 0x00) */
+typedef struct _i2c_ic_con
+{
+    uint32_t master_mode                    : 1;
+    uint32_t speed                          : 2;
+    uint32_t slave_10bit_addr               : 1;
+    uint32_t master_10bit_addr              : 1;
+    uint32_t restart_en                     : 1;
+    uint32_t slave_disable                  : 1;
+    uint32_t stop_det_ifaddressed           : 1;
+    uint32_t tx_empty_ctrl                  : 1;
+    uint32_t rx_fifo_full_hld_ctrl          : 1;
+    uint32_t stop_det_if_master_active      : 1;
+    uint32_t bus_clear_feature_ctrl         : 1;
+    uint32_t rsvd_1                         : 4;    /* reserved */
+    uint32_t optional_sar_ctrl              : 1;
+    uint32_t smbus_slave_quick_en           : 1;
+    uint32_t smbus_arp_en                   : 1;
+    uint32_t smbus_persisent_slv_addr_en    : 1;
+    uint32_t rsvd_2                         : 12;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_con_t;
+
+/* i2c target address register(offset address 0x04) */
+typedef struct _i2c_ic_tar
+{
+    uint32_t tar               : 10;
+    uint32_t gc_or_start       : 1;
+    uint32_t special           : 1;
+    uint32_t master_10bit_addr : 1;
+    uint32_t device_id         : 1;
+    uint32_t rsvd_1            : 2;     /* reserved */
+    uint32_t smbus_quick_cmd   : 1;
+    uint32_t rsvd_2            : 15;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_tar_t;
+
+/* i2c slave address register(offset address 0x08) */
+typedef struct _i2c_ic_sar
+{
+    uint32_t sar  : 10;
+    uint32_t rsvd : 22; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_sar_t;
+
+/* i2c high speed master mode code address register(offset address 0x0c) */
+typedef struct _i2c_ic_hs_maddr
+{
+    uint32_t mar  : 3;
+    uint32_t rsvd : 29; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_hs_maddr_t;
+
+/* i2c rx/tx data buffer and command register(offset address 0x10) */
+typedef struct _i2c_ic_data_cmd
+{
+    uint32_t dat             : 8;
+    uint32_t cmd             : 1;
+    uint32_t stop            : 1;
+    uint32_t restart         : 1;
+    uint32_t first_data_byte : 1;
+    uint32_t rsvd            : 20;  /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_data_cmd_t;
+
+/* i2c standard/ultra-fast speed clock scl high count register(offset address 0x14) */
+typedef struct _i2c_ic_ss_ufm_scl_hcnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_ss_ufm_scl_hcnt_t;
+
+/* i2c standard/ultra-fast speed clock scl low count register(offset address 0x18) */
+typedef struct _i2c_ic_ss_ufm_scl_lcnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_ss_ufm_scl_lcnt_t;
+
+/* i2c fast mode speed clock scl low count/ultra-fast mode speed tbuf idle count register(offset address 0x1c) */
+typedef struct _i2c_ic_fs_scl_hcnt_ufm_tbuf_cnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_fs_scl_hcnt_ufm_tbuf_cnt_t;
+
+/* i2c fast mode clock scl low count register(offset address 0x20) */
+typedef struct _i2c_ic_fs_scl_lcnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_fs_scl_lcnt_t;
+
+/* i2c high speed mode clock scl high count register(offset address 0x24) */
+typedef struct _i2c_ic_hs_scl_hcnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_hs_scl_hcnt_t;
+
+/* i2c high speed mode clock scl low count register(offset address 0x28) */
+typedef struct _i2c_ic_hs_scl_lcnt
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_hs_scl_lcnt_t;
+
+/* i2c interrupt status register(offset address 0x2c) */
+typedef struct _i2c_ic_intr_stat
+{
+    uint32_t r_rx_under         : 1;
+    uint32_t r_rx_over          : 1;
+    uint32_t r_rx_full          : 1;
+    uint32_t r_tx_over          : 1;
+    uint32_t r_tx_empty         : 1;
+    uint32_t r_rd_req           : 1;
+    uint32_t r_tx_abrt          : 1;
+    uint32_t r_rx_done          : 1;
+    uint32_t r_activity         : 1;
+    uint32_t r_stop_det         : 1;
+    uint32_t r_start_det        : 1;
+    uint32_t r_gen_call         : 1;
+    uint32_t r_restart_det      : 1;
+    uint32_t r_master_on_hold   : 1;
+    uint32_t r_slc_stuck_at_low : 1;
+    uint32_t rsvd               : 17;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_intr_stat_t;
+
+/* i2c interrupt mask register(offset address 0x30) */
+typedef struct _i2c_ic_intr_mask
+{
+    uint32_t m_rx_under         : 1;
+    uint32_t m_rx_over          : 1;
+    uint32_t m_rx_full          : 1;
+    uint32_t m_tx_over          : 1;
+    uint32_t m_tx_empty         : 1;
+    uint32_t m_rd_req           : 1;
+    uint32_t m_tx_abrt          : 1;
+    uint32_t m_rx_done          : 1;
+    uint32_t m_activity         : 1;
+    uint32_t m_stop_det         : 1;
+    uint32_t m_start_det        : 1;
+    uint32_t m_gen_call         : 1;
+    uint32_t m_restart_det      : 1;
+    uint32_t m_master_on_hold   : 1;
+    uint32_t m_slc_stuck_at_low : 1;
+    uint32_t rsvd               : 17;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_intr_mask_t;
+
+/* i2c raw interrupt status register(offset address 0x34) */
+typedef struct _i2c_ic_raw_intr_stat
+{
+    uint32_t rx_under           : 1;
+    uint32_t rx_over            : 1;
+    uint32_t rx_full            : 1;
+    uint32_t tx_over            : 1;
+    uint32_t tx_empty           : 1;
+    uint32_t rd_req             : 1;
+    uint32_t tx_abrt            : 1;
+    uint32_t rx_done            : 1;
+    uint32_t activity           : 1;
+    uint32_t stop_det           : 1;
+    uint32_t start_det          : 1;
+    uint32_t gen_call           : 1;
+    uint32_t restart_det        : 1;
+    uint32_t master_on_hold     : 1;
+    uint32_t scl_stuck_at_low   : 1;
+    uint32_t rsvd               : 17;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_raw_intr_stat_t;
+
+/* i2c receive FIFO threshold register(offset address 0x38) */
+typedef struct _i2c_ic_rx_tl
+{
+    uint32_t tl   : 8;
+    uint32_t rsvd : 24;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_rx_tl_t;
+
+/* i2c transmit FIFO threshold register(offset address 0x3c) */
+typedef struct _i2c_ic_tx_tl
+{
+    uint32_t tl   : 8;
+    uint32_t rsvd : 24; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_tx_tl_t;
+
+/* i2c clear combined and individual interrupt register(offset address 0x40) */
+typedef struct _i2c_ic_clr_intr
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_intr_t;
+
+/* i2c clear rx under interrupt register(offset address 0x44) */
+typedef struct _i2c_ic_clr_rx_under
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_rx_under_t;
+
+/* i2c clear rx over interrupt register(offset address 0x48) */
+typedef struct _i2c_ic_clr_rx_over
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_rx_over_t;
+
+/* i2c clear tx over interrupt register(offset address 0x4c) */
+typedef struct _i2c_ic_clr_tx_over
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_tx_over_t;
+
+/* i2c clear rd req interrupt register(offset address 0x50) */
+typedef struct _i2c_ic_clr_rd_req
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_rd_req_t;
+
+/* i2c clear tx abrt interrupt register(offset address 0x54) */
+typedef struct _i2c_ic_clr_tx_abrt
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_tx_abrt_t;
+
+/* i2c clear rx done interrupt register(offset address 0x58) */
+typedef struct _i2c_ic_clr_rx_done
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_rx_done_t;
+
+/* i2c clear activity interrupt register(offset address 0x5c) */
+typedef struct _i2c_ic_clr_activity
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_activity_t;
+
+/* i2c clear stop det interrupt register(offset address 0x60) */
+typedef struct _i2c_clr_stop_det
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_stop_det_t;
+
+/* i2c clear start det interrupt register(offset address 0x64) */
+typedef struct _i2c_ic_clr_start_det
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_start_det_t;
+
+/* i2c clear gen call interrupt register(offset address 0x68) */
+typedef struct _i2c_ic_clr_gen_call
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_gen_call_t;
+
+/* i2c enable register(offset address 0x6c) */
+typedef struct _i2c_ic_enable
+{
+    uint32_t enable                    : 1;
+    uint32_t abort                     : 1;
+    uint32_t tx_cmd_block              : 1;
+    uint32_t sda_stuck_recovery_enable : 1;
+    uint32_t rsvd_1                    : 12;    /* reserved */
+    uint32_t smbus_clk_reset           : 1;
+    uint32_t smbus_suspned_en          : 1;
+    uint32_t smbus_alert_en            : 1;
+    uint32_t rsvd_2                    : 13;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_enable_t;
+
+/* i2c status register(offset address 0x70) */
+typedef struct _i2c_ic_status
+{
+    uint32_t activity                  : 1;
+    uint32_t tfnf                      : 1;
+    uint32_t tfe                       : 1;
+    uint32_t rfne                      : 1;
+    uint32_t rff                       : 1;
+    uint32_t mst_activity              : 1;
+    uint32_t slv_activity              : 1;
+    uint32_t mst_hold_tx_fifo_empty    : 1;
+    uint32_t mst_hold_rx_fifo_full     : 1;
+    uint32_t slv_hold_tx_fifo_empty    : 1;
+    uint32_t slv_hold_rx_fifo_full     : 1;
+    uint32_t sda_stuck_not_recovered   : 1;
+    uint32_t rsvd_1                    : 4;     /* reserved */
+    uint32_t smbus_quick_cmd_bit       : 1;
+    uint32_t smbus_slave_addr_valid    : 1;
+    uint32_t smbus_slave_addr_resolved : 1;
+    uint32_t smbus_suspend_status      : 1;
+    uint32_t smbus_alert               : 1;
+    uint32_t rsvd_2                    : 11;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_status_t;
+
+/* i2c transmit fifo level register(offset address 0x74) */
+typedef struct _i2c_ic_txflr
+{
+    uint32_t txflr : 5;
+    uint32_t rsvd  : 27;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_txflr_t;
+
+/* i2c receive fifo level register(offset address 0x78) */
+typedef struct _i2c_ic_rxflr
+{
+    uint32_t rxflr : 5;
+    uint32_t rsvd  : 27;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_rxflr_t;
+
+/* i2c sda hold time length register(offset address 0x7c) */
+typedef struct _i2c_ic_sda_hold
+{
+    uint32_t tx_hold : 16;
+    uint32_t rx_hold : 8;
+    uint32_t rsvd    : 8;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_sda_hold_t;
+
+/* i2c transmit abort source register(offset address 0x80) */
+typedef struct _i2c_ic_tx_abrt_source
+{
+    uint32_t abrt_7b_addr_noack        : 1;
+    uint32_t abrt_10addr1_noack        : 1;
+    uint32_t abrt_10addr2_noack        : 1;
+    uint32_t abrt_txdata_noack         : 1;
+    uint32_t abrt_gcall_noack          : 1;
+    uint32_t abrt_gcall_read           : 1;
+    uint32_t abrt_hs_ackdet            : 1;
+    uint32_t abrt_sbyte_ackdet         : 1;
+    uint32_t abrt_hs_norstrt           : 1;
+    uint32_t abrt_sbyte_norstrt        : 1;
+    uint32_t abrt_10b_rd_norstrt       : 1;
+    uint32_t abrt_master_dis           : 1;
+    uint32_t abrt_lost                 : 1;
+    uint32_t abrt_slvflush_txfifo      : 1;
+    uint32_t abrt_slv_arblost          : 1;
+    uint32_t abrt_slvrd_intx           : 1;
+    uint32_t abrt_user_abrt            : 1;
+    uint32_t abrt_sda_stuck_at_low     : 1;
+    uint32_t abrt_device_noack         : 1;
+    uint32_t abrt_device_slvaddr_noack : 1;
+    uint32_t abrt_device_write         : 1;
+    uint32_t rsvd                      : 2; /* reserved */
+    uint32_t tx_flush_cnt              : 9;
+} __attribute__((packed, aligned(4))) i2c_ic_tx_abrt_source_t;
+
+/* i2c generate slave data nack register(offset address 0x84) */
+typedef struct _i2c_ic_slv_data_nack_only
+{
+    uint32_t nack : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_slv_data_nack_only_t;
+
+/* i2c dma control register(offset address 0x88) */
+typedef struct _i2c_ic_dma_cr
+{
+    uint32_t rdmae : 1;
+    uint32_t tdmae : 1;
+    uint32_t rsvd  : 30;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_dma_cr_t;
+
+/* i2c dma transmit data level register(offset address 0x8c) */
+typedef struct _i2c_ic_dma_tdlr
+{
+    uint32_t dmatdl : 5;
+    uint32_t rsvd   : 27;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_dma_tdlr_t;
+
+/* i2c dma receive data level register(offset address 0x90) */
+typedef struct _i2c_ic_dma_rdlr
+{
+    uint32_t dmardl : 5;
+    uint32_t rsvd   : 27;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_dma_rdlr_t;
+
+/* i2c sda setup register(offset address 0x94) */
+typedef struct _i2c_ic_sda_setup
+{
+    uint32_t setup : 8;
+    uint32_t rsvd  : 24;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_sda_setup_t;
+
+/* i2c ack general call register(offset address 0x98) */
+typedef struct _i2c_ic_ack_general_call
+{
+    uint32_t ask  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_ack_general_call_t;
+
+/* i2c enable status register(offset address 0x9c) */
+typedef struct _i2c_ic_enable_status
+{
+    uint32_t en                      : 1;
+    uint32_t slv_disabled_while_busy : 1;
+    uint32_t slv_rx_data_lost        : 1;
+    uint32_t rsvd                    : 29;  /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_enable_status_t;
+
+/* i2c ss, fs, or fm+/ufm spike suppression limit register(offset address 0xa0) */
+typedef struct _i2c_ic_fs_ufm_spklen
+{
+    uint32_t spklen : 8;
+    uint32_t rsvd   : 24;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_fs_ufm_spklen_t;
+
+/* i2c hs spike suppression limit register(offset address 0xa4) */
+typedef struct _i2c_ic_hs_spklen
+{
+    uint32_t spklen : 8;
+    uint32_t rsvd   : 24;   /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_hs_spklen_t;
+
+/* i2c clear restart det interrupt register(offset address 0xa8) */
+typedef struct _i2c_ic_clr_restart_det
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_restart_det_t;
+
+/* i2c scl stuck at low timeout register(offset address 0xac) */
+typedef struct _i2c_ic_scl_stuck_at_low_timeout
+{
+    uint32_t timeout  : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_scl_stuck_at_low_timeout_t;
+
+/* i2c sda stuck at low timeout register(offset address 0xb0) */
+typedef struct _i2c_ic_sda_stuck_at_low_timeout
+{
+    uint32_t timeout  : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_sda_stuck_at_low_timeout_t;
+
+/* i2c clear scl stuck at low detect interrupt register(offset address 0xb4) */
+typedef struct _i2c_ic_clr_slc_stuck_det
+{
+    uint32_t clr  : 1;
+    uint32_t rsvd : 31; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_slc_stuck_det_t;
+
+/* i2c device id register(offset address 0xb8) */
+typedef struct _i2c_ic_device_id
+{
+    uint32_t device_id : 24;
+    uint32_t rsvd      : 8; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_device_id_t;
+
+/* i2c smbus slave clock extend timeout register(offset address 0xbc) */
+typedef struct _i2c_ic_smbus_clk_low_sext
+{
+    uint32_t timeout : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_clk_low_sext_t;
+
+/* i2c smbus master clock extend timeout register(offset address 0xc0) */
+typedef struct _i2c_ic_smbus_clk_low_mext
+{
+    uint32_t timeout : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_clk_low_mext_t;
+
+/* i2c smbus master thigh max bus-idle count register(offset address 0xc4) */
+typedef struct _i2c_ic_smbus_thigh_max_idle_count
+{
+    uint32_t cnt  : 16;
+    uint32_t rsvd : 16; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_thigh_max_idle_count_t;
+
+/* i2c smbus interrupt status register(offset address 0xc8) */
+typedef struct _i2c_ic_smbus_intr_stat
+{
+    uint32_t r_slv_clock_extnd_timeout : 1;
+    uint32_t r_mst_clock_extnd_timeout : 1;
+    uint32_t r_quick_cmd_det           : 1;
+    uint32_t r_host_notify_mst_det     : 1;
+    uint32_t r_arp_prepare_cmd_det     : 1;
+    uint32_t r_arp_rst_cmd_det         : 1;
+    uint32_t r_arp_get_udid_cmd_det    : 1;
+    uint32_t r_arp_assgn_addr_cmd_det  : 1;
+    uint32_t r_slv_rx_pec_nack         : 1;
+    uint32_t r_smbus_suspend_det       : 1;
+    uint32_t r_smbus_alert_det         : 1;
+    uint32_t rsvd                      : 21;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_intr_stat_t;
+
+/* i2c smbus interrupt mask register(offset address 0xcc) */
+typedef struct _i2c_ic_smbus_intr_mask
+{
+    uint32_t m_slv_clock_extnd_timeout : 1;
+    uint32_t m_mst_clock_extnd_timeout : 1;
+    uint32_t m_quick_cmd_det           : 1;
+    uint32_t m_host_notify_mst_det     : 1;
+    uint32_t m_arp_prepare_cmd_det     : 1;
+    uint32_t m_arp_rst_cmd_det         : 1;
+    uint32_t m_arp_get_udid_cmd_det    : 1;
+    uint32_t m_arp_assgn_addr_cmd_det  : 1;
+    uint32_t m_slv_rx_pec_nack         : 1;
+    uint32_t m_smbus_suspend_det       : 1;
+    uint32_t m_smbus_alert_det         : 1;
+    uint32_t rsvd                      : 21;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_intr_mask_t;
+
+/* i2c smbus raw interrupt status register(offset address 0xd0) */
+typedef struct _i2c_ic_smbus_raw_intr_stat
+{
+    uint32_t slv_clock_extnd_timeout : 1;
+    uint32_t mst_clock_extnd_timeout : 1;
+    uint32_t quick_cmd_det           : 1;
+    uint32_t host_notify_mst_det     : 1;
+    uint32_t arp_prepare_cmd_det     : 1;
+    uint32_t arp_rst_cmd_det         : 1;
+    uint32_t arp_get_udid_cmd_det    : 1;
+    uint32_t arp_assgn_addr_cmd_det  : 1;
+    uint32_t slv_rx_pec_nack         : 1;
+    uint32_t smbus_suspend_det       : 1;
+    uint32_t smbus_alert_det         : 1;
+    uint32_t rsvd                    : 21;  /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_raw_intr_stat_t;
+
+/* i2c smbus clear interrupt register(offset address 0xd4) */
+typedef struct _i2c_ic_clr_smbus_intr
+{
+    uint32_t slv_clock_extnd_timeout : 1;
+    uint32_t mst_clock_extnd_timeout : 1;
+    uint32_t quick_cmd_det           : 1;
+    uint32_t host_notify_mst_det     : 1;
+    uint32_t arp_prepare_cmd_det     : 1;
+    uint32_t arp_rst_cmd_det         : 1;
+    uint32_t arp_get_udid_cmd_det    : 1;
+    uint32_t arp_assgn_addr_cmd_det  : 1;
+    uint32_t slv_rx_pec_nack         : 1;
+    uint32_t smbus_suspend_det       : 1;
+    uint32_t smbus_alert_det         : 1;
+    uint32_t rsvd                    : 21;  /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_clr_smbus_intr_t;
+
+/* i2c optional slave address register(offset address 0xd8) */
+typedef struct _i2c_ic_optional_sar
+{
+    uint32_t sar  : 7;
+    uint32_t rsvd : 25; /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_optional_sar_t;
+
+/* i2c smbus udid lsb register(offset address 0xdc) */
+typedef struct _i2c_ic_smbus_udid_lsb
+{
+    uint32_t udid_lsb : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_smbus_udid_lsb_t;
+
+/* i2c component parameter 1 register(offset address 0xf4) */
+typedef struct _i2c_ic_comp_param_1
+{
+    uint32_t apb_data_width     : 2;
+    uint32_t max_speed_mode     : 2;
+    uint32_t hc_count_values    : 1;
+    uint32_t intr_io            : 1;
+    uint32_t has_dma            : 1;
+    uint32_t add_encoded_params : 1;
+    uint32_t rx_buffer_depth    : 8;
+    uint32_t tx_buffer_depth    : 8;
+    uint32_t rsvd               : 8;    /* reserved */
+} __attribute__((packed, aligned(4))) i2c_ic_comp_param_1_t;
+
+/* i2c component version register(offset address 0xf8) */
+typedef struct _i2c_ic_comp_version
+{
+    uint32_t version : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_comp_version_t;
+
+/* i2c component type register(offset address 0xfc) */
+typedef struct _i2c_ic_comp_type
+{
+    uint32_t type : 32;
+} __attribute__((packed, aligned(4))) i2c_ic_comp_type_t;
+
+/* i2c register */
+typedef struct _i2c
+{
+    i2c_ic_con_t                        con;                        /* 0x00 */
+    i2c_ic_tar_t                        tar;                        /* 0x04 */
+    i2c_ic_sar_t                        sar;                        /* 0x08 */
+    i2c_ic_hs_maddr_t                   hs_maddr;                   /* 0x0c */
+    i2c_ic_data_cmd_t                   data_cmd;                   /* 0x10 */
+    i2c_ic_ss_ufm_scl_hcnt_t            ss_ufm_scl_hcnt;            /* 0x14 */
+    i2c_ic_ss_ufm_scl_lcnt_t            ss_ufm_scl_lcnt;            /* 0x18 */
+    i2c_ic_fs_scl_hcnt_ufm_tbuf_cnt_t   fs_scl_hcnt_ufm_tbuf_cnt;   /* 0x1c */
+    i2c_ic_fs_scl_lcnt_t                fs_scl_lcnt;                /* 0x20 */
+    i2c_ic_hs_scl_hcnt_t                hs_scl_hcnt;                /* 0x24 */
+    i2c_ic_hs_scl_lcnt_t                hs_scl_lcnt;                /* 0x28 */
+    i2c_ic_intr_stat_t                  intr_stat;                  /* 0x2c */
+    i2c_ic_intr_mask_t                  intr_mask;                  /* 0x30 */
+    i2c_ic_raw_intr_stat_t              raw_intr_stat;              /* 0x34 */
+    i2c_ic_rx_tl_t                      rx_tl;                      /* 0x38 */
+    i2c_ic_tx_tl_t                      tx_tl;                      /* 0x3c */
+    i2c_ic_clr_intr_t                   clr_intr;                   /* 0x40 */
+    i2c_ic_clr_rx_under_t               clr_rx_under;               /* 0x44 */
+    i2c_ic_clr_rx_over_t                clr_rx_over;                /* 0x48 */
+    i2c_ic_clr_tx_over_t                clr_tx_over;                /* 0x4c */
+    i2c_ic_clr_rd_req_t                 clr_rd_req;                 /* 0x50 */
+    i2c_ic_clr_tx_abrt_t                clr_tx_abrt;                /* 0x54 */
+    i2c_ic_clr_rx_done_t                clr_rx_done;                /* 0x58 */
+    i2c_ic_clr_activity_t               clr_activity;               /* 0x5c */
+    i2c_ic_clr_stop_det_t               clr_stop_det;               /* 0x60 */
+    i2c_ic_clr_start_det_t              clr_start_det;              /* 0x64 */
+    i2c_ic_clr_gen_call_t               clr_gen_call;               /* 0x68 */
+    i2c_ic_enable_t                     enable;                     /* 0x6c */
+    i2c_ic_status_t                     status;                     /* 0x70 */
+    i2c_ic_txflr_t                      txflr;                      /* 0x74 */
+    i2c_ic_rxflr_t                      rxflr;                      /* 0x78 */
+    i2c_ic_sda_hold_t                   sda_hold;                   /* 0x7c */
+    i2c_ic_tx_abrt_source_t             tx_abrt_source;             /* 0x80 */
+    i2c_ic_slv_data_nack_only_t         slv_data_nack_only;         /* 0x84 */
+    i2c_ic_dma_cr_t                     dma_cr;                     /* 0x88 */
+    i2c_ic_dma_tdlr_t                   dma_tdlr;                   /* 0x8c */
+    i2c_ic_dma_rdlr_t                   dma_rdlr;                   /* 0x90 */
+    i2c_ic_sda_setup_t                  sda_setup;                  /* 0x94 */
+    i2c_ic_ack_general_call_t           ack_general_call;           /* 0x98 */
+    i2c_ic_enable_status_t              enable_status;              /* 0x9c */
+    i2c_ic_fs_ufm_spklen_t              fs_ufm_spklen;              /* 0xa0 */
+    i2c_ic_hs_spklen_t                  hs_spklen;                  /* 0xa4 */
+    i2c_ic_clr_restart_det_t            clr_restart_det;            /* 0xa8 */
+    i2c_ic_scl_stuck_at_low_timeout_t   scl_stuck_at_low_timeout;   /* 0xac */
+    i2c_ic_sda_stuck_at_low_timeout_t   sda_stuck_at_low_timeout;   /* 0xb0 */
+    i2c_ic_clr_slc_stuck_det_t          clr_slc_stuck_det;          /* 0xb4 */
+    i2c_ic_device_id_t                  device_id;                  /* 0xb8 */
+    i2c_ic_smbus_clk_low_sext_t         smbus_clk_low_sext;         /* 0xbc */
+    i2c_ic_smbus_clk_low_mext_t         smbus_clk_low_mext;         /* 0xc0 */
+    i2c_ic_smbus_thigh_max_idle_count_t smbus_thigh_max_idle_count; /* 0xc4 */
+    i2c_ic_smbus_intr_stat_t            smbus_intr_stat;            /* 0xc8 */
+    i2c_ic_smbus_intr_mask_t            smbus_intr_mask;            /* 0xcc */
+    i2c_ic_smbus_raw_intr_stat_t        smbus_raw_intr_stat;        /* 0xd0 */
+    i2c_ic_clr_smbus_intr_t             clr_smbus_intr;             /* 0xd4 */
+    i2c_ic_optional_sar_t               optional_sar;               /* 0xd8 */
+    i2c_ic_smbus_udid_lsb_t             smbus_udid_lsb;             /* 0xdc */
+    uint32_t                            rsvd_1[5];                  /* 0xe0-0xf0 reserved */
+    i2c_ic_comp_param_1_t               comp_param_1;               /* 0xf4 */
+    i2c_ic_comp_version_t               comp_version;               /* 0xf8 */
+    i2c_ic_comp_type_t                  comp_type;                  /* 0xfc */
+} __attribute__((packed, aligned(4))) i2c_t;
+
+#endif /* __DRV_I2C_H__ */

bsp/k230/drivers/utest/SConscript

@@ -30,6 +30,9 @@ if GetDepend('BSP_UTEST_DRIVERS'):
     if GetDepend('BSP_USING_RTC'):
         src += ['test_rtc.c']
 
+    if GetDepend('BSP_USING_I2C'):
+        src += ['test_i2c.c']
+
 group = DefineGroup('utestcases', src, depend = [''])
 
 Return('group')

bsp/k230/drivers/utest/test_i2c.c

@@ -0,0 +1,204 @@
+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2006-2025 RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <utest.h>
+#include <string.h>
+#include "drv_i2c.h"
+#include "drv_pinctrl.h"
+#include "drv_gpio.h"
+
+/*
+ * 测试K230 I2C的主从机通信，在这里采用I2C0作为测试对象
+ *
+ * 硬件平台：
+ * 测试的硬件平台为庐山派开发板，使用的I2C0引脚是GPIO048(SCL)
+ * 和GPIO049(SDA)。
+ *
+ * 测试说明：
+ * 1. 测试I2C0主机模式
+ *     主机模式下，主机向从机发送16字节数据（不包括写读地址），
+ *     然后再读取回来进行校验，共执行两次，分别是400kHz和1MHz速率。
+ *     注：使用的从机为AT24C08 EEPROM，设备地址为0x50。
+ */
+
+#define I2C_NAME            "i2c0"
+#define TARGET_ADDR         0x50
+
+#define TEST_BUFFER_SIZE    16
+
+#define I2C_SCL_PIN         48
+#define I2C_SDA_PIN         49
+#define I2C_SCL_PIN_AF      IOMUX_FUNC4
+#define I2C_SDA_PIN_AF      IOMUX_FUNC4
+
+static void test_i2c0_deinit_pin(void)
+{
+    k230_pinctrl_set_function(I2C_SCL_PIN, IOMUX_FUNC1);
+    k230_pinctrl_set_function(I2C_SDA_PIN, IOMUX_FUNC1);
+    k230_pinctrl_set_oe(I2C_SCL_PIN, 0);
+    k230_pinctrl_set_oe(I2C_SDA_PIN, 0);
+    k230_pinctrl_set_ie(I2C_SCL_PIN, 1);
+    k230_pinctrl_set_ie(I2C_SDA_PIN, 1);
+
+    kd_pin_mode(I2C_SCL_PIN, GPIO_DM_INPUT);
+    kd_pin_mode(I2C_SDA_PIN, GPIO_DM_INPUT);
+}
+
+static void test_i2c0_init_pin(void)
+{
+    k230_pinctrl_set_function(I2C_SCL_PIN, I2C_SCL_PIN_AF); // I2C0_SCL
+    k230_pinctrl_set_function(I2C_SDA_PIN, I2C_SDA_PIN_AF); // I2C0_SDA
+    k230_pinctrl_set_oe(I2C_SCL_PIN, 1);
+    k230_pinctrl_set_oe(I2C_SDA_PIN, 1);
+    k230_pinctrl_set_ie(I2C_SCL_PIN, 1);
+    k230_pinctrl_set_ie(I2C_SDA_PIN, 1);
+}
+
+static int test_i2c_check_pin(void)
+{
+    test_i2c0_deinit_pin();
+
+    if(kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1)
+    {
+        LOG_W("i2c bus is not idle, try to recover it.");
+        k230_pinctrl_set_oe(I2C_SCL_PIN, 1);
+        kd_pin_mode(I2C_SCL_PIN, GPIO_DM_OUTPUT);
+        for(rt_uint8_t i = 0; i < 9; i++)
+        {
+            kd_pin_write(I2C_SCL_PIN, 0);
+            rt_hw_us_delay(2);
+            kd_pin_write(I2C_SCL_PIN, 1);
+            rt_hw_us_delay(2);
+        }
+        k230_pinctrl_set_oe(I2C_SCL_PIN, 0);
+        kd_pin_mode(I2C_SCL_PIN, GPIO_DM_INPUT);
+    }
+
+    if(kd_pin_read(I2C_SCL_PIN) != 1 || kd_pin_read(I2C_SDA_PIN) != 1)
+    {
+        LOG_E("i2c bus recover failed");
+        return -RT_ERROR;
+    }
+
+    LOG_I("i2c bus(pin: %u, %u) is idle, init i2c bus pin", I2C_SCL_PIN, I2C_SDA_PIN);
+    test_i2c0_init_pin();
+
+    return RT_EOK;
+}
+
+static void _test_i2c0_master(rt_uint8_t *buffer_w, rt_uint8_t *buffer_r, rt_uint32_t size, rt_uint32_t speed)
+{
+    rt_err_t ret = RT_EOK;
+    struct rt_i2c_bus_device *dev;
+    struct rt_i2c_msg msgs[2];
+
+    dev = rt_i2c_bus_device_find(I2C_NAME);
+    uassert_not_null(dev);
+    rt_i2c_control(dev, RT_I2C_DEV_CTRL_CLK, (void *)&speed);
+
+    msgs[0].addr  = TARGET_ADDR;
+    msgs[0].flags = RT_I2C_WR;
+    msgs[0].buf   = buffer_w;
+    msgs[0].len   = size + 1;
+
+    if(rt_i2c_transfer(dev, msgs, 1) != 1)
+    {
+        LOG_E("i2c transfer failed");
+        uassert_true(0);
+    }
+
+    rt_thread_mdelay(10);
+
+    msgs[0].addr  = TARGET_ADDR;
+    msgs[0].flags = RT_I2C_WR | RT_I2C_NO_STOP;
+    msgs[0].buf   = &buffer_r[0];
+    msgs[0].len   = 1;
+
+    msgs[1].addr  = TARGET_ADDR;
+    msgs[1].flags = RT_I2C_RD | RT_I2C_NO_START;
+    msgs[1].buf   = &buffer_r[1];
+    msgs[1].len   = size;
+
+    if(rt_i2c_transfer(dev, msgs, 2) != 2)
+    {
+        LOG_E("i2c transfer failed");
+        uassert_true(0);
+    }
+
+    LOG_I("Read data:\n");
+    for(rt_uint8_t i = 1; i < size + 1; i++)
+    {
+        LOG_I("0x%02X ", buffer_r[i]);
+    }
+    uassert_buf_equal(buffer_w + 1, buffer_r + 1, size);
+}
+
+static void test_i2c0_master(void)
+{
+    rt_uint8_t buffer_w[TEST_BUFFER_SIZE + 1];
+    rt_uint8_t buffer_r[TEST_BUFFER_SIZE + 1];
+    rt_uint32_t size = TEST_BUFFER_SIZE;
+    rt_uint32_t speed = 400000; // 400kHz
+
+    memset(buffer_w + 1, 0xAA, TEST_BUFFER_SIZE);
+    buffer_w[0] = 0x00; // memory address
+    memset(buffer_r, 0x00, TEST_BUFFER_SIZE + 1);
+
+    _test_i2c0_master(buffer_w, buffer_r, size, speed);
+
+    speed = 1000000; // 1MHz
+    memset(buffer_w + 1, 0x55, TEST_BUFFER_SIZE);
+    buffer_w[0] = 0x00; // memory address
+    memset(buffer_r, 0x00, TEST_BUFFER_SIZE + 1);
+
+    _test_i2c0_master(buffer_w, buffer_r, size, speed);
+}
+
+static void testcase(void)
+{
+    LOG_I("This is a i2c test case.\n");
+    UTEST_UNIT_RUN(test_i2c0_master);
+}
+
+static rt_err_t utest_tc_init(void)
+{
+    return test_i2c_check_pin();
+}
+
+static rt_err_t utest_tc_cleanup(void)
+{
+    LOG_I("i2c bus pin deinit.\n");
+    test_i2c0_deinit_pin();
+    return RT_EOK;
+}
+UTEST_TC_EXPORT(testcase, "bsp.k230.drivers.i2c", utest_tc_init, utest_tc_cleanup, 100);

bsp/k230/rtconfig.h

@@ -276,6 +276,7 @@
 
 #define RT_USING_SAL
 #define SAL_INTERNET_CHECK
+#define SOCKET_TABLE_STEP_LEN 4
 
 /* Docking with protocol stacks */
 

bsp/microchip/.clang-format-ignore

@@ -2,6 +2,5 @@
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-dir_path:
-- CMSIS
-- VangoV85xx_standard_peripheral
+# 从 .ignore_format.yml 迁移的规则
+/sam*/bsp/

bsp/microchip/samd51-seeed-wio-terminal/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- bsp

bsp/microchip/same54/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- bsp

bsp/microchip/same70/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- bsp

bsp/microchip/saml10/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- bsp

bsp/mm32f103x/.clang-format-ignore

@@ -1,7 +1,7 @@
+
 # files format check exclude path, please follow the instructions below to modify;
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-dir_path:
-- Libraries/N32_Std_Driver
-
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/

bsp/mm32f103x/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- Libraries

bsp/mm32f327x/.clang-format-ignore

@@ -1,9 +1,7 @@
+
 # files format check exclude path, please follow the instructions below to modify;
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-file_path:
-
-
-dir_path:
-- Libraries
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/

bsp/mm32f327x/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- Libraries

bsp/mm32f526x/.clang-format-ignore

@@ -1,6 +1,7 @@
+
 # files format check exclude path, please follow the instructions below to modify;
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-dir_path:
-- bsp
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/

bsp/mm32f526x/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- Libraries

bsp/mm32l07x/.clang-format-ignore

@@ -2,6 +2,5 @@
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-dir_path:
-- CMSIS
-- VangoV85xxP_standard_peripheral
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/

bsp/mm32l3xx/.clang-format-ignore

@@ -2,5 +2,5 @@
 # If you need to exclude an entire folder, add the folder path in dir_path;
 # If you need to exclude a file, add the path to the file in file_path.
 
-dir_path:
-- bsp
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/

bsp/n32/.clang-format-ignore

@@ -0,0 +1,7 @@
+
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+# 从 .ignore_format.yml 迁移的规则
+/libraries/N32G45x_Firmware_Library/

bsp/n32/libraries/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- N32G45x_Firmware_Library

bsp/n32g452xx/.clang-format-ignore

@@ -0,0 +1,7 @@
+
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+# 从 .ignore_format.yml 迁移的规则
+/Libraries/N32_Std_Driver/

bsp/nxp/.clang-format-ignore

@@ -0,0 +1,17 @@
+
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+# 从 .ignore_format.yml 迁移的规则
+/imx/imxrt/imxrt1060-nxp-evk/board/board.c/
+/imx/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/
+/imx/imxrt/imxrt1060-nxp-evk/xip/
+
+/imx/imxrt/libraries/MIMXRT1060/
+
+/lpc/lpc55sxx/Libraries/LPC55*/
+
+/mcx/mcxa/Libraries/MCXA153/
+/mcx/mcxc/Libraries/MCXC444/
+/mcx/mcxn/Libraries/MCXN947/

bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/.clang-format-ignore

@@ -0,0 +1,10 @@
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+# NXP imxrt1060-nxp-evk library
+/board/MCUX_Config/
+/xip/

bsp/nxp/imx/imxrt/imxrt1060-nxp-evk/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- board/board.c
-- board/MCUX_Config
-- xip

bsp/nxp/imx/imxrt/libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MIMXRT1060

bsp/nxp/lpc/lpc55sxx/Libraries/.ignore_format.yml

@@ -1,8 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- LPC55S6X
-- LPC55S06
-- LPC5502
-- LPC55S28
-- LPC55S36

bsp/nxp/mcx/mcxa/Libraries/.clang-format-ignore

@@ -0,0 +1,9 @@
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+# NXP MCXA library
+/MCXA153/

bsp/nxp/mcx/mcxa/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXA153

bsp/nxp/mcx/mcxc/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXC444

bsp/nxp/mcx/mcxn/Libraries/.ignore_format.yml

@@ -1,4 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-
-dir_path:
-- MCXN947

bsp/renesas/.clang-format-ignore

@@ -1,4 +1,14 @@
-# clang-format ignore file  
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+# Renesas Vendor library
+<<<<<<< HEAD
 /**/ra/
 /**/ra_cfg/
 /**/ra_gen/
+/libraries/bsp-template/
+/**/RTE/

bsp/renesas/libraries/bsp-template/.ignore_format.yml

@@ -1,9 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- ra
-- ra_gen
-- ra_cfg
-- RTE

bsp/rockchip/.clang-format-ignore

@@ -0,0 +1,9 @@
+# .clang-format-ignore File Description:
+# ----------------------------------------------------------------------------------------
+# 1. Used to specify which files or directories should be skipped by the clang-format tool.
+# 2. Follows syntax rules similar to .gitignore.
+# 3. Supports wildcard patterns and path matching.
+# 4. clang-format will recursively apply the .clang-format-ignore rules.
+
+
+/common/rk_hal/

bsp/rockchip/common/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- rk_hal

bsp/stm32/.clang-format-ignore

@@ -0,0 +1,12 @@
+
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+# 从 .ignore_format.yml 迁移的规则
+# 忽略所有 STM32 HAL 库目录
+/libraries/STM32*_HAL/
+
+# 忽略所有 STM32 BSP 的 CubeMX 配置目录
+/stm32*/board/CubeMX_Config/
+

bsp/stm32/libraries/.ignore_format.yml

@@ -1,23 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- STM32F0xx_HAL
-- STM32F1xx_HAL
-- STM32F2xx_HAL
-- STM32F3xx_HAL
-- STM32F4xx_HAL
-- STM32F7xx_HAL
-- STM32G0xx_HAL
-- STM32G4xx_HAL
-- STM32H7xx_HAL
-- STM32L0xx_HAL
-- STM32L1xx_HAL
-- STM32L4xx_HAL
-- STM32L5xx_HAL
-- STM32MPxx_HAL
-- STM32U5xx_HAL
-- STM32H5xx_HAL
-- STM32WBxx_HAL
-- STM32WLxx_HAL

bsp/stm32/libraries/HAL_Drivers/drivers/SConscript

@@ -50,6 +50,9 @@ if GetDepend(['RT_USING_DAC']):
     src += ['drv_dac.c']
 
 if GetDepend(['RT_USING_CAN']):
+    if GetDepend(['SOC_SERIES_STM32H7']):
+        src += ['drv_fdcan.c']
+    else:
         src += ['drv_can.c']
 
 if GetDepend(['RT_USING_PM']):

bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/uart_config.h

@@ -145,6 +145,17 @@ extern "C" {
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
 
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "hlpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#endif /* BSP_USING_LPUART1 */
+
 #ifdef __cplusplus
 }
 #endif

bsp/stm32/libraries/HAL_Drivers/drivers/drv_can.c

@@ -472,11 +472,23 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
         argval = (rt_uint32_t) arg;
         if (argval == 0)
         {
-            HAL_CAN_Stop(&drv_can->CanHandle);
+            if (HAL_CAN_DeInit(&drv_can->CanHandle) != HAL_OK)
+            {
+                LOG_E("CAN deinitialization failed");
+                return -RT_ERROR;
+            }
         }
         else
         {
-            HAL_CAN_Start(&drv_can->CanHandle);
+            rt_err_t result = _can_config(&drv_can->device, &drv_can->device.config);
+            if (result != RT_EOK)
+            {
+                return result;
+            }
+            if (HAL_CAN_Start(&drv_can->CanHandle) != HAL_OK)
+            {
+                return -RT_ERROR;
+            }
         }
 
         break;
@@ -500,7 +512,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  *
  * @return `RT_EOK` on success, or an error code on failure.
  */
-static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
 {
     CAN_HandleTypeDef *hcan;
     hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
@@ -515,32 +527,31 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t
             (state == HAL_CAN_STATE_LISTENING))
     {
         /*check select mailbox  is empty */
+        uint32_t mailbox_mask;
+        uint32_t tme_flag;
+
         switch (1 << box_num)
         {
         case CAN_TX_MAILBOX0:
-            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0) != SET)
-            {
-                /* Return function status */
-                return -RT_ERROR;
-            }
+            mailbox_mask = CAN_TX_MAILBOX0;
+            tme_flag = CAN_TSR_TME0;
             break;
         case CAN_TX_MAILBOX1:
-            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1) != SET)
-            {
-                /* Return function status */
-                return -RT_ERROR;
-            }
+            mailbox_mask = CAN_TX_MAILBOX1;
+            tme_flag = CAN_TSR_TME1;
             break;
         case CAN_TX_MAILBOX2:
-            if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2) != SET)
-            {
-                /* Return function status */
-                return -RT_ERROR;
-            }
+            mailbox_mask = CAN_TX_MAILBOX2;
+            tme_flag = CAN_TSR_TME2;
             break;
         default:
             RT_ASSERT(0);
-            break;
+            return -RT_ERROR;
+        }
+
+        if (HAL_IS_BIT_SET(hcan->Instance->TSR, tme_flag) != SET)
+        {
+            return -RT_ERROR;
         }
 
         if (RT_CAN_STDID == pmsg->ide)
@@ -649,7 +660,7 @@ static rt_ssize_t _can_sendmsg_nonblocking(struct rt_can_device *can, const void
     return RT_EOK;
 }
 
-static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
 {
     HAL_StatusTypeDef status;
     CAN_HandleTypeDef *hcan;

bsp/stm32/libraries/HAL_Drivers/drivers/drv_fdcan.c

@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-02-24     heyuan       the first version
+ * 2020-08-17     malongwei    Fix something
+ * 2025-10-27     pandafeng    Fix some bugs
+ */
+
+#include "drv_fdcan.h"
+
+#if defined(RT_USING_CAN) && defined(RT_CAN_USING_CANFD)
+
+#if defined(BSP_USING_FDCAN1) || defined(BSP_USING_FDCAN2)
+
+
+//#define DRV_DEBUG
+#define LOG_TAG    "drv_fdcan"
+#include <drv_log.h>
+
+#ifdef BSP_USING_FDCAN1
+static stm32_fdcan_t st_DrvCan1=
+{
+    .name = "fdcan1",
+    .fdcanHandle.Instance = FDCAN1,
+};
+#endif
+
+#ifdef BSP_USING_FDCAN2
+static stm32_fdcan_t st_DrvCan2=
+{
+    .name = "fdcan2",
+    .fdcanHandle.Instance = FDCAN2,
+};
+#endif
+
+/* 40MHz CAN clock */
+static const stm32_fdcan_timing_t st_FDCAN_ArbTiming[] =
+{
+    {CAN1MBaud, {1, 29, 10, 8, 0}},   /* 1Mbps */
+    {CAN800kBaud,  {1, 37, 12, 8, 0}},   /* 800kbps */
+    {CAN500kBaud,  {1, 59, 20, 8, 0}},   /* 500kbps */
+    {CAN250kBaud,  {2, 63, 16, 8, 0}},  /* 250kbps */
+    {CAN125kBaud,  {5, 55, 8, 8, 0}},  /* 125kbps */
+    {CAN100kBaud,  {8, 41, 8, 8, 0}},  /* 100kbps */
+    {CAN50kBaud,   {16, 41, 8, 8, 0}},   /* 50kbps */
+    {CAN20kBaud,   {40,41,8,8,0}},     /* 20kbps */
+    {CAN10kBaud,   {100,31,8,8,0}}      /* 10kbps */
+};
+/* 40MHz CAN clock */
+static const stm32_fdcan_timing_t st_FDCAN_DataTiming[] =
+{
+    {CAN1MBaud * 8, {1, 3, 1, 1, 0}},   /* 8Mbps */
+    {CAN500kBaud *8,  {1, 7, 2, 1, 0}},   /* 4Mbps */
+    {CAN250kBaud * 8,  {4, 3, 1, 1, 0}},  /* 2Mbps */
+    {CAN125kBaud *8,  {1, 31, 8, 1, 0}},  /* 1Mkbps */
+    {CAN100kBaud*8,  {2, 19, 5, 1, 0}},  /* 800kbps */
+    {CAN50kBaud *8,   {5, 15, 4, 1, 0}},   /* 400kbps */
+};
+/**
+ * @brief  Convert CAN-FD frame length to DLC (Data Length Code)
+ *
+ * CAN-FD DLC mapping (length → DLC):
+ *  Length 0~8   -> DLC 0~8
+ *  Length 9~12  -> DLC 9
+ *  Length 13~16 -> DLC 10
+ *  Length 17~20 -> DLC 11
+ *  Length 21~24 -> DLC 12
+ *  Length 25~32 -> DLC 13
+ *  Length 33~48 -> DLC 14
+ *  Length 49~64 -> DLC 15
+ *
+ * @param len  Frame length in bytes (0~64)
+ * @return     DLC code (0~15)
+ */
+uint8_t length_to_dlc(uint8_t len) {
+    return (len <= 8) ? len :
+           (len <= 12) ? 9 :
+           (len <= 16) ? 10 :
+           (len <= 20) ? 11 :
+           (len <= 24) ? 12 :
+           (len <= 32) ? 13 :
+           (len <= 48) ? 14 : 15;
+}
+
+/**
+ * @brief  获取 FDCAN 仲裁段波特率配置索引
+ */
+static uint32_t _inline_get_ArbBaudIndex(uint32_t baud_rate)
+{
+    uint32_t len = sizeof(st_FDCAN_ArbTiming) / sizeof(st_FDCAN_ArbTiming[0]);
+
+    for (uint32_t i = 0; i < len; i++)
+    {
+        if (st_FDCAN_ArbTiming[i].u32Baudrate == baud_rate)
+            return i;
+    }
+    return -1;
+}
+
+/**
+ * @brief  Get the index of the FDCAN data segment bitrate configuration.
+ *
+ * @param  baud_rate  The desired data phase baud rate (in bps).
+ * @retval uint32_t   Index of the matching data segment configuration.
+ *                     Returns -1 if no matching configuration is found.
+ */
+static uint32_t _inline_get_DataBaudIndex(uint32_t baud_rate)
+{
+    uint32_t len = sizeof(st_FDCAN_DataTiming) / sizeof(st_FDCAN_DataTiming[0]);
+
+    for (uint32_t i = 0; i < len; i++)
+    {
+        if (st_FDCAN_DataTiming[i].u32Baudrate == baud_rate)
+            return i;
+    }
+    return -1;
+}
+
+static rt_err_t _inline_can_config(struct rt_can_device *can, struct can_configure *cfg)
+{
+    stm32_fdcan_t *pdrv_can;
+    rt_uint32_t tmp_u32Index;
+
+    RT_ASSERT(can);
+    RT_ASSERT(cfg);
+
+    pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
+
+    RT_ASSERT(pdrv_can);
+
+    pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
+    pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+    pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE;
+
+    pdrv_can->fdcanHandle.Init.TransmitPause = DISABLE;
+    pdrv_can->fdcanHandle.Init.ProtocolException = ENABLE;
+
+    switch (cfg->mode)
+    {
+    case RT_CAN_MODE_NORMAL:
+        pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+        break;
+    case RT_CAN_MODE_LISTEN:
+        pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_BUS_MONITORING;
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK;
+        break;
+    default:
+        pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
+        break;
+    }
+
+    uint32_t arb_idx  = _inline_get_ArbBaudIndex(cfg->baud_rate);
+    if (arb_idx == (uint32_t)-1)
+    {
+        LOG_E("not support %d baudrate", cfg->baud_rate);
+        return -RT_ERROR;
+    }
+    /* FDCAN arbitration segment */
+    pdrv_can->fdcanHandle.Init.NominalPrescaler      = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.prescaler;
+    pdrv_can->fdcanHandle.Init.NominalSyncJumpWidth  = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_sjw;
+    pdrv_can->fdcanHandle.Init.NominalTimeSeg1       = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_seg1;
+    pdrv_can->fdcanHandle.Init.NominalTimeSeg2       = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_seg2;
+#ifdef RT_CAN_USING_CANFD
+    if(cfg->enable_canfd) {
+        uint32_t data_idx = _inline_get_DataBaudIndex(cfg->baud_rate_fd);
+        if (data_idx == (uint32_t)-1)
+        {
+            LOG_E("not support %d baudrate", cfg->baud_rate_fd);
+            return -RT_ERROR;
+        }
+        /* 数据段 */
+        pdrv_can->fdcanHandle.Init.DataPrescaler         = st_FDCAN_DataTiming[data_idx].cam_bit_timing.prescaler;
+        pdrv_can->fdcanHandle.Init.DataSyncJumpWidth     = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_sjw;
+        pdrv_can->fdcanHandle.Init.DataTimeSeg1          = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_seg1;
+        pdrv_can->fdcanHandle.Init.DataTimeSeg2          = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_seg2;
+    }
+#endif
+    /* Configure Message RAM */
+    if(pdrv_can->fdcanHandle.Instance == FDCAN1)
+    {
+        pdrv_can->fdcanHandle.Init.MessageRAMOffset = 0;
+    }
+    else
+    {
+        pdrv_can->fdcanHandle.Init.MessageRAMOffset = 1280;
+    }
+    pdrv_can->fdcanHandle.Init.StdFiltersNbr = 2;
+    pdrv_can->fdcanHandle.Init.ExtFiltersNbr = 2;
+    pdrv_can->fdcanHandle.Init.RxFifo0ElmtsNbr = 1;
+    pdrv_can->fdcanHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
+    pdrv_can->fdcanHandle.Init.RxFifo1ElmtsNbr = 0;
+    pdrv_can->fdcanHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
+    pdrv_can->fdcanHandle.Init.RxBuffersNbr = 0;
+    pdrv_can->fdcanHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
+    pdrv_can->fdcanHandle.Init.TxEventsNbr = 0;
+    pdrv_can->fdcanHandle.Init.TxBuffersNbr = 3;
+    pdrv_can->fdcanHandle.Init.TxFifoQueueElmtsNbr = 0;
+    pdrv_can->fdcanHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
+    pdrv_can->fdcanHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
+
+    if (HAL_FDCAN_Init(&pdrv_can->fdcanHandle) != HAL_OK)
+    {
+        return -RT_ERROR;
+    }
+    /* default filter config */
+    HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig);
+    /*init fdcan tx header*/
+    pdrv_can->TxHeader.Identifier = 0x000000;
+    pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID;
+    pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
+    pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_8;
+    pdrv_can->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
+    pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_OFF;
+    pdrv_can->TxHeader.FDFormat = FDCAN_CLASSIC_CAN;
+    pdrv_can->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
+    pdrv_can->TxHeader.MessageMarker = 0;
+    /* can start */
+    HAL_FDCAN_Start(&pdrv_can->fdcanHandle);
+    return RT_EOK;
+}
+
+static rt_err_t _inline_can_filter_config(stm32_fdcan_t *pdrv_can,struct rt_can_filter_config *puser_can_filter_config)
+{
+    int tmp_i32IndexCount;
+    RT_ASSERT(pdrv_can);
+    RT_ASSERT(puser_can_filter_config);
+     /* get default filter */
+    for (tmp_i32IndexCount = 0; tmp_i32IndexCount < puser_can_filter_config->count; tmp_i32IndexCount++)
+    {
+        pdrv_can->FilterConfig.FilterIndex = puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank;
+        pdrv_can->FilterConfig.FilterID1 = puser_can_filter_config->items[tmp_i32IndexCount].id;
+        pdrv_can->FilterConfig.FilterID2 = puser_can_filter_config->items[tmp_i32IndexCount].mask;
+        if(puser_can_filter_config->items[tmp_i32IndexCount].ide == RT_CAN_EXTID)
+        {
+            pdrv_can->FilterConfig.IdType = FDCAN_EXTENDED_ID;
+        }
+        else
+        {
+            pdrv_can->FilterConfig.IdType = FDCAN_STANDARD_ID;
+        }
+        pdrv_can->FilterConfig.FilterType = FDCAN_FILTER_MASK;
+        pdrv_can->FilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+        if(HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig) != HAL_OK)
+        {
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+}
+
+static rt_err_t _inline_can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+
+    rt_uint32_t argval;
+    stm32_fdcan_t *pdrv_can;
+    struct rt_can_filter_config *filter_cfg;
+    RT_ASSERT(can != RT_NULL);
+    pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
+    RT_ASSERT(pdrv_can != RT_NULL);
+    switch (cmd) {
+        case RT_DEVICE_CTRL_CLR_INT:
+            argval = (rt_uint32_t) arg;
+            if (argval == RT_DEVICE_FLAG_INT_RX) {
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE);
+            } else if (argval == RT_DEVICE_FLAG_INT_TX) {
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_FIFO_EMPTY);
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE);
+            } else if (argval == RT_DEVICE_CAN_INT_ERR) {
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING);
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE);
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_LOGGING_OVERFLOW);
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF);
+                HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR);
+            }
+            break;
+        case RT_DEVICE_CTRL_SET_INT:
+            argval = (rt_uint32_t) arg;
+            if (argval == RT_DEVICE_FLAG_INT_RX) {
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE,
+                                               FDCAN_INTERRUPT_LINE0);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0);
+
+                if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
+                    HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 1);
+                    HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
+                } else {
+                    HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 1);
+                    HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
+                }
+            } else if (argval == RT_DEVICE_FLAG_INT_TX) {
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_INTERRUPT_LINE1);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER0);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER1);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER2);
+
+                if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
+                    HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
+                    HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
+                } else {
+                    HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
+                    HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
+                }
+            } else if (argval == RT_DEVICE_CAN_INT_ERR) {
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, FDCAN_INTERRUPT_LINE1);
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, FDCAN_INTERRUPT_LINE1);
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, FDCAN_INTERRUPT_LINE1);
+                HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR,
+                                               FDCAN_INTERRUPT_LINE1);
+
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, 0);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, 0);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, 0);
+                HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, 0);
+                if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
+                    HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
+                    HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
+                } else {
+                    HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
+                    HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
+                }
+            }
+            break;
+        case RT_CAN_CMD_SET_FILTER:
+            if (RT_NULL == arg) {
+                /* default filter config */
+                HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &pdrv_can->FilterConfig);
+            } else {
+                filter_cfg = (struct rt_can_filter_config *) arg;
+                _inline_can_filter_config(pdrv_can, filter_cfg);
+            }
+            break;
+        case RT_CAN_CMD_SET_MODE:
+            argval = (rt_uint32_t) arg;
+            if (argval != RT_CAN_MODE_NORMAL &&
+                argval != RT_CAN_MODE_LISTEN &&
+                argval != RT_CAN_MODE_LOOPBACK &&
+                argval != RT_CAN_MODE_LOOPBACKANLISTEN) {
+                return -RT_ERROR;
+            }
+            if (argval != pdrv_can->device.config.mode) {
+                pdrv_can->device.config.mode = argval;
+                return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+            }
+            break;
+        case RT_CAN_CMD_SET_BAUD:
+            argval = (rt_uint32_t) arg;
+            uint32_t arb_idx = _inline_get_ArbBaudIndex(argval);
+            if (arb_idx == (uint32_t) -1) {
+                return -RT_ERROR; 
+            }
+            if (argval != pdrv_can->device.config.baud_rate) {
+                pdrv_can->device.config.baud_rate = argval;
+                return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+            }
+            break;
+
+        case RT_CAN_CMD_SET_PRIV:
+            argval = (rt_uint32_t) arg;
+            if (argval != RT_CAN_MODE_PRIV &&
+                argval != RT_CAN_MODE_NOPRIV) {
+                return -RT_ERROR;
+            }
+            if (argval != pdrv_can->device.config.privmode) {
+                pdrv_can->device.config.privmode = argval;
+
+                return RT_EOK;
+            }
+            break;
+        case RT_CAN_CMD_GET_STATUS: {
+            rt_uint32_t tmp_u32Errcount;
+            rt_uint32_t tmp_u32status;
+            tmp_u32Errcount = pdrv_can->fdcanHandle.Instance->ECR;
+            tmp_u32status = pdrv_can->fdcanHandle.Instance->PSR;
+
+            pdrv_can->device.status.rcverrcnt = (tmp_u32Errcount >> 8) & 0x000000ff;
+            pdrv_can->device.status.snderrcnt = (tmp_u32Errcount) & 0x000000ff;
+            pdrv_can->device.status.lasterrtype = tmp_u32status & 0x000000007;
+
+            rt_memcpy(arg, &pdrv_can->device.status, sizeof(pdrv_can->device.status));
+        }
+        break;
+        case RT_CAN_CMD_SET_BAUD_FD: {
+            argval = (rt_uint32_t) arg;
+            uint32_t data_idx = _inline_get_DataBaudIndex(argval);
+            if (data_idx == (uint32_t) -1) {
+                return -RT_ERROR;
+            }
+            if (argval != pdrv_can->device.config.baud_rate_fd) {
+                pdrv_can->device.config.baud_rate_fd = argval;
+                return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
+            }
+        }
+    }
+
+
+    return RT_EOK;
+}
+
+static int _inline_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+
+    stm32_fdcan_t *pdrv_can;
+    struct rt_can_msg *pmsg;
+    uint32_t tmp_u32DataLen;
+    RT_ASSERT(can);
+    RT_ASSERT(buf);
+
+    pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
+
+    RT_ASSERT(pdrv_can);
+
+    pmsg = (struct rt_can_msg *) buf;
+
+    /* Check the parameters */
+    tmp_u32DataLen = length_to_dlc( pmsg->len);
+
+    if(pmsg->ide == RT_CAN_EXTID)
+    {
+        pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID;
+    }
+    else
+    {
+        pdrv_can->TxHeader.IdType = FDCAN_STANDARD_ID;
+    }
+
+    if (RT_CAN_DTR == pmsg->rtr)
+    {
+        pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
+    }
+    else
+    {
+        pdrv_can->TxHeader.TxFrameType = FDCAN_REMOTE_FRAME;
+    }
+
+
+    pdrv_can->TxHeader.Identifier = pmsg->id;
+
+    pdrv_can->TxHeader.DataLength = tmp_u32DataLen;
+
+
+    if (pmsg->fd_frame == 1)
+    {
+        pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN;
+    }
+    else {
+        pdrv_can->TxHeader.FDFormat = FDCAN_CLASSIC_CAN;
+    }
+
+    if(HAL_FDCAN_AddMessageToTxBuffer(&pdrv_can->fdcanHandle, &pdrv_can->TxHeader, pmsg->data, FDCAN_TX_BUFFER0 + box_num) != HAL_OK)
+    {
+        return -RT_ERROR;
+    }
+    else
+    {
+        /* Request transmission */
+        HAL_FDCAN_EnableTxBufferRequest(&pdrv_can->fdcanHandle,FDCAN_TX_BUFFER0+box_num);
+        return RT_EOK;
+    }
+}
+
+static int _inline_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+    struct rt_can_msg *pmsg;
+    stm32_fdcan_t *pdrv_can;
+
+    RT_ASSERT(can);
+    RT_ASSERT(buf);
+
+    pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
+    pmsg = (struct rt_can_msg *) buf;
+    if(HAL_FDCAN_GetRxMessage(&pdrv_can->fdcanHandle,FDCAN_RX_FIFO0+fifo, &pdrv_can->RxHeader, pmsg->data) != HAL_OK)
+    {
+        return 0;
+    }
+    else
+    {
+        if(pdrv_can->RxHeader.IdType == FDCAN_EXTENDED_ID)
+        {
+            pmsg->ide = RT_CAN_EXTID;
+        }
+        else
+        {
+            pmsg->ide = RT_CAN_STDID;
+        }
+
+        if(pdrv_can->RxHeader.RxFrameType == FDCAN_DATA_FRAME)
+        {
+            pmsg->rtr = RT_CAN_DTR;
+        }
+        else
+        {
+            pmsg->rtr = RT_CAN_RTR;
+        }
+        pmsg->id = pdrv_can->RxHeader.Identifier;
+
+        pmsg->len = pdrv_can->RxHeader.DataLength;
+        pmsg->hdr_index = pdrv_can->RxHeader.FilterIndex;
+
+        #ifdef RT_CAN_USING_CANFD
+        pmsg->fd_frame =  (pdrv_can->RxHeader.FDFormat >> 16) && 0x20;
+        pmsg->brs = (pdrv_can->RxHeader.BitRateSwitch >> 16) && 0x10;
+        #endif
+
+        return sizeof(struct rt_can_msg);
+    }
+}
+
+static const struct rt_can_ops _can_ops =
+{
+    _inline_can_config,
+    _inline_can_control,
+    _inline_can_sendmsg,
+    _inline_can_recvmsg,
+};
+
+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
+{
+    if((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET)
+      {
+          if(hfdcan->Instance == FDCAN1)
+          {
+#ifdef BSP_USING_FDCAN1
+              //CAN1
+              /* Retreive Rx messages from RX FIFO0 */
+              rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_RX_IND | 0 << 8);
+#endif
+          }
+        else
+        {
+#ifdef BSP_USING_FDCAN2
+            //CAN2
+            /* Retreive Rx messages from RX FIFO0 */
+            rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_RX_IND | 0 << 8);
+#endif
+        }
+    }
+}
+
+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
+{
+    if(hfdcan->Instance == FDCAN1)
+    {
+#ifdef BSP_USING_FDCAN1
+        //can1
+        rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8));
+#endif
+    }
+    else
+    {
+#ifdef BSP_USING_FDCAN2
+        //can2
+        rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8));
+#endif
+    }
+}
+
+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+    if(hfdcan->Instance == FDCAN1)
+    {
+#ifdef BSP_USING_FDCAN1
+        rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE);
+#endif
+    }
+    else
+    {
+#ifdef BSP_USING_FDCAN2
+        rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE);
+#endif
+    }
+}
+
+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
+{
+    rt_uint32_t tmp_u32Errcount;
+    rt_uint32_t tmp_u32status;
+    uint32_t ret = HAL_FDCAN_GetError(hfdcan);
+
+    if(hfdcan->Instance == FDCAN1)
+    {
+#ifdef BSP_USING_FDCAN1
+        if((ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
+            (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
+        {
+            //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
+            hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
+            st_DrvCan1.device.status.errcode = 0xff;
+        }
+        else
+        {
+            tmp_u32Errcount = st_DrvCan1.fdcanHandle.Instance->ECR;
+            tmp_u32status = st_DrvCan1.fdcanHandle.Instance->PSR;
+            st_DrvCan1.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
+            st_DrvCan1.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
+            st_DrvCan1.device.status.lasterrtype = tmp_u32status&0x000000007;
+            rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_FAIL);
+
+        }
+#endif /*BSP_USING_FDCAN1*/
+    }
+    else
+    {
+#ifdef BSP_USING_FDCAN2
+        if(    (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
+            (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
+        {
+            //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
+            hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
+            st_DrvCan2.device.status.errcode = 0xff;
+        }
+        else
+        {
+            //can2
+            tmp_u32Errcount = st_DrvCan2.fdcanHandle.Instance->ECR;
+            tmp_u32status = st_DrvCan2.fdcanHandle.Instance->PSR;
+            st_DrvCan2.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
+            st_DrvCan2.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
+            st_DrvCan2.device.status.lasterrtype = tmp_u32status&0x000000007;
+            rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_FAIL);
+        }
+#endif /*BSP_USING_FDCAN2*/
+    }
+}
+
+#ifdef BSP_USING_FDCAN1
+void FDCAN1_IT0_IRQHandler(void)             /* FDCAN1 interrupt line 0      */
+{
+    rt_interrupt_enter();
+    HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
+    rt_interrupt_leave();
+}
+
+void FDCAN1_IT1_IRQHandler(void)             /* FDCAN1 interrupt line 1      */
+{
+    rt_interrupt_enter();
+    HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
+    rt_interrupt_leave();
+}
+#endif /*BSP_USING_FDCAN1*/
+#ifdef BSP_USING_FDCAN2
+void FDCAN2_IT0_IRQHandler(void)             /* FDCAN2 interrupt line 0      */
+{
+    rt_interrupt_enter();
+    HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
+    rt_interrupt_leave();
+}
+
+void FDCAN2_IT1_IRQHandler(void)             /* FDCAN2 interrupt line 1      */
+{
+    rt_interrupt_enter();
+    HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
+    rt_interrupt_leave();
+}
+#endif/*BSP_USING_FDCAN2*/
+
+static int rt_hw_can_init(void)
+{
+    struct can_configure config;
+    config.baud_rate = CAN1MBaud;
+    config.msgboxsz = 48;
+    config.sndboxnumber = 1;
+    config.mode = RT_CAN_MODE_NORMAL;
+    config.privmode = RT_CAN_MODE_NOPRIV;
+    config.ticks = 50;
+#ifdef RT_CAN_USING_HDR
+    config.maxhdr = 14;
+#endif
+#ifdef RT_CAN_USING_CANFD
+    config.baud_rate_fd = CAN1MBaud * 8;
+    config.enable_canfd = 1;
+#endif
+    /* config default filter */
+    FDCAN_FilterTypeDef sFilterConfig;
+    sFilterConfig.IdType = FDCAN_STANDARD_ID;
+    sFilterConfig.FilterIndex = 0;
+    sFilterConfig.FilterType = FDCAN_FILTER_MASK;
+    sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
+    sFilterConfig.FilterID1 = 0;
+    sFilterConfig.FilterID2 = 0x7FF;
+#ifdef BSP_USING_FDCAN1
+    st_DrvCan1.FilterConfig = sFilterConfig;
+    st_DrvCan1.device.config = config;
+    /* register FDCAN1 device */
+    rt_hw_can_register(&st_DrvCan1.device, st_DrvCan1.name, &_can_ops, &st_DrvCan1);
+#endif /* BSP_USING_FDCAN1 */
+#ifdef BSP_USING_FDCAN2
+    st_DrvCan2.FilterConfig = sFilterConfig;
+    st_DrvCan2.device.config = config;
+    /* register FDCAN2 device */
+    rt_hw_can_register(&st_DrvCan2.device, st_DrvCan2.name, &_can_ops, &st_DrvCan2);
+#endif /* BSP_USING_FDCAN2 */
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+#endif /* BSP_USING_FDCAN1 || BSP_USING_FDCAN2 */
+#endif /* RT_USING_CAN */

bsp/stm32/libraries/HAL_Drivers/drivers/drv_fdcan.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-02-24     heyuan       the first version
+ * 2020-08-17     malongwei    Fix something
+ */
+
+#ifndef __DRV_FDCAN_H__
+#define __DRV_FDCAN_H__
+
+#include <board.h>
+#include <rtdevice.h>
+
+#if defined(RT_USING_CAN) && defined(RT_CAN_USING_CANFD)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+    const char *name;
+    FDCAN_HandleTypeDef fdcanHandle;
+    FDCAN_RxHeaderTypeDef RxHeader;
+    FDCAN_TxHeaderTypeDef TxHeader;
+    uint8_t u8RxDataBuffer[8];
+    uint8_t u8TxDataBuffer[8];
+    FDCAN_FilterTypeDef FilterConfig; /*FDCAN filter*/
+    struct rt_can_device device;      /* inherit from can device */
+} stm32_fdcan_t;
+
+typedef struct {
+    uint32_t u32Baudrate;
+    struct rt_can_bit_timing cam_bit_timing;
+}stm32_fdcan_timing_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_CAN */
+#endif /* __DRV_FDCAN_H__ */

bsp/stm32/libraries/templates/stm32l5xx/board/.ignore_format.yml

@@ -1,7 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config
-- linker_scripts

bsp/stm32/stm32f091-st-nucleo/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-atk-nano/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-atk-warshipv3/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-blue-pill/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-dofly-M3S/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-dofly-lyc8/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-fire-arbitrary/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-gizwits-gokitv21/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-hw100k-ibox/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-keysking-learning/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-onenet-nbiot/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f103-yf-ufun/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f107-uc-eval/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f207-st-nucleo/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f302-st-nucleo/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f334-st-nucleo/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f401-st-nucleo/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f405-smdz-breadfruit/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f407-armfly-v5/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f407-atk-explorer/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f407-lckfb-skystar/board/.ignore_format.yml

@@ -1,6 +0,0 @@
-# files format check exclude path, please follow the instructions below to modify;
-# If you need to exclude an entire folder, add the folder path in dir_path;
-# If you need to exclude a file, add the path to the file in file_path.
-
-dir_path:
-- CubeMX_Config

bsp/stm32/stm32f407-micu/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/stm32/stm32f407-micu/Kconfig

@@ -0,0 +1,15 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+
+if !RT_USING_NANO
+rsource "board/Kconfig"
+endif

bsp/stm32/stm32f407-micu/README.md

@@ -0,0 +1,137 @@
+# 米醋·McoreSTM32电控板 BSP 说明
+
+## 简介
+
+本文档为 **米醋·McoreSTM32电控板** 的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+STM32F407VET6是一款泛用性很高的芯片，基于 ARM Cortex-M4 内核的 32 位微控制器，属于 STM32 系列。它具有高性能、低功耗和丰富的外设，非常适合用于各种嵌入式应用。我们基于这款芯片设计出一块核心板用于嵌入式学习，板载了GD32芯片，搭载DAP-LINK，可用于keil下载调试。板子上还预留一个三色LED、一个用户按键、一个4M的FLASH、一个TF卡槽，此外还搭载了比较常用的传感器，温湿度传感器和姿态传感器。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32F407VET6，主频 168MHz，512KB FLASH ，192KB RAM
+- 外部 FLASH：ZD25WQ32，4MB
+- 常用外设
+  - LED：3个，DS0（红色，PC2），DS1（绿色，PC1），DS2（蓝色，PC0）
+  - 按键：1个，USER（PC3）
+- 常用接口：USB 转串口、SD 卡接口等
+- 调试接口，支持SWD（板载DAPLink）
+
+开发板更多详细信息请参考【立创开源硬件平台】 [米醋·McoreSTM32电控板](https://oshwhub.com/the-first-development-team-of-no/kong-zhi-ban)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| DAPLink虚拟串口        |     支持     | 已连接到芯片的UART1（PA9,PA10）                                      |
+| 三色LED(RGB)        |     支持     | 作为系统状态指示灯                                      |
+| 按键         |     暂不支持     | 即将支持                                      |
+| SPI Flash         |     暂不支持     | 即将支持                                      |
+| TF卡              |   暂不支持   | 即将支持                                      |
+| CAN               |   暂不支持   | 即将支持                                      |
+| ICM-20608-G               |   暂不支持   | 即将支持                                      |
+| AHT20               |   暂不支持   |即将支持                                       |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | 所有GPIO引脚 |
+| UART              |     支持     | UART1                         |
+| SPI               |     暂不支持     | 即将支持                              |
+| I2C               |     暂不支持     | 即将支持                              |
+| SDIO              |   暂不支持   | 即将支持                              |
+| RTC               |   暂不支持   | 即将支持                              |
+| PWM               |   暂不支持   | 即将支持                              |
+| USB Device        |   暂不支持   | 即将支持                              |
+| USB Host          |   暂不支持   | 即将支持                              |
+| IWG               |   暂不支持   | 即将支持                              |
+| **扩展模块**      | **支持情况** | **备注**                              |
+|     舵机      |   暂不支持   | 即将支持                                     |
+|     编码电机      |   暂不支持   | 即将支持                                     |
+|     步进电机      |   暂不支持   | 即将支持                                   |
+|     蓝牙      |   暂不支持   |即将支持                                     |
+|     CAM      |   暂不支持   | 即将支持                                     |
+|     OLED      |   暂不支持   | 即将支持                                     |
+|     陀螺仪      |   暂不支持   | 即将支持                                     |
+|     八路灰度      |   暂不支持   | 即将支持                                     |
+|     LED灯      |   暂不支持   | 即将支持                                     |
+|     按键      |   暂不支持   | 即将支持                                     |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+##### 请注意！！！
+在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
+```bash
+pkgs --update
+```
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+> 工程默认配置使用 DAPLink 仿真器下载程序，在通过 USB 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，【开发板上的三色LED会以1HZ的频率闪烁】。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.2 build Nov  8 2025 16:39:56
+ 2006 - 2024 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 暂无
+
+## 联系人信息
+
+维护人:
+
+-  [戴凌祥](https://gitee.com/dai-lingxiang), 邮箱：<3070269033@qq.com>

bsp/stm32/stm32f407-micu/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32f407-micu/SConstruct

@@ -0,0 +1,76 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+def bsp_pkg_check():
+    import subprocess
+
+    check_paths = [
+        os.path.join("packages", "CMSIS-Core-latest"),
+        os.path.join("packages", "stm32f4_cmsis_driver-latest"),
+        os.path.join("packages", "stm32f4_hal_driver-latest")
+    ]
+
+    need_update = not all(os.path.exists(p) for p in check_paths)
+
+    if need_update:
+        print("\n===============================================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
+        print("===============================================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('env')
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0))
+
+#objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/stm32/stm32f407-micu/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/stm32/stm32f407-micu/applications/main.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-11-08     Dailingxiang   first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED0 pin: PC2 */
+#define LED0_PIN    GET_PIN(C, 2)
+/* defined the LED1 pin: PC1 */
+#define LED1_PIN        GET_PIN(C, 1)
+/* defined the LED2 pin: PC0 */
+#define LED2_PIN        GET_PIN(C, 0)
+
+int main(void)
+{
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+    /* set LED1 pin mode to output */
+    rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+    /* set LED2 pin mode to output */
+    rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+    while (1)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_pin_write(LED1_PIN, PIN_HIGH);
+        rt_pin_write(LED2_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_pin_write(LED1_PIN, PIN_LOW);
+        rt_pin_write(LED2_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/stm32/stm32f407-micu/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,127 @@
+#MicroXplorer Configuration settings - do not modify
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.CPN=STM32F407VET6
+Mcu.Family=STM32F4
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SYS
+Mcu.IP3=USART1
+Mcu.IPNb=4
+Mcu.Name=STM32F407V(E-G)Tx
+Mcu.Package=LQFP100
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin2=PH0-OSC_IN
+Mcu.Pin3=PH1-OSC_OUT
+Mcu.Pin4=PA9
+Mcu.Pin5=PA10
+Mcu.Pin6=PA13
+Mcu.Pin7=PA14
+Mcu.Pin8=VP_SYS_VS_Systick
+Mcu.PinsNb=9
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F407VETx
+MxCube.Version=6.15.0
+MxDb.Version=DB.6.0.150
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerLinker=GCC
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F407VETx
+ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.3
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.ProjectStructure=
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5.32
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true
+RCC.48MHZClocksFreq_Value=84000000
+RCC.AHBFreq_Value=168000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=42000000
+RCC.APB1TimFreq_Value=84000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=84000000
+RCC.APB2TimFreq_Value=168000000
+RCC.CortexFreq_Value=168000000
+RCC.EthernetFreq_Value=168000000
+RCC.FCLKCortexFreq_Value=168000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=168000000
+RCC.HSE_VALUE=8000000
+RCC.HSI_VALUE=16000000
+RCC.I2SClocksFreq_Value=192000000
+RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
+RCC.LSI_VALUE=32000
+RCC.MCO2PinFreq_Value=168000000
+RCC.PLLCLKFreq_Value=168000000
+RCC.PLLM=8
+RCC.PLLN=168
+RCC.PLLQCLKFreq_Value=84000000
+RCC.RTCFreq_Value=32000
+RCC.RTCHSEDivFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=168000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.VCOI2SOutputFreq_Value=384000000
+RCC.VCOInputFreq_Value=2000000
+RCC.VCOOutputFreq_Value=336000000
+RCC.VcooutputI2S=192000000
+USART1.IPParameters=VirtualMode
+USART1.VirtualMode=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Inc/main.h

@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h

@@ -0,0 +1,495 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+/* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_ADC_MODULE_ENABLED */
+/* #define HAL_CAN_MODULE_ENABLED */
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_FMPI2C_MODULE_ENABLED */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE            3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            15U   /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t))    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t))  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t))  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+#include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+#include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+#include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+#include "stm32f4xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+#include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+#include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+#include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+#include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+#include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+#include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+#include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Inc/stm32f4xx_it.h

@@ -0,0 +1,66 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Src/main.c

@@ -0,0 +1,240 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+
+    /* USER CODE BEGIN 1 */
+
+    /* USER CODE END 1 */
+
+    /* MCU Configuration--------------------------------------------------------*/
+
+    /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+    HAL_Init();
+
+    /* USER CODE BEGIN Init */
+
+    /* USER CODE END Init */
+
+    /* Configure the system clock */
+    SystemClock_Config();
+
+    /* USER CODE BEGIN SysInit */
+
+    /* USER CODE END SysInit */
+
+    /* Initialize all configured peripherals */
+    MX_GPIO_Init();
+    MX_USART1_UART_Init();
+    /* USER CODE BEGIN 2 */
+
+    /* USER CODE END 2 */
+
+    /* Infinite loop */
+    /* USER CODE BEGIN WHILE */
+    while (1)
+    {
+        /* USER CODE END WHILE */
+
+        /* USER CODE BEGIN 3 */
+    }
+    /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    /** Configure the main internal regulator output voltage
+    */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /** Initializes the RCC Oscillators according to the specified parameters
+    * in the RCC_OscInitTypeDef structure.
+    */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLM = 8;
+    RCC_OscInitStruct.PLL.PLLN = 168;
+    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+    RCC_OscInitStruct.PLL.PLLQ = 4;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        Error_Handler();
+    }
+
+    /** Initializes the CPU, AHB and APB buses clocks
+    */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+                                  | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
+    {
+        Error_Handler();
+    }
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+    /* USER CODE BEGIN USART1_Init 0 */
+
+    /* USER CODE END USART1_Init 0 */
+
+    /* USER CODE BEGIN USART1_Init 1 */
+
+    /* USER CODE END USART1_Init 1 */
+    huart1.Instance = USART1;
+    huart1.Init.BaudRate = 115200;
+    huart1.Init.WordLength = UART_WORDLENGTH_8B;
+    huart1.Init.StopBits = UART_STOPBITS_1;
+    huart1.Init.Parity = UART_PARITY_NONE;
+    huart1.Init.Mode = UART_MODE_TX_RX;
+    huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+    huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+    if (HAL_UART_Init(&huart1) != HAL_OK)
+    {
+        Error_Handler();
+    }
+    /* USER CODE BEGIN USART1_Init 2 */
+
+    /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+    /* USER CODE BEGIN MX_GPIO_Init_1 */
+
+    /* USER CODE END MX_GPIO_Init_1 */
+
+    /* GPIO Ports Clock Enable */
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+
+    /* USER CODE BEGIN MX_GPIO_Init_2 */
+
+    /* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+    /* USER CODE BEGIN Error_Handler_Debug */
+    /* User can add his own implementation to report the HAL error return state */
+    __disable_irq();
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler_Debug */
+}
+#ifdef USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+    /* USER CODE BEGIN 6 */
+    /* User can add his own implementation to report the file name and line number,
+       ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+    /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c

@@ -0,0 +1,148 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32f4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+#include <drv_common.h>
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+
+    /* USER CODE BEGIN MspInit 0 */
+
+    /* USER CODE END MspInit 0 */
+
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* System interrupt init*/
+
+    /* USER CODE BEGIN MspInit 1 */
+
+    /* USER CODE END MspInit 1 */
+}
+
+/**
+  * @brief UART MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+    if (huart->Instance == USART1)
+    {
+        /* USER CODE BEGIN USART1_MspInit 0 */
+
+        /* USER CODE END USART1_MspInit 0 */
+        /* Peripheral clock enable */
+        __HAL_RCC_USART1_CLK_ENABLE();
+
+        __HAL_RCC_GPIOA_CLK_ENABLE();
+        /**USART1 GPIO Configuration
+        PA9     ------> USART1_TX
+        PA10     ------> USART1_RX
+        */
+        GPIO_InitStruct.Pin = GPIO_PIN_9 | GPIO_PIN_10;
+        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+        GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        /* USER CODE BEGIN USART1_MspInit 1 */
+
+        /* USER CODE END USART1_MspInit 1 */
+
+    }
+
+}
+
+/**
+  * @brief UART MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+    if (huart->Instance == USART1)
+    {
+        /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+        /* USER CODE END USART1_MspDeInit 0 */
+        /* Peripheral clock disable */
+        __HAL_RCC_USART1_CLK_DISABLE();
+
+        /**USART1 GPIO Configuration
+        PA9     ------> USART1_TX
+        PA10     ------> USART1_RX
+        */
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9 | GPIO_PIN_10);
+
+        /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+        /* USER CODE END USART1_MspDeInit 1 */
+    }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Src/stm32f4xx_it.c

@@ -0,0 +1,203 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+    /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+    /* USER CODE END NonMaskableInt_IRQn 0 */
+    /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+    while (1)
+    {
+    }
+    /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+    /* USER CODE BEGIN HardFault_IRQn 0 */
+
+    /* USER CODE END HardFault_IRQn 0 */
+    while (1)
+    {
+        /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+        /* USER CODE END W1_HardFault_IRQn 0 */
+    }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+    /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+    /* USER CODE END MemoryManagement_IRQn 0 */
+    while (1)
+    {
+        /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+        /* USER CODE END W1_MemoryManagement_IRQn 0 */
+    }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+    /* USER CODE BEGIN BusFault_IRQn 0 */
+
+    /* USER CODE END BusFault_IRQn 0 */
+    while (1)
+    {
+        /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+        /* USER CODE END W1_BusFault_IRQn 0 */
+    }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+    /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+    /* USER CODE END UsageFault_IRQn 0 */
+    while (1)
+    {
+        /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+        /* USER CODE END W1_UsageFault_IRQn 0 */
+    }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+    /* USER CODE BEGIN SVCall_IRQn 0 */
+
+    /* USER CODE END SVCall_IRQn 0 */
+    /* USER CODE BEGIN SVCall_IRQn 1 */
+
+    /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+    /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+    /* USER CODE END DebugMonitor_IRQn 0 */
+    /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+    /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+    /* USER CODE BEGIN PendSV_IRQn 0 */
+
+    /* USER CODE END PendSV_IRQn 0 */
+    /* USER CODE BEGIN PendSV_IRQn 1 */
+
+    /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+    /* USER CODE BEGIN SysTick_IRQn 0 */
+
+    /* USER CODE END SysTick_IRQn 0 */
+    HAL_IncTick();
+    /* USER CODE BEGIN SysTick_IRQn 1 */
+
+    /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f4xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */

bsp/stm32/stm32f407-micu/board/CubeMX_Config/Src/system_stm32f4xx.c

@@ -0,0 +1,747 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+
+#include "stm32f4xx.h"
+
+#if !defined  (HSE_VALUE)
+    #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+    #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+    || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+    || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+    /* #define DATA_IN_ExtSRAM */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
+STM32F412Zx || STM32F412Vx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+    || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    /* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
+STM32F479xx */
+
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in Flash or Sram, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+    /*!< Uncomment the following line if you need to relocate your vector Table
+    in Sram else user remap will be done in Flash. */
+    /* #define VECT_TAB_SRAM */
+    #if defined(VECT_TAB_SRAM)
+        #define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
+        This value must be a multiple of 0x200. */
+    #else
+        #define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
+        This value must be a multiple of 0x200. */
+    #endif /* VECT_TAB_SRAM */
+    #if !defined(VECT_TAB_OFFSET)
+        #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table offset field.
+        This value must be a multiple of 0x200. */
+    #endif /* VECT_TAB_OFFSET */
+#endif /* USER_VECT_TAB_ADDRESS */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+/* This variable is updated in three ways:
+    1) by calling CMSIS function SystemCoreClockUpdate()
+    2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+    3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+       Note: If you use this function to configure the system clock; then there
+             is no need to call the 2 first functions listed above, since SystemCoreClock
+             variable is updated automatically.
+*/
+uint32_t SystemCoreClock = 16000000;
+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting, vector table location and External memory
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+    /* Configure the Vector Table location -------------------------------------*/
+#if defined(USER_VECT_TAB_ADDRESS)
+    SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t tmp, pllvco, pllp, pllsource, pllm;
+
+    /* Get SYSCLK source -------------------------------------------------------*/
+    tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+    switch (tmp)
+    {
+    case 0x00:  /* HSI used as system clock source */
+        SystemCoreClock = HSI_VALUE;
+        break;
+    case 0x04:  /* HSE used as system clock source */
+        SystemCoreClock = HSE_VALUE;
+        break;
+    case 0x08:  /* PLL used as system clock source */
+
+        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+           SYSCLK = PLL_VCO / PLL_P
+           */
+        pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+        pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+        if (pllsource != 0)
+        {
+            /* HSE used as PLL clock source */
+            pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+        }
+        else
+        {
+            /* HSI used as PLL clock source */
+            pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+        }
+
+        pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 16) + 1) * 2;
+        SystemCoreClock = pllvco / pllp;
+        break;
+    default:
+        SystemCoreClock = HSI_VALUE;
+        break;
+    }
+    /* Compute HCLK frequency --------------------------------------------------*/
+    /* Get HCLK prescaler */
+    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+    /* HCLK frequency */
+    SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+    __IO uint32_t tmp = 0x00;
+
+    register uint32_t tmpreg = 0, timeout = 0xFFFF;
+    register __IO uint32_t index;
+
+    /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+    RCC->AHB1ENR |= 0x000001F8;
+
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0]  = 0x00CCC0CC;
+    GPIOD->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER   = 0xAAAA0A8A;
+    /* Configure PDx pins speed to 100 MHz */
+    GPIOD->OSPEEDR = 0xFFFF0FCF;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR   = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0]  = 0xC00CC0CC;
+    GPIOE->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER   = 0xAAAA828A;
+    /* Configure PEx pins speed to 100 MHz */
+    GPIOE->OSPEEDR = 0xFFFFC3CF;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR   = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0]  = 0xCCCCCCCC;
+    GPIOF->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER   = 0xAA800AAA;
+    /* Configure PFx pins speed to 50 MHz */
+    GPIOF->OSPEEDR = 0xAA800AAA;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR   = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0]  = 0xCCCCCCCC;
+    GPIOG->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER   = 0xAAAAAAAA;
+    /* Configure PGx pins speed to 50 MHz */
+    GPIOG->OSPEEDR = 0xAAAAAAAA;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR   = 0x00000000;
+
+    /* Connect PHx pins to FMC Alternate function */
+    GPIOH->AFR[0]  = 0x00C0CC00;
+    GPIOH->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PHx pins in Alternate function mode */
+    GPIOH->MODER   = 0xAAAA08A0;
+    /* Configure PHx pins speed to 50 MHz */
+    GPIOH->OSPEEDR = 0xAAAA08A0;
+    /* Configure PHx pins Output type to push-pull */
+    GPIOH->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PHx pins */
+    GPIOH->PUPDR   = 0x00000000;
+
+    /* Connect PIx pins to FMC Alternate function */
+    GPIOI->AFR[0]  = 0xCCCCCCCC;
+    GPIOI->AFR[1]  = 0x00000CC0;
+    /* Configure PIx pins in Alternate function mode */
+    GPIOI->MODER   = 0x0028AAAA;
+    /* Configure PIx pins speed to 50 MHz */
+    GPIOI->OSPEEDR = 0x0028AAAA;
+    /* Configure PIx pins Output type to push-pull */
+    GPIOI->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PIx pins */
+    GPIOI->PUPDR   = 0x00000000;
+
+    /*-- FMC Configuration -------------------------------------------------------*/
+    /* Enable the FMC interface clock */
+    RCC->AHB3ENR |= 0x00000001;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+    FMC_Bank5_6->SDCR[0] = 0x000019E4;
+    FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+    /* SDRAM initialization sequence */
+    /* Clock enable command */
+    FMC_Bank5_6->SDCMR = 0x00000011;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Delay */
+    for (index = 0; index < 1000; index++);
+
+    /* PALL command */
+    FMC_Bank5_6->SDCMR = 0x00000012;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Auto refresh command */
+    FMC_Bank5_6->SDCMR = 0x00000073;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* MRD register program */
+    FMC_Bank5_6->SDCMR = 0x00046014;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Set refresh count */
+    tmpreg = FMC_Bank5_6->SDRTR;
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
+
+    /* Disable write protection */
+    tmpreg = FMC_Bank5_6->SDCR[0];
+    FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2]  = 0x00001011;
+    FMC_Bank1->BTCR[3]  = 0x00000201;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2]  = 0x00001091;
+    FMC_Bank1->BTCR[3]  = 0x00110212;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+
+    (void)(tmp);
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external memories (SRAM/SDRAM)
+  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+    __IO uint32_t tmp = 0x00;
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined (DATA_IN_ExtSDRAM)
+    register uint32_t tmpreg = 0, timeout = 0xFFFF;
+    register __IO uint32_t index;
+
+#if defined(STM32F446xx)
+    /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
+        clock */
+    RCC->AHB1ENR |= 0x0000007D;
+#else
+    /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+        clock */
+    RCC->AHB1ENR |= 0x000001F8;
+#endif /* STM32F446xx */
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
+
+#if defined(STM32F446xx)
+    /* Connect PAx pins to FMC Alternate function */
+    GPIOA->AFR[0]  |= 0xC0000000;
+    GPIOA->AFR[1]  |= 0x00000000;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOA->MODER   |= 0x00008000;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOA->OSPEEDR |= 0x00008000;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOA->OTYPER  |= 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOA->PUPDR   |= 0x00000000;
+
+    /* Connect PCx pins to FMC Alternate function */
+    GPIOC->AFR[0]  |= 0x00CC0000;
+    GPIOC->AFR[1]  |= 0x00000000;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOC->MODER   |= 0x00000A00;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOC->OSPEEDR |= 0x00000A00;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOC->OTYPER  |= 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOC->PUPDR   |= 0x00000000;
+#endif /* STM32F446xx */
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0]  = 0x000000CC;
+    GPIOD->AFR[1]  = 0xCC000CCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER   = 0xA02A000A;
+    /* Configure PDx pins speed to 50 MHz */
+    GPIOD->OSPEEDR = 0xA02A000A;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR   = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0]  = 0xC00000CC;
+    GPIOE->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER   = 0xAAAA800A;
+    /* Configure PEx pins speed to 50 MHz */
+    GPIOE->OSPEEDR = 0xAAAA800A;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR   = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0]  = 0xCCCCCCCC;
+    GPIOF->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER   = 0xAA800AAA;
+    /* Configure PFx pins speed to 50 MHz */
+    GPIOF->OSPEEDR = 0xAA800AAA;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR   = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0]  = 0xCCCCCCCC;
+    GPIOG->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER   = 0xAAAAAAAA;
+    /* Configure PGx pins speed to 50 MHz */
+    GPIOG->OSPEEDR = 0xAAAAAAAA;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR   = 0x00000000;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx)
+    /* Connect PHx pins to FMC Alternate function */
+    GPIOH->AFR[0]  = 0x00C0CC00;
+    GPIOH->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PHx pins in Alternate function mode */
+    GPIOH->MODER   = 0xAAAA08A0;
+    /* Configure PHx pins speed to 50 MHz */
+    GPIOH->OSPEEDR = 0xAAAA08A0;
+    /* Configure PHx pins Output type to push-pull */
+    GPIOH->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PHx pins */
+    GPIOH->PUPDR   = 0x00000000;
+
+    /* Connect PIx pins to FMC Alternate function */
+    GPIOI->AFR[0]  = 0xCCCCCCCC;
+    GPIOI->AFR[1]  = 0x00000CC0;
+    /* Configure PIx pins in Alternate function mode */
+    GPIOI->MODER   = 0x0028AAAA;
+    /* Configure PIx pins speed to 50 MHz */
+    GPIOI->OSPEEDR = 0x0028AAAA;
+    /* Configure PIx pins Output type to push-pull */
+    GPIOI->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PIx pins */
+    GPIOI->PUPDR   = 0x00000000;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+    /*-- FMC Configuration -------------------------------------------------------*/
+    /* Enable the FMC interface clock */
+    RCC->AHB3ENR |= 0x00000001;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+
+    /* Configure and enable SDRAM bank1 */
+#if defined(STM32F446xx)
+    FMC_Bank5_6->SDCR[0] = 0x00001954;
+#else
+    FMC_Bank5_6->SDCR[0] = 0x000019E4;
+#endif /* STM32F446xx */
+    FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+    /* SDRAM initialization sequence */
+    /* Clock enable command */
+    FMC_Bank5_6->SDCMR = 0x00000011;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Delay */
+    for (index = 0; index < 1000; index++);
+
+    /* PALL command */
+    FMC_Bank5_6->SDCMR = 0x00000012;
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Auto refresh command */
+#if defined(STM32F446xx)
+    FMC_Bank5_6->SDCMR = 0x000000F3;
+#else
+    FMC_Bank5_6->SDCMR = 0x00000073;
+#endif /* STM32F446xx */
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* MRD register program */
+#if defined(STM32F446xx)
+    FMC_Bank5_6->SDCMR = 0x00044014;
+#else
+    FMC_Bank5_6->SDCMR = 0x00046014;
+#endif /* STM32F446xx */
+    tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    timeout = 0xFFFF;
+    while ((tmpreg != 0) && (timeout-- > 0))
+    {
+        tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+    }
+
+    /* Set refresh count */
+    tmpreg = FMC_Bank5_6->SDRTR;
+#if defined(STM32F446xx)
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C << 1));
+#else
+    FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C << 1));
+#endif /* STM32F446xx */
+
+    /* Disable write protection */
+    tmpreg = FMC_Bank5_6->SDCR[0];
+    FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
+ || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
+ || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
+
+#if defined(DATA_IN_ExtSRAM)
+    /*-- GPIOs Configuration -----------------------------------------------------*/
+    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+    RCC->AHB1ENR   |= 0x00000078;
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+
+    /* Connect PDx pins to FMC Alternate function */
+    GPIOD->AFR[0]  = 0x00CCC0CC;
+    GPIOD->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PDx pins in Alternate function mode */
+    GPIOD->MODER   = 0xAAAA0A8A;
+    /* Configure PDx pins speed to 100 MHz */
+    GPIOD->OSPEEDR = 0xFFFF0FCF;
+    /* Configure PDx pins Output type to push-pull */
+    GPIOD->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PDx pins */
+    GPIOD->PUPDR   = 0x00000000;
+
+    /* Connect PEx pins to FMC Alternate function */
+    GPIOE->AFR[0]  = 0xC00CC0CC;
+    GPIOE->AFR[1]  = 0xCCCCCCCC;
+    /* Configure PEx pins in Alternate function mode */
+    GPIOE->MODER   = 0xAAAA828A;
+    /* Configure PEx pins speed to 100 MHz */
+    GPIOE->OSPEEDR = 0xFFFFC3CF;
+    /* Configure PEx pins Output type to push-pull */
+    GPIOE->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PEx pins */
+    GPIOE->PUPDR   = 0x00000000;
+
+    /* Connect PFx pins to FMC Alternate function */
+    GPIOF->AFR[0]  = 0x00CCCCCC;
+    GPIOF->AFR[1]  = 0xCCCC0000;
+    /* Configure PFx pins in Alternate function mode */
+    GPIOF->MODER   = 0xAA000AAA;
+    /* Configure PFx pins speed to 100 MHz */
+    GPIOF->OSPEEDR = 0xFF000FFF;
+    /* Configure PFx pins Output type to push-pull */
+    GPIOF->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PFx pins */
+    GPIOF->PUPDR   = 0x00000000;
+
+    /* Connect PGx pins to FMC Alternate function */
+    GPIOG->AFR[0]  = 0x00CCCCCC;
+    GPIOG->AFR[1]  = 0x000000C0;
+    /* Configure PGx pins in Alternate function mode */
+    GPIOG->MODER   = 0x00085AAA;
+    /* Configure PGx pins speed to 100 MHz */
+    GPIOG->OSPEEDR = 0x000CAFFF;
+    /* Configure PGx pins Output type to push-pull */
+    GPIOG->OTYPER  = 0x00000000;
+    /* No pull-up, pull-down for PGx pins */
+    GPIOG->PUPDR   = 0x00000000;
+
+    /*-- FMC/FSMC Configuration --------------------------------------------------*/
+    /* Enable the FMC/FSMC interface clock */
+    RCC->AHB3ENR         |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2]  = 0x00001011;
+    FMC_Bank1->BTCR[3]  = 0x00000201;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FMC_Bank1->BTCR[2]  = 0x00001091;
+    FMC_Bank1->BTCR[3]  = 0x00110212;
+    FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F469xx || STM32F479xx */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
+   || defined(STM32F412Zx) || defined(STM32F412Vx)
+    /* Delay after an RCC peripheral clock enabling */
+    tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
+    /* Configure and enable Bank1_SRAM2 */
+    FSMC_Bank1->BTCR[2]  = 0x00001011;
+    FSMC_Bank1->BTCR[3]  = 0x00000201;
+    FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */
+    (void)(tmp);
+}
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */