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[bsp/xuantie] 添加E901BSP #10836

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This commit is contained in:
WangShun
2025-10-29 13:31:38 +08:00
committed by GitHub
parent 6a9a1df437
commit e4f014eb96
46 changed files with 7057 additions and 240 deletions
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1
.github/ALL_BSP_COMPILE.json vendored
View File

@@ -482,6 +482,7 @@
"RTT_BSP": "xuantie",
"RTT_TOOL_CHAIN": "sourcery-Xuantie-900-gcc-elf-newlib",
"SUB_RTT_BSP": [
"xuantie/smartl/e901",
"xuantie/smartl/e902",
"xuantie/smartl/e906",
"xuantie/smartl/e907",

8
.github/workflows/bsp_buildings.yml vendored
View File

@@ -177,10 +177,10 @@ jobs:
- name: Install Xuantie-900-gcc-elf-newlib Tools
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-Xuantie-900-gcc-elf-newlib' && success() }}
run: |
wget -q https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1744884010580/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2-20250410.tar.gz
sudo tar -zxvf Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2-20250410.tar.gz -C /opt
/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2/bin/riscv64-unknown-elf-gcc --version
echo "RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.0.2/bin" >> $GITHUB_ENV
wget -q https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1751370399722/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz
sudo tar -zxvf Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0-20250627.tar.gz -C /opt
/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin/riscv64-unknown-elf-gcc --version
echo "RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V3.2.0/bin" >> $GITHUB_ENV
- name: Install Xuantie-900-gcc-linux-musl Tools
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-Xuantie-900-gcc-linux-musl' && success() }}

268
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl_lite.ld Normal file
View File

@@ -0,0 +1,268 @@
/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file gcc_csky.ld
* @brief csky linker file
* @version V1.0
* @date 02. June 2017
******************************************************************************/
MEMORY
{
ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000 /* ISRAM 128KB*/
DSRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000 /* DSRAM 512KB*/
SRAM : ORIGIN = 0x60000000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/
}
__min_heap_size = 0x200;
PROVIDE (__ram_end = 0x20080000);
PROVIDE (__heap_end = __ram_end);
REGION_ALIAS("REGION_TEXT", ISRAM);
REGION_ALIAS("REGION_RODATA", ISRAM);
REGION_ALIAS("REGION_DATA", DSRAM);
REGION_ALIAS("REGION_BSS", DSRAM);
ENTRY(Reset_Handler)
SECTIONS
{
.text : {
. = ALIGN(0x4) ;
__stext = . ;
KEEP(*startup.o(*.text))
KEEP(*startup.o(*.vectors))
KEEP(*vectors.o(*.text))
KEEP(*(.text.entry))
*(.text*)
*(.gnu.warning)
*(.stub)
*(.gnu.linkonce.t*)
*(.glue_7t)
*(.glue_7)
*(.jcr)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN (0x4) ;
PROVIDE(__ctbp = .);
*(.call_table_data)
*(.call_table_text)
. = ALIGN(0x10) ;
__etext = . ;
} > REGION_TEXT
.eh_frame_hdr : {
*(.eh_frame_hdr)
} > REGION_TEXT
.eh_frame : ONLY_IF_RO {
KEEP (*(.eh_frame))
} > REGION_TEXT
.rodata : {
. = ALIGN(0x4) ;
__srodata = .;
*(.rdata)
*(.rdata*)
*(.rdata1)
*(.rdata.*)
*(.rodata*)
*(.srodata*)
. = ALIGN(0x4) ;
__init_array_start = .;
__ctors_start__ = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
__ctors_end__ = .;
__fini_array_start = .;
__dtors_start__ = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
__dtors_end__ = .;
. = ALIGN(0x4) ;
__ctor_start__ = .;
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__ctor_end__ = .;
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__dtor_end__ = .;
. = ALIGN(0x4) ;
/*****************************************/
/* section information for finsh shell */
. = ALIGN(0x4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(0x4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(0x4);
/* section information for initial. */
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(0x4) ;
/* section information for at utest */
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(0x4);
/* section information for at server */
. = ALIGN(0x4);
__rtatcmdtab_start = .;
KEEP(*(RtAtCmdTab))
__rtatcmdtab_end = .;
. = ALIGN(0x4);
/* section information for modules */
. = ALIGN(0x4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for uPRC */
. = ALIGN(0x4);
__uRPCSvcTab_start = .;
KEEP(*(uRPCSvcTab))
__uRPCSvcTab_end = .;
/* section information for var export */
. = ALIGN(0x4);
__ve_table_start = .;
KEEP(*(SORT(*.VarExpTab.*)))
__ve_table_end = .;
/*****************************************/
/************** added drivers **************/
_cli_region_begin = .;
KEEP(*(CliRegion))
. = ALIGN(0x4);
_cli_region_end = .;
__core_driver_start__ = .;
KEEP(*(.core_driver_entry))
. = ALIGN(0x4);
__core_driver_end__ = .;
__bus_driver_start__ = .;
KEEP(*(*.bus_driver_entry))
__bus_driver_end__ = .;
__early_driver_start__ = .;
KEEP(*(*.early_driver_entry))
__early_driver_end__ = .;
__vfs_driver_start__ = .;
KEEP(*(*.vfs_driver_entry))
__vfs_driver_end__ = .;
__level0_driver_start__ = .;
KEEP(*(*.level0_driver_entry))
__level0_driver_end__ = .;
__level1_driver_start__ = .;
KEEP(*(*.level1_driver_entry))
__level1_driver_end__ = .;
__level2_driver_start__ = .;
KEEP(*(*.level2_driver_entry))
__level2_driver_end__ = .;
__level3_driver_start__ = .;
KEEP(*(*.level3_driver_entry))
__level3_driver_end__ = .;
__post_driver_start__ = .;
KEEP(*(*.post_driver_entry))
__post_driver_end__ = .;
/************** end of drivers *********/
. = ALIGN(0x40) ;
__jvt_base$ = .;
KEEP(*(*.riscv.jvt))
. = ALIGN(0x8) ;
__erodata = .;
__rodata_end__ = .;
} > REGION_RODATA
.data : {
. = ALIGN(0x4) ;
__sdata = . ;
__data_start__ = . ;
data_start = . ;
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table*)
__start_init_call = .;
*(.initcall.init)
__stop_init_call = .;
__start_cmd = .;
*(.bootloaddata.cmd)
. = ALIGN(0x4) ;
__stop_cmd = .;
__global_pointer$ = .;
*(.sdata)
*(.sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
*(__libc_atexit)
*(__libc_subinit)
*(__libc_subfreeres)
*(.note.ABI-tag)
. = ALIGN(0x4) ;
__edata = .;
__data_end__ = .;
} > REGION_DATA AT > REGION_RODATA
._ram_code : {
. = ALIGN(0x4) ;
__ram_code_start__ = .;
*(.ram.code*)
. = ALIGN(0x4) ;
__ram_code_end__ = .;
} > REGION_DATA AT > REGION_RODATA
.bss : {
. = ALIGN(0x4) ;
__sbss = ALIGN(0x4) ;
__bss_start__ = . ;
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.dynbss)
*(.bss*)
*(COMMON)
. = ALIGN(0x4) ;
__ebss = . ;
__bss_end__ = .;
__end = . ;
end = . ;
} > REGION_BSS AT > REGION_BSS
._user_heap (NOLOAD): {
. = ALIGN(0x4) ;
*(.stack*)
. = ALIGN(0x4) ;
__heap_start = .;
. += __min_heap_size;
. = ALIGN(0x4) ;
} > REGION_BSS AT > REGION_BSS
}

281
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartm_fixed.ld Normal file
View File

@@ -0,0 +1,281 @@
/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file gcc_csky.ld
* @brief csky linker file
* @version V1.0
* @date 02. June 2017
******************************************************************************/
MEMORY
{
ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000 /* ISRAM 128KB*/
DSRAM : ORIGIN = 0x00100000 , LENGTH = 0x80000 /* DSRAM 512KB*/
SRAM : ORIGIN = 0x001D0000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/
}
__min_heap_size = 0x200;
PROVIDE (__ram_end = 0x00180000);
PROVIDE (__heap_end = __ram_end);
REGION_ALIAS("REGION_TEXT", ISRAM);
REGION_ALIAS("REGION_RODATA", ISRAM);
REGION_ALIAS("REGION_DATA", DSRAM);
REGION_ALIAS("REGION_BSS", DSRAM);
ENTRY(Reset_Handler)
SECTIONS
{
.text : {
. = ALIGN(0x4) ;
__stext = . ;
KEEP(*startup.o(*.text))
} > REGION_TEXT
.mtvec 0x40 : {
KEEP(*vectors.o(*.mtvec))
} > REGION_TEXT
. = MAX(., 0x80);
.vectors 0x80 : {
KEEP(*startup.o(*.vectors))
} > REGION_TEXT
. = MAX(., 0x300);
.text 0x300 : {
__jvt_base$ = .;
KEEP(*(*.riscv.jvt))
. = ALIGN(0x4) ;
__jvt_end$ = .;
} > REGION_TEXT
.text : {
. = ALIGN(0x4) ;
KEEP(*vectors.o(*.text))
KEEP(*(.text.entry))
*(.text*)
*(.gnu.warning)
*(.stub)
*(.gnu.linkonce.t*)
*(.glue_7t)
*(.glue_7)
*(.jcr)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN (0x4) ;
PROVIDE(__ctbp = .);
*(.call_table_data)
*(.call_table_text)
. = ALIGN(0x10) ;
__etext = . ;
} > REGION_TEXT
.eh_frame_hdr : {
*(.eh_frame_hdr)
} > REGION_TEXT
.eh_frame : ONLY_IF_RO {
KEEP (*(.eh_frame))
} > REGION_TEXT
.rodata : {
. = ALIGN(0x4) ;
__srodata = .;
*(.rdata)
*(.rdata*)
*(.rdata1)
*(.rdata.*)
*(.rodata*)
*(.srodata*)
. = ALIGN(0x4) ;
__init_array_start = .;
__ctors_start__ = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
__ctors_end__ = .;
__fini_array_start = .;
__dtors_start__ = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
__dtors_end__ = .;
. = ALIGN(0x4) ;
__ctor_start__ = .;
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__ctor_end__ = .;
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__dtor_end__ = .;
. = ALIGN(0x4) ;
/*****************************************/
/* section information for finsh shell */
. = ALIGN(0x4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(0x4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(0x4);
/* section information for initial. */
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(0x4) ;
/* section information for at utest */
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(0x4);
/* section information for at server */
. = ALIGN(0x4);
__rtatcmdtab_start = .;
KEEP(*(RtAtCmdTab))
__rtatcmdtab_end = .;
. = ALIGN(0x4);
/* section information for modules */
. = ALIGN(0x4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for uPRC */
. = ALIGN(0x4);
__uRPCSvcTab_start = .;
KEEP(*(uRPCSvcTab))
__uRPCSvcTab_end = .;
/* section information for var export */
. = ALIGN(0x4);
__ve_table_start = .;
KEEP(*(SORT(*.VarExpTab.*)))
__ve_table_end = .;
/*****************************************/
/************** added drivers **************/
_cli_region_begin = .;
KEEP(*(CliRegion))
. = ALIGN(0x4);
_cli_region_end = .;
__core_driver_start__ = .;
KEEP(*(.core_driver_entry))
. = ALIGN(0x4);
__core_driver_end__ = .;
__bus_driver_start__ = .;
KEEP(*(*.bus_driver_entry))
__bus_driver_end__ = .;
__early_driver_start__ = .;
KEEP(*(*.early_driver_entry))
__early_driver_end__ = .;
__vfs_driver_start__ = .;
KEEP(*(*.vfs_driver_entry))
__vfs_driver_end__ = .;
__level0_driver_start__ = .;
KEEP(*(*.level0_driver_entry))
__level0_driver_end__ = .;
__level1_driver_start__ = .;
KEEP(*(*.level1_driver_entry))
__level1_driver_end__ = .;
__level2_driver_start__ = .;
KEEP(*(*.level2_driver_entry))
__level2_driver_end__ = .;
__level3_driver_start__ = .;
KEEP(*(*.level3_driver_entry))
__level3_driver_end__ = .;
__post_driver_start__ = .;
KEEP(*(*.post_driver_entry))
__post_driver_end__ = .;
/************** end of drivers *********/
. = ALIGN(0x8) ;
__erodata = .;
__rodata_end__ = .;
} > REGION_RODATA
.data : {
. = ALIGN(0x4) ;
__sdata = . ;
__data_start__ = . ;
data_start = . ;
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table*)
__start_init_call = .;
*(.initcall.init)
__stop_init_call = .;
__start_cmd = .;
*(.bootloaddata.cmd)
. = ALIGN(0x4) ;
__stop_cmd = .;
__global_pointer$ = .;
*(.sdata)
*(.sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
*(__libc_atexit)
*(__libc_subinit)
*(__libc_subfreeres)
*(.note.ABI-tag)
. = ALIGN(0x4) ;
__edata = .;
__data_end__ = .;
} > REGION_DATA AT > REGION_RODATA
._ram_code : {
. = ALIGN(0x4) ;
__ram_code_start__ = .;
*(.ram.code*)
. = ALIGN(0x4) ;
__ram_code_end__ = .;
} > REGION_DATA AT > REGION_RODATA
.bss : {
. = ALIGN(0x4) ;
__sbss = ALIGN(0x4) ;
__bss_start__ = . ;
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.dynbss)
*(.bss*)
*(COMMON)
. = ALIGN(0x4) ;
__ebss = . ;
__bss_end__ = .;
__end = . ;
end = . ;
} > REGION_BSS AT > REGION_BSS
._user_heap (NOLOAD): {
. = ALIGN(0x4) ;
*(.stack*)
. = ALIGN(0x4) ;
__heap_start = .;
. += __min_heap_size;
. = ALIGN(0x4) ;
} > REGION_BSS AT > REGION_BSS
}

273
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartm_flexible.ld Normal file
View File

@@ -0,0 +1,273 @@
/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file gcc_csky.ld
* @brief csky linker file
* @version V1.0
* @date 02. June 2017
******************************************************************************/
MEMORY
{
ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x20000 /* ISRAM 128KB*/
DSRAM : ORIGIN = 0x00100000 , LENGTH = 0x80000 /* DSRAM 512KB*/
SRAM : ORIGIN = 0x001D0000 , LENGTH = 0x20000 /* SRAM 128KB, no cacheable*/
}
__min_heap_size = 0x200;
PROVIDE (__ram_end = 0x00180000);
PROVIDE (__heap_end = __ram_end);
REGION_ALIAS("REGION_TEXT", ISRAM);
REGION_ALIAS("REGION_RODATA", ISRAM);
REGION_ALIAS("REGION_DATA", DSRAM);
REGION_ALIAS("REGION_BSS", DSRAM);
ENTRY(Reset_Handler)
SECTIONS
{
.text : {
. = ALIGN(0x4) ;
__stext = . ;
KEEP(*startup.o(*.text))
KEEP(*startup.o(*.vectors))
. = ALIGN(0x40) ;
KEEP(*vectors.o(*.mtvec))
} > REGION_TEXT
.text : {
. = ALIGN(0x4) ;
KEEP(*vectors.o(*.text))
KEEP(*(.text.entry))
*(.text*)
*(.gnu.warning)
*(.stub)
*(.gnu.linkonce.t*)
*(.glue_7t)
*(.glue_7)
*(.jcr)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN (0x4) ;
PROVIDE(__ctbp = .);
*(.call_table_data)
*(.call_table_text)
. = ALIGN(0x10) ;
__etext = . ;
} > REGION_TEXT
.eh_frame_hdr : {
*(.eh_frame_hdr)
} > REGION_TEXT
.eh_frame : ONLY_IF_RO {
KEEP (*(.eh_frame))
} > REGION_TEXT
.rodata : {
. = ALIGN(0x4) ;
__srodata = .;
*(.rdata)
*(.rdata*)
*(.rdata1)
*(.rdata.*)
*(.rodata*)
*(.srodata*)
. = ALIGN(0x4) ;
__init_array_start = .;
__ctors_start__ = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
__ctors_end__ = .;
__fini_array_start = .;
__dtors_start__ = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
__dtors_end__ = .;
. = ALIGN(0x4) ;
__ctor_start__ = .;
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__ctor_end__ = .;
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__dtor_end__ = .;
. = ALIGN(0x4) ;
/*****************************************/
/* section information for finsh shell */
. = ALIGN(0x4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(0x4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(0x4);
/* section information for initial. */
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(0x4) ;
/* section information for at utest */
__rt_utest_tc_tab_start = .;
KEEP(*(UtestTcTab))
__rt_utest_tc_tab_end = .;
. = ALIGN(0x4);
/* section information for at server */
. = ALIGN(0x4);
__rtatcmdtab_start = .;
KEEP(*(RtAtCmdTab))
__rtatcmdtab_end = .;
. = ALIGN(0x4);
/* section information for modules */
. = ALIGN(0x4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for uPRC */
. = ALIGN(0x4);
__uRPCSvcTab_start = .;
KEEP(*(uRPCSvcTab))
__uRPCSvcTab_end = .;
/* section information for var export */
. = ALIGN(0x4);
__ve_table_start = .;
KEEP(*(SORT(*.VarExpTab.*)))
__ve_table_end = .;
/*****************************************/
/************** added drivers **************/
_cli_region_begin = .;
KEEP(*(CliRegion))
. = ALIGN(0x4);
_cli_region_end = .;
__core_driver_start__ = .;
KEEP(*(.core_driver_entry))
. = ALIGN(0x4);
__core_driver_end__ = .;
__bus_driver_start__ = .;
KEEP(*(*.bus_driver_entry))
__bus_driver_end__ = .;
__early_driver_start__ = .;
KEEP(*(*.early_driver_entry))
__early_driver_end__ = .;
__vfs_driver_start__ = .;
KEEP(*(*.vfs_driver_entry))
__vfs_driver_end__ = .;
__level0_driver_start__ = .;
KEEP(*(*.level0_driver_entry))
__level0_driver_end__ = .;
__level1_driver_start__ = .;
KEEP(*(*.level1_driver_entry))
__level1_driver_end__ = .;
__level2_driver_start__ = .;
KEEP(*(*.level2_driver_entry))
__level2_driver_end__ = .;
__level3_driver_start__ = .;
KEEP(*(*.level3_driver_entry))
__level3_driver_end__ = .;
__post_driver_start__ = .;
KEEP(*(*.post_driver_entry))
__post_driver_end__ = .;
/************** end of drivers *********/
. = ALIGN(0x40) ;
__jvt_base$ = .;
KEEP(*(*.riscv.jvt))
. = ALIGN(0x8) ;
__erodata = .;
__rodata_end__ = .;
} > REGION_RODATA
.data : {
. = ALIGN(0x4) ;
__sdata = . ;
__data_start__ = . ;
data_start = . ;
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table*)
__start_init_call = .;
*(.initcall.init)
__stop_init_call = .;
__start_cmd = .;
*(.bootloaddata.cmd)
. = ALIGN(0x4) ;
__stop_cmd = .;
__global_pointer$ = .;
*(.sdata)
*(.sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
*(__libc_atexit)
*(__libc_subinit)
*(__libc_subfreeres)
*(.note.ABI-tag)
. = ALIGN(0x4) ;
__edata = .;
__data_end__ = .;
} > REGION_DATA AT > REGION_RODATA
._ram_code : {
. = ALIGN(0x4) ;
__ram_code_start__ = .;
*(.ram.code*)
. = ALIGN(0x4) ;
__ram_code_end__ = .;
} > REGION_DATA AT > REGION_RODATA
.bss : {
. = ALIGN(0x4) ;
__sbss = ALIGN(0x4) ;
__bss_start__ = . ;
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.dynbss)
*(.bss*)
*(COMMON)
. = ALIGN(0x4) ;
__ebss = . ;
__bss_end__ = .;
__end = . ;
end = . ;
} > REGION_BSS AT > REGION_BSS
._user_heap (NOLOAD): {
. = ALIGN(0x4) ;
*(.stack*)
. = ALIGN(0x4) ;
__heap_start = .;
. += __min_heap_size;
. = ALIGN(0x4) ;
} > REGION_BSS AT > REGION_BSS
}

13
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/SConscript Normal file
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from building import *
import os
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = ['startup.S']
src += ['system.c']
src += ['trap_c.c']
src += ['vectors.S']
group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

200
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/startup.S Normal file
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/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <csi_config.h>
.global __rt_rvstack
#ifndef CONFIG_SUPPORT_NON_VECTOR_IRQ
.section .vectors, "aw", @progbits
.align 6
.globl __Vectors
.type __Vectors, @object
__Vectors:
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long tspend_handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_IRQHandler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
/* External interrupts */
.long Default_IRQHandler
#if CONFIG_IRQ_LATENCY
.long IRQ_LATENCY_IRQHandler
#else
.long Default_IRQHandler
#endif
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
#else
.section .vectors, "aw", @progbits
.align 6
.globl __Vectors
.type __Vectors, @object
__Vectors:
.long do_irq
.long do_irq
.long do_irq
.long tspend_handler
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
/* External interrupts */
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
.long do_irq
#endif
.text
.align 2
j Reset_Handler
.align 2
.long 0x594B5343 /* CSKY ASCII */
.long 0x594B5343 /* CSKY ASCII */
.align 2
_start:
.text
.globl Reset_Handler
.align 2
.type Reset_Handler, %function
Reset_Handler:
.option push
.option norelax
la gp, __global_pointer$
la a0, __jvt_base$
csrw jvt, a0
.option pop
la a0, Default_Handler
ori a0, a0, 3
csrw mtvec, a0
la a0, __Vectors
csrw mtvt, a0
la sp, g_top_irqstack
csrw mscratch, sp
#ifdef CONFIG_KERNEL_NONE
la sp, g_top_mainstack
#endif
#ifndef __NO_SYSTEM_INIT
jal SystemInit
#endif
jal rtthread_startup
.size Reset_Handler, . - Reset_Handler
__exit:
j __exit
.section .stack, "aw", @nobits
.align 3
.global g_base_irqstack
.global g_top_irqstack
g_base_irqstack:
.space CONFIG_ARCH_INTERRUPTSTACK
g_top_irqstack:
__rt_rvstack:
#ifdef CONFIG_KERNEL_NONE
.align 3
.global g_base_mainstack
.global g_top_mainstack
g_base_mainstack:
.space CONFIG_ARCH_MAINSTACK
g_top_mainstack:
#endif
.section .data
.weak __jvt_base$
.long 0

105
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/system.c Normal file
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/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <csi_config.h>
#include <soc.h>
#include <csi_core.h>
#include <drv/irq.h>
#include <drv/dma.h>
#include <drv/tick.h>
#include <drv/etb.h>
#include <drv/spiflash.h>
#include "riscv_csr.h"
#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE)
#error "Please check the current system is baremetal or not!!!"
#endif
extern void section_data_copy(void);
extern void section_ram_code_copy(void);
extern void section_bss_clear(void);
static void cache_init(void)
{
csi_icache_enable();
}
static void section_init(void)
{
#if CONFIG_XIP
section_data_copy();
section_ram_code_copy();
#endif
section_bss_clear();
}
static void clic_init(void)
{
int i;
/* get interrupt level from info */
CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
for (i = 0; i < 64; i++)
{
CLIC->CLICINT[i].IP = 0;
#ifndef CONFIG_SUPPORT_NON_VECTOR_IRQ
CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
#else
CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */
#endif
csi_vic_set_prio(i, 3);
}
/* tspend use vector&positive interrupt */
CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
csi_vic_set_prio(Machine_Software_IRQn, 1);
csi_irq_enable(Machine_Software_IRQn);
}
static void interrupt_init(void)
{
clic_init();
#ifdef CONFIG_KERNEL_NONE
__enable_excp_irq();
#endif
}
/**
* @brief initialize the system
* Initialize the psr and vbr.
* @param None
* @return None
*/
void SystemInit(void)
{
extern int cpu_features_init(void);
cpu_features_init();
/* enable XUANTIEISAEE & COPINSTEE */
uint32_t status = __get_MXSTATUS();
status |= (1 << 22) | (1 << 24);
__set_MXSTATUS(status);
cache_init();
section_init();
interrupt_init();
soc_set_sys_freq(20000000);
csi_tick_init();
}

67
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/trap_c.c Normal file
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/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <csi_core.h>
#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0)
#include <debug/dbg.h>
#else
#define printk printf
#endif
void (*trap_c_callback)(void);
void trap_c(uintptr_t *regs)
{
int i;
unsigned long vec = 0;
vec = __get_MCAUSE();
printk("CPU Exception(mcause);: NO.0x%lx", vec);
printk("\n");
for (i = 0; i < 15; i++)
{
printk("x%d: %p\t", i + 1, (void *)regs[i]);
if ((i % 4) == 3)
{
printk("\n");
}
}
printk("\n");
printk("mepc : %p\n", (void *)regs[15]);
printk("mstatus: %p\n", (void *)regs[16]);
if (trap_c_callback)
{
trap_c_callback();
}
while (1);
}
__attribute__((weak)) void exceptionHandler(void *context)
{
trap_c((uintptr_t *)context);
}

496
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/arch/e901/vectors.S Normal file
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/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "riscv_asm_macro.h"
#define RISCV_MCAUSE_IRQ_POS 31
#define MSTATUS_IEN 8
.section .stack, "aw", @nobits
.align 2
.global g_trapstackbase
.global g_top_trapstack
g_trapstackbase:
.space CONFIG_ARCH_INTERRUPTSTACK
g_top_trapstack:
#if CONFIG_SUPPORT_IRQ_NESTED
#define IRQ_NESTED_MAX (6)
.section .bss
.align 2
irq_nested_level:
.long 0
irq_nested_mcause:
.long 0, 0, 0, 0, 0, 0
#endif
/* for interrupt tail-chaining debug */
#if CONFIG_DEBUG_TAIL_CHAINING
.global g_irq_tailchain_loops
g_irq_tailchain_loops:
.long 0
#endif
.text
#if !CONFIG_SUPPORT_IRQ_NESTED
.align 2
.weak Default_IRQHandler
.type Default_IRQHandler, %function
Default_IRQHandler:
#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
addi sp, sp, -4
sw s0, (sp)
#endif
csrw mscratch, sp
la sp, g_top_irqstack
addi sp, sp, -52
sw t0, 4(sp)
sw t1, 8(sp)
sw t2, 12(sp)
csrr t0, mepc
csrr t1, mcause
csrr t2, mstatus
sw t1, 40(sp)
sw t0, 44(sp)
sw t2, 48(sp)
sw ra, 0(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw a4, 32(sp)
sw a5, 36(sp)
la t0, do_irq
jalr t0
lw a1, 40(sp)
andi a0, a1, 0x3FF
slli a0, a0, 2
/* clear pending */
li a2, 0xE0801000
add a2, a2, a0
lb a3, 0(a2)
li a4, 1
not a4, a4
and a5, a4, a3
sb a5, 0(a2)
csrw mcause, a1
lw t0, 44(sp)
lw t1, 48(sp)
csrw mepc, t0
csrw mstatus, t1
lw ra, 0(sp)
lw t0, 4(sp)
lw t1, 8(sp)
lw t2, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw a4, 32(sp)
lw a5, 36(sp)
addi sp, sp, 52
csrr sp, mscratch
#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
addi sp, sp, 4
#endif
mret
#else
.align 2
.weak Default_IRQHandler
.type Default_IRQHandler, %function
Default_IRQHandler:
addi sp, sp, -8
sw t0, 0(sp)
sw t1, 4(sp)
la t0, irq_nested_level
lw t1, (t0)
addi t1, t1, 1
sw t1, (t0)
li t0, IRQ_NESTED_MAX
/* nested too deeply, may be error happens */
bgt t1, t0, Default_Handler
addi t1, t1, -1
la t0, irq_nested_mcause
slli t1, t1, 2
add t0, t0, t1
csrr t1, mcause
sw t1, (t0)
la t0, irq_nested_level
lw t1, (t0)
li t0, 1
bgt t1, t0, .Lnested1
#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
addi sp, sp, -8
sw s0, (sp)
csrr t0, mepc
sw t0, 4(sp)
#endif
csrw mscratch, sp
la sp, g_top_irqstack
j .Lnested2
.Lnested1:
lw t0, 0(sp)
lw t1, 4(sp)
addi sp, sp, 8
.Lnested2:
addi sp, sp, -52
sw t0, 4(sp)
sw t1, 8(sp)
sw t2, 12(sp)
csrr t0, mepc
csrr t1, mcause
csrr t2, mstatus
sw t1, 40(sp)
sw t0, 44(sp)
sw t2, 48(sp)
csrs mstatus, 8
sw ra, 0(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw a4, 32(sp)
sw a5, 36(sp)
la t0, do_irq
jalr t0
csrc mstatus, 8
lw a1, 40(sp)
andi a0, a1, 0x3FF
slli a0, a0, 2
/* clear pending */
li a2, 0xE0801000
add a2, a2, a0
lb a3, 0(a2)
li a4, 1
not a4, a4
and a5, a4, a3
sb a5, 0(a2)
la t0, irq_nested_level
lw t1, (t0)
addi t1, t1, -1
sw t1, (t0)
bgt t1, zero, .Lnested3
csrw mcause, a1
lw t0, 44(sp)
lw t1, 48(sp)
csrw mepc, t0
csrw mstatus, t1
lw ra, 0(sp)
lw t0, 4(sp)
lw t1, 8(sp)
lw t2, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw a4, 32(sp)
lw a5, 36(sp)
addi sp, sp, 52
csrr sp, mscratch
#if CONFIG_PROFILING_PERF && CONFIG_PERF_BACKTRACE_USE_FP
addi sp, sp, 8
#endif
lw t0, 0(sp)
lw t1, 4(sp)
addi sp, sp, 8
mret
.Lnested3:
/* keep mpil in current mcause & load exception code before */
addi t1, t1, -1
la t0, irq_nested_mcause
slli t1, t1, 2
add t1, t0, t1
lw t0, (t1)
andi t0, t0, 0x3FF
andi a0, a1, 0xFFFFFC00
or t0, a0, t0
csrw mcause, t0
lw t0, 44(sp)
lw t1, 48(sp)
csrw mepc, t0
csrw mstatus, t1
lw ra, 0(sp)
lw t0, 4(sp)
lw t1, 8(sp)
lw t2, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw a4, 32(sp)
lw a5, 36(sp)
addi sp, sp, 52
mret
#endif
.size Default_IRQHandler, . - Default_IRQHandler
/******************************************************************************
* Functions:
* void trap(void);
* default exception handler
******************************************************************************/
.align 2
.global trap
.type trap, %function
trap:
csrw mscratch, sp
la sp, g_top_trapstack
addi sp, sp, -76
sw x1, (0 )(sp)
sw x3, (8 )(sp)
sw x4, (12)(sp)
sw x5, (16)(sp)
sw x6, (20)(sp)
sw x7, (24)(sp)
sw x8, (28)(sp)
sw x9, (32)(sp)
sw x10,(36)(sp)
sw x11,(40)(sp)
sw x12,(44)(sp)
sw x13,(48)(sp)
sw x14,(52)(sp)
sw x15,(56)(sp)
csrr a0, mepc
sw a0, (60)(sp)
csrr a0, mstatus
sw a0, (64)(sp)
csrr a0, mcause
sw a0, (68)(sp)
csrr a0, mtval
sw a0, (72)(sp)
csrr a0, mscratch
sw a0, (4 )(sp)
mv a0, sp
la a1, exceptionHandler
jalr a1
.size trap, . - trap
.align 6
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
/* Check for nmi */
addi sp, sp, -8
sw t0, 0x0(sp)
sw t1, 0x4(sp)
csrr t0, mcause
#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED)
srli t1, t0, RISCV_MCAUSE_IRQ_POS
bnez t1, is_interrupt
#endif
andi t0, t0, 0x3FF
li t1, 24
beq t0, t1, .NMI_Handler
lw t0, 0x0(sp)
lw t1, 0x4(sp)
addi sp, sp, 8
j trap
#if (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED)
is_interrupt:
lw t0, 0x0(sp)
lw t1, 0x4(sp)
addi sp, sp, 8
csrw mscratch, sp
la sp, g_top_irqstack
addi sp, sp, -52
sw t0, 4(sp)
sw t1, 8(sp)
sw t2, 12(sp)
csrr t0, mepc
csrr t1, mcause
csrr t2, mstatus
sw t1, 40(sp)
sw t0, 44(sp)
sw t2, 48(sp)
sw ra, 0(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw a4, 32(sp)
sw a5, 36(sp)
#if CONFIG_DEBUG_TAIL_CHAINING
li t2, 0
la t1, g_irq_tailchain_loops
sw t2, 0(t1)
#endif
csrrsi t0, mnxti, MSTATUS_IEN
beqz t0, irq_done
irq_loop:
#if CONFIG_DEBUG_TAIL_CHAINING
la t2, g_irq_tailchain_loops
lw t1, 0(t2)
addi t1, t1, 1
sw t1, 0(t2)
#endif
lw t1, 0(t0)
jalr t1
csrrsi t0, mnxti, MSTATUS_IEN
bnez t0, irq_loop
#if CONFIG_DEBUG_TAIL_CHAINING
li t2, 0
la a1, g_irq_tailchain_loops
sw t2, 0(a1)
#endif
irq_done:
lw t0, 40(sp)
lw t1, 44(sp)
lw t2, 48(sp)
csrw mcause, t0
csrw mepc, t1
csrw mstatus, t2
lw ra, 0(sp)
lw t0, 4(sp)
lw t1, 8(sp)
lw t2, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw a4, 32(sp)
lw a5, 36(sp)
addi sp, sp, 52
csrr sp, mscratch
mret
#endif /* (CONFIG_SUPPORT_NON_VECTOR_IRQ) && (!CONFIG_SUPPORT_IRQ_NESTED) */
.NMI_Handler:
/* mscratch may be used before */
addi sp, sp, -4
csrr t0, mscratch
sw t0, 0x0(sp)
csrw mscratch, sp
la sp, g_top_trapstack
addi sp, sp, -52
sw t0, 4(sp)
sw t1, 8(sp)
sw t2, 12(sp)
csrr t0, mepc
csrr t1, mcause
csrr t2, mstatus
sw t1, 40(sp)
sw t0, 44(sp)
sw t2, 48(sp)
sw ra, 0(sp)
sw a0, 16(sp)
sw a1, 20(sp)
sw a2, 24(sp)
sw a3, 28(sp)
sw a4, 32(sp)
sw a5, 36(sp)
la t0, handle_nmi_exception
jalr t0
lw a1, 40(sp)
andi a0, a1, 0x3FF
slli a0, a0, 2
/* clear pending */
li a2, 0xE0801000
add a2, a2, a0
lb a3, 0(a2)
li a4, 1
not a4, a4
and a5, a4, a3
sb a5, 0(a2)
csrw mcause, a1
lw t0, 44(sp)
lw t1, 48(sp)
csrw mepc, t0
csrw mstatus, t1
lw ra, 0(sp)
lw t0, 4(sp)
lw t1, 8(sp)
lw t2, 12(sp)
lw a0, 16(sp)
lw a1, 20(sp)
lw a2, 24(sp)
lw a3, 28(sp)
lw a4, 32(sp)
lw a5, 36(sp)
addi sp, sp, 52
csrr sp, mscratch
/* restore mscratch */
lw t0, 0x0(sp)
csrw mscratch, t0
addi sp, sp, 4
lw t0, 0x0(sp)
lw t1, 0x4(sp)
addi sp, sp, 8
mret
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler tspend_handler

1
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/SConscript
View File

@@ -9,6 +9,7 @@ src += ['sys_clk.c']
src += ['tick.c']
src += ['target_get.c']
src += ['devices.c']
src += ['feature.c']
group = DefineGroup('sys', src, depend = [''], CPPPATH = CPPPATH)

319
bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/src/sys/feature.c Normal file
View File

@@ -0,0 +1,319 @@
/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <csi_core.h>
/* I/D Cache will enable in cache_init */
void cpu_features_init(void)
{
#if CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP
return;
#endif
#if CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP
return;
#endif
#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT
return;
#endif
#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP
rv_csr_write(CSR_MXSTATUS, 0x440800);
rv_csr_write(CSR_MHCR, 0x103f & (~0x3));
return;
#endif
#if CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP
rv_csr_write(CSR_MXSTATUS, 0x440800);
rv_csr_write(CSR_MHINT, 0x600c);
rv_csr_write(CSR_MHCR, 0x103f & (~0x3));
return;
#endif
volatile unsigned int i, cpu_type, cpu_ver, cpu_tnmodel;
unsigned long version[8];
/* As CPUID is a fifo register, try to find
* the CPUID[0] whose index(bit[31:28]) == 0 */
for (i = 0; i < 8; i++)
{
version[0] = rv_csr_read(CSR_MCPUID);
if (((version[0]&0xf0000000) >> 28) == 0)
break;
}
for (i = 1; i < 8; i++)
version[i] = rv_csr_read(CSR_MCPUID);
cpu_type = (version[0] >> 18) & 0xf;
cpu_tnmodel = (version[0] >> 14) & 0x1;
cpu_ver = (version[1] >> 12) & 0xffff;
rv_csr_write(CSR_MCOR, 0x70013);
/*
* Warning: CSR_MCCR2 contains an L2 cache latency setting,
* you need to confirm it by your own soc design.
*/
switch (cpu_type)
{
case 0x1:
if (cpu_ver >= 0x0)
{
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x1ee30c);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
rv_csr_write(CSR_MHINT2,0x180);
} else {
while(1);
}
break;
case 0x2:
if (cpu_ver >= 0x0)
{
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xa042000a);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x21aa10c);
rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3));
rv_csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
case 0x3:
if (cpu_ver >= 0x1080 && cpu_ver <= 0x10bf)
{ /* 1.2.0~1.2.x */
rv_csr_write(CSR_MCCR2, 0xe0010009);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x6e30c);
rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
} else if (cpu_ver == 0x10ca)
{ /* 1.3.10 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe2490009);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x66e30c);
rv_csr_write(CSR_MHCR, 0x17f & (~0x3));
rv_csr_write(CSR_MHINT2, 0x420000);
rv_csr_write(CSR_MHINT4, 0x410);
} else if (cpu_ver >= 0x1100 && cpu_ver <= 0x113f)
{ /* 1.4.0~1.4.x */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe2490009);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x16e30c);
rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
} else if (cpu_ver >= 0x1140 && cpu_ver <= 0x117f)
{ /* 1.5.0~1.5.x */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe2490009);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0xe6e30c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
} else if (cpu_ver >= 0x1180 && cpu_ver <= 0x1183)
{ /* 1.6.0~1.6.3 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x1ee30c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x1ff & (~0x3));
} else if (cpu_ver >= 0x1184 && cpu_ver <= 0x123f)
{ /* 1.6.4~1.8.x */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x1ee30c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0x200e)
{ /* 2.0.0~2.0.14 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x31ea32c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x200f && cpu_ver <= 0x2045)
{ /* 2.0.15~2.1.5 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x11ea32c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x2046 && cpu_ver <= 0x20c3)
{ /* 2.1.6~2.3.3 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x31ea32c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x20c4 && cpu_ver <= 0x2fff)
{ /* 2.3.4~2.x.x */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x31ea32c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
rv_csr_write(CSR_MHINT4, 0x2080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x3000 && cpu_ver <= 0x3fff)
{ /* 3.0.0~3.x.x */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe249000b);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x31ea32c);
rv_csr_write(CSR_MHINT2, 0x180);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
rv_csr_write(CSR_MHINT4, 0x2080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
case 0x4:
if (cpu_ver >= 0x1002 && cpu_ver <= 0xffff)
{
rv_csr_write(CSR_MHCR, 0x17f & (~0x3));
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x650c);
} else {
while(1);
}
break;
case 0x5:
if(cpu_tnmodel == 0)
{ /* c908 */
if (cpu_ver >= 0x0000 && cpu_ver <= 0x0007)
{ /* 0.0.0~0.0.7 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xe0420008);
rv_csr_write(CSR_MXSTATUS, 0x638000);
rv_csr_write(CSR_MHINT, 0x2c50c);
rv_csr_write(CSR_MHCR, 0x11ff & (~0x3));
} else if (cpu_ver >= 0x0040 && cpu_ver <= 0x1002)
{ /* 0.1.0~1.0.2 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xa042000a);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x21aa10c);
rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x1003 && cpu_ver <= 0x100b)
{ /* 1.0.3~1.0.11 */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xa042000a);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x1aa10c);
rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x100c && cpu_ver <= 0x1fff)
{ /* 1.0.12~ */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xa042000a);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x21aa10c);
rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3));
rv_csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else if (cpu_ver >= 0x2000 && cpu_ver <= 0xffff)
{ /* 2.0.0~ */
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xa042000a);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x21aa10c);
rv_csr_write(CSR_MHCR, 0x10011ff & (~0x3));
rv_csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
} else if (cpu_tnmodel == 1)
{
if (cpu_ver >= 0x0)
{
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xA0420002);
rv_csr_write(CSR_MXSTATUS, 0x438100);
rv_csr_write(CSR_MHINT, 0x21AA10C);
rv_csr_write(CSR_MHCR, 0x10011FF & (~0x3));
rv_csr_write(CSR_MHINT4, 0x10000080);
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
} else {
while(1);
}
break;
case 0x6:
if (cpu_ver >= 0x0)
{
rv_csr_write(CSR_MSMPR, 0x1);
rv_csr_write(CSR_MCCR2, 0xA0420002);
rv_csr_write(CSR_MXSTATUS, 0x438000);
rv_csr_write(CSR_MHINT, 0x3A1AA10C);
rv_csr_write(CSR_MHCR, 0x10011BF & (~0x3));
#if __riscv_xlen == 64
rv_csr_write(CSR_MENVCFG, 0x4000000000000000);
#endif
} else {
while(1);
}
break;
default:
/* FIXME: maybe qemu */
break;
}
}

103
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/core_rv32.h
View File

@@ -295,7 +295,13 @@ typedef struct {
#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */
#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \
|| CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \
|| CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP
#define CACHE_INV_ADDR_Pos 4U
#else
#define CACHE_INV_ADDR_Pos 5U
#endif
#define CACHE_INV_ADDR_Msk (0xFFFFFFFFUL << CACHE_INV_ADDR_Pos)
/*@} end of group CSI_CACHE */
@@ -433,8 +439,12 @@ typedef struct {
*/
/* Memory mapping of THEAD CPU */
#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */
#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */
#ifndef CONFIG_TCIP_BASE
#define CONFIG_TCIP_BASE 0xE0000000UL
#endif
#define CORET_BASE (CONFIG_TCIP_BASE + 0x4000UL) /*!< CORET Base Address */
#define CLIC_BASE (CONFIG_TCIP_BASE + 0x800000UL) /*!< CLIC Base Address */
#define SYSMAP_BASE (0xEFFFF000UL) /*!< SYSMAP Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
@@ -471,11 +481,12 @@ __STATIC_INLINE int csi_get_cpu_id(void)
*/
__STATIC_INLINE int csi_get_cache_line_size(void)
{
#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \
|| CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP
return 8;
#if CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \
|| CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \
|| CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP
return 16;
#else
return 4;
return 32;
#endif
}
@@ -546,6 +557,7 @@ __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
__STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk;
__DSB();
}
/**
@@ -556,6 +568,7 @@ __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
__STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk;
__DSB();
}
/**
@@ -568,7 +581,10 @@ __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
__STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits));
uint8_t ctl = CLIC->CLICINT[IRQn].CTL;
ctl <<= nlbits;
ctl >>= nlbits;
CLIC->CLICINT[IRQn].CTL = ctl | (priority << (8 - nlbits));
__DSB();
}
@@ -614,6 +630,7 @@ __STATIC_INLINE uint32_t csi_vic_set_thresh(uint32_t thresh)
CLIC->MINTTHRESH = 0xff << 24;
CLIC->MINTTHRESH = thresh << 24;
__DSB();
return temp;
}
@@ -642,18 +659,22 @@ __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, reg
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
if (idx > 15)
{
return;
}
if (!enable) {
if (!enable)
{
attr.a = (address_matching_e)0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
if (attr.a == ADDRESS_MATCHING_TOR)
{
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
if (size == REGION_SIZE_4B)
{
addr = base_addr >> 2;
attr.a = (address_matching_e)2;
} else {
@@ -693,7 +714,8 @@ __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
__STATIC_INLINE uint32_t _csi_coret_config(unsigned long coret_base, uint32_t ticks, int32_t IRQn)
{
CORET_Type *coret = (CORET_Type *)coret_base;
if ((coret->MTIMECMP != 0) && (coret->MTIMECMP != 0xffffffffffffffff)) {
if ((coret->MTIMECMP != 0) && (coret->MTIMECMP != 0xFFFFFFFFFFFFFFFFULL))
{
coret->MTIMECMP = coret->MTIMECMP + ticks;
} else {
coret->MTIMECMP = coret->MTIME + ticks;
@@ -814,7 +836,8 @@ __ALWAYS_STATIC_INLINE void csi_coret_irq_disable(void)
*/
__STATIC_INLINE uint8_t __get_SYSMAPCFGx(uint32_t idx)
{
switch (idx) {
switch (idx)
{
case 0:
return SYSMAP->SYSMAPCFG0;
case 1:
@@ -844,7 +867,8 @@ __STATIC_INLINE uint8_t __get_SYSMAPCFGx(uint32_t idx)
*/
__STATIC_INLINE void __set_SYSMAPCFGx(uint32_t idx, uint32_t sysmapxcfg)
{
switch (idx) {
switch (idx)
{
case 0:
SYSMAP->SYSMAPCFG0 = sysmapxcfg;
break;
@@ -882,7 +906,8 @@ __STATIC_INLINE void __set_SYSMAPCFGx(uint32_t idx, uint32_t sysmapxcfg)
*/
__STATIC_INLINE uint32_t __get_SYSMAPADDRx(uint32_t idx)
{
switch(idx) {
switch(idx)
{
case 0:
return SYSMAP->SYSMAPADDR0;
case 1:
@@ -912,7 +937,8 @@ __STATIC_INLINE uint32_t __get_SYSMAPADDRx(uint32_t idx)
*/
__STATIC_INLINE void __set_SYSMAPADDRx(uint32_t idx, uint32_t sysmapxaddr)
{
switch (idx) {
switch (idx)
{
case 0:
SYSMAP->SYSMAPADDR0 = sysmapxaddr;
break;
@@ -953,7 +979,8 @@ __STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr,
{
uint32_t addr = 0;
if (idx > 7) {
if (idx > 7)
{
return;
}
@@ -990,16 +1017,15 @@ __STATIC_INLINE int csi_icache_is_enable()
__STATIC_INLINE void csi_icache_enable (void)
{
#if (__ICACHE_PRESENT == 1U)
if (!csi_icache_is_enable()) {
if (!csi_icache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
__ICACHE_IALL();
cache = __get_MHCR();
cache |= CACHE_MHCR_IE_Msk;
__set_MHCR(cache);
__DSB();
__ISB();
}
#endif
}
@@ -1012,16 +1038,15 @@ __STATIC_INLINE void csi_icache_enable (void)
__STATIC_INLINE void csi_icache_disable (void)
{
#if (__ICACHE_PRESENT == 1U)
if (csi_icache_is_enable()) {
if (csi_icache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */
__set_MHCR(cache);
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
}
#endif
}
@@ -1035,10 +1060,8 @@ __STATIC_INLINE void csi_icache_invalid (void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
@@ -1058,17 +1081,16 @@ __STATIC_INLINE int csi_dcache_is_enable()
__STATIC_INLINE void csi_dcache_enable (void)
{
#if (__DCACHE_PRESENT == 1U)
if (!csi_dcache_is_enable()) {
if (!csi_dcache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all dcache */
cache = __get_MHCR();
cache |= CACHE_MHCR_DE_Msk; /* enable dcache */
__set_MHCR(cache);
__DSB();
__ISB();
}
#endif
}
@@ -1081,16 +1103,15 @@ __STATIC_INLINE void csi_dcache_enable (void)
__STATIC_INLINE void csi_dcache_disable (void)
{
#if (__DCACHE_PRESENT == 1U)
if (csi_dcache_is_enable()) {
if (csi_dcache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
__set_MHCR(cache);
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
}
#endif
}
@@ -1104,10 +1125,8 @@ __STATIC_INLINE void csi_dcache_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
@@ -1120,10 +1139,8 @@ __STATIC_INLINE void csi_dcache_clean (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CALL(); /* clean all Cache */
__DSB();
__ISB();
#endif
}
@@ -1136,10 +1153,8 @@ __STATIC_INLINE void csi_dcache_clean_invalid (void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CIALL(); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
@@ -1155,11 +1170,12 @@ __STATIC_INLINE void csi_dcache_invalid_range (unsigned long *addr, size_t dsize
#if (__DCACHE_PRESENT == 1U)
int linesize = csi_get_cache_line_size();
long op_size = dsize + (unsigned long)addr % linesize;
unsigned long op_addr = (unsigned long)addr;
unsigned long op_addr = (unsigned long)addr & CACHE_INV_ADDR_Msk;
__DSB();
while (op_size > 0) {
while (op_size > 0)
{
__DCACHE_IPA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1186,7 +1202,8 @@ __STATIC_INLINE void csi_dcache_clean_range (unsigned long *addr, size_t dsize)
__DSB();
while (op_size > 0) {
while (op_size > 0)
{
__DCACHE_CPA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1209,11 +1226,12 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range (unsigned long *addr, size_t
#if (__DCACHE_PRESENT == 1U)
int linesize = csi_get_cache_line_size();
long op_size = dsize + (unsigned long)addr % linesize;
unsigned long op_addr = (unsigned long) addr;
unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk;
__DSB();
while (op_size > 0) {
while (op_size > 0)
{
__DCACHE_CIPA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1449,3 +1467,4 @@ __STATIC_INLINE void csi_irq_restore(uint32_t irq_state)
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */

164
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/core_rv64.h
View File

@@ -219,7 +219,7 @@ typedef struct {
*/
typedef struct {
uint32_t RESERVED0; /*!< Offset: 0x000 (R/W) CLINT configure register */
uint32_t RESERVED0;
__IOM uint32_t PLIC_PRIO[1023];
__IOM uint32_t PLIC_IP[32];
uint32_t RESERVED1[3972 / 4 - 1];
@@ -403,7 +403,9 @@ typedef struct {
#define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
#if CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \
|| CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP
|| CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \
|| CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT \
|| CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT
#define MCER_ECC_FATAL_Pos 34U
#define MCER_ECC_FATAL_Msk (0x1ULL << MCER_ECC_FATAL_Pos)
@@ -440,7 +442,7 @@ typedef struct {
#define CACHE_MCER2H_RAMID_Msk (0x3ULL << CACHE_MCER2H_RAMID_Pos)
#define CACHE_INV_ADDR_Pos 6U
#define CACHE_INV_ADDR_Msk (0xFFFFFFFFULL << CACHE_INV_ADDR_Pos)
#define CACHE_INV_ADDR_Msk (~((0x1ULL << CACHE_INV_ADDR_Pos) - 1))
enum MCER_FAULT_RAMID {
/* L1 Cache, JTLB and TCM (RAMID of MCER)*/
@@ -462,19 +464,19 @@ enum MCER2_FAULT_RAMID {
/*@} end of group CSI_CACHE */
// MSTATUS Register
#define MSTATUS_TVM_MASK (1L << 20) // mstatus.TVM [20]
#define MSTATUS_MPP_MASK (3L << 11) // mstatus.SPP [11:12]
/* MSTATUS Register */
#define MSTATUS_TVM_MASK (1L << 20) /* mstatus.TVM [20] */
#define MSTATUS_MPP_MASK (3L << 11) /* mstatus.SPP [11:12] */
#ifndef MSTATUS_MPP_M
#define MSTATUS_MPP_M (3L << 11) // Machine mode 11
#define MSTATUS_MPP_M (3L << 11) /* Machine mode 11 */
#endif
#define MSTATUS_MPP_S (1L << 11) // Supervisor mode 01
#define MSTATUS_MPP_U (0L << 11) // User mode 00
#define MSTATUS_MPP_S (1L << 11) /* Supervisor mode 01 */
#define MSTATUS_MPP_U (0L << 11) /* User mode 00 */
// SSTATUS Register
#define SSTATUS_SPP_MASK (3L << 8) // sstatus.SPP [8:9]
#define SSTATUS_SPP_S (1L << 8) // Supervisor mode 01
#define SSTATUS_SPP_U (0L << 8) // User mode 00
/* SSTATUS Register */
#define SSTATUS_SPP_MASK (3L << 8) /* sstatus.SPP [8:9] */
#define SSTATUS_SPP_S (1L << 8) /* Supervisor mode 01 */
#define SSTATUS_SPP_U (0L << 8) /* User mode 00 */
typedef enum {
USER_MODE = 0,
@@ -675,7 +677,8 @@ __STATIC_INLINE void csi_vic_enable_irq(int32_t IRQn)
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
CLIC->CLICINT[IRQn].IE |= CLIC_INTIE_IE_Msk;
@@ -719,7 +722,8 @@ __STATIC_INLINE void csi_vic_disable_irq(int32_t IRQn)
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
CLIC->CLICINT[IRQn].IE &= ~CLIC_INTIE_IE_Msk;
@@ -765,7 +769,8 @@ __STATIC_INLINE uint32_t csi_vic_get_enabled_irq(int32_t IRQn)
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
return (uint32_t)(CLIC->CLICINT[IRQn].IE & CLIC_INTIE_IE_Msk);
@@ -808,7 +813,8 @@ __STATIC_INLINE uint32_t csi_vic_get_pending_irq(int32_t IRQn)
{
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
return (uint32_t)(CLIC->CLICINT[IRQn].IP & CLIC_INTIP_IP_Msk);
@@ -826,14 +832,17 @@ __STATIC_INLINE void csi_vic_set_pending_irq(int32_t IRQn)
{
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
CLIC->CLICINT[IRQn].IP |= CLIC_INTIP_IP_Msk;
__DSB();
return;
}
#endif
plic->PLIC_IP[IRQn/32] = plic->PLIC_IP[IRQn/32] | (0x1 << (IRQn%32));
__DSB();
}
/**
@@ -845,14 +854,17 @@ __STATIC_INLINE void csi_vic_clear_pending_irq(int32_t IRQn)
{
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
CLIC->CLICINT[IRQn].IP &= ~CLIC_INTIP_IP_Msk;
__DSB();
return;
}
#endif
plic->PLIC_H0_SCLAIM = IRQn;
__DSB();
}
/**
@@ -901,16 +913,21 @@ __STATIC_INLINE void csi_vic_set_prio(int32_t IRQn, uint32_t priority)
{
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
CLIC->CLICINT[IRQn].CTL = (CLIC->CLICINT[IRQn].CTL & (~CLIC_INTCFG_PRIO_Msk)) | (priority << (8 - nlbits));
uint8_t ctl = CLIC->CLICINT[IRQn].CTL;
ctl <<= nlbits;
ctl >>= nlbits;
CLIC->CLICINT[IRQn].CTL = ctl | (priority << (8 - nlbits));
__DSB();
return;
}
#endif
plic->PLIC_PRIO[IRQn - 1] = priority;
__DSB();
}
/**
@@ -926,7 +943,8 @@ __STATIC_INLINE uint32_t csi_vic_get_prio(int32_t IRQn)
{
PLIC_Type *plic = (PLIC_Type *)CONFIG_PLIC_BASE;
#if CONFIG_INTC_CLIC_PLIC
if (IRQn > PLIC_IRQ_OFFSET) {
if (IRQn > PLIC_IRQ_OFFSET)
{
IRQn -= PLIC_IRQ_OFFSET;
} else {
uint8_t nlbits = (CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos;
@@ -991,18 +1009,22 @@ __STATIC_INLINE void csi_mpu_config_region(uint32_t idx, uint32_t base_addr, reg
uint8_t pmpxcfg = 0;
uint32_t addr = 0;
if (idx > 15) {
if (idx > 15)
{
return;
}
if (!enable) {
if (!enable)
{
attr.a = (address_matching_e)0;
}
if (attr.a == ADDRESS_MATCHING_TOR) {
if (attr.a == ADDRESS_MATCHING_TOR)
{
addr = base_addr >> 2;
} else {
if (size == REGION_SIZE_4B) {
if (size == REGION_SIZE_4B)
{
addr = base_addr >> 2;
attr.a = (address_matching_e)2;
} else {
@@ -1049,7 +1071,8 @@ __STATIC_INLINE uint32_t _csi_clint_config2(unsigned long coret_base, uint16_t h
uint64_t value = (((uint64_t)(CLINT_TIMECMPn_VAL(&clint->STIMECMPH0, hartid))) << 32) + \
(uint64_t)(CLINT_TIMECMPn_VAL(&clint->STIMECMPL0, hartid));
if ((value != 0) && (value != 0xffffffffffffffff)) {
if ((value != 0) && (value != 0xffffffffffffffff))
{
value = value + (uint64_t)ticks;
} else {
value = __get_MTIME() + ticks;
@@ -1060,7 +1083,8 @@ __STATIC_INLINE uint32_t _csi_clint_config2(unsigned long coret_base, uint16_t h
uint64_t value = (((uint64_t)(CLINT_TIMECMPn_VAL(&clint->MTIMECMPH0, hartid))) << 32) + \
(uint64_t)(CLINT_TIMECMPn_VAL(&clint->MTIMECMPL0, hartid));
if ((value != 0) && (value != 0xffffffffffffffff)) {
if ((value != 0) && (value != 0xffffffffffffffff))
{
value = value + (uint64_t)ticks;
} else {
value = __get_MTIME() + ticks;
@@ -1274,16 +1298,15 @@ __STATIC_INLINE int csi_icache_is_enable()
__STATIC_INLINE void csi_icache_enable(void)
{
#if (__ICACHE_PRESENT == 1U)
if (!csi_icache_is_enable()) {
if (!csi_icache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
__ICACHE_IALL();
cache = __get_MHCR();
cache |= CACHE_MHCR_IE_Msk;
__set_MHCR(cache);
__DSB();
__ISB();
}
#endif
}
@@ -1296,16 +1319,15 @@ __STATIC_INLINE void csi_icache_enable(void)
__STATIC_INLINE void csi_icache_disable(void)
{
#if (__ICACHE_PRESENT == 1U)
if (csi_icache_is_enable()) {
if (csi_icache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~CACHE_MHCR_IE_Msk; /* disable icache */
__set_MHCR(cache);
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
}
#endif
}
@@ -1319,10 +1341,8 @@ __STATIC_INLINE void csi_icache_invalid(void)
{
#if (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
__ICACHE_IALL(); /* invalidate all icache */
__DSB();
__ISB();
#endif
}
@@ -1342,17 +1362,16 @@ __STATIC_INLINE int csi_dcache_is_enable()
__STATIC_INLINE void csi_dcache_enable(void)
{
#if (__DCACHE_PRESENT == 1U)
if (!csi_dcache_is_enable()) {
if (!csi_dcache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all dcache */
cache = __get_MHCR();
cache |= CACHE_MHCR_DE_Msk; /* enable dcache */
__set_MHCR(cache);
__DSB();
__ISB();
}
#endif
}
@@ -1365,16 +1384,15 @@ __STATIC_INLINE void csi_dcache_enable(void)
__STATIC_INLINE void csi_dcache_disable(void)
{
#if (__DCACHE_PRESENT == 1U)
if (csi_dcache_is_enable()) {
if (csi_dcache_is_enable())
{
uint32_t cache;
__DSB();
__ISB();
cache = __get_MHCR();
cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
__set_MHCR(cache);
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
}
#endif
}
@@ -1387,10 +1405,8 @@ __STATIC_INLINE void csi_dcache_invalid(void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_IALL(); /* invalidate all Cache */
__DSB();
__ISB();
#endif
}
@@ -1403,10 +1419,8 @@ __STATIC_INLINE void csi_dcache_clean(void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CALL(); /* clean all Cache */
__DSB();
__ISB();
#endif
}
@@ -1419,10 +1433,8 @@ __STATIC_INLINE void csi_dcache_clean_invalid(void)
{
#if (__DCACHE_PRESENT == 1U)
__DSB();
__ISB();
__DCACHE_CIALL(); /* clean and inv all Cache */
__DSB();
__ISB();
#endif
}
@@ -1437,11 +1449,12 @@ __STATIC_INLINE void csi_dcache_invalid_range(unsigned long *addr, size_t dsize)
#if (__DCACHE_PRESENT == 1U)
int linesize = csi_get_cache_line_size();
long op_size = dsize + (unsigned long)addr % linesize;
unsigned long op_addr = (unsigned long)addr;
unsigned long op_addr = (unsigned long)addr & CACHE_INV_ADDR_Msk;
__DSB();
#if CBO_INSN_SUPPORT
while (op_size > 0) {
while (op_size > 0)
{
__CBO_INVAL(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1450,14 +1463,18 @@ __STATIC_INLINE void csi_dcache_invalid_range(unsigned long *addr, size_t dsize)
cpu_work_mode_t cpu_work_mode;
cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE();
if (cpu_work_mode == MACHINE_MODE) {
while (op_size > 0) {
if (cpu_work_mode == MACHINE_MODE)
{
while (op_size > 0)
{
__DCACHE_IPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
} else if (cpu_work_mode == SUPERVISOR_MODE) {
while (op_size > 0) {
} else if (cpu_work_mode == SUPERVISOR_MODE)
{
while (op_size > 0)
{
__DCACHE_IVA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1487,7 +1504,8 @@ __STATIC_INLINE void csi_dcache_clean_range(unsigned long *addr, size_t dsize)
__DSB();
#if CBO_INSN_SUPPORT
while (op_size > 0) {
while (op_size > 0)
{
__CBO_CLEAN(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1496,14 +1514,18 @@ __STATIC_INLINE void csi_dcache_clean_range(unsigned long *addr, size_t dsize)
cpu_work_mode_t cpu_work_mode;
cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE();
if (cpu_work_mode == MACHINE_MODE) {
while (op_size > 0) {
if (cpu_work_mode == MACHINE_MODE)
{
while (op_size > 0)
{
__DCACHE_CPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
} else if (cpu_work_mode == SUPERVISOR_MODE) {
while (op_size > 0) {
} else if (cpu_work_mode == SUPERVISOR_MODE)
{
while (op_size > 0)
{
__DCACHE_CVA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1528,11 +1550,12 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range(unsigned long *addr, size_t
#if (__DCACHE_PRESENT == 1U)
int linesize = csi_get_cache_line_size();
long op_size = dsize + (unsigned long)addr % linesize;
unsigned long op_addr = (unsigned long) addr;
unsigned long op_addr = (unsigned long) addr & CACHE_INV_ADDR_Msk;
__DSB();
#if CBO_INSN_SUPPORT
while (op_size > 0) {
while (op_size > 0)
{
__CBO_FLUSH(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1541,14 +1564,18 @@ __STATIC_INLINE void csi_dcache_clean_invalid_range(unsigned long *addr, size_t
cpu_work_mode_t cpu_work_mode;
cpu_work_mode = (cpu_work_mode_t)__get_CPU_WORK_MODE();
if (cpu_work_mode == MACHINE_MODE) {
while (op_size > 0) {
if (cpu_work_mode == MACHINE_MODE)
{
while (op_size > 0)
{
__DCACHE_CIPA(op_addr);
op_addr += linesize;
op_size -= linesize;
}
} else if (cpu_work_mode == SUPERVISOR_MODE) {
while (op_size > 0) {
} else if (cpu_work_mode == SUPERVISOR_MODE)
{
while (op_size > 0)
{
__DCACHE_CIVA(op_addr);
op_addr += linesize;
op_size -= linesize;
@@ -1709,10 +1736,14 @@ __STATIC_INLINE void csi_mmu_invalid_tlb_all(void)
#if CONFIG_CPU_XUANTIE_C907 || CONFIG_CPU_XUANTIE_C907FD || CONFIG_CPU_XUANTIE_C907FDV || CONFIG_CPU_XUANTIE_C907FDVM \
|| CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
|| CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT \
|| CONFIG_CPU_XUANTIE_C910V2 || CONFIG_CPU_XUANTIE_C920V2 \
|| CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3 || CONFIG_CPU_XUANTIE_C920V3_CP \
|| CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C920V3 \
|| CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP \
|| CONFIG_CPU_XUANTIE_C910V3_CP_XT || CONFIG_CPU_XUANTIE_C920V3_CP_XT \
|| CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \
|| CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \
|| CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT \
|| CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
/**
\ingroup CSI_tcm_register
@@ -2001,3 +2032,4 @@ __STATIC_INLINE int csi_xmlenb_get_value(void)
#endif /* __CORE_RV32_H_DEPENDANT */
#endif /* __CSI_GENERIC */

74
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_arm64_gcc.h
View File

@@ -704,15 +704,19 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(unsigned long idx)
{
unsigned long pmpcfgx = 0;
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
} else if (idx >= 4 && idx < 8) {
} else if (idx >= 4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
} else if (idx >= 8 && idx < 12) {
} else if (idx >= 8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else if (idx >= 12 && idx < 16) {
} else if (idx >= 12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
} else {
@@ -757,21 +761,25 @@ __STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg)
{
unsigned long pmpcfgx = 0;
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >= 4 && idx < 8) {
} else if (idx >= 4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG1(pmpcfgx);
} else if (idx >= 8 && idx < 12) {
} else if (idx >= 8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG2(pmpcfgx);
} else if (idx >= 12 && idx < 16) {
} else if (idx >= 12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
@@ -922,7 +930,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR15(void)
*/
__STATIC_INLINE unsigned long __get_PMPADDRx(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 0:
return __get_PMPADDR0();
@@ -1069,7 +1078,8 @@ __ALWAYS_STATIC_INLINE void __set_PMPADDR15(unsigned long pmpaddr)
*/
__STATIC_INLINE void __set_PMPADDRx(unsigned long idx, unsigned long pmpaddr)
{
switch (idx) {
switch (idx)
{
case 0:
__set_PMPADDR0(pmpaddr);
break;
@@ -1627,7 +1637,8 @@ __ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
@@ -1659,26 +1670,30 @@ __ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
posMax = 1;
for (i = 0; i < (y - 1); i++) {
for (i = 0; i < (y - 1); i++)
{
posMax = posMax * 2;
}
if (x > 0) {
if (x > 0)
{
posMax = (posMax - 1);
if (x > posMax) {
if (x > posMax)
{
x = posMax;
}
// x &= (posMax * 2 + 1);
/* x &= (posMax * 2 + 1); */
} else {
negMin = -posMax;
if (x < negMin) {
if (x < negMin)
{
x = negMin;
}
// x &= (posMax * 2 - 1);
/* x &= (posMax * 2 - 1); */
}
return (x);
@@ -1695,7 +1710,8 @@ __ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -1715,9 +1731,11 @@ __ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
if (value & 0x80000000)
{ /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -2943,14 +2961,17 @@ __ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) {
if (y >= 0)
{
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x)
{
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x) {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x)
{
result = x + y;
} else {
result = 0x80000000;
@@ -2976,9 +2997,11 @@ __ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
tmp = (long)x - (long)y;
if (tmp > 0x7fffffff) {
if (tmp > 0x7fffffff)
{
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
} else if (tmp < (-2147483647 - 1))
{
tmp = -2147483647 - 1;
}
@@ -3284,3 +3307,4 @@ __ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
#endif
#endif /* _CSI_RV32_GCC_H_ */

58
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_gcc.h
View File

@@ -1589,7 +1589,8 @@ __ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
@@ -1621,26 +1622,30 @@ __ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
posMax = 1;
for (i = 0; i < (y - 1); i++) {
for (i = 0; i < (y - 1); i++)
{
posMax = posMax * 2;
}
if (x > 0) {
if (x > 0)
{
posMax = (posMax - 1);
if (x > posMax) {
if (x > posMax)
{
x = posMax;
}
// x &= (posMax * 2 + 1);
/* x &= (posMax * 2 + 1); */
} else {
negMin = -posMax;
if (x < negMin) {
if (x < negMin)
{
x = negMin;
}
// x &= (posMax * 2 - 1);
/* x &= (posMax * 2 - 1); */
}
return (x);
@@ -1657,7 +1662,8 @@ __ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -1677,9 +1683,11 @@ __ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
if (value & 0x80000000)
{ /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -1729,7 +1737,7 @@ __ALWAYS_STATIC_INLINE uint32_t __RRX(uint32_t op1)
__ALWAYS_STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
//#warning "__LDRBT"
/* #warning "__LDRBT" */
__ASM volatile("ldb %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint8_t) result); /* Add explicit type cast here */
}
@@ -1745,7 +1753,7 @@ __ALWAYS_STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
//#warning "__LDRHT"
/* #warning "__LDRHT" */
__ASM volatile("ldh %0, (%1, 0)" : "=r"(result) : "r"(addr));
return ((uint16_t) result); /* Add explicit type cast here */
}
@@ -1761,7 +1769,7 @@ __ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
//#warning "__LDRT"
/* #warning "__LDRT" */
__ASM volatile("ldw %0, (%1, 0)" : "=r"(result) : "r"(addr));
return (result);
}
@@ -1775,7 +1783,7 @@ __ALWAYS_STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
*/
__ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
//#warning "__STRBT"
/* #warning "__STRBT" */
__ASM volatile("stb %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
@@ -1788,7 +1796,7 @@ __ALWAYS_STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
*/
__ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
//#warning "__STRHT"
/* #warning "__STRHT" */
__ASM volatile("sth %1, (%0, 0)" :: "r"(addr), "r"((uint32_t)value) : "memory");
}
@@ -1801,7 +1809,7 @@ __ALWAYS_STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
*/
__ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
//#warning "__STRT"
/* #warning "__STRT" */
__ASM volatile("stw %1, (%0, 0)" :: "r"(addr), "r"(value) : "memory");
}
@@ -1826,7 +1834,7 @@ __ALWAYS_STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
*/
__ALWAYS_STATIC_INLINE uint32_t __get_FPUType(void)
{
//FIXME:
/* FIXME: */
return 0;
}
@@ -2951,14 +2959,17 @@ __ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if (x + y >= x) {
if (y >= 0)
{
if (x + y >= x)
{
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if (x + y < x) {
if (x + y < x)
{
result = x + y;
} else {
result = 0x80000000;
@@ -2984,9 +2995,11 @@ __ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
if (tmp > 0x7fffffff)
{
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
} else if (tmp < (-2147483647 - 1))
{
tmp = -2147483647 - 1;
}
@@ -3291,3 +3304,4 @@ __ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
}
#endif /* _CSI_GCC_H_ */

531
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv32_gcc.h
View File

@@ -31,7 +31,9 @@
#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \
|| CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \
|| CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT
|| CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \
|| CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \
|| CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP
#define CONFIG_CPU_XUANTIE_E9XX 1
#endif
@@ -305,6 +307,30 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MTVT(void)
return (result);
}
/**
\brief Get MTIME
\details Returns the content of the MTIME Register.
\return MTIME Register value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MTIME(void)
{
unsigned long result;
__ASM volatile("rdtime %0" : "=r"(result));
return (result);
}
/**
\brief Get MTIMEH
\details Returns the content of the MTIME Register.
\return MTIME Register value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MTIMEH(void)
{
unsigned long result;
__ASM volatile("rdtimeh %0" : "=r"(result));
return (result);
}
/**
\brief Get SP
\details Returns the content of the SP Register.
@@ -472,6 +498,16 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MCYCLE(void)
return (result);
}
/**
\brief Set MCYCLE
\details Write MCYCLE Register
\param [in] value MCYCLE Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MCYCLE(unsigned long value)
{
__ASM volatile("csrw mcycle, %0" : : "r"(value));
}
/**
\brief Get MCYCLEH Register
\details Returns the content of the MCYCLEH Register.
@@ -485,6 +521,16 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MCYCLEH(void)
return (result);
}
/**
\brief Set MCYCLEH
\details Write MCYCLEH Register
\param [in] value MCYCLEH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MCYCLEH(unsigned long value)
{
__ASM volatile("csrw mcycleh, %0" : : "r"(value));
}
/**
\brief Get MINSTRET Register
\details Returns the content of the MINSTRET Register.
@@ -498,6 +544,16 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MINSTRET(void)
return (result);
}
/**
\brief Set MINSTRET
\details Write MINSTRET Register
\param [in] value MINSTRET Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MINSTRET(unsigned long value)
{
__ASM volatile("csrw minstret, %0" : : "r"(value));
}
/**
\brief Get MINSTRETH Register
\details Returns the content of the MINSTRETH Register.
@@ -511,6 +567,16 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MINSTRETH(void)
return (result);
}
/**
\brief Set MINSTRETH
\details Write MINSTRETH Register
\param [in] value MINSTRETH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MINSTRETH(unsigned long value)
{
__ASM volatile("csrw minstreth, %0" : : "r"(value));
}
#if (CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP)
/**
\brief Get MITCMCR
@@ -558,6 +624,375 @@ __ALWAYS_STATIC_INLINE void __set_MDTCMCR(unsigned long mdtcmcr)
}
#endif /* end e907xx */
/**
\brief Set MCOUNTINHIBIT
\details Write MCOUNTINHIBIT Register.
\param [in] value MCOUNTINHIBIT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MCOUNTINHIBIT(uint32_t value)
{
__ASM volatile("csrw mcountinhibit, %0" : : "r"(value));
}
/**
\brief Get MCOUNTINHIBIT
\details Read MCOUNTINHIBIT Register
\return MCOUNTINHIBIT Register value
*/
__ALWAYS_STATIC_INLINE unsigned int __get_MCOUNTINHIBIT(void)
{
uint32_t result;
__ASM volatile("csrr %0, mcountinhibit" : "=r"(result));
return result;
}
/**
\brief Set MHPMEVENT
\details Write MHPMEVENT Register
\param [in] idx Index of MHPMEVENT Register
\param [in] value MHPMEVENT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHPMEVENT(unsigned long idx, unsigned long value)
{
switch (idx)
{
case 0: rv_csr_write(0x7E0, value); break;
case 2: rv_csr_write(0x7E1, value); break;
case 3: rv_csr_write(0x323, value); break;
case 4: rv_csr_write(0x324, value); break;
case 5: rv_csr_write(0x325, value); break;
case 6: rv_csr_write(0x326, value); break;
case 7: rv_csr_write(0x327, value); break;
case 8: rv_csr_write(0x328, value); break;
case 9: rv_csr_write(0x329, value); break;
case 10: rv_csr_write(0x32a, value); break;
case 11: rv_csr_write(0x32b, value); break;
case 12: rv_csr_write(0x32c, value); break;
case 13: rv_csr_write(0x32d, value); break;
case 14: rv_csr_write(0x32e, value); break;
case 15: rv_csr_write(0x32f, value); break;
case 16: rv_csr_write(0x330, value); break;
case 17: rv_csr_write(0x331, value); break;
case 18: rv_csr_write(0x332, value); break;
case 19: rv_csr_write(0x333, value); break;
case 20: rv_csr_write(0x334, value); break;
case 21: rv_csr_write(0x335, value); break;
case 22: rv_csr_write(0x336, value); break;
case 23: rv_csr_write(0x337, value); break;
case 24: rv_csr_write(0x338, value); break;
case 25: rv_csr_write(0x339, value); break;
case 26: rv_csr_write(0x33a, value); break;
case 27: rv_csr_write(0x33b, value); break;
case 28: rv_csr_write(0x33c, value); break;
case 29: rv_csr_write(0x33d, value); break;
case 30: rv_csr_write(0x33e, value); break;
case 31: rv_csr_write(0x33F, value); break;
default: break;
}
}
/**
\brief Get MHPMEVENT
\details Read MHPMEVENT Register.
\param [in] idx Index of MHPMEVENT Register to read.
\return MHPMEVENT Register Value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENT(unsigned long idx)
{
switch (idx)
{
case 0: return rv_csr_read(0x7E0);
case 2: return rv_csr_read(0x7E1);
case 3: return rv_csr_read(0x323);
case 4: return rv_csr_read(0x324);
case 5: return rv_csr_read(0x325);
case 6: return rv_csr_read(0x326);
case 7: return rv_csr_read(0x327);
case 8: return rv_csr_read(0x328);
case 9: return rv_csr_read(0x329);
case 10: return rv_csr_read(0x32a);
case 11: return rv_csr_read(0x32b);
case 12: return rv_csr_read(0x32c);
case 13: return rv_csr_read(0x32d);
case 14: return rv_csr_read(0x32e);
case 15: return rv_csr_read(0x32f);
case 16: return rv_csr_read(0x330);
case 17: return rv_csr_read(0x331);
case 18: return rv_csr_read(0x332);
case 19: return rv_csr_read(0x333);
case 20: return rv_csr_read(0x334);
case 21: return rv_csr_read(0x335);
case 22: return rv_csr_read(0x336);
case 23: return rv_csr_read(0x337);
case 24: return rv_csr_read(0x338);
case 25: return rv_csr_read(0x339);
case 26: return rv_csr_read(0x33a);
case 27: return rv_csr_read(0x33b);
case 28: return rv_csr_read(0x33c);
case 29: return rv_csr_read(0x33d);
case 30: return rv_csr_read(0x33e);
case 31: return rv_csr_read(0x33F);
default: return 0;
}
}
/**
\brief Set MHPMEVENTH
\details Write MHPMEVENTH Register
\param [in] idx Index of MHPMEVENT Register
\param [in] value MHPMEVENTH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHPMEVENTH(unsigned long idx, unsigned long value)
{
switch (idx)
{
case 3: rv_csr_write(0x723, value); break;
case 4: rv_csr_write(0x724, value); break;
case 5: rv_csr_write(0x725, value); break;
case 6: rv_csr_write(0x726, value); break;
case 7: rv_csr_write(0x727, value); break;
case 8: rv_csr_write(0x728, value); break;
case 9: rv_csr_write(0x729, value); break;
case 10: rv_csr_write(0x72A, value); break;
case 11: rv_csr_write(0x72B, value); break;
case 12: rv_csr_write(0x72C, value); break;
case 13: rv_csr_write(0x72D, value); break;
case 14: rv_csr_write(0x72E, value); break;
case 15: rv_csr_write(0x72F, value); break;
case 16: rv_csr_write(0x730, value); break;
case 17: rv_csr_write(0x731, value); break;
case 18: rv_csr_write(0x732, value); break;
case 19: rv_csr_write(0x733, value); break;
case 20: rv_csr_write(0x734, value); break;
case 21: rv_csr_write(0x735, value); break;
case 22: rv_csr_write(0x736, value); break;
case 23: rv_csr_write(0x737, value); break;
case 24: rv_csr_write(0x738, value); break;
case 25: rv_csr_write(0x739, value); break;
case 26: rv_csr_write(0x73A, value); break;
case 27: rv_csr_write(0x73B, value); break;
case 28: rv_csr_write(0x73C, value); break;
case 29: rv_csr_write(0x73D, value); break;
case 30: rv_csr_write(0x73E, value); break;
case 31: rv_csr_write(0x73F, value); break;
default: break;
}
}
/**
\brief Get MHPMEVENTH
\details Read MHPMEVENTH Register.
\param [in] idx Index of MHPMEVENTH Register to read.
\return MHPMEVENTH Register Value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENTH(unsigned long idx)
{
switch (idx)
{
case 3: return rv_csr_read(0x723);
case 4: return rv_csr_read(0x724);
case 5: return rv_csr_read(0x725);
case 6: return rv_csr_read(0x726);
case 7: return rv_csr_read(0x727);
case 8: return rv_csr_read(0x728);
case 9: return rv_csr_read(0x729);
case 10: return rv_csr_read(0x72A);
case 11: return rv_csr_read(0x72B);
case 12: return rv_csr_read(0x72C);
case 13: return rv_csr_read(0x72D);
case 14: return rv_csr_read(0x72E);
case 15: return rv_csr_read(0x72F);
case 16: return rv_csr_read(0x730);
case 17: return rv_csr_read(0x731);
case 18: return rv_csr_read(0x732);
case 19: return rv_csr_read(0x733);
case 20: return rv_csr_read(0x734);
case 21: return rv_csr_read(0x735);
case 22: return rv_csr_read(0x736);
case 23: return rv_csr_read(0x737);
case 24: return rv_csr_read(0x738);
case 25: return rv_csr_read(0x739);
case 26: return rv_csr_read(0x73A);
case 27: return rv_csr_read(0x73B);
case 28: return rv_csr_read(0x73C);
case 29: return rv_csr_read(0x73D);
case 30: return rv_csr_read(0x73E);
case 31: return rv_csr_read(0x73F);
default: return 0;
}
}
/**
\brief Set MHPMCOUNTER
\details Write MHPMCOUNTER Register
\param [in] idx Index of MHPMCOUNTER Register
\param [in] value MHPMCOUNTER Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTER(unsigned long idx, unsigned long value)
{
switch (idx)
{
case 3: rv_csr_write(0xB03, (value)); break;
case 4: rv_csr_write(0xB04, (value)); break;
case 5: rv_csr_write(0xB05, (value)); break;
case 6: rv_csr_write(0xB06, (value)); break;
case 7: rv_csr_write(0xB07, (value)); break;
case 8: rv_csr_write(0xB08, (value)); break;
case 9: rv_csr_write(0xB09, (value)); break;
case 10: rv_csr_write(0xB0A, (value)); break;
case 11: rv_csr_write(0xB0B, (value)); break;
case 12: rv_csr_write(0xB0C, (value)); break;
case 13: rv_csr_write(0xB0D, (value)); break;
case 14: rv_csr_write(0xB0E, (value)); break;
case 15: rv_csr_write(0xB0F, (value)); break;
case 16: rv_csr_write(0xB10, (value)); break;
case 17: rv_csr_write(0xB11, (value)); break;
case 18: rv_csr_write(0xB12, (value)); break;
case 19: rv_csr_write(0xB13, (value)); break;
case 20: rv_csr_write(0xB14, (value)); break;
case 21: rv_csr_write(0xB15, (value)); break;
case 22: rv_csr_write(0xB16, (value)); break;
case 23: rv_csr_write(0xB17, (value)); break;
case 24: rv_csr_write(0xB18, (value)); break;
case 25: rv_csr_write(0xB19, (value)); break;
case 26: rv_csr_write(0xB1A, (value)); break;
case 27: rv_csr_write(0xB1B, (value)); break;
case 28: rv_csr_write(0xB1C, (value)); break;
case 29: rv_csr_write(0xB1D, (value)); break;
case 30: rv_csr_write(0xB1E, (value)); break;
case 31: rv_csr_write(0xB1F, (value)); break;
default: break;
}
}
/**
\brief Get MHPMCOUNTER
\details Write MHPMCOUNTER Register.
\param [in] idx Index of MHPMCOUNTER Register
\return MHPMCOUNTER Register Value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTER(unsigned long idx)
{
switch (idx)
{
case 3: return rv_csr_read(0xB03);
case 4: return rv_csr_read(0xB04);
case 5: return rv_csr_read(0xB05);
case 6: return rv_csr_read(0xB06);
case 7: return rv_csr_read(0xB07);
case 8: return rv_csr_read(0xB08);
case 9: return rv_csr_read(0xB09);
case 10: return rv_csr_read(0xB0A);
case 11: return rv_csr_read(0xB0B);
case 12: return rv_csr_read(0xB0C);
case 13: return rv_csr_read(0xB0D);
case 14: return rv_csr_read(0xB0E);
case 15: return rv_csr_read(0xB0F);
case 16: return rv_csr_read(0xB10);
case 17: return rv_csr_read(0xB11);
case 18: return rv_csr_read(0xB12);
case 19: return rv_csr_read(0xB13);
case 20: return rv_csr_read(0xB14);
case 21: return rv_csr_read(0xB15);
case 22: return rv_csr_read(0xB16);
case 23: return rv_csr_read(0xB17);
case 24: return rv_csr_read(0xB18);
case 25: return rv_csr_read(0xB19);
case 26: return rv_csr_read(0xB1A);
case 27: return rv_csr_read(0xB1B);
case 28: return rv_csr_read(0xB1C);
case 29: return rv_csr_read(0xB1D);
case 30: return rv_csr_read(0xB1E);
case 31: return rv_csr_read(0xB1F);
default: return 0;
}
}
/**
\brief Set MHPMCOUNTERH
\details Write MHPMCOUNTERH Register
\param [in] idx Index of MHPMCOUNTERH Register
\param [in] value MHPMCOUNTERH Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTERH(unsigned long idx, unsigned long value)
{
switch (idx)
{
case 3: rv_csr_write(0xB83, (value)); break;
case 4: rv_csr_write(0xB84, (value)); break;
case 5: rv_csr_write(0xB85, (value)); break;
case 6: rv_csr_write(0xB86, (value)); break;
case 7: rv_csr_write(0xB87, (value)); break;
case 8: rv_csr_write(0xB88, (value)); break;
case 9: rv_csr_write(0xB89, (value)); break;
case 10: rv_csr_write(0xB8A, (value)); break;
case 11: rv_csr_write(0xB8B, (value)); break;
case 12: rv_csr_write(0xB8C, (value)); break;
case 13: rv_csr_write(0xB8D, (value)); break;
case 14: rv_csr_write(0xB8E, (value)); break;
case 15: rv_csr_write(0xB8F, (value)); break;
case 16: rv_csr_write(0xB90, (value)); break;
case 17: rv_csr_write(0xB91, (value)); break;
case 18: rv_csr_write(0xB92, (value)); break;
case 19: rv_csr_write(0xB93, (value)); break;
case 20: rv_csr_write(0xB94, (value)); break;
case 21: rv_csr_write(0xB95, (value)); break;
case 22: rv_csr_write(0xB96, (value)); break;
case 23: rv_csr_write(0xB97, (value)); break;
case 24: rv_csr_write(0xB98, (value)); break;
case 25: rv_csr_write(0xB99, (value)); break;
case 26: rv_csr_write(0xB9A, (value)); break;
case 27: rv_csr_write(0xB9B, (value)); break;
case 28: rv_csr_write(0xB9C, (value)); break;
case 29: rv_csr_write(0xB9D, (value)); break;
case 30: rv_csr_write(0xB9E, (value)); break;
case 31: rv_csr_write(0xB9F, (value)); break;
default: break;
}
}
/**
\brief Get MHPMCOUNTERH
\details Write MHPMCOUNTERH Register.
\param [in] idx Index of MHPMCOUNTERH Register
\return MHPMCOUNTERH Register Value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTERH(unsigned long idx)
{
switch (idx)
{
case 3: return rv_csr_read(0xB83);
case 4: return rv_csr_read(0xB84);
case 5: return rv_csr_read(0xB85);
case 6: return rv_csr_read(0xB86);
case 7: return rv_csr_read(0xB87);
case 8: return rv_csr_read(0xB88);
case 9: return rv_csr_read(0xB89);
case 10: return rv_csr_read(0xB8A);
case 11: return rv_csr_read(0xB8B);
case 12: return rv_csr_read(0xB8C);
case 13: return rv_csr_read(0xB8D);
case 14: return rv_csr_read(0xB8E);
case 15: return rv_csr_read(0xB8F);
case 16: return rv_csr_read(0xB90);
case 17: return rv_csr_read(0xB91);
case 18: return rv_csr_read(0xB92);
case 19: return rv_csr_read(0xB93);
case 20: return rv_csr_read(0xB94);
case 21: return rv_csr_read(0xB95);
case 22: return rv_csr_read(0xB96);
case 23: return rv_csr_read(0xB97);
case 24: return rv_csr_read(0xB98);
case 25: return rv_csr_read(0xB99);
case 26: return rv_csr_read(0xB9A);
case 27: return rv_csr_read(0xB9B);
case 28: return rv_csr_read(0xB9C);
case 29: return rv_csr_read(0xB9D);
case 30: return rv_csr_read(0xB9E);
case 31: return rv_csr_read(0xB9F);
default: return 0;
}
}
/**
\brief Get MVENDORID Register
@@ -658,15 +1093,19 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(unsigned long idx)
{
unsigned long pmpcfgx = 0;
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
} else if (idx >=4 && idx < 8) {
} else if (idx >=4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
} else if (idx >=8 && idx < 12) {
} else if (idx >=8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else if (idx >=12 && idx < 16) {
} else if (idx >=12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
} else {
@@ -711,21 +1150,25 @@ __STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg)
{
unsigned long pmpcfgx = 0;
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >=4 && idx < 8) {
} else if (idx >=4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG1(pmpcfgx);
} else if (idx >=8 && idx < 12) {
} else if (idx >=8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
__set_PMPCFG2(pmpcfgx);
} else if (idx >=12 && idx < 16) {
} else if (idx >=12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | (pmpxcfg << (idx << 3));
@@ -876,7 +1319,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR15(void)
*/
__STATIC_INLINE unsigned long __get_PMPADDRx(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 0: return __get_PMPADDR0();
case 1: return __get_PMPADDR1();
case 2: return __get_PMPADDR2();
@@ -990,7 +1434,8 @@ __ALWAYS_STATIC_INLINE void __set_PMPADDR15(unsigned long pmpaddr)
*/
__STATIC_INLINE void __set_PMPADDRx(unsigned long idx, unsigned long pmpaddr)
{
switch (idx) {
switch (idx)
{
case 0: __set_PMPADDR0(pmpaddr); break;
case 1: __set_PMPADDR1(pmpaddr); break;
case 2: __set_PMPADDR2(pmpaddr); break;
@@ -1101,7 +1546,7 @@ __ALWAYS_STATIC_INLINE void __ISB(void)
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("fence iorw, iorw");
#ifndef __riscv_xtheadse
#if __riscv_xtheadsync
__ASM volatile("sync");
#endif
}
@@ -1112,7 +1557,9 @@ __ALWAYS_STATIC_INLINE void __DSB(void)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.iall");
#endif
}
/**
@@ -1122,7 +1569,9 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.ipa %0" : : "r"(addr));
#endif
}
/**
@@ -1131,7 +1580,7 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
{
#ifndef __riscv_xtheadse
#if __riscv_xtheadcmo
__ASM volatile("dcache.iall");
#endif
}
@@ -1142,7 +1591,7 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
{
#ifndef __riscv_xtheadse
#if __riscv_xtheadcmo
__ASM volatile("dcache.call");
#endif
}
@@ -1153,7 +1602,7 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
{
#ifndef __riscv_xtheadse
#if __riscv_xtheadcmo
__ASM volatile("dcache.ciall");
#endif
}
@@ -1165,7 +1614,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.ipa %0" : : "r"(addr));
#endif
}
/**
@@ -1175,7 +1626,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cpa %0" : : "r"(addr));
#endif
}
/**
@@ -1185,7 +1638,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cipa %0" : : "r"(addr));
#endif
}
@@ -1277,7 +1732,8 @@ __ALWAYS_STATIC_INLINE unsigned long __RBIT(unsigned long value)
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
@@ -1309,26 +1765,30 @@ __ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, unsigned long y)
posMax = 1;
for (i = 0; i < (y - 1); i++) {
for (i = 0; i < (y - 1); i++)
{
posMax = posMax * 2;
}
if (x > 0) {
if (x > 0)
{
posMax = (posMax - 1);
if (x > posMax) {
if (x > posMax)
{
x = posMax;
}
// x &= (posMax * 2 + 1);
/* x &= (posMax * 2 + 1); */
} else {
negMin = -posMax;
if (x < negMin) {
if (x < negMin)
{
x = negMin;
}
// x &= (posMax * 2 - 1);
/* x &= (posMax * 2 - 1); */
}
return (x);
@@ -1345,7 +1805,8 @@ __ALWAYS_STATIC_INLINE unsigned long __USAT(unsigned long value, unsigned long s
{
unsigned long result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -1365,9 +1826,11 @@ __ALWAYS_STATIC_INLINE unsigned long __IUSAT(unsigned long value, unsigned long
{
unsigned long result;
if (value & 0x80000000) { /* only overflow set bit-31 */
if (value & 0x80000000)
{ /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -1814,6 +2277,7 @@ __ALWAYS_STATIC_INLINE unsigned long __USAD8(unsigned long x, unsigned long y)
return (u + t + s + r);
}
#if 0
/**
\brief Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate.
\details This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values
@@ -1851,6 +2315,7 @@ __ALWAYS_STATIC_INLINE unsigned long __USADA8(unsigned long x, unsigned long y,
#endif
return (u + t + s + r + sum);
}
#endif
/**
\brief Dual 16-bit saturating addition.
@@ -2593,14 +3058,17 @@ __ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if ((int32_t)((unsigned long)x + (unsigned long)y) >= x) {
if (y >= 0)
{
if ((int32_t)((unsigned long)x + (unsigned long)y) >= x)
{
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if ((int32_t)((unsigned long)x + (unsigned long)y) < x) {
if ((int32_t)((unsigned long)x + (unsigned long)y) < x)
{
result = x + y;
} else {
result = 0x80000000;
@@ -2626,9 +3094,11 @@ __ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
tmp = (int64_t)x - (int64_t)y;
if (tmp > 0x7fffffff) {
if (tmp > 0x7fffffff)
{
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
} else if (tmp < (-2147483647 - 1))
{
tmp = -2147483647 - 1;
}
@@ -2933,3 +3403,4 @@ __ALWAYS_STATIC_INLINE unsigned long __UXTB16(unsigned long x)
}
#endif /* _CSI_RV32_GCC_H_ */

188
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv64_gcc.h
View File

@@ -32,10 +32,14 @@
#if CONFIG_CPU_XUANTIE_C907 || CONFIG_CPU_XUANTIE_C907FD || CONFIG_CPU_XUANTIE_C907FDV || CONFIG_CPU_XUANTIE_C907FDVM \
|| CONFIG_CPU_XUANTIE_C907_RV32 || CONFIG_CPU_XUANTIE_C907FD_RV32 || CONFIG_CPU_XUANTIE_C907FDV_RV32 || CONFIG_CPU_XUANTIE_C907FDVM_RV32 \
|| CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
|| CONFIG_CPU_XUANTIE_C910V2 || CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C910V3_CP \
|| CONFIG_CPU_XUANTIE_C920V2 || CONFIG_CPU_XUANTIE_C920V3 || CONFIG_CPU_XUANTIE_C920V3_CP \
|| CONFIG_CPU_XUANTIE_C908X || CONFIG_CPU_XUANTIE_C908X_CP || CONFIG_CPU_XUANTIE_C908X_CP_XT \
|| CONFIG_CPU_XUANTIE_C910V2 || CONFIG_CPU_XUANTIE_C920V2 \
|| CONFIG_CPU_XUANTIE_C910V3 || CONFIG_CPU_XUANTIE_C920V3 \
|| CONFIG_CPU_XUANTIE_C910V3_CP || CONFIG_CPU_XUANTIE_C920V3_CP \
|| CONFIG_CPU_XUANTIE_C910V3_CP_XT || CONFIG_CPU_XUANTIE_C920V3_CP_XT \
|| CONFIG_CPU_XUANTIE_R908 || CONFIG_CPU_XUANTIE_R908FD || CONFIG_CPU_XUANTIE_R908FDV \
|| CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP
|| CONFIG_CPU_XUANTIE_R908_CP || CONFIG_CPU_XUANTIE_R908FD_CP || CONFIG_CPU_XUANTIE_R908FDV_CP \
|| CONFIG_CPU_XUANTIE_R908_CP_XT || CONFIG_CPU_XUANTIE_R908FD_CP_XT || CONFIG_CPU_XUANTIE_R908FDV_CP_XT
#define CBO_INSN_SUPPORT 1
#endif
@@ -494,7 +498,19 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MTIME(void)
unsigned long result;
__ASM volatile("rdtime %0" : "=r"(result));
//__ASM volatile("csrr %0, 0xc01" : "=r"(result));
/* __ASM volatile("csrr %0, 0xc01" : "=r"(result)); */
return (result);
}
/**
\brief Get MTIMEH
\details Returns the content of the MTIME Register.
\return MTIME Register value
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MTIMEH(void)
{
unsigned long result;
__ASM volatile("rdtimeh %0" : "=r"(result));
return (result);
}
@@ -838,24 +854,30 @@ __STATIC_INLINE uint8_t __get_PMPxCFG(unsigned long idx)
unsigned long pmpcfgx = 0;
#if __riscv_xlen == 32
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
} else if (idx >= 4 && idx < 8) {
} else if (idx >= 4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
} else if (idx >= 8 && idx < 12) {
} else if (idx >= 8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else if (idx >= 12 && idx < 16) {
} else if (idx >= 12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
} else {
return 0;
}
#else
if (idx < 8) {
if (idx < 8)
{
pmpcfgx = __get_PMPCFG0();
} else if (idx >= 8 && idx < 16) {
} else if (idx >= 8 && idx < 16)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
} else {
@@ -906,21 +928,25 @@ __STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg)
unsigned long pmpcfgx = 0;
#if __riscv_xlen == 32
if (idx < 4) {
if (idx < 4)
{
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >= 4 && idx < 8) {
} else if (idx >= 4 && idx < 8)
{
idx -= 4;
pmpcfgx = __get_PMPCFG1();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG1(pmpcfgx);
} else if (idx >= 8 && idx < 12) {
} else if (idx >= 8 && idx < 12)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG2(pmpcfgx);
} else if (idx >= 12 && idx < 16) {
} else if (idx >= 12 && idx < 16)
{
idx -= 12;
pmpcfgx = __get_PMPCFG3();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
@@ -929,11 +955,13 @@ __STATIC_INLINE void __set_PMPxCFG(unsigned long idx, uint8_t pmpxcfg)
return;
}
#else
if (idx < 8) {
if (idx < 8)
{
pmpcfgx = __get_PMPCFG0();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
__set_PMPCFG0(pmpcfgx);
} else if (idx >= 8 && idx < 16) {
} else if (idx >= 8 && idx < 16)
{
idx -= 8;
pmpcfgx = __get_PMPCFG2();
pmpcfgx = (pmpcfgx & ~(0xFF << (idx << 3))) | ((unsigned long)(pmpxcfg) << (idx << 3));
@@ -1085,7 +1113,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_PMPADDR15(void)
*/
__STATIC_INLINE unsigned long __get_PMPADDRx(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 0:
return __get_PMPADDR0();
@@ -1232,7 +1261,8 @@ __ALWAYS_STATIC_INLINE void __set_PMPADDR15(unsigned long pmpaddr)
*/
__STATIC_INLINE void __set_PMPADDRx(unsigned long idx, unsigned long pmpaddr)
{
switch (idx) {
switch (idx)
{
case 0:
__set_PMPADDR0(pmpaddr);
break;
@@ -1588,7 +1618,9 @@ __ALWAYS_STATIC_INLINE void __ISB(void)
__ALWAYS_STATIC_INLINE void __DSB(void)
{
__ASM volatile("fence iorw, iorw");
#if __riscv_xtheadsync
__ASM volatile("sync");
#endif
}
/**
@@ -1608,7 +1640,9 @@ __ALWAYS_STATIC_INLINE void __DMB(void)
*/
__ALWAYS_STATIC_INLINE void __SYNC_IS(void)
{
#if __riscv_xtheadsync
__ASM volatile("sync.is");
#endif
}
/**
@@ -1617,7 +1651,9 @@ __ALWAYS_STATIC_INLINE void __SYNC_IS(void)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.iall");
#endif
}
/**
@@ -1626,7 +1662,9 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALL(void)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.ialls");
#endif
}
/**
@@ -1636,7 +1674,9 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IALLS(void)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.ipa %0" : : "r"(addr));
#endif
}
/**
@@ -1646,7 +1686,9 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __ICACHE_IVA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("icache.iva %0" : : "r"(addr));
#endif
}
/**
@@ -1655,7 +1697,9 @@ __ALWAYS_STATIC_INLINE void __ICACHE_IVA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.iall");
#endif
}
/**
@@ -1664,7 +1708,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.call");
#endif
}
/**
@@ -1673,7 +1719,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.ciall");
#endif
}
/**
@@ -1683,7 +1731,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIALL(void)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CISW(unsigned long wayset)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cisw %0" : : "r"(wayset));
#endif
}
#if CBO_INSN_SUPPORT
@@ -1734,7 +1784,9 @@ __ALWAYS_STATIC_INLINE void __CBO_ZERO(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cpa %0" : : "r"(addr));
#endif
}
/**
@@ -1744,7 +1796,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CVA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cva %0" : : "r"(addr));
#endif
}
/**
@@ -1754,7 +1808,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CVA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cipa %0" : : "r"(addr));
#endif
}
/**
@@ -1764,7 +1820,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CIVA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.civa %0" : : "r"(addr));
#endif
}
/**
@@ -1774,7 +1832,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CIVA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.ipa %0" : : "r"(addr));
#endif
}
/**
@@ -1784,7 +1844,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IPA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_IVA(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.iva %0" : : "r"(addr));
#endif
}
#endif
@@ -1796,7 +1858,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_IVA(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CPAL1(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cpal1 %0" : : "r"(addr));
#endif
}
/**
@@ -1806,7 +1870,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CPAL1(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_CVAL1(unsigned long addr)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.cval1 %0" : : "r"(addr));
#endif
}
/**
@@ -1816,7 +1882,9 @@ __ALWAYS_STATIC_INLINE void __DCACHE_CVAL1(unsigned long addr)
*/
__ALWAYS_STATIC_INLINE void __DCACHE_ISW(unsigned long wayset)
{
#if __riscv_xtheadcmo
__ASM volatile("dcache.isw %0" : : "r"(wayset));
#endif
}
#if (__L2CACHE_PRESENT == 1U)
@@ -1948,7 +2016,7 @@ __ALWAYS_STATIC_INLINE void __set_MCER2H(unsigned long mcer2h)
__ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA2(void)
{
register unsigned long result;
//__ASM volatile("csrr %0, ssbepa2" : "=r"(result));
/* __ASM volatile("csrr %0, ssbepa2" : "=r"(result)); */
__ASM volatile("csrr %0, 0x5d2" : "=r"(result));
return (result);
}
@@ -1960,7 +2028,7 @@ __ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA2(void)
*/
__ALWAYS_STATIC_INLINE void __set_SSBEPA2(unsigned long ssbepa2)
{
//__ASM volatile("csrw ssbepa2, %0" : : "r"(ssbepa2));
/* __ASM volatile("csrw ssbepa2, %0" : : "r"(ssbepa2)); */
__ASM volatile("csrw 0x5d2, %0" : : "r"(ssbepa2));
}
@@ -1972,7 +2040,7 @@ __ALWAYS_STATIC_INLINE void __set_SSBEPA2(unsigned long ssbepa2)
__ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA2(void)
{
register unsigned long result;
//__ASM volatile("csrr %0, msbepa2" : "=r"(result));
/* __ASM volatile("csrr %0, msbepa2" : "=r"(result)); */
__ASM volatile("csrr %0, 0x7fc" : "=r"(result));
return (result);
}
@@ -1984,7 +2052,7 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA2(void)
*/
__ALWAYS_STATIC_INLINE void __set_MSBEPA2(unsigned long msbepa2)
{
//__ASM volatile("csrw msbepa2, %0" : : "r"(msbepa2));
/* __ASM volatile("csrw msbepa2, %0" : : "r"(msbepa2)); */
__ASM volatile("csrw 0x7fc, %0" : : "r"(msbepa2));
}
@@ -2064,7 +2132,7 @@ __ALWAYS_STATIC_INLINE void __set_MCERH(unsigned long mcerh)
__ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA(void)
{
register unsigned long result;
//__ASM volatile("csrr %0, ssbepa" : "=r"(result));
/* __ASM volatile("csrr %0, ssbepa" : "=r"(result)); */
__ASM volatile("csrr %0, 0x5d1" : "=r"(result));
return (result);
}
@@ -2076,7 +2144,7 @@ __ALWAYS_STATIC_INLINE unsigned long __get_SSBEPA(void)
*/
__ALWAYS_STATIC_INLINE void __set_SSBEPA(unsigned long ssbepa)
{
//__ASM volatile("csrw ssbepa, %0" : : "r"(ssbepa));
/* __ASM volatile("csrw ssbepa, %0" : : "r"(ssbepa)); */
__ASM volatile("csrw 0x5d1, %0" : : "r"(ssbepa));
}
@@ -2088,7 +2156,7 @@ __ALWAYS_STATIC_INLINE void __set_SSBEPA(unsigned long ssbepa)
__ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA(void)
{
register unsigned long result;
//__ASM volatile("csrr %0, msbepa" : "=r"(result));
/* __ASM volatile("csrr %0, msbepa" : "=r"(result)); */
__ASM volatile("csrr %0, 0x7fb" : "=r"(result));
return (result);
}
@@ -2100,7 +2168,7 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MSBEPA(void)
*/
__ALWAYS_STATIC_INLINE void __set_MSBEPA(unsigned long msbepa)
{
//__ASM volatile("csrw msbepa, %0" : : "r"(msbepa));
/* __ASM volatile("csrw msbepa, %0" : : "r"(msbepa)); */
__ASM volatile("csrw 0x7fb, %0" : : "r"(msbepa));
}
@@ -2259,7 +2327,8 @@ __ALWAYS_STATIC_INLINE unsigned int __get_MCOUNTINHIBIT(void)
*/
__ALWAYS_STATIC_INLINE void __set_MHPMEVENT(unsigned long idx, unsigned long value)
{
switch (idx) {
switch (idx)
{
case 0: rv_csr_write(0x7E0, value); break;
case 2: rv_csr_write(0x7E1, value); break;
case 3: rv_csr_write(0x323, value); break;
@@ -2303,7 +2372,8 @@ __ALWAYS_STATIC_INLINE void __set_MHPMEVENT(unsigned long idx, unsigned long val
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENT(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 0: return rv_csr_read(0x7E0);
case 2: return rv_csr_read(0x7E1);
case 3: return rv_csr_read(0x323);
@@ -2347,7 +2417,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENT(unsigned long idx)
*/
__ALWAYS_STATIC_INLINE void __set_MHPMEVENTH(unsigned long idx, unsigned long value)
{
switch (idx) {
switch (idx)
{
case 3: rv_csr_write(0x723, value); break;
case 4: rv_csr_write(0x724, value); break;
case 5: rv_csr_write(0x725, value); break;
@@ -2389,7 +2460,8 @@ __ALWAYS_STATIC_INLINE void __set_MHPMEVENTH(unsigned long idx, unsigned long va
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENTH(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 3: return rv_csr_read(0x723);
case 4: return rv_csr_read(0x724);
case 5: return rv_csr_read(0x725);
@@ -2431,7 +2503,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MHPMEVENTH(unsigned long idx)
*/
__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTER(unsigned long idx, unsigned long value)
{
switch (idx) {
switch (idx)
{
case 3: rv_csr_write(0xB03, (value)); break;
case 4: rv_csr_write(0xB04, (value)); break;
case 5: rv_csr_write(0xB05, (value)); break;
@@ -2473,7 +2546,8 @@ __ALWAYS_STATIC_INLINE void __set_MHPMCOUNTER(unsigned long idx, unsigned long v
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTER(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 3: return rv_csr_read(0xB03);
case 4: return rv_csr_read(0xB04);
case 5: return rv_csr_read(0xB05);
@@ -2515,7 +2589,8 @@ __ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTER(unsigned long idx)
*/
__ALWAYS_STATIC_INLINE void __set_MHPMCOUNTERH(unsigned long idx, unsigned long value)
{
switch (idx) {
switch (idx)
{
case 3: rv_csr_write(0xB83, (value)); break;
case 4: rv_csr_write(0xB84, (value)); break;
case 5: rv_csr_write(0xB85, (value)); break;
@@ -2557,7 +2632,8 @@ __ALWAYS_STATIC_INLINE void __set_MHPMCOUNTERH(unsigned long idx, unsigned long
*/
__ALWAYS_STATIC_INLINE unsigned long __get_MHPMCOUNTERH(unsigned long idx)
{
switch (idx) {
switch (idx)
{
case 3: return rv_csr_read(0xB83);
case 4: return rv_csr_read(0xB84);
case 5: return rv_csr_read(0xB85);
@@ -2670,7 +2746,8 @@ __ALWAYS_STATIC_INLINE uint32_t __RBIT(uint32_t value)
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U) {
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
@@ -2702,26 +2779,30 @@ __ALWAYS_STATIC_INLINE int32_t __SSAT(int32_t x, uint32_t y)
posMax = 1;
for (i = 0; i < (y - 1); i++) {
for (i = 0; i < (y - 1); i++)
{
posMax = posMax * 2;
}
if (x > 0) {
if (x > 0)
{
posMax = (posMax - 1);
if (x > posMax) {
if (x > posMax)
{
x = posMax;
}
// x &= (posMax * 2 + 1);
/* x &= (posMax * 2 + 1); */
} else {
negMin = -posMax;
if (x < negMin) {
if (x < negMin)
{
x = negMin;
}
// x &= (posMax * 2 - 1);
/* x &= (posMax * 2 - 1); */
}
return (x);
@@ -2738,7 +2819,8 @@ __ALWAYS_STATIC_INLINE uint32_t __USAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -2758,9 +2840,11 @@ __ALWAYS_STATIC_INLINE uint32_t __IUSAT(uint32_t value, uint32_t sat)
{
uint32_t result;
if (value & 0x80000000) { /* only overflow set bit-31 */
if (value & 0x80000000)
{ /* only overflow set bit-31 */
result = 0;
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0) {
} else if ((((0xFFFFFFFF >> sat) << sat) & value) != 0)
{
result = 0xFFFFFFFF >> (32 - sat);
} else {
result = value;
@@ -3986,14 +4070,17 @@ __ALWAYS_STATIC_INLINE int32_t __QADD(int32_t x, int32_t y)
{
int32_t result;
if (y >= 0) {
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x) {
if (y >= 0)
{
if ((int32_t)((uint32_t)x + (uint32_t)y) >= x)
{
result = x + y;
} else {
result = 0x7FFFFFFF;
}
} else {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x) {
if ((int32_t)((uint32_t)x + (uint32_t)y) < x)
{
result = x + y;
} else {
result = 0x80000000;
@@ -4019,9 +4106,11 @@ __ALWAYS_STATIC_INLINE int32_t __QSUB(int32_t x, int32_t y)
tmp = (long)x - (long)y;
if (tmp > 0x7fffffff) {
if (tmp > 0x7fffffff)
{
tmp = 0x7fffffff;
} else if (tmp < (-2147483647 - 1)) {
} else if (tmp < (-2147483647 - 1))
{
tmp = -2147483647 - 1;
}
@@ -4327,3 +4416,4 @@ __ALWAYS_STATIC_INLINE uint32_t __UXTB16(uint32_t x)
#endif
#endif /* _CSI_RV32_GCC_H_ */

60
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/core/csi_rv_common.h
View File

@@ -123,7 +123,67 @@
})
#endif
#define CSR_MCOR 0x7c2
#define CSR_MHCR 0x7c1
#define CSR_MCCR2 0x7c3
#define CSR_MHINT 0x7c5
#define CSR_MHINT2 0x7cc
#define CSR_MHINT3 0x7cd
#define CSR_MHINT4 0x7ce
#define CSR_MXSTATUS 0x7c0
#define CSR_PLIC_BASE 0xfc1
#define CSR_MRMR 0x7c6
#define CSR_MRVBR 0x7c7
#define CSR_MCOUNTERWEN 0x7c9
#define CSR_MSMPR 0x7f3
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MCPUID 0xfc0
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MCOUNTEREN 0x306
#define CSR_MENVCFG 0x30a
#define CSR_MSTATUSH 0x310
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
/* Machine Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
#define CSR_PMPCFG3 0x3a3
#define CSR_PMPCFG4 0x3a4
#define CSR_PMPCFG5 0x3a5
#define CSR_PMPCFG6 0x3a6
#define CSR_PMPCFG7 0x3a7
#define CSR_PMPCFG8 0x3a8
#define CSR_PMPCFG9 0x3a9
#define CSR_PMPCFG10 0x3aa
#define CSR_PMPCFG11 0x3ab
#define CSR_PMPCFG12 0x3ac
#define CSR_PMPCFG13 0x3ad
#define CSR_PMPCFG14 0x3ae
#define CSR_PMPCFG15 0x3af
#define CSR_PMPADDR0 0x3b0
#define CSR_PMPADDR1 0x3b1
#define CSR_PMPADDR2 0x3b2
#define CSR_PMPADDR3 0x3b3
#define CSR_PMPADDR4 0x3b4
#define CSR_PMPADDR5 0x3b5
#define CSR_PMPADDR6 0x3b6
#define CSR_PMPADDR7 0x3b7
#endif /* __CSI_RV_COMMON_H__ */

38
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/csi_core.h
View File

@@ -54,7 +54,9 @@
#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \
|| CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP \
|| CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT
|| CONFIG_CPU_XUANTIE_E902 || CONFIG_CPU_XUANTIE_E902M || CONFIG_CPU_XUANTIE_E902T || CONFIG_CPU_XUANTIE_E902MT \
|| CONFIG_CPU_XUANTIE_E901PLUS_CP || CONFIG_CPU_XUANTIE_E901PLUS_B_CP || CONFIG_CPU_XUANTIE_E901PLUS_M_CP || CONFIG_CPU_XUANTIE_E901PLUS_BM_CP \
|| CONFIG_CPU_XUANTIE_E901_CP || CONFIG_CPU_XUANTIE_E901_B_CP || CONFIG_CPU_XUANTIE_E901_ZM_CP || CONFIG_CPU_XUANTIE_E901_BZM_CP
#include <core/core_rv32.h>
#include <core/csi_rv32_gcc.h>
#else
@@ -112,18 +114,28 @@ __STATIC_INLINE const char* csi_get_cpu_name()
return "c908v";
#elif CONFIG_CPU_XUANTIE_C908I
return "c908i";
#elif CONFIG_CPU_XUANTIE_C908X
return "c908x";
#elif CONFIG_CPU_XUANTIE_C908X_CP
return "c908x-cp";
#elif CONFIG_CPU_XUANTIE_C908X_CP_XT
return "c908x-cp-xt";
#elif CONFIG_CPU_XUANTIE_C910V2
return "c910v2";
#elif CONFIG_CPU_XUANTIE_C910V3
return "c910v3";
#elif CONFIG_CPU_XUANTIE_C910V3_CP
return "c910v3-cp";
#elif CONFIG_CPU_XUANTIE_C910V3_CP_XT
return "c910v3-cp-xt";
#elif CONFIG_CPU_XUANTIE_C920V2
return "c920v2";
#elif CONFIG_CPU_XUANTIE_C920V3
return "c920v3";
#elif CONFIG_CPU_XUANTIE_C920V3_CP
return "c920v3-cp";
#elif CONFIG_CPU_XUANTIE_C920V3_CP_XT
return "c920v3-cp-xt";
#elif CONFIG_CPU_XUANTIE_R910
return "r910";
#elif CONFIG_CPU_XUANTIE_R920
@@ -140,7 +152,28 @@ __STATIC_INLINE const char* csi_get_cpu_name()
return "r908fd-cp";
#elif CONFIG_CPU_XUANTIE_R908FDV_CP
return "r908fdv-cp";
#elif CONFIG_CPU_XUANTIE_R908_CP_XT
return "r908-cp-xt";
#elif CONFIG_CPU_XUANTIE_R908FD_CP_XT
return "r908fd-cp-xt";
#elif CONFIG_CPU_XUANTIE_R908FDV_CP_XT
return "r908fdv-cp-xt";
#elif CONFIG_CPU_XUANTIE_E901PLUS_CP
return "e901plus-cp";
#elif CONFIG_CPU_XUANTIE_E901PLUS_B_CP
return "e901plusb-cp";
#elif CONFIG_CPU_XUANTIE_E901PLUS_M_CP
return "e901plusm-cp";
#elif CONFIG_CPU_XUANTIE_E901PLUS_BM_CP
return "e901plusbm-cp";
#elif CONFIG_CPU_XUANTIE_E901_CP
return "e901-cp";
#elif CONFIG_CPU_XUANTIE_E901_B_CP
return "e901b-cp";
#elif CONFIG_CPU_XUANTIE_E901_ZM_CP
return "e901zm-cp";
#elif CONFIG_CPU_XUANTIE_E901_BZM_CP
return "e901bzm-cp";
#elif CONFIG_CPU_XUANTIE_E902
return "e902";
#elif CONFIG_CPU_XUANTIE_E902M
@@ -184,3 +217,4 @@ __STATIC_INLINE const char* csi_get_cpu_name()
#endif
#endif /* _CORE_H_ */

1
bsp/xuantie/libraries/xuantie_libraries/csi/csi2/include/syslog.h
View File

@@ -119,3 +119,4 @@ extern const char *PFORMAT_E;
#endif
#endif /* _SYSLOG_H_ */

1418
bsp/xuantie/smartl/e901/.config Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>project</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources />
</projectDescription>

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content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1

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#RT-Thread Studio Project Configuration
# Mon Sep 22 13:30:04 2025
cfg_version=v3.0
board_name=
bsp_version=
bsp_path=
chip_name=
project_base_rtt_bsp=true
is_use_scons_build=true
hardware_adapter=
selected_rtt_version=latest
board_base_nano_proj=false
is_base_example_project=false
example_name=
project_type=rt-thread
os_branch=master
os_version=latest
project_name=project
output_project_path=E:\rt-thread\bsp\xuantie\smartl\e901

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mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../../../
PKGS_DIR := packages
config XUANTIAN_SMARTL_E901
bool
select ARCH_RISCV32
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "$(RTT_DIR)/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$BSP_DIR/board/Kconfig"

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# XuanTie - E901 Series
## 一 简介
### 1. 内核
玄铁 E901+ 是基于 RISC-V 指令架构的低成本、高能效的 32 位嵌入式 CPU 处理器，用户可以以近似 8 位CPU 的成本获得 32 位嵌入式处理器的效率与性能。E901+ 处理器兼容 RV32E[M] [B]_Zc 指令架构，采用 16/32 位混合编码系统，指令系统与流水线硬件结构精简高效。同时支持配置协处理器接口，用于满足用户 DSA（Domain Specific Accelerator）需求，加速特定应用执行，并支持用户进行自定义指令扩展。
E901+ 主要针对智能卡、智能电网、低成本微控制器、无线传感网络等嵌入式应用。
### 2.特点
E902 处理器体系结构的主要特点如下：
E901+ 处理器体系结构的主要特点如下：
• 支持 RV32E [M] [B]_Zc 指令集
• 16 个 32 位通用寄存器
• 两级顺序执行流水线
• 支持 RISC-V 机器模式和用户模式
• 支持 RISC-V Debug 架构，支持标准五线 JTAG 调试接口，支持 CJTAG 两线调试接口
• 支持以下硬件乘/除法器配置：
**–** 不配置硬件乘/除法器
**–** 配置单周期快速硬件乘法器，以及多周期（1-33）慢速硬件除法器
**–** 配置多周期（3-33）慢速硬件乘法器，以及多周期（1-33）慢速硬件除法器
• 兼容 RISC-V CLIC 中断标准，支持中断优先级可配置，支持中断嵌套和中断咬尾
• 外部中断源数量最高可配置为 112 个
• 兼容 RISC-V PMP 内存保护标准，0/2/4/8/16 区域可配置
• 支持指令总线和系统总线，指令总线支持 AHB-Lite（即 AHB 3.0）协议，系统总线协议支持 AHB 2.0
和 AHB-Lite
• 支持指令高速缓存，缓存行 16 字节，容量 2KiB/4KiB/8KiB 可配
• 支持玄铁扩展编程模型
• 支持复位启动地址硬件集成时可配置
• 支持软复位操作
• 支持协处理器接口可配置
### 3.BSP支持情况
- 当前BSP支持下述内核：
```asciiarmor
e901plusbm-cp
```
- 当前BSP默认设置的内核是e901plusbm-cp。
- 当使用其他内核架构时需要修改，rtconfig.py文件中的`MCPU`字段。
### 4.运行QEMU
- BSP根目录下存在`qemu.bat`脚本，生成可执行文件后可点击该脚本直接启动QEMU.
## 二 工具
- 编译器： https://www.xrvm.cn/community/download?id=4433353576298909696
- 模拟器： https://www.xrvm.cn/community/download?id=4397435198627713024
注：若上述链接中的编译器与模拟器不能使用，可以使用下述CDK中的编译器与模拟器
- SDK：https://www.xrvm.cn/community/download?id=4397799570420076544
## 三 调试方法
**下述调试方法以E902举例，本BSP操作方式一致**，搭建完成RT-Thread开发环境，在BSP根目录使用env工具在当前目录打开env。
![](figures/1.env.png)
使用前执行一次**menuconfig**命令，更新rtconfig.h配置，然后在当前目录执行**scons -j12**命令编译生成可可执行文件。
<img src="figures/2.scons.png" alt="env" style="zoom: 95%;" />
生成可执行文件，可以直接在命令行启动qemu或者配置vscode脚本借助vscode强大的插件进行图形化调试，qemu的相关命令可以查看玄铁qemu的[用户手册](https://www.xrvm.cn/community/download?id=4397435198627713024)，下述是启动qemu的命令，在powershell或命令行可直接执行下述命令，注意qemu需要导出至环境变量或者使用绝对路径。
```shell
qemu-system-riscv64 -machine smartl -nographic -kernel rtthread.elf -cpu e906
```
下述是使用vscode调试的展示。
<img src="figures/3.vscode.png" alt="env" style="zoom: 63%;" />
一起为RISC-V加油！

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for item in list:
path = os.path.join(cwd, item)
if item == 'libraries' or not os.path.isdir(path):
continue
sconscript_path = os.path.join(path, 'SConscript')
if os.path.isfile(sconscript_path):
objs.extend(SConscript(os.path.join(item, 'SConscript')))
Return('objs')

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import os
import sys
import rtconfig
from SCons.Script import *
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '../libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
bsp_vdir = 'build'
library_vdir = 'build/libraries'
# common include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript'), variant_dir=library_vdir, duplicate=0))
# make a building
DoBuilding(TARGET, objs)

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from building import *
import os
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = ['main.c']
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-04-21 Wangshun first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "pre_main.h"
int main(void)
{
rt_kprintf("Hello RT-Thread!\r\n");
}

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bsp/xuantie/smartl/e901/board/Kconfig Normal file
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menu "Hardware Drivers Config"
config SOC_XUANTIE
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
select RT_USING_SERIAL
default n
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
endif
menuconfig ENABLE_FPU
bool "Enable FPU"
select ARCH_RISCV_FPU
default n
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = ['board.c']
path = [cwd]
CPPDEFINES = [
'CONFIG_KERNEL_RTTHREAD=1',
'__RT_KERNEL_SOURCE__=1',
'CONFIG_CSI_V2=1',
'CONFIG_CSI=csi2',
'CONFIG_INIT_TASK_STACK_SIZE=4096',
'CONFIG_APP_TASK_STACK_SIZE=8192',
'CONFIG_ARCH_MAINSTACK=4096',
'CONFIG_ARCH_INTERRUPTSTACK=4096',
'CONFIG_XIP=1',
'CONFIG_LIBC_MINI_PRINTF_SUPPORT=1',
'CONFIG_SYSTICK_HZ=100',
'CONFIG_BOARD_SMARTL_EVB=1',
'CONFIG_DEBUG=1',
'CLI_CONFIG_STACK_SIZE=4096',
'CONFIG_CPU_XUANTIE_E901PLUS_BM_CP=1',
]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2025-04-23 Wangshun first version
*/
#include <board.h>
#include <rthw.h>
#include <rtthread.h>
#include <drv_usart.h>
extern unsigned long __heap_start;
extern unsigned long __heap_end;
/**
* This function will initialize your board.
*/
void rt_hw_board_init()
{
rt_hw_interrupt_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)&__heap_start, (void *)&__heap_end);
#endif
#ifdef BSP_USING_UART
rt_hw_usart_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

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/*
* Copyright (C) 2017-2024 Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
This is an example board.h for Board Compment, New Board should flow the macro defines.
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Common Board Features Define */
/*
The Common BOARD_XXX Macro Defines Boards supported features which may reference by Solutions.
Common board macro include:
. BOARD_NAME
· UART
· GPIO
· PWM
· ADC
· BUTTON
· LED
· WIFI
· BT
· AUDIO
BOARD_XXX Macro descripted below should be defined if the board support.
*/
/****************************************************************************/
/*
This riscv dummy board include:
· UART x1
· GPIO x2
· PWM x2
· ADC x1
· BUTTON x2
· LED x2
· WIFI x0
· BT x0
· AUDIO x1
*/
#ifndef CONFIG_BOARD_UART
#define CONFIG_BOARD_UART 1
#endif
#ifndef CONFIG_BOARD_GPIO
#define CONFIG_BOARD_GPIO 0
#endif
#ifndef CONFIG_BOARD_PWM
#define CONFIG_BOARD_PWM 0
#endif
#ifndef CONFIG_BOARD_ADC
#define CONFIG_BOARD_ADC 0
#endif
#ifndef CONFIG_BOARD_BUTTON
#define CONFIG_BOARD_BUTTON 0
#endif
#ifndef CONFIG_BOARD_LED
#define CONFIG_BOARD_LED 0
#endif
#ifndef CONFIG_BOARD_WIFI
#define CONFIG_BOARD_WIFI 0
#endif
#ifndef CONFIG_BOARD_BT
#define CONFIG_BOARD_BT 0
#endif
#ifndef CONFIG_BOARD_AUDIO
#define CONFIG_BOARD_AUDIO 0
#endif
#define BOARD_NAME "RISCV_DUMMY"
/* the board pins, can be used as uart, gpio, pwd... */
#define BOARD_PIN0 (0)
#define BOARD_PIN1 (1)
#define BOARD_PIN2 (2)
#define BOARD_PIN3 (3)
#define BOARD_PIN4 (4)
#define BOARD_PIN5 (5)
#define BOARD_PIN6 (6)
#define BOARD_PIN7 (7)
#define BOARD_PIN8 (8)
#define BOARD_PIN9 (9)
#define BOARD_PIN10 (10)
#define BOARD_PIN11 (11)
#define BOARD_PIN12 (12)
/* ... */
#if defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART
/* UART */
/*
The total supported uart numbers on this board, 0 meas No uart support.
the BOARD_UART<x>_XXX, x in rang of (0, BOARD_UART_NUM - 1)
*/
#ifndef BOARD_UART_NUM
#define BOARD_UART_NUM (1)
#endif
#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0
/* the board uart0 tx pin */
#define BOARD_UART0_TX_PIN (BOARD_PIN0)
/* the borad uart0 rx pin */
#define BOARD_UART0_RX_PIN (BOARD_PIN1)
/* The real UART port reference to board logic port 0 */
#define BOARD_UART0_IDX (0)
/* The default baudrate for uart0 */
#define BOARD_UART0_BAUD (115200)
/* #define BOARD_UART1_IDX (1) */
/* #define BOARD_UART1_BAUD (115200) */
/* ... */
#endif /* defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0 */
#endif /* defined(CONFIG_BOARD_UART) && CONFIG_BOARD_UART */
#if defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO
/* GPIO */
/*
The total supported GPIO Pin numbers on this board, 0 meas No uart support.
the BOARD_GPIO_PIN<x>, x in rang of (0, BOARD_GPIO_PIN_NUM - 1)
*/
#ifndef BOARD_GPIO_PIN_NUM
#define BOARD_GPIO_PIN_NUM (2)
#endif
#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0
/* The real gpio reference to board logic gpio pin */
#define BOARD_GPIO_PIN0 (BOARD_PIN2)
#define BOARD_GPIO_PIN1 (BOARD_PIN3)
/* #define BOARD_GPIO_PIN2 (x) */
/* #define BOARD_GPIO_PIN3 (x) */
#endif /* defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0 */
#endif /* defined(CONFIG_BOARD_GPIO) && CONFIG_BOARD_GPIO */
#if defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM
/* PWM */
/* the board supported pwm channels */
#ifndef BOARD_PWM_NUM
#define BOARD_PWM_NUM (2)
#endif
#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0
/* the board pwm pin */
#define BOARD_PWM0_PIN (BOARD_PIN4)
/* The real pwm channel reference to board logic pwm channel */
#define BOARD_PWM0_CH (0)
#define BOARD_PWM1_PIN (BOARD_PIN5)
#define BOARD_PWM1_CH (1)
#endif /* defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0 */
#endif /* defined(CONFIG_BOARD_PWM) && CONFIG_BOARD_PWM */
#if defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0
/* ADC */
/* the board supported adc channels */
#ifndef BOARD_ADC_NUM
#define BOARD_ADC_NUM (1)
#endif
#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0
/* the board adc pin */
#define BOARD_ADC0_PIN (BOARD_PIN6)
/* The real adc channel reference to board logic adc channel */
#define BOARD_ADC0_CH (0)
#endif /* defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0 */
#endif /* defined(CONFIG_BOARD_ADC) && CONFIG_BOARD_ADC > 0 */
#if defined(CONFIG_BOARD_BUTTON) && CONFIG_BOARD_BUTTON > 0
/* BUTTON */
#ifndef BOARD_BUTTON_NUM
/*
the board supported buttons, include gpio button and adc button,
BOARD_BUTTON_NUM = BOARD_BUTTON_GPIO_NUM + BOARD_BUTTON_ADC_NUM.
*/
#define BOARD_BUTTON_NUM (4)
#endif
#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0
#define BOARD_BUTTON0_PIN (BOARD_PIN7)
#define BOARD_BUTTON1_PIN (BOARD_PIN8)
#define BOARD_BUTTON2_PIN (BOARD_PIN9)
#define BOARD_BUTTON3_PIN (BOARD_PIN10)
/* GPIO BUTTON */
/* the board supported GPIO Buttons */
#ifndef BOARD_BUTTON_GPIO_NUM
#define BOARD_BUTTON_GPIO_NUM (2)
#endif
#if defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0
/* the board logic button id, in range of (0, BOARD_BUTTON_GPIO_NUM - 1) */
#define BOARD_BUTTON0 (0)
/* for gpio button, define the pin numner. if the gpio pin used as gpio button, it shoudn't reference as BOARD_GPIO_PINx
*/
#define BOARD_BUTTON0_GPIO_PIN (BOARD_BUTTON0_PIN)
#define BOARD_BUTTON1 (1)
#define BOARD_BUTTON1_GPIO_PIN (BOARD_BUTTON1_PIN)
#endif /* defined(BOARD_BUTTON_GPIO_NUM) && BOARD_BUTTON_GPIO_NUM > 0 */
/* ADC BUTTON */
/* the board supported adc Buttons */
#ifndef BOARD_BUTTON_ADC_NUM
#define BOARD_BUTTON_ADC_NUM (2)
#endif
#if defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0
/* the board logic adc button id, in range of (BOARD_BUTTON_GPIO_NUM, BOARD_BUTTON_NUM - 1), if not suuport GPIO Button,
* BOARD_BUTTON_GPIO_NUM should be 0 */
#define BOARD_BUTTON2 (BOARD_BUTTON_GPIO_NUM + 0)
#define BOARD_BUTTON2_ADC_PIN (BOARD_BUTTON2_PIN)
/* the adc channel used for button2, if the adc channel used as adc button, it shoudn't reference as BOARD_ADCx_CH*/
#define BOARD_BUTTON2_ADC_CH (1)
/* the adc device name */
#define BOARD_BUTTON2_ADC_NAME "adc1"
/* adc voltage reference */
#define BOARD_BUTTON2_ADC_REF (100)
/* adc voltage range */
#define BOARD_BUTTON2_ADC_RANG (500)
#define BOARD_BUTTON3 (BOARD_BUTTON_GPIO_NUM + 1)
#define BOARD_BUTTON3_ADC_PIN (BOARD_BUTTON3_PIN)
#define BOARD_BUTTON3_ADC_CH (1)
#define BOARD_BUTTON3_ADC_NAME "adc1"
#define BOARD_BUTTON3_ADC_REF (600)
#define BOARD_BUTTON3_ADC_RANG (500)
/* #define BOARD_ADC_BUTTON2 (2) */
/* #define BOARD_ADC_BUTTON2_CH (1) */
/* #define BOARD_ADC_BUTTON2_NAME "adc1" */
/* #define BOARD_ADC_BUTTON2_REF xxx */
/* #define BOARD_ADC_BUTTON2_RANG xxx */
#endif /* defined(BOARD_BUTTON_ADC_NUM) && BOARD_BUTTON_ADC_NUM > 0 */
#endif /* defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 */
#endif /* defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0 */
#if defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0
/* LED */
/* the board supported leds */
#ifndef BOARD_LED_NUM
#define BOARD_LED_NUM (2)
#endif
#define BOARD_LED0_PIN BOARD_PIN11
#define BOARD_LED1_PIN BOARD_PIN12
/* PWM LED */
/* the board supported pwm leds */
#ifndef BOARD_LED_PWM_NUM
#define BOARD_LED_PWM_NUM (1)
#endif
#if defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0
#define BOARD_LED0_PWM_PIN (BOARD_LED0_PIN)
/* the pwm channel used for led0, if the pwm channel used as led0, it shoudn't reference as BOARD_PWMx_CH */
#define BOARD_LED0_PWM_CH (0)
#endif /* defined(BOARD_LED_PWM_NUM) && BOARD_LED_PWM_NUM > 0 */
/* GPIO LED */
#ifndef BOARD_LED_GPIO_NUM
#define BOARD_LED_GPIO_NUM (1)
#endif
#if defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0
/* the gpio pin used for led0, if the gpio pin used as led, it shoudn't reference as BOARD_GPIO_PINx */
#define BOARD_LED1_GPIO_PIN (BOARD_LED1_PIN)
#endif /* defined(BOARD_LED_GPIO_NUM) && BOARD_LED_GPIO_NUM > 0 */
#endif /* defined(CONFIG_BOARD_LED) && CONFIG_BOARD_LED > 0 */
#if defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0
/* BT */
/* the board support bluetooth */
#ifndef BOARD_BT_SUPPORT
#define BOARD_BT_SUPPORT 1
#endif
#endif /* defined(CONFIG_BOARD_BT) && CONFIG_BOARD_BT > 0 */
#if defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0
/* WIFI */
/* the board support wifi */
#ifndef BOARD_WIFI_SUPPORT
#define BOARD_WIFI_SUPPORT 1
#endif
#endif /* defined(CONFIG_BOARD_WIFI) && CONFIG_BOARD_WIFI > 0 */
#if defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0
/* Audio */
/* the board support audio */
#ifndef BOARD_AUDIO_SUPPORT
#define BOARD_AUDIO_SUPPORT 1
#endif
#endif /* defined(CONFIG_BOARD_AUDIO) && CONFIG_BOARD_AUDIO > 0 */
/****************************************************************************/
/* Common solutions defines */
/* Console config, Almost all solutions and demos use these. */
#ifndef CONSOLE_UART_IDX
#define CONSOLE_UART_IDX (BOARD_UART0_IDX)
#endif
#ifndef CONFIG_CLI_USART_BAUD
#define CONFIG_CLI_USART_BAUD (BOARD_UART0_BAUD)
#endif
#ifndef CONFIG_CONSOLE_UART_BUFSIZE
#define CONFIG_CONSOLE_UART_BUFSIZE (128)
#endif
/****************************************************************************/
/* Commom test demos defines */
/* i2c */
#define EXAMPLE_IIC_IDX 0 /* 1 */
#define EXAMPLE_PIN_IIC_SDA 0 /* PC1 */
#define EXAMPLE_PIN_IIC_SCL 0 /* PC0 */
#define EXAMPLE_PIN_IIC_SDA_FUNC 0 /* PC1_I2C1_SDA */
#define EXAMPLE_PIN_IIC_SCL_FUNC 0 /* PC0_I2C1_SCL */
/* adc */
#define EXAMPLE_ADC_CH0 0 /* PA8 */
#define EXAMPLE_ADC_CH0_FUNC 0 /* PA8_ADC_A0 */
#define EXAMPLE_ADC_CH12 0 /* PA26 */
#define EXAMPLE_ADC_CH12_FUNC 0 /* PA26_ADC_A12 */
/****************************************************************************/
/* Vendor board defines */
/* other board specific defines */
/* #define CUSTOM_BOARD_xxx */
/****************************************************************************/
/**
* @brief init the board for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_init(void);
/**
* @brief init the board gpio pin for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_gpio_pin_init(void);
/**
* @brief init the board uart for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_uart_init(void);
/**
* @brief init the board pwm for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_pwm_init(void);
/**
* @brief init the board adc for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_adc_init(void);
/**
* @brief init the board button for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_button_init(void);
/**
* @brief init the board led for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_led_init(void);
/**
* @brief init the board wifi for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_wifi_init(void);
/**
* @brief init the board bt for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_bt_init(void);
/**
* @brief init the board audio for default: pin mux, etc.
* re-implement if need.
* @return
*/
void board_audio_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

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@echo off
set OBJDUMP=D:\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\RISC-V\XTGccElfNewlib\V3.0.1\R\bin\riscv64-unknown-elf-objdump
set TARGET=E:\rt-thread\bsp\xuantie\smartl\e901\rtthread.elf
set OUTPUT=rtthread.asm
%OBJDUMP% -d %TARGET% > %OUTPUT%
echo Disassembly generated to %OUTPUT%
pause

91
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@echo off
cls
echo /*
echo * Copyright (c) 2006 - 2025, RT-Thread Development Team
echo *
echo * SPDX-License-Identifier: Apache-2.0
echo *
echo * Change Logs:
echo * Date Author Notes
echo * 2025/04/29 Wangshun first version
echo * 2025/05/14 Optimized Improved robustness and error handling
echo */
echo.
setlocal enabledelayedexpansion
set "CONFIG_FILE=qemu_config.txt"
set "CPU_CONFIG_FILE=cpu_config.txt"
set "DEFAULT_QEMU_DIR=E:\XuanTieCore\6.QEMU"
set "ELF_PATH=%CD%\rtthread.elf"
:: Load QEMU directory from config file or set default
if exist "!CONFIG_FILE!" (
set /p QEMU_DIR=<"!CONFIG_FILE!"
if not defined QEMU_DIR set "QEMU_DIR=!DEFAULT_QEMU_DIR!"
) else (
set "QEMU_DIR=!DEFAULT_QEMU_DIR!"
)
:: Load CPU parameter from config file or set default
if exist "!CPU_CONFIG_FILE!" (
set /p CPU_PARAM=<"!CPU_CONFIG_FILE!"
if not defined CPU_PARAM set "CPU_PARAM=e901"
) else (
set "CPU_PARAM=e901"
)
:: Prompt for new QEMU directory
set /p "USER_INPUT=Enter new QEMU directory (Enter for default: !QEMU_DIR!): "
if defined USER_INPUT (
set "USER_INPUT=!USER_INPUT: =!"
if not "!USER_INPUT!"=="" (
set "QEMU_DIR=!USER_INPUT!"
echo !QEMU_DIR!>"!CONFIG_FILE!"
)
)
:: Validate QEMU path
set "QEMU_PATH=!QEMU_DIR!\qemu-system-riscv32.exe"
if not exist "!QEMU_PATH!" (
echo Error: QEMU executable not found at "!QEMU_PATH!".
echo Please verify the QEMU directory and try again.
pause
exit /b 1
)
:: Prompt for new CPU parameter
echo Current CPU parameter: !CPU_PARAM!
set /p "CPU_INPUT=Enter new -cpu parameter (Enter for default): "
if defined CPU_INPUT (
set "CPU_INPUT=!CPU_INPUT: =!"
if not "!CPU_INPUT!"=="" (
set "CPU_PARAM=!CPU_INPUT!"
echo !CPU_PARAM!>"!CPU_CONFIG_FILE!"
)
)
:: Validate ELF file
if not exist "!ELF_PATH!" (
echo Error: rtthread.elf not found at "!ELF_PATH!".
pause
exit /b 1
)
:: Display QEMU version
echo.
"!QEMU_PATH!" --version
:: Run QEMU
echo.
"!QEMU_PATH!" -machine smartl -kernel "!ELF_PATH!" -nographic -cpu !CPU_PARAM!
if !ERRORLEVEL! neq 0 (
echo Error: QEMU failed to run. Check configuration or paths.
pause
exit /b !ERRORLEVEL!
)
echo QEMU terminated.
pause
endlocal

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bsp/xuantie/smartl/e901/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#define XUANTIAN_SMARTL_E901
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 8
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 1024
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define ARCH_RISCV
#define ARCH_RISCV32
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_DEVFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* WCH HAL & SDK Drivers */
/* end of WCH HAL & SDK Drivers */
/* AT32 HAL & SDK Drivers */
/* end of AT32 HAL & SDK Drivers */
/* HC32 DDL Drivers */
/* end of HC32 DDL Drivers */
/* NXP HAL & SDK Drivers */
/* end of NXP HAL & SDK Drivers */
/* NUVOTON Drivers */
/* end of NUVOTON Drivers */
/* GD32 Drivers */
/* end of GD32 Drivers */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers Config */
#define SOC_XUANTIE
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
#endif

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bsp/xuantie/smartl/e901/rtconfig.py Normal file
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import os
ARCH = 'risc-v'
CPU = 'e901'
# toolchains options
CROSS_TOOL = 'gcc'
#------- toolchains path -------------------------------------------------------
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'D:\C-Sky\CDKRepo\Toolchain\XTGccElfNewlib\V3.2.0\R\bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
CORE = 'risc-v'
MAP_FILE = 'rtthread.map'
LINK_FILE = '../../libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl_lite.ld'
if os.path.exists('./libraries'):
LINK_FILE = './libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl_lite.ld'
TARGET_NAME = 'rtthread.bin'
#------- GCC settings ----------------------------------------------------------
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'riscv64-unknown-elf-'
CC = PREFIX + 'gcc'
CXX= PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
MCPU = ' -mcpu=e901plusbm-cp ' # Modify here based on CPU architecture.
MCPU_DEFINE = ' -DCONFIG_CPU_XUANTIE_E901PLUS_BM_CP=1 ' # Modify here based on CPU architecture.
DEVICE = MCPU + MCPU_DEFINE + ' -Wno-main -mcmodel=medany'
GLOBAL_DEFINES = (
'-DCONFIG_KERNEL_RTTHREAD=1 '
'-D__RT_KERNEL_SOURCE__=1 '
'-DCONFIG_CSI_V2=1 '
'-DCONFIG_CSI=csi2 '
'-DCONFIG_INIT_TASK_STACK_SIZE=4096 '
'-DCONFIG_APP_TASK_STACK_SIZE=8192 '
'-DCONFIG_ARCH_MAINSTACK=4096 '
'-DCONFIG_ARCH_INTERRUPTSTACK=4096 '
'-DCONFIG_XIP=1 '
'-DCONFIG_LIBC_MINI_PRINTF_SUPPORT=1 '
'-DCONFIG_SYSTICK_HZ=100 '
'-DCONFIG_BOARD_SMARTL_EVB=1 '
'-DCONFIG_DEBUG=1 '
'-DCLI_CONFIG_STACK_SIZE=4096 '
)
CFLAGS = DEVICE + ' -g -Wall -Wno-unused-function -Wformat -Wformat-security -Warray-bounds -Wuninitialized \
-Wreturn-type -Wcomment -Wswitch -Wparentheses -specs=minilibc.specs -MP -MMD -Os -Wpointer-arith \
-Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin \
-fno-strict-aliasing -Wno-char-subscripts -Wno-unused-but-set-variable ' + GLOBAL_DEFINES
AFLAGS = DEVICE + ' -g -Wall -Wno-unused-function -Wformat -Wformat-security -Warray-bounds -Wuninitialized \
-Wreturn-type -Wcomment -Wswitch -Wparentheses -specs=minilibc.specs -MP -MMD -Os -Wpointer-arith \
-Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin \
-fno-strict-aliasing -Wno-char-subscripts -Wno-unused-but-set-variable ' + ' -MP -MMD -D"Default_IRQHandler=SW_handler" ' + GLOBAL_DEFINES
LFLAGS = DEVICE + ' -MP -MMD -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,-zmax-page-size=1024 -Wl,-Map=yoc.map -Wl,--whole-archive -Wl,--no-whole-archive -specs=minilibc.specs -nostartfiles -Wl,--gc-sections '
LFLAGS += ' -T ' + LINK_FILE
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -Os -g3'
AFLAGS += ' -g3'
else:
CFLAGS += ' -O2 -g2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
POST_ACTION += SIZE + ' $TARGET\n'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '../tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

250
bsp/xuantie/smartl/e901/template.cdkproj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Project Name="xuantie_rtthread" Version="1" Language="C">
<Description/>
<Dependencies Name="Debug"/>
<VendorInfo>
<VendorName>new_psf_project_SmartL_E906FD-R2S2(V1.7.9)</VendorName>
</VendorInfo>
<ToolsConfig>
<Compiler>
<Name>XTGccElfNewlib</Name>
<Version>latest</Version>
</Compiler>
</ToolsConfig>
<DebugSessions>
<watchExpressions/>
<memoryExpressions>;;;</memoryExpressions>
<statistics>;;MHZ</statistics>
<peripheralTabs/>
<WatchDisplayFormat/>
<LocalDisplayFormat/>
<debugLayout/>
<memoryTabColSizeExpressions/>
<QuickWatchDisplayFormat/>
</DebugSessions>
<BuildConfigs>
<BuildConfig Name="BuildSet">
<Target>
<ROMBank Selected="1">
<ROM1>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM1>
<ROM2>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM2>
<ROM3>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM3>
<ROM4>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM4>
<ROM5>
<InUse>no</InUse>
<Start/>
<Size/>
</ROM5>
</ROMBank>
<RAMBank>
<RAM1>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM1>
<RAM2>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM2>
<RAM3>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM3>
<RAM4>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM4>
<RAM5>
<InUse>no</InUse>
<Start/>
<Size/>
<Init>yes</Init>
</RAM5>
</RAMBank>
<CPU>e901plusbm-cp</CPU>
<UseMiniLib>yes</UseMiniLib>
<Endian>little</Endian>
<UseHardFloat>no</UseHardFloat>
<UseEnhancedLRW>no</UseEnhancedLRW>
<UseContinueBuild>no</UseContinueBuild>
<ToolchainID/>
<ToolchainVersion/>
<UseSemiHost>no</UseSemiHost>
</Target>
<Output>
<OutputName>$(ProjectName)</OutputName>
<Type>Executable</Type>
<CreateHexFile>no</CreateHexFile>
<CreateBinFile>no</CreateBinFile>
<Preprocessor>no</Preprocessor>
<Disassmeble>yes</Disassmeble>
<CallGraph>no</CallGraph>
<Map>no</Map>
</Output>
<User>
<BeforeCompile>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</BeforeCompile>
<BeforeMake>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</BeforeMake>
<AfterMake>
<RunUserProg>no</RunUserProg>
<UserProgName/>
<IsBatchScript>no</IsBatchScript>
</AfterMake>
<Tools/>
</User>
<Compiler>
<Define/>
<Undefine/>
<Optim>Optimize size (-Os)</Optim>
<DebugLevel>Maximum (-g3)</DebugLevel>
<IncludePath>$(ProjectPath);$(ProjectPath)/../../../../../csi_core/include;$(ProjectPath)/../../../../../csi_driver/include;$(ProjectPath)/../../../../../libs/include;$(ProjectPath)/../../../../../csi_driver/smartl_rv32/include;$(ProjectPath)/../../../../../csi_kernel/include;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/include/;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/include;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/portable/GCC/riscv;$(ProjectPath)/../../../../../csi_kernel/freertosv10.3.1/FreeRTOS/Source/portable/GCC/riscv/chip_specific_extensions/thead_rv32;$(ProjectPath)/../../../../../board/smartl_e906_evb/include;$(ProjectPath)/../../../../../projects/tests/dtest/include;$(ProjectPath)/../../../../../projects/tests/kernel/include;;;;;;;$(ProjectPath)/../../../../../projects/tests/kernel/freertos/configs</IncludePath>
<OtherFlags>-ffunction-sections -fdata-sections</OtherFlags>
<Verbose>no</Verbose>
<Ansi>no</Ansi>
<Syntax>no</Syntax>
<Pedantic>no</Pedantic>
<PedanticErr>no</PedanticErr>
<InhibitWarn>no</InhibitWarn>
<AllWarn>yes</AllWarn>
<WarnErr>no</WarnErr>
<OneElfS>yes</OneElfS>
<OneElfSPerData>no</OneElfSPerData>
<Fstrict>no</Fstrict>
</Compiler>
<Asm>
<Define/>
<Undefine/>
<IncludePath/>
<OtherFlags>-D"Default_IRQHandler=SW_handler"</OtherFlags>
<DebugLevel>gdwarf2</DebugLevel>
</Asm>
<Linker>
<Garbage>yes</Garbage>
<Garbage2>yes</Garbage2>
<LDFile>$(ProjectPath)/../../libraries/xuantie_libraries/chip_riscv_dummy/gcc_flash_smartl.ld</LDFile>
<LibName>m</LibName>
<LibPath/>
<OtherFlags>-Wl,-zmax-page-size=1024</OtherFlags>
<AutoLDFile>no</AutoLDFile>
<LinkType/>
<IncludeAllLibs>no</IncludeAllLibs>
<LinkSpecsType>none</LinkSpecsType>
<LinkUseNewlibNano>no</LinkUseNewlibNano>
<LinkUseMinilibc>no</LinkUseMinilibc>
</Linker>
<Debug>
<LoadApplicationAtStartup>yes</LoadApplicationAtStartup>
<Connector>SIM</Connector>
<StopAt>yes</StopAt>
<StopAtText>main</StopAtText>
<InitFile>$(ProjectPath)/utilities/gdb.init</InitFile>
<PreInit/>
<AfterLoadFile/>
<AutoRun>yes</AutoRun>
<ResetType>Hard Reset</ResetType>
<SoftResetVal>0</SoftResetVal>
<ResetAfterLoad>no</ResetAfterLoad>
<AfterResetFile/>
<Dumpcore>no</Dumpcore>
<DumpcoreText/>
<SVCFile/>
<ConfigICE>
<IP>localhost</IP>
<PORT>1025</PORT>
<CPUNumber>0</CPUNumber>
<Clock>12000</Clock>
<Delay>10</Delay>
<NResetDelay>100</NResetDelay>
<WaitReset>50</WaitReset>
<DDC>yes</DDC>
<TRST>no</TRST>
<PreReset>no</PreReset>
<DebugPrint>no</DebugPrint>
<Connect>Normal</Connect>
<ResetType>soft</ResetType>
<SoftResetVal>0</SoftResetVal>
<RTOSType>None</RTOSType>
<DownloadToFlash>no</DownloadToFlash>
<ResetAfterConnect>yes</ResetAfterConnect>
<GDBName/>
<GDBServerType>Local</GDBServerType>
<OtherFlags/>
<ICEEnablePCSampling>no</ICEEnablePCSampling>
<ICESamplingFreq>1000</ICESamplingFreq>
<RemoteICEEnablePCSampling>no</RemoteICEEnablePCSampling>
<RemoteICESamplingPort>1026</RemoteICESamplingPort>
<Version>latest</Version>
<SupportRemoteICEAsyncDebug>no</SupportRemoteICEAsyncDebug>
</ConfigICE>
<ConfigSIM>
<SIMTarget>soccfg/riscv32/smartl_e901_cfg.xml</SIMTarget>
<OtherFlags/>
<NoGraphic>yes</NoGraphic>
<Log>no</Log>
<SimTrace>no</SimTrace>
<Version>latest</Version>
</ConfigSIM>
<ConfigOpenOCD>
<OpenOCDExecutablePath/>
<OpenOCDLocally>yes</OpenOCDLocally>
<OpenOCDTelnetPortEnable>no</OpenOCDTelnetPortEnable>
<OpenOCDTelnetPort>4444</OpenOCDTelnetPort>
<OpenOCDTclPortEnable>no</OpenOCDTclPortEnable>
<OpenOCDTclPort>6666</OpenOCDTclPort>
<OpenOCDConfigOptions/>
<OpenOCDTimeout>5000</OpenOCDTimeout>
<OpenOCDRemoteIP>localhost</OpenOCDRemoteIP>
<OpenOCDRemotePort>3333</OpenOCDRemotePort>
<PluginID>openocd-sifive</PluginID>
<Version>latest</Version>
</ConfigOpenOCD>
</Debug>
<Flash>
<InitFile>$(ProjectPath)/../../../../../utilities//flash.init</InitFile>
<PreInit/>
<Erase>Erase Sectors</Erase>
<Algorithms Path=""/>
<Program>yes</Program>
<Verify>no</Verify>
<ResetAndRun>no</ResetAndRun>
<ResetType/>
<SoftResetVal/>
<FlashIndex>no</FlashIndex>
<FlashIndexVal>0</FlashIndexVal>
<External>no</External>
<Command/>
<Arguments/>
</Flash>
</BuildConfig>
</BuildConfigs>
</Project>

11
bsp/xuantie/smartl/e901/template.cdkws Normal file
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@@ -0,0 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<CDK_Workspace Name="template" Database="LanguageSever" DoubleClick="Yes">
<DefaultPackPath>$(CDKWS)\__workspace_pack__</DefaultPackPath>
<Project Name="xuantie_rtthread" Path="template.cdkproj" RootPath="" Active="Yes"/>
<BuildMatrix>
<WorkspaceConfiguration Name="Debug" Selected="yes">
<Environment/>
<Project Name="xuantie_rtthread" ConfigName="BuildSet"/>
</WorkspaceConfiguration>
</BuildMatrix>
</CDK_Workspace>

6
bsp/xuantie/smartl/e901/utilities/gdb.init Normal file
View File

@@ -0,0 +1,6 @@
set *(int *)0x0=0x6f
si
reset
set *(int *)0x40011008=0x0
set *(int *)0x4001101c=0x0