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[ADD][BSP]:Phytium开发板驱动适配 (#10533)

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适配Phytium开发板
This commit is contained in:
zhangyan
2025-08-11 10:50:30 +08:00
committed by GitHub
parent 302370720e
commit dce06ba907
116 changed files with 6058 additions and 40475 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
bsp/phytium/README.md
View File

@@ -33,6 +33,7 @@
| CAN | 支持 | CAN/CANFD设备通信 |
| I2C | 支持 | I2C设备通信 |
| SPI | 支持 | SPI设备通信 |
| QSPI | 支持 | QSPI设备通信 |
| DC | 支持 | DC显示设备 |
| USB3(XHCI) | 支持 | USB3(XHCI)设备支持|
| USB2(Host/Device) | 支持 | USB2(Host/Device)设备支持|
@@ -42,6 +43,7 @@
| Phytium PI | 支持 | 支持SMP |
| E2000D | 支持 | 支持SMP |
| E2000Q | 支持 | 支持SMP |
| PD2408 | 支持 | 支持SMP |
## 3. 如何在 Ubuntu, RT-Thread env, RT-Thread Studio 环境下使用此BSP
@@ -66,7 +68,7 @@
## 4. 如何添加开发板
>注:BSP已适配E2000Q_DEMO，E2000D_DEMO，PHYTIUMPI开发板，若需填加系列其他开发板，请按以下步骤进行
>注:BSP已适配E2000Q_DEMO，E2000D_DEMO，PHYTIUMPI，PD2408_TEST_A，PD2408_TEST_B开发板，若需填加系列其他开发板，请按以下步骤进行
- 请[阅读文档](./doc/how_to_add_cus_board.md)，按照指导添加自定义开发板

199
bsp/phytium/aarch32/.ci/attachconfig/ci.attachconfig.yml Normal file
View File

@@ -0,0 +1,199 @@
board.e2000d_demo_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.can
- devices.gpio
- devices.i2s
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PE2202=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO15=y
- CONFIG_RT_USING_CAN0=y
- CONFIG_RT_USING_CAN1=y
- CONFIG_RT_USING_I2S0=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_RT_USING_XMAC0=y
- CONFIG_RT_USING_SPIM2=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_USE_SDIF0_EMMC=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_MMCSD_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_RT_USING_DC_CHANNEL1=y
- CONFIG_BSP_USING_ES8336=y
- CONFIG_I2C_USE_MIO=y
board.e2000q_demo_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.can
- devices.gpio
- devices.i2s
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_E2000Q_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO15=y
- CONFIG_RT_USING_CAN0=y
- CONFIG_RT_USING_CAN1=y
- CONFIG_RT_USING_I2S0=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_RT_USING_XMAC0=y
- CONFIG_RT_USING_SPIM2=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_USE_SDIF0_EMMC=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_MMCSD_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_RT_USING_DC_CHANNEL1=y
- CONFIG_BSP_USING_ES8336=y
- CONFIG_I2C_USE_MIO=y
board.phytium_pi_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.gpio
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO10=y
- CONFIG_RT_USING_PWM1=y
- CONFIG_RT_USING_SPIM0=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_I2C_USE_MIO=y
board.e2000d_demo_rtthread_pusb2_dc:
kconfig:
- CONFIG_TARGET_PE2202=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_DEVICE=y
- CONFIG_RT_CHERRYUSB_DEVICE_SPEED_HS=y
- CONFIG_RT_CHERRYUSB_DEVICE_CUSTOM=y
- CONFIG_RT_CHERRYUSB_DEVICE_TEMPLATE_NONE=y
- CONFIG_RT_USING_USB=y
- CONFIG_RT_USING_USB_DEVICE=y
- CONFIG_RT_USBD_THREAD_STACK_SZ=4096
- CONFIG_USB_VENDOR_ID=0x0FFE
- CONFIG_USB_PRODUCT_ID=0x0001
- CONFIG_RT_USB_DEVICE_NONE=y
board.e2000d_demo_rtthread_pusb2_xhic:
kconfig:
- CONFIG_TARGET_PE2202=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_XHCI=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST_MSC=y
board.phytium_pi_pusb2_hc:
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_PUSB2=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST=y
board.phytium_pi_pusb2_xhic:
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_XHCI=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST_MSC=y
devices.i2c:
kconfig:
- CONFIG_BSP_USING_I2C_LAYER=y
- CONFIG_BSP_USING_I2C=y
devices.dc:
kconfig:
- CONFIG_BSP_USING_DC=y
devices.can:
kconfig:
- CONFIG_BSP_USING_CAN=y
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.i2s:
kconfig:
- CONFIG_BSP_USING_I2S=y
devices.pwm:
kconfig:
- CONFIG_BSP_USING_PWM=y
devices.spi:
kconfig:
- CONFIG_BSP_USING_SPI=y
devices.qspi:
kconfig:
- CONFIG_BSP_USING_QSPI=y
devices.uart:
kconfig:
- CONFIG_BSP_USING_UART=y
devices.xmac:
kconfig:
- CONFIG_BSP_USING_ETH=y
devices.sdif:
kconfig:
- CONFIG_BSP_USING_SDIF=y
devices.devices_auto_test:
kconfig:
- CONFIG_BSP_USING_DRIVERS_EXAMPLE=y
- CONFIG_BSP_USING_DRIVERS_AUTO_TEST=y
scons.args: &scons
scons_arg:
- '--strict'

121
bsp/phytium/aarch32/.config
View File

@@ -113,8 +113,8 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_CPUS_NR=1
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@@ -128,7 +128,6 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
@@ -146,8 +145,6 @@ CONFIG_RT_DEBUGING_ASSERT=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
# CONFIG_RT_DEBUGING_AUTO_INIT is not set
# CONFIG_RT_DEBUGING_SPINLOCK is not set
# CONFIG_RT_DEBUGING_CRITICAL is not set
# CONFIG_RT_USING_CI_ACTION is not set
#
@@ -188,7 +185,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50200
CONFIG_RT_VER_NUM=0x50201
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -359,7 +356,6 @@ CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
# end of Device Drivers
#
@@ -1448,72 +1444,27 @@ CONFIG_RT_PAGE_MAX_ORDER=11
#
# On-chip Peripheral Drivers
#
# CONFIG_BSP_USING_DRIVERS_EXAMPLE is not set
CONFIG_BSP_USING_DRIVERS_EXAMPLE=y
CONFIG_BSP_USING_DRIVERS_AUTO_TEST=y
CONFIG_BSP_USING_IOPAD=y
CONFIG_BSP_USING_UART_LAYER=y
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART0=y
# CONFIG_BSP_USING_UART_MSG is not set
# CONFIG_RT_USING_UART0 is not set
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_BSP_USING_SPI=y
# CONFIG_RT_USING_SPIM0 is not set
# CONFIG_RT_USING_SPIM1 is not set
CONFIG_RT_USING_SPIM2=y
# CONFIG_RT_USING_SPIM3 is not set
CONFIG_BSP_USING_CAN=y
CONFIG_RT_USING_CANFD=y
# CONFIG_RT_USING_FILTER is not set
CONFIG_RT_USING_CAN0=y
CONFIG_RT_USING_CAN1=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_QSPI=y
CONFIG_RT_USING_QSPI0=y
CONFIG_USING_QSPI_CHANNEL0=y
# CONFIG_USING_QSPI_CHANNEL1 is not set
CONFIG_BSP_USING_ETH=y
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
# CONFIG_RT_USING_PWM6 is not set
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
# CONFIG_RT_USING_MIO0 is not set
# CONFIG_RT_USING_MIO1 is not set
# CONFIG_RT_USING_MIO2 is not set
# CONFIG_RT_USING_MIO3 is not set
# CONFIG_RT_USING_MIO4 is not set
# CONFIG_RT_USING_MIO5 is not set
# CONFIG_RT_USING_MIO6 is not set
# CONFIG_RT_USING_MIO7 is not set
# CONFIG_RT_USING_MIO8 is not set
# CONFIG_RT_USING_MIO9 is not set
# CONFIG_RT_USING_MIO10 is not set
# CONFIG_RT_USING_MIO11 is not set
# CONFIG_RT_USING_MIO12 is not set
# CONFIG_RT_USING_MIO13 is not set
# CONFIG_RT_USING_MIO14 is not set
CONFIG_RT_USING_MIO15=y
# CONFIG_I2C_USE_CONTROLLER is not set
CONFIG_BSP_USING_SDIF=y
CONFIG_BSP_USING_SDCARD_FATFS=y
CONFIG_USING_SDIF0=y
# CONFIG_USE_SDIF0_TF is not set
CONFIG_USE_SDIF0_EMMC=y
CONFIG_USING_SDIF1=y
CONFIG_USE_SDIF1_TF=y
# CONFIG_USE_SDIF1_EMMC is not set
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
CONFIG_BSP_USING_I2S=y
CONFIG_RT_I2S_SAMPLERATE=8000
CONFIG_RT_I2S_SAMPLEBITS=16
CONFIG_RT_USING_I2S0=y
# CONFIG_BSP_USING_SPI_LAYER is not set
# CONFIG_BSP_USING_I2C_LAYER is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_ETH_LAYER is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIF_LAYER is not set
# CONFIG_BSP_USING_DC is not set
# CONFIG_BSP_USING_I2S is not set
# CONFIG_BSP_USING_DEVICE is not set
# end of On-chip Peripheral Drivers
#
@@ -1532,23 +1483,23 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# Soc configuration
#
# CONFIG_TARGET_PHYTIUMPI is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
# CONFIG_TARGET_FT2004 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_PE2204 is not set
CONFIG_TARGET_PE2202=y
# CONFIG_TARGET_PE2201 is not set
# CONFIG_TARGET_PD1904 is not set
# CONFIG_TARGET_PD2008 is not set
# CONFIG_TARGET_PD2308 is not set
# CONFIG_TARGET_PS2316 is not set
# CONFIG_TARGET_PD2408 is not set
# CONFIG_TARGET_QEMU_VIRT is not set
CONFIG_SOC_NAME="e2000"
CONFIG_TARGET_TYPE_NAME="q"
CONFIG_SOC_CORE_NUM=4
CONFIG_SOC_NAME="pe220x"
CONFIG_TARGET_TYPE_NAME="pe2202"
CONFIG_SOC_CORE_NUM=2
CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000
CONFIG_F64BIT_MEMORY_LENGTH=0x800000000
CONFIG_TARGET_E2000=y
CONFIG_TARGET_PE220X=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -1557,7 +1508,12 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Board Configuration
#
CONFIG_BOARD_NAME="demo"
CONFIG_E2000D_DEMO_BOARD=y
CONFIG_BOARD_NAME="pe2202_demo"
#
# IO mux configuration when board start up
#
# CONFIG_USE_SPI_IOPAD is not set
# CONFIG_USE_GPIO_IOPAD is not set
# CONFIG_USE_CAN_IOPAD is not set
@@ -1567,11 +1523,6 @@ CONFIG_BOARD_NAME="demo"
# CONFIG_USE_TACHO_IOPAD is not set
# CONFIG_USE_UART_IOPAD is not set
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
CONFIG_E2000Q_DEMO_BOARD=y
#
# IO mux configuration when board start up
#
# end of IO mux configuration when board start up
# CONFIG_CUS_DEMO_BOARD is not set
@@ -1590,6 +1541,8 @@ CONFIG_LOG_ERROR=y
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_NS_GTIMER=y
# CONFIG_USE_VIRTUAL_GTIMER is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set

121
bsp/phytium/aarch32/configs/e2000q_demo_rtthread → bsp/phytium/aarch32/.config.origin
View File

@@ -113,8 +113,8 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_CPUS_NR=1
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@@ -128,7 +128,6 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
@@ -146,8 +145,6 @@ CONFIG_RT_DEBUGING_ASSERT=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
# CONFIG_RT_DEBUGING_AUTO_INIT is not set
# CONFIG_RT_DEBUGING_SPINLOCK is not set
# CONFIG_RT_DEBUGING_CRITICAL is not set
# CONFIG_RT_USING_CI_ACTION is not set
#
@@ -188,7 +185,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50200
CONFIG_RT_VER_NUM=0x50201
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -359,7 +356,6 @@ CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
# end of Device Drivers
#
@@ -1448,72 +1444,27 @@ CONFIG_RT_PAGE_MAX_ORDER=11
#
# On-chip Peripheral Drivers
#
# CONFIG_BSP_USING_DRIVERS_EXAMPLE is not set
CONFIG_BSP_USING_DRIVERS_EXAMPLE=y
CONFIG_BSP_USING_DRIVERS_AUTO_TEST=y
CONFIG_BSP_USING_IOPAD=y
CONFIG_BSP_USING_UART_LAYER=y
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART0=y
# CONFIG_BSP_USING_UART_MSG is not set
# CONFIG_RT_USING_UART0 is not set
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_BSP_USING_SPI=y
# CONFIG_RT_USING_SPIM0 is not set
# CONFIG_RT_USING_SPIM1 is not set
CONFIG_RT_USING_SPIM2=y
# CONFIG_RT_USING_SPIM3 is not set
CONFIG_BSP_USING_CAN=y
CONFIG_RT_USING_CANFD=y
# CONFIG_RT_USING_FILTER is not set
CONFIG_RT_USING_CAN0=y
CONFIG_RT_USING_CAN1=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_QSPI=y
CONFIG_RT_USING_QSPI0=y
CONFIG_USING_QSPI_CHANNEL0=y
# CONFIG_USING_QSPI_CHANNEL1 is not set
CONFIG_BSP_USING_ETH=y
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
# CONFIG_RT_USING_PWM6 is not set
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
# CONFIG_RT_USING_MIO0 is not set
# CONFIG_RT_USING_MIO1 is not set
# CONFIG_RT_USING_MIO2 is not set
# CONFIG_RT_USING_MIO3 is not set
# CONFIG_RT_USING_MIO4 is not set
# CONFIG_RT_USING_MIO5 is not set
# CONFIG_RT_USING_MIO6 is not set
# CONFIG_RT_USING_MIO7 is not set
# CONFIG_RT_USING_MIO8 is not set
# CONFIG_RT_USING_MIO9 is not set
# CONFIG_RT_USING_MIO10 is not set
# CONFIG_RT_USING_MIO11 is not set
# CONFIG_RT_USING_MIO12 is not set
# CONFIG_RT_USING_MIO13 is not set
# CONFIG_RT_USING_MIO14 is not set
CONFIG_RT_USING_MIO15=y
# CONFIG_I2C_USE_CONTROLLER is not set
CONFIG_BSP_USING_SDIF=y
CONFIG_BSP_USING_SDCARD_FATFS=y
CONFIG_USING_SDIF0=y
# CONFIG_USE_SDIF0_TF is not set
CONFIG_USE_SDIF0_EMMC=y
CONFIG_USING_SDIF1=y
CONFIG_USE_SDIF1_TF=y
# CONFIG_USE_SDIF1_EMMC is not set
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
CONFIG_BSP_USING_I2S=y
CONFIG_RT_I2S_SAMPLERATE=8000
CONFIG_RT_I2S_SAMPLEBITS=16
CONFIG_RT_USING_I2S0=y
# CONFIG_BSP_USING_SPI_LAYER is not set
# CONFIG_BSP_USING_I2C_LAYER is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_ETH_LAYER is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIF_LAYER is not set
# CONFIG_BSP_USING_DC is not set
# CONFIG_BSP_USING_I2S is not set
# CONFIG_BSP_USING_DEVICE is not set
# end of On-chip Peripheral Drivers
#
@@ -1532,23 +1483,23 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# Soc configuration
#
# CONFIG_TARGET_PHYTIUMPI is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
# CONFIG_TARGET_FT2004 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_PE2204 is not set
CONFIG_TARGET_PE2202=y
# CONFIG_TARGET_PE2201 is not set
# CONFIG_TARGET_PD1904 is not set
# CONFIG_TARGET_PD2008 is not set
# CONFIG_TARGET_PD2308 is not set
# CONFIG_TARGET_PS2316 is not set
# CONFIG_TARGET_PD2408 is not set
# CONFIG_TARGET_QEMU_VIRT is not set
CONFIG_SOC_NAME="e2000"
CONFIG_TARGET_TYPE_NAME="q"
CONFIG_SOC_CORE_NUM=4
CONFIG_SOC_NAME="pe220x"
CONFIG_TARGET_TYPE_NAME="pe2202"
CONFIG_SOC_CORE_NUM=2
CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000
CONFIG_F64BIT_MEMORY_LENGTH=0x800000000
CONFIG_TARGET_E2000=y
CONFIG_TARGET_PE220X=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -1557,7 +1508,12 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Board Configuration
#
CONFIG_BOARD_NAME="demo"
CONFIG_E2000D_DEMO_BOARD=y
CONFIG_BOARD_NAME="pe2202_demo"
#
# IO mux configuration when board start up
#
# CONFIG_USE_SPI_IOPAD is not set
# CONFIG_USE_GPIO_IOPAD is not set
# CONFIG_USE_CAN_IOPAD is not set
@@ -1567,11 +1523,6 @@ CONFIG_BOARD_NAME="demo"
# CONFIG_USE_TACHO_IOPAD is not set
# CONFIG_USE_UART_IOPAD is not set
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
CONFIG_E2000Q_DEMO_BOARD=y
#
# IO mux configuration when board start up
#
# end of IO mux configuration when board start up
# CONFIG_CUS_DEMO_BOARD is not set
@@ -1590,6 +1541,8 @@ CONFIG_LOG_ERROR=y
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_NS_GTIMER=y
# CONFIG_USE_VIRTUAL_GTIMER is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set

38
bsp/phytium/aarch32/README.md
View File

@@ -106,21 +106,15 @@ rtthread_a32.map
## 2. 如何选择开发板
>注：在 RT-Thread env 环境下使用`menuconfig`指令即可打开配置菜单，在Ubuntu下需要使用`scons --menuconfig`
- 使用`scons --attach=?`查看当前支持的开发板
![](./figures/scons_attach.png)
- 以 E2000Q RT-Thread为例，Linux 环境下，运行`make load_e2000d_demo_rtthread`加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置
- 以`E2000Q_DEMO`开发板为例，进入aarch64目录后，运行`scons --attach=board.e2000q_demo_rtthread`加载默认的`rtconfig.h`, 然后输入下列命令，进入`menuconfig`进一步配置
```shell
scons --menuconfig
```
开发者通过以下选择进行配置
```
Standalone Setting > Board Configuration > Chip
```
![](./figures/board_select.png)
## 3. 如何选择驱动
```shell
@@ -128,9 +122,8 @@ scons --menuconfig
```
开发者通过以下选项进行驱动的使能
```
Hardware Drivers > On-chip Peripheral Drivers
Hardware Drivers Config > On-chip Peripheral Drivers
```
![](./figures/select_driver.png)
@@ -145,28 +138,15 @@ scons --menuconfig
![](./figures/debug_info.png)
## 5. 如何切换至 RT-Thread Smart 工作模式
### Ubuntu环境下可使用以下指令加载RT-Smart默认配置
- 以E2000D_DEMO开发板为例
- 输入下列命令，进入`menuconfig`进一步配置
```shell
make load_e2000d_demo_rtsmart
```
### RT-Thread env环境不方便安装make工具，可按照以下步骤加载RT-Smart默认配置
1. 查看`makefile`文件，找到`make load_e2000d_demo_rtsmart`
![load_e2000d_rtsmart](./figures/load_e2000d_rtsmart.png)
2. 输入以下指令
```shell
cp ./configs/e2000d_demo_rtsmart ./.config -f
cp ./configs/e2000d_demo_rtsmart.h ./rtconfig.h -f
scons -c
scons --menuconfig
```
- 在RT-Thread Kernel菜单中勾选以下选项
![](./figures/rtsmart_config.png)
## 6. 启动镜像程序
1. 完成配置后，使用以下指令进行clean和重新编译
@@ -174,4 +154,4 @@ scons -c
scons -c
scons -j8
```
2. 按照指导[启动镜像程序](../doc/how_to_flashed_binary.md)
2. 按照指导[启动镜像程序](../doc/how_to_flashed_binary.md)

12
bsp/phytium/aarch32/applications/main.c
View File

@@ -15,7 +15,9 @@
#include <rtthread.h>
#include <board.h>
#ifdef BSP_USING_DRIVERS_EXAMPLE
#include "auto_test.h"
#endif
#define ASSERT_STATIC(expression) \
extern int assert_static[(expression) ? 1 : -1]
@@ -26,9 +28,9 @@
#ifndef RT_USING_SMP
ASSERT_STATIC(RT_CPUS_NR == 1U); /* please set RT_CPUS_NR = 1 when SMP off */
#else
#if defined(TARGET_E2000D)
#if defined(TARGET_PE2202)
ASSERT_STATIC(RT_CPUS_NR <= 2U); /* use 2 cores at most */
#elif defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#elif defined(TARGET_PE2204)
ASSERT_STATIC(RT_CPUS_NR <= 4U); /* use 4 cores at most */
#endif
#endif
@@ -87,7 +89,9 @@ void demo_core(void)
int main(void)
{
#ifdef RT_USING_SMP
#ifdef BSP_USING_DRIVERS_EXAMPLE
auto_test();
#elif defined RT_USING_SMP
demo_core();
#endif
return RT_EOK;

1618
bsp/phytium/aarch32/configs/e2000d_demo_rtsmart
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File diff suppressed because it is too large Load Diff

635
bsp/phytium/aarch32/configs/e2000d_demo_rtsmart.h
View File

@@ -1,635 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_DFS_MQUEUE
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

1637
bsp/phytium/aarch32/configs/e2000d_demo_rtthread
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622
bsp/phytium/aarch32/configs/e2000d_demo_rtthread.h
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@@ -1,622 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch32/configs/e2000d_demo_rtthread_pusb2_dc.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_DEVICE
#define RT_CHERRYUSB_DEVICE_SPEED_HS
#define RT_CHERRYUSB_DEVICE_PUSB2
#define RT_CHERRYUSB_DEVICE_MSC
#define RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch32/configs/e2000q_demo_rtsmart.h
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@@ -1,639 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_DFS_MQUEUE
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

616
bsp/phytium/aarch32/configs/e2000q_demo_rtthread.h
View File

@@ -1,616 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch32/configs/phytium_pi_rtsmart
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bsp/phytium/aarch32/configs/phytium_pi_rtsmart.h
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@@ -1,629 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xc0000000
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_DFS_MQUEUE
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define LWP_ENABLE_ASID
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch32/configs/phytium_pi_rtthread_pusb2_hc.h
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@@ -1,603 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_MESSAGEQUEUE_PRIORITY
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
#define RT_USING_DFS_MQUEUE
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 1024
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 4096
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 4096
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_PUSB2
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_AIO
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
#define RT_USING_POSIX_PIPE
#define RT_USING_POSIX_PIPE_SIZE 512
#define RT_USING_POSIX_MESSAGE_QUEUE
#define RT_USING_POSIX_MESSAGE_SEMAPHORE
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 11
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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@@ -1,3 +1,5 @@
include .config
.PHONY: debug boot all clean menuconfig
CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
@@ -11,46 +13,23 @@ AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
include .config
ifdef CONFIG_E2000Q_DEMO_BOARD
RTCONFIG := e2000q_demo
endif
ifdef CONFIG_E2000D_DEMO_BOARD
RTCONFIG := e2000d_demo
endif
ifdef CONFIG_TARGET_PHYTIUMPI
RTCONFIG := phytium_pi
endif
ifdef CONFIG_RT_USING_SMART
RTCONFIG := $(RTCONFIG)_rtsmart
else
RTCONFIG := $(RTCONFIG)_rtthread
endif
ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
ifdef CONFIG_RT_CHERRYUSB_HOST_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_hc
endif
ifdef CONFIG_RT_CHERRYUSB_DEVICE_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_dc
endif
boot:
make all
cp rtthread_a32.elf /mnt/d/tftpboot
cp rtthread_a32.bin /mnt/d/tftpboot
make mv_file
mv_file:
mv rtthread_a32.elf rtthread_a32_$(CONFIG_BOARD_NAME).elf
mv rtthread_a32.bin rtthread_a32_$(CONFIG_BOARD_NAME).bin
cp rtthread_a32_$(CONFIG_BOARD_NAME).elf /mnt/d/tftpboot/rtthread_a32.elf
cp rtthread_a32_$(CONFIG_BOARD_NAME).bin /mnt/d/tftpboot/rtthread_a32.bin
mv_auto_test_file:
mv rtthread_a32.elf rtthread_a32_$(CONFIG_BOARD_NAME).elf
mv rtthread_a32_$(CONFIG_BOARD_NAME).elf /home/zhugy/tftpboot/rtthread_elfs/
debug:
@$(OD) -D rtthread_a32.elf > rtthread_a32.asm
@$(OD) -S rtthread_a32.elf > rtthread_a32.dis
@$(OD) -D rtthread_a32_$(CONFIG_BOARD_NAME).elf > rtthread_a32_$(CONFIG_BOARD_NAME).asm
@$(OD) -S rtthread_a32_$(CONFIG_BOARD_NAME).elf > rtthread_a32_$(CONFIG_BOARD_NAME).dis
all:
@echo "Build started..."
@@ -63,80 +42,3 @@ clean:
menuconfig:
@echo "Running menuconfig..."
scons --menuconfig
saveconfig:
@echo "Save configs to" ./configs/$(RTCONFIG)
@cp ./.config ./configs/$(RTCONFIG) -f
@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
load_e2000q_demo_rtsmart:
@echo "Load configs from ./configs/e2000q_demo_rtsmart"
@cp ./configs/e2000q_demo_rtsmart ./.config -f
@cp ./configs/e2000q_demo_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtsmart_test:
@echo "Load configs from ./configs/e2000q_demo_rtsmart_test"
@cp ./configs/e2000q_demo_rtsmart_test ./.config -f
@cp ./configs/e2000q_demo_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtthread:
@echo "Load configs from ./configs/e2000q_demo_rtthread"
@cp ./configs/e2000q_demo_rtthread ./.config -f
@cp ./configs/e2000q_demo_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtthread_test:
@echo "Load configs from ./configs/e2000q_demo_rtthread_test"
@cp ./configs/e2000q_demo_rtthread_test ./.config -f
@cp ./configs/e2000q_demo_rtthread_test.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtsmart:
@echo "Load configs from ./configs/e2000d_demo_rtsmart"
@cp ./configs/e2000d_demo_rtsmart ./.config -f
@cp ./configs/e2000d_demo_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtsmart_test:
@echo "Load configs from ./configs/e2000d_demo_rtsmart_test"
@cp ./configs/e2000d_demo_rtsmart_test ./.config -f
@cp ./configs/e2000d_demo_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtthread:
@echo "Load configs from ./configs/e2000d_demo_rtthread"
@cp ./configs/e2000d_demo_rtthread ./.config -f
@cp ./configs/e2000d_demo_rtthread.h ./rtconfig.h -f
scons -c
load_e2000d_demo_rtthread_pusb2_dc:
@echo "Load configs from ./configs/e2000d_demo_rtthread_pusb2_dc"
@cp ./configs/e2000d_demo_rtthread_pusb2_dc ./.config -f
@cp ./configs/e2000d_demo_rtthread_pusb2_dc.h ./rtconfig.h -f
scons -c
load_e2000d_demo_rtthread_test:
@echo "Load configs from ./configs/e2000d_demo_rtthread_test"
@cp ./configs/e2000d_demo_rtthread_test ./.config -f
@cp ./configs/e2000d_demo_rtthread_test.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtthread:
@echo "Load configs from ./configs/phytium_pi_rtthread"
@cp ./configs/phytium_pi_rtthread ./.config -f
@cp ./configs/phytium_pi_rtthread.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtthread_pusb2_hc:
@echo "Load configs from ./configs/phytium_pi_rtthread_pusb2_hc"
@cp ./configs/phytium_pi_rtthread_pusb2_hc ./.config -f
@cp ./configs/phytium_pi_rtthread_pusb2_hc.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtsmart:
@echo "Load configs from ./configs/phytium_pi_rtsmart"
@cp ./configs/phytium_pi_rtsmart ./.config -f
@cp ./configs/phytium_pi_rtsmart.h ./rtconfig.h -f
@scons -c

55
bsp/phytium/aarch32/rtconfig.h
View File

@@ -62,8 +62,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
@@ -74,7 +73,6 @@
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
@@ -111,7 +109,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
@@ -216,7 +214,6 @@
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@@ -535,39 +532,12 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_DRIVERS_EXAMPLE
#define BSP_USING_DRIVERS_AUTO_TEST
#define BSP_USING_IOPAD
#define BSP_USING_UART_LAYER
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
@@ -582,22 +552,22 @@
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define TARGET_PE2202
#define SOC_NAME "pe220x"
#define TARGET_TYPE_NAME "pe2202"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define TARGET_PE220X
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
#define E2000D_DEMO_BOARD
#define BOARD_NAME "pe2202_demo"
/* IO mux configuration when board start up */
@@ -608,6 +578,7 @@
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_NS_GTIMER
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */

52
bsp/phytium/aarch32/configs/phytium_pi_rtthread.h → bsp/phytium/aarch32/rtconfig.h.origin
View File

@@ -62,8 +62,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
@@ -74,7 +73,6 @@
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
@@ -99,6 +97,7 @@
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
@@ -110,8 +109,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_CACHE
@@ -203,6 +201,10 @@
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
@@ -212,12 +214,6 @@
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@@ -536,26 +532,12 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_DRIVERS_EXAMPLE
#define BSP_USING_DRIVERS_AUTO_TEST
#define BSP_USING_IOPAD
#define BSP_USING_UART_LAYER
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define BSP_USING_SDIF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
@@ -570,21 +552,22 @@
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define TARGET_PE2202
#define SOC_NAME "pe220x"
#define TARGET_TYPE_NAME "pe2202"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define TARGET_PE220X
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
#define E2000D_DEMO_BOARD
#define BOARD_NAME "pe2202_demo"
/* IO mux configuration when board start up */
@@ -595,6 +578,7 @@
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_ERROR
#define USE_NS_GTIMER
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
/* end of Sdk common configuration */

2
bsp/phytium/aarch32/thread-env.sh
View File

@@ -5,7 +5,7 @@ export RTT_EXEC_PATH=$(pwd)/tools/gcc-arm-10.3-2021.07-x86_64-arm-none-eabi/bin
export RTT_CC_PREFIX=arm-none-eabi-
export PATH=$PATH:$RTT_EXEC_PATH
echo "arch => aarch64"
echo "arch => aarch32"
echo "CC => ${RTT_CC}"
echo "PREFIX => ${RTT_CC_PREFIX}"
echo "EXEC_PATH => ${RTT_EXEC_PATH}"

268
bsp/phytium/aarch64/.ci/attachconfig/ci.attachconfig.yml Normal file
View File

@@ -0,0 +1,268 @@
board.pd2408_test_a_rtthread:
depends:
- devices.uart
- devices.qspi
- devices.i2c_msg
- devices.spi_msg
- devices.xmac_msg
- devices.pwm
- devices.sdif_msg
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PD2408=y
- CONFIG_PD2408_TEST_A_BOARD=y
- CONFIG_RT_CPUS_NR=8
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_RT_USING_I2C3_MSG=y
- CONFIG_RT_USING_SPIM0_MSG=y
- CONFIG_RT_USING_XMAC0_MSG=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USE_SDIF0_TF=y
board.pd2408_test_b_rtthread:
depends:
- devices.uart
- devices.qspi
- devices.i2c_msg
- devices.spi_msg
- devices.xmac_msg
- devices.pwm
- devices.sdif_msg
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PD2408=y
- CONFIG_PD2408_TEST_B_BOARD=y
- CONFIG_RT_CPUS_NR=8
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_RT_USING_I2C3_MSG=y
- CONFIG_RT_USING_SPIM0_MSG=y
- CONFIG_RT_USING_XMAC0_MSG=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USE_SDIF0_TF=y
board.e2000d_demo_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.can
- devices.gpio
- devices.i2s
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PE2202=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO15=y
- CONFIG_RT_USING_CAN0=y
- CONFIG_RT_USING_CAN1=y
- CONFIG_RT_USING_I2S0=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_RT_USING_XMAC0=y
- CONFIG_RT_USING_SPIM2=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_USE_SDIF0_EMMC=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_MMCSD_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_RT_USING_DC_CHANNEL1=y
- CONFIG_BSP_USING_ES8336=y
- CONFIG_I2C_USE_MIO=y
board.e2000q_demo_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.can
- devices.gpio
- devices.i2s
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
- devices.devices_auto_test
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_E2000Q_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO15=y
- CONFIG_RT_USING_CAN0=y
- CONFIG_RT_USING_CAN1=y
- CONFIG_RT_USING_I2S0=y
- CONFIG_RT_USING_PWM0=y
- CONFIG_RT_USING_XMAC0=y
- CONFIG_RT_USING_SPIM2=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF0=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_USE_SDIF0_EMMC=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_MMCSD_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_RT_USING_DC_CHANNEL1=y
- CONFIG_BSP_USING_ES8336=y
- CONFIG_I2C_USE_MIO=y
board.phytium_pi_rtthread:
depends:
- devices.uart
- devices.i2c
- devices.gpio
- devices.pwm
- devices.spi
- devices.qspi
- devices.xmac
- devices.sdif
- devices.dc
kconfig:
- CONFIG_TARGET_PE2204=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_UART1=y
- CONFIG_RT_USING_MIO10=y
- CONFIG_RT_USING_PWM1=y
- CONFIG_RT_USING_SPIM0=y
- CONFIG_RT_USING_QSPI0=y
- CONFIG_RT_USING_XMAC0=y
- CONFIG_USING_QSPI_CHANNEL0=y
- CONFIG_BSP_USING_SDCARD_FATFS=y
- CONFIG_USING_SDIF1=y
- CONFIG_USE_SDIF1_TF=y
- CONFIG_RT_SDIO_STACK_SIZE=4096
- CONFIG_RT_USING_DC_CHANNEL0=y
- CONFIG_I2C_USE_MIO=y
board.e2000d_demo_rtthread_pusb2_dc:
kconfig:
- CONFIG_TARGET_E2000D=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_DEVICE=y
- CONFIG_RT_CHERRYUSB_DEVICE_SPEED_HS=y
- CONFIG_RT_CHERRYUSB_DEVICE_CUSTOM=y
- CONFIG_RT_CHERRYUSB_DEVICE_TEMPLATE_NONE=y
- CONFIG_RT_USING_USB=y
- CONFIG_RT_USING_USB_DEVICE=y
- CONFIG_RT_USBD_THREAD_STACK_SZ=4096
- CONFIG_USB_VENDOR_ID=0x0FFE
- CONFIG_USB_PRODUCT_ID=0x0001
- CONFIG_RT_USB_DEVICE_NONE=y
board.e2000d_demo_rtthread_pusb2_xhic:
kconfig:
- CONFIG_TARGET_E2000D=y
- CONFIG_E2000D_DEMO_BOARD=y
- CONFIG_RT_CPUS_NR=2
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_XHCI=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST_MSC=y
board.phytium_pi_pusb2_hc:
kconfig:
- CONFIG_TARGET_PHYTIUMPI=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_PUSB2=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST=y
board.phytium_pi_pusb2_xhic:
kconfig:
- CONFIG_TARGET_PHYTIUMPI=y
- CONFIG_PHYTIUMPI_FIREFLY_BOARD=y
- CONFIG_RT_CPUS_NR=4
- CONFIG_RT_USING_CHERRYUSB=y
- CONFIG_RT_CHERRYUSB_HOST=y
- CONFIG_RT_CHERRYUSB_HOST_XHCI=y
- CONFIG_RT_CHERRYUSB_HOST_HID=y
- CONFIG_RT_CHERRYUSB_HOST_MSC=y
devices.i2c:
kconfig:
- CONFIG_BSP_USING_I2C_LAYER=y
- CONFIG_BSP_USING_I2C=y
devices.i2c_msg:
kconfig:
- CONFIG_BSP_USING_I2C_LAYER=y
- CONFIG_BSP_USING_I2C_MSG=y
devices.spi:
kconfig:
- CONFIG_BSP_USING_SPI_LAYER=y
- CONFIG_BSP_USING_SPI=y
devices.spi_msg:
kconfig:
- CONFIG_BSP_USING_SPI_LAYER=y
- CONFIG_BSP_USING_SPI_MSG=y
devices.dc:
kconfig:
- CONFIG_BSP_USING_DC=y
devices.can:
kconfig:
- CONFIG_BSP_USING_CAN=y
devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.i2s:
kconfig:
- CONFIG_BSP_USING_I2S=y
devices.pwm:
kconfig:
- CONFIG_BSP_USING_PWM=y
devices.qspi:
kconfig:
- CONFIG_BSP_USING_QSPI=y
devices.uart:
kconfig:
- CONFIG_BSP_USING_UART=y
devices.uart_msg:
kconfig:
- CONFIG_BSP_USING_UART_MSG=y
devices.xmac:
kconfig:
- CONFIG_BSP_USING_ETH=y
devices.xmac_msg:
kconfig:
- CONFIG_BSP_USING_ETH_MSG=y
devices.sdif:
kconfig:
- CONFIG_BSP_USING_SDIF=y
devices.sdif_msg:
kconfig:
- CONFIG_BSP_USING_SDIF_MSG=y
devices.devices_auto_test:
kconfig:
- CONFIG_BSP_USING_DRIVERS_EXAMPLE=y
- CONFIG_BSP_USING_DRIVERS_AUTO_TEST=y
scons.args: &scons
scons_arg:
- '--strict'

175
bsp/phytium/aarch64/.config
View File

@@ -124,7 +124,7 @@ CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_AMP is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_CPUS_NR=2
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@@ -192,13 +192,13 @@ CONFIG_RT_USING_HEAP=y
# end of Memory Management
CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_DEVICE_OPS=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_THREADSAFE_PRINTF is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50200
CONFIG_RT_VER_NUM=0x50201
# CONFIG_RT_USING_STDC_ATOMIC is not set
CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
# end of RT-Thread Kernel
@@ -258,9 +258,12 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_V1 is not set
CONFIG_RT_USING_DFS_V2=y
CONFIG_RT_USING_DFS_V1=y
# CONFIG_RT_USING_DFS_V2 is not set
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_RT_USING_DFS_ELMFAT=y
#
@@ -288,10 +291,13 @@ CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
# end of elm-chan's FatFs, Generic FAT Filesystem Module
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ISO9660 is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
CONFIG_RT_USING_DFS_RAMFS=y
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_MQUEUE is not set
# CONFIG_RT_USING_DFS_NFS is not set
# end of DFS: device virtual file system
# CONFIG_RT_USING_FAL is not set
@@ -313,8 +319,8 @@ CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_SERIAL_BYPASS is not set
CONFIG_RT_USING_CAN=y
CONFIG_RT_CAN_USING_HDR=y
CONFIG_RT_CAN_USING_CANFD=y
# CONFIG_RT_CAN_USING_HDR is not set
# CONFIG_RT_CAN_USING_CANFD is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
@@ -337,14 +343,7 @@ CONFIG_RT_USING_PWM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
CONFIG_RT_USING_SDIO=y
CONFIG_RT_SDIO_STACK_SIZE=8192
CONFIG_RT_SDIO_THREAD_PRIORITY=15
CONFIG_RT_MMCSD_STACK_SIZE=8192
CONFIG_RT_MMCSD_THREAD_PRIORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SDHCI is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SOFT_SPI is not set
CONFIG_RT_USING_QSPI=y
@@ -376,7 +375,6 @@ CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_KTIME=y
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CHERRYUSB is not set
CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700
# end of Device Drivers
#
@@ -467,7 +465,7 @@ CONFIG_RT_USING_LWIP212=y
CONFIG_RT_USING_LWIP_VER_NUM=0x20102
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=64
CONFIG_RT_LWIP_IGMP=y
# CONFIG_RT_LWIP_IGMP is not set
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
@@ -493,14 +491,14 @@ CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=16
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=256
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=16
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=256
CONFIG_RT_LWIP_REASSEMBLY_FRAG=y
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
@@ -1159,31 +1157,7 @@ CONFIG_RT_PAGE_MAX_ORDER=16
#
# samples: kernel and components samples
#
CONFIG_PKG_USING_KERNEL_SAMPLES=y
CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
@@ -1486,70 +1460,24 @@ CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
#
# CONFIG_BSP_USING_DRIVERS_EXAMPLE is not set
CONFIG_BSP_USING_IOPAD=y
CONFIG_BSP_USING_UART_LAYER=y
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART0=y
# CONFIG_BSP_USING_UART_MSG is not set
# CONFIG_RT_USING_UART0 is not set
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_BSP_USING_SPI=y
# CONFIG_RT_USING_SPIM0 is not set
# CONFIG_RT_USING_SPIM1 is not set
CONFIG_RT_USING_SPIM2=y
# CONFIG_RT_USING_SPIM3 is not set
CONFIG_BSP_USING_CAN=y
CONFIG_RT_USING_CANFD=y
# CONFIG_RT_USING_FILTER is not set
CONFIG_RT_USING_CAN0=y
CONFIG_RT_USING_CAN1=y
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_QSPI=y
CONFIG_RT_USING_QSPI0=y
CONFIG_USING_QSPI_CHANNEL0=y
# CONFIG_USING_QSPI_CHANNEL1 is not set
CONFIG_BSP_USING_ETH=y
CONFIG_BSP_USING_PWM=y
# CONFIG_RT_USING_PWM0 is not set
# CONFIG_RT_USING_PWM1 is not set
CONFIG_RT_USING_PWM2=y
# CONFIG_RT_USING_PWM3 is not set
# CONFIG_RT_USING_PWM4 is not set
# CONFIG_RT_USING_PWM5 is not set
# CONFIG_RT_USING_PWM6 is not set
# CONFIG_RT_USING_PWM7 is not set
CONFIG_BSP_USING_I2C=y
CONFIG_I2C_USE_MIO=y
# CONFIG_RT_USING_MIO0 is not set
# CONFIG_RT_USING_MIO1 is not set
# CONFIG_RT_USING_MIO2 is not set
# CONFIG_RT_USING_MIO3 is not set
# CONFIG_RT_USING_MIO4 is not set
# CONFIG_RT_USING_MIO5 is not set
# CONFIG_RT_USING_MIO6 is not set
# CONFIG_RT_USING_MIO7 is not set
# CONFIG_RT_USING_MIO8 is not set
# CONFIG_RT_USING_MIO9 is not set
# CONFIG_RT_USING_MIO10 is not set
# CONFIG_RT_USING_MIO11 is not set
# CONFIG_RT_USING_MIO12 is not set
# CONFIG_RT_USING_MIO13 is not set
# CONFIG_RT_USING_MIO14 is not set
CONFIG_RT_USING_MIO15=y
# CONFIG_I2C_USE_CONTROLLER is not set
CONFIG_BSP_USING_SDIF=y
CONFIG_BSP_USING_SDCARD_FATFS=y
CONFIG_USING_SDIF0=y
# CONFIG_USE_SDIF0_TF is not set
CONFIG_USE_SDIF0_EMMC=y
CONFIG_USING_SDIF1=y
CONFIG_USE_SDIF1_TF=y
# CONFIG_USE_SDIF1_EMMC is not set
CONFIG_BSP_USING_DC=y
CONFIG_RT_USING_DC_CHANNEL0=y
CONFIG_RT_USING_DC_CHANNEL1=y
CONFIG_BSP_USING_I2S=y
CONFIG_RT_I2S_SAMPLERATE=8000
CONFIG_RT_I2S_SAMPLEBITS=16
CONFIG_RT_USING_I2S0=y
# CONFIG_BSP_USING_SPI_LAYER is not set
# CONFIG_BSP_USING_I2C_LAYER is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_GPIO is not set
# CONFIG_BSP_USING_QSPI is not set
# CONFIG_BSP_USING_ETH_LAYER is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SDIF_LAYER is not set
# CONFIG_BSP_USING_DC is not set
# CONFIG_BSP_USING_I2S is not set
# CONFIG_BSP_USING_DEVICE is not set
# end of On-chip Peripheral Drivers
#
@@ -1560,7 +1488,6 @@ CONFIG_RT_USING_I2S0=y
CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GICV3=y
CONFIG_PHYTIUM_ARCH_AARCH64=y
CONFIG_ARM_SPI_BIND_CPU_ID=2
#
# Standalone Setting
@@ -1570,23 +1497,23 @@ CONFIG_TARGET_ARMV8_AARCH64=y
#
# Soc configuration
#
# CONFIG_TARGET_PHYTIUMPI is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
# CONFIG_TARGET_FT2004 is not set
# CONFIG_TARGET_D2000 is not set
# CONFIG_TARGET_PE2204 is not set
CONFIG_TARGET_PE2202=y
# CONFIG_TARGET_PE2201 is not set
# CONFIG_TARGET_PD1904 is not set
# CONFIG_TARGET_PD2008 is not set
# CONFIG_TARGET_PD2308 is not set
# CONFIG_TARGET_PS2316 is not set
# CONFIG_TARGET_PD2408 is not set
# CONFIG_TARGET_QEMU_VIRT is not set
CONFIG_SOC_NAME="e2000"
CONFIG_TARGET_TYPE_NAME="q"
CONFIG_SOC_CORE_NUM=4
CONFIG_SOC_NAME="pe220x"
CONFIG_TARGET_TYPE_NAME="pe2202"
CONFIG_SOC_CORE_NUM=2
CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000
CONFIG_F32BIT_MEMORY_LENGTH=0x80000000
CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000
CONFIG_F64BIT_MEMORY_LENGTH=0x800000000
CONFIG_TARGET_E2000=y
CONFIG_TARGET_PE220X=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
@@ -1595,7 +1522,12 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
#
# Board Configuration
#
CONFIG_BOARD_NAME="demo"
CONFIG_E2000D_DEMO_BOARD=y
CONFIG_BOARD_NAME="pe2202_demo"
#
# IO mux configuration when board start up
#
# CONFIG_USE_SPI_IOPAD is not set
# CONFIG_USE_GPIO_IOPAD is not set
# CONFIG_USE_CAN_IOPAD is not set
@@ -1605,11 +1537,6 @@ CONFIG_BOARD_NAME="demo"
# CONFIG_USE_TACHO_IOPAD is not set
# CONFIG_USE_UART_IOPAD is not set
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
CONFIG_E2000Q_DEMO_BOARD=y
#
# IO mux configuration when board start up
#
# end of IO mux configuration when board start up
# CONFIG_CUS_DEMO_BOARD is not set
@@ -1628,6 +1555,8 @@ CONFIG_LOG_DEBUG=y
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set
CONFIG_USE_NS_GTIMER=y
# CONFIG_USE_VIRTUAL_GTIMER is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# end of Sdk common configuration
# end of Standalone Setting

32
bsp/phytium/aarch64/README.md
View File

@@ -115,21 +115,15 @@ rtthread_a64.map
## 2. 如何选择开发板
>注：在 RT-Thread env 环境下使用`menuconfig`指令即可打开配置菜单，在Ubuntu下需要使用`scons --menuconfig`
- 使用`scons --attach=?`查看当前支持的开发板
![](./figures/scons_attach.png)
- 以 E2000Q RT-Thread为例，Linux 环境下，运行`make load_e2000d_demo_rtthread`加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置
- 以`E2000Q_DEMO`开发板为例，进入aarch64目录后，运行`scons --attach=board.e2000q_demo_rtthread`加载默认的`rtconfig.h`, 然后输入下列命令，进入`menuconfig`进一步配置
```shell
scons --menuconfig
```
开发者通过以下选择进行配置
```
Standalone Setting > Board Configuration
```
![board_select](./figures/board_select.png)
## 3. 如何选择驱动
```shell
@@ -155,25 +149,13 @@ scons --menuconfig
## 5. 如何切换至 RT-Thread Smart 工作模式
### Ubuntu环境下可使用以下指令加载RT-Smart默认配置
- 以E2000D_DEMO开发板为例
- 输入下列命令，进入`menuconfig`进一步配置
```shell
make load_e2000d_demo_rtsmart
```
### RT-Thread env环境不方便安装make工具，可按照以下步骤加载RT-Smart默认配置
1. 查看`makefile`文件，找到`make load_e2000d_demo_rtsmart`
![load_e2000d_rtsmart](./figures/load_e2000d_rtsmart.png)
2. 输入以下指令
```shell
cp ./configs/e2000d_demo_rtsmart ./.config -f
cp ./configs/e2000d_demo_rtsmart.h ./rtconfig.h -f
scons -c
scons --menuconfig
```
- 在RT-Thread Kernel菜单中勾选以下选项
![](./figures/rtsmart_config.png)
## 6. 启动镜像程序
1. 完成配置后，使用以下指令进行clean和重新编译

14
bsp/phytium/aarch64/applications/main.c
View File

@@ -15,6 +15,9 @@
#include <rtthread.h>
#include <board.h>
#ifdef BSP_USING_DRIVERS_EXAMPLE
#include "auto_test.h"
#endif
#define ASSERT_STATIC(expression) \
extern int assert_static[(expression) ? 1 : -1]
@@ -23,10 +26,12 @@
#ifndef RT_USING_SMP
ASSERT_STATIC(RT_CPUS_NR == 1U); /* please set RT_CPUS_NR = 1 when SMP off */
#else
#if defined(TARGET_E2000D)
#if defined(TARGET_PE2202)
ASSERT_STATIC(RT_CPUS_NR <= 2U); /* use 2 cores at most */
#elif defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#elif defined(TARGET_PE2204)
ASSERT_STATIC(RT_CPUS_NR <= 4U); /* use 4 cores at most */
#elif defined(TARGET_PD2408)
ASSERT_STATIC(RT_CPUS_NR <= 8U); /* use 4 cores at most */
#endif
#endif
@@ -83,7 +88,10 @@ void demo_core(void)
int main(void)
{
#ifdef RT_USING_SMP
#ifdef BSP_USING_DRIVERS_EXAMPLE
rt_thread_mdelay(2000);
auto_test();
#elif defined RT_USING_SMP
demo_core();
#endif
return RT_EOK;

1689
bsp/phytium/aarch64/configs/e2000d_demo_rtsmart
View File

File diff suppressed because it is too large Load Diff

659
bsp/phytium/aarch64/configs/e2000d_demo_rtsmart.h
View File

@@ -1,659 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50201
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
#define RT_USING_VDSO
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM3
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch64/configs/e2000d_demo_rtthread
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bsp/phytium/aarch64/configs/e2000d_demo_rtthread.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_DEVICE
#define RT_CHERRYUSB_DEVICE_SPEED_HS
#define RT_CHERRYUSB_DEVICE_PUSB2
#define RT_CHERRYUSB_DEVICE_MSC
#define RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
#define RT_USING_USB
#define RT_USING_USB_DEVICE
#define RT_USBD_THREAD_STACK_SZ 4096
#define USB_VENDOR_ID 0x0FFE
#define USB_PRODUCT_ID 0x0001
#define _RT_USB_DEVICE_NONE
#define RT_USB_DEVICE_NONE
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
#define RT_LWIP_DEBUG
#define RT_LWIP_NETIF_DEBUG
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
#define RT_USING_VDSO
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM3
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch64/configs/e2000q_demo_rtthread
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch64/configs/phytium_pi_rtsmart
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bsp/phytium/aarch64/configs/phytium_pi_rtsmart.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMART
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
#define RT_USING_CPU_USAGE_TRACER
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_DEBUGING_CRITICAL
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_THREADSAFE_PRINTF
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define KERNEL_VADDR_START 0xffff000000000000
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_PTYFS
#define RT_USING_PAGECACHE
/* page cache config */
#define RT_PAGECACHE_COUNT 4096
#define RT_PAGECACHE_ASPACE_COUNT 1024
#define RT_PAGECACHE_PRELOAD 4
#define RT_PAGECACHE_HASH_NR 1024
#define RT_PAGECACHE_GC_WORK_LEVEL 90
#define RT_PAGECACHE_GC_STOP_LEVEL 70
/* end of page cache config */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_SERIAL_BYPASS
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_EPOLL
#define RT_USING_POSIX_SIGNALFD
#define RT_SIGNALFD_MAX_NUM 10
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
#define RT_USING_LWP
#define LWP_USING_RUNTIME
#define RT_LWP_MAX_NR 30
#define LWP_TASK_STACK_SIZE 16384
#define RT_CH_MSG_MAX_NR 1024
#define LWP_TID_MAX_NR 64
#define RT_LWP_SHM_MAX_NR 64
#define RT_USING_LDSO
#define LWP_USING_TERMINAL
#define LWP_PTY_MAX_PARIS_LIMIT 64
#define RT_USING_VDSO
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_TF
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch64/configs/phytium_pi_rtthread
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bsp/phytium/aarch64/configs/phytium_pi_rtthread.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

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bsp/phytium/aarch64/configs/phytium_pi_rtthread_pusb2_hc
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bsp/phytium/aarch64/configs/phytium_pi_rtthread_pusb2_hc.h
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@@ -1,630 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_USING_STDC_ATOMIC
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_PUSB2
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_CAN
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

1671
bsp/phytium/aarch64/configs/phytium_pi_rtthread_xhci
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630
bsp/phytium/aarch64/configs/phytium_pi_rtthread_xhci.h
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@@ -1,630 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
/* klibc options */
/* rt_vsnprintf options */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
#define RT_KLIBC_USING_VSNPRINTF_STANDARD
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
/* end of rt_vsnprintf options */
/* rt_vsscanf options */
/* end of rt_vsscanf options */
/* rt_memset options */
/* end of rt_memset options */
/* rt_memcpy options */
/* end of rt_memcpy options */
/* rt_memmove options */
/* end of rt_memmove options */
/* rt_memcmp options */
/* end of rt_memcmp options */
/* rt_strstr options */
/* end of rt_strstr options */
/* rt_strcasecmp options */
/* end of rt_strcasecmp options */
/* rt_strncpy options */
/* end of rt_strncpy options */
/* rt_strcpy options */
/* end of rt_strcpy options */
/* rt_strncmp options */
/* end of rt_strncmp options */
/* rt_strcmp options */
/* end of rt_strcmp options */
/* rt_strlen options */
/* end of rt_strlen options */
/* rt_strnlen options */
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice options */
/* end of kservice options */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
#define ARCH_USING_ASID
#define ARCH_USING_IRQ_CTX_LIST
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_BLK
/* Partition Types */
#define RT_BLK_PARTITION_DFS
#define RT_BLK_PARTITION_EFI
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
/* end of Utilities */
/* Memory management */
#define RT_PAGE_AFFINITY_BLOCK_SIZE 0x1000
#define RT_PAGE_MAX_ORDER 16
/* Debugging */
/* end of Debugging */
/* end of Memory management */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM0
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO0
#define RT_USING_MIO1
#define RT_USING_MIO2
#define RT_USING_MIO10
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_PHYTIUMPI
#define SOC_NAME "phytiumpi"
#define SOC_CORE_NUM 4
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "firefly"
#define FIREFLY_DEMO_BOARD
/* IO mux configuration when board start up */
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif

0
bsp/phytium/aarch64/disassembly.txt
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bsp/phytium/aarch64/makefile
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@@ -1,3 +1,5 @@
include .config
.PHONY: debug boot all clean menuconfig
CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
@@ -10,52 +12,24 @@ LD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ld
AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
RTCONFIG =
include .config
ifdef CONFIG_E2000Q_DEMO_BOARD
RTCONFIG := e2000q_demo
endif
ifdef CONFIG_E2000D_DEMO_BOARD
RTCONFIG := e2000d_demo
endif
ifdef CONFIG_TARGET_PHYTIUMPI
RTCONFIG := phytium_pi
endif
ifdef CONFIG_RT_USING_SMART
RTCONFIG := $(RTCONFIG)_rtsmart
else
RTCONFIG := $(RTCONFIG)_rtthread
endif
ifdef CONFIG_PHYTIUM_RTT_TEST
RTCONFIG := $(RTCONFIG)_test
endif
ifdef CONFIG_RT_CHERRYUSB_HOST_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_hc
endif
ifdef CONFIG_RT_CHERRYUSB_DEVICE_PUSB2
RTCONFIG := $(RTCONFIG)_pusb2_dc
endif
ifdef CONFIG_RT_CHERRYUSB_HOST_XHCI
RTCONFIG := $(RTCONFIG)_xhci
endif
boot:
make all
cp rtthread_a64.elf /mnt/d/tftpboot
cp rtthread_a64.bin /mnt/d/tftpboot
make mv_file
mv_file:
mv rtthread_a64.elf rtthread_a64_$(CONFIG_BOARD_NAME).elf
mv rtthread_a64.bin rtthread_a64_$(CONFIG_BOARD_NAME).bin
cp rtthread_a64_$(CONFIG_BOARD_NAME).elf /mnt/d/tftpboot/rtthread_a64.elf
cp rtthread_a64_$(CONFIG_BOARD_NAME).bin /mnt/d/tftpboot/rtthread_a64.bin
mv_auto_test_file:
mv rtthread_a64.elf rtthread_a64_$(CONFIG_BOARD_NAME).elf
mv rtthread_a64_$(CONFIG_BOARD_NAME).elf /home/zhugy/tftpboot/rtthread_elfs/
debug:
@$(OD) -D rtthread_a64.elf > rtthread_a64.asm
@$(OD) -S rtthread_a64.elf > rtthread_a64.dis
@$(OD) -D rtthread_a64_$(CONFIG_BOARD_NAME).elf > rtthread_a64_$(CONFIG_BOARD_NAME).asm
@$(OD) -S rtthread_a64_$(CONFIG_BOARD_NAME).elf > rtthread_a64_$(CONFIG_BOARD_NAME).dis
all:
@echo "Build started..."
@@ -67,91 +41,4 @@ clean:
menuconfig:
@echo "Running menuconfig..."
scons --menuconfig
saveconfig:
@echo "Save configs to" ./configs/$(RTCONFIG)
@cp ./.config ./configs/$(RTCONFIG) -f
@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
load_e2000q_demo_rtsmart:
@echo "Load configs from ./configs/e2000q_demo_rtsmart"
@cp ./configs/e2000q_demo_rtsmart ./.config -f
@cp ./configs/e2000q_demo_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtsmart_test:
@echo "Load configs from ./configs/e2000q_demo_rtsmart_test"
@cp ./configs/e2000q_demo_rtsmart_test ./.config -f
@cp ./configs/e2000q_demo_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtthread:
@echo "Load configs from ./configs/e2000q_demo_rtthread"
@cp ./configs/e2000q_demo_rtthread ./.config -f
@cp ./configs/e2000q_demo_rtthread.h ./rtconfig.h -f
@scons -c
load_e2000q_demo_rtthread_test:
@echo "Load configs from ./configs/e2000q_demo_rtthread_test"
@cp ./configs/e2000q_demo_rtthread_test ./.config -f
@cp ./configs/e2000q_demo_rtthread_test.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtsmart:
@echo "Load configs from ./configs/e2000d_demo_rtsmart"
@cp ./configs/e2000d_demo_rtsmart ./.config -f
@cp ./configs/e2000d_demo_rtsmart.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtsmart_test:
@echo "Load configs from ./configs/e2000d_demo_rtsmart_test"
@cp ./configs/e2000d_demo_rtsmart_test ./.config -f
@cp ./configs/e2000d_demo_rtsmart_test.h ./rtconfig.h -f
@scons -c
load_e2000d_demo_rtthread:
@echo "Load configs from ./configs/e2000d_demo_rtthread"
@cp ./configs/e2000d_demo_rtthread ./.config -f
@cp ./configs/e2000d_demo_rtthread.h ./rtconfig.h -f
scons -c
load_e2000d_demo_rtthread_test:
@echo "Load configs from ./configs/e2000d_demo_rtthread_test"
@cp ./configs/e2000d_demo_rtthread_test ./.config -f
@cp ./configs/e2000d_demo_rtthread_test.h ./rtconfig.h -f
scons -c
load_e2000d_demo_rtthread_pusb2_dc:
@echo "Load configs from ./configs/e2000d_demo_rtthread_pusb2_dc"
@cp ./configs/e2000d_demo_rtthread_pusb2_dc ./.config -f
@cp ./configs/e2000d_demo_rtthread_pusb2_dc.h ./rtconfig.h -f
load_e2000d_demo_rtthread_xhci:
@echo "Load configs from ./configs/e2000d_demo_rtthread_xhci"
@cp ./configs/e2000d_demo_rtthread_xhci ./.config -f
@cp ./configs/e2000d_demo_rtthread_xhci.h ./rtconfig.h -f
load_phytium_pi_rtthread_pusb2_hc:
@echo "Load configs from ./configs/phytium_pi_rtthread_pusb2_hc"
@cp ./configs/phytium_pi_rtthread_pusb2_hc ./.config -f
@cp ./configs/phytium_pi_rtthread_pusb2_hc.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtthread_xhic:
@echo "Load configs from ./configs/phytium_pi_rtthread_xhci"
@cp ./configs/phytium_pi_rtthread_xhci ./.config -f
@cp ./configs/phytium_pi_rtthread_xhci.h ./rtconfig.h -f
scons -c
load_phytium_pi_rtsmart:
@echo "Load configs from ./configs/phytium_pi_rtsmart"
@cp ./configs/phytium_pi_rtsmart ./.config -f
@cp ./configs/phytium_pi_rtsmart.h ./rtconfig.h -f
@scons -c
load_phytium_pi_rtthread:
@echo "Load configs from ./configs/phytium_pi_rtthread"
@cp ./configs/phytium_pi_rtthread ./.config -f
@cp ./configs/phytium_pi_rtthread.h ./rtconfig.h -f
@scons -c
scons --menuconfig

78
bsp/phytium/aarch64/rtconfig.h
View File

@@ -74,7 +74,7 @@
/* end of klibc options */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
@@ -117,11 +117,10 @@
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50200
#define RT_VER_NUM 0x50201
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
@@ -173,7 +172,9 @@
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V2
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
@@ -191,6 +192,7 @@
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
/* end of DFS: device virtual file system */
/* Device Drivers */
@@ -206,8 +208,6 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
@@ -215,12 +215,6 @@
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PRIORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_AUDIO
@@ -236,7 +230,6 @@
/* end of Partition Types */
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@@ -292,7 +285,6 @@
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
@@ -313,12 +305,12 @@
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 256
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_PRIORITY 16
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 256
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
@@ -487,9 +479,6 @@
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
@@ -549,38 +538,9 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART_LAYER
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
#define BSP_USING_PWM
#define RT_USING_PWM2
#define BSP_USING_I2C
#define I2C_USE_MIO
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
#define RT_USING_DC_CHANNEL0
#define RT_USING_DC_CHANNEL1
#define BSP_USING_I2S
#define RT_I2S_SAMPLERATE 8000
#define RT_I2S_SAMPLEBITS 16
#define RT_USING_I2S0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
@@ -589,7 +549,6 @@
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 2
/* Standalone Setting */
@@ -597,22 +556,22 @@
/* Soc configuration */
#define TARGET_E2000Q
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "q"
#define SOC_CORE_NUM 4
#define TARGET_PE2202
#define SOC_NAME "pe220x"
#define TARGET_TYPE_NAME "pe2202"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define TARGET_PE220X
#define DEFAULT_DEBUG_PRINT_UART1
/* end of Soc configuration */
/* Board Configuration */
#define BOARD_NAME "demo"
#define E2000Q_DEMO_BOARD
#define E2000D_DEMO_BOARD
#define BOARD_NAME "pe2202_demo"
/* IO mux configuration when board start up */
@@ -623,6 +582,7 @@
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
#define USE_NS_GTIMER
/* end of Sdk common configuration */
/* end of Standalone Setting */

28
bsp/phytium/board/board.c
View File

@@ -52,7 +52,6 @@ extern FIOPadCtrl iopad_ctrl;
/* mmu config */
extern struct mem_desc platform_mem_desc[];
extern const rt_uint32_t platform_mem_desc_size;
rt_uint64_t rt_cpu_mpidr_table[RT_CPUS_NR];
void idle_wfi(void)
{
@@ -164,10 +163,10 @@ void rt_hw_board_aarch64_init(void)
rt_hw_gtimer_init();
FEarlyUartProbe();
FIOMuxInit();
FEarlyUartProbe();
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
@@ -190,9 +189,29 @@ void rt_hw_board_aarch64_init(void)
#endif
}
void rt_hw_console_output(const char *str)
{
rt_size_t i = 0, size = 0;
char a = '\r';
rt_enter_critical();
size = rt_strlen(str);
for( i = 0; i < size; i++)
{
if (*(str + i) == '\n')
{
OutByte(a);
}
OutByte(*(str + i));
}
rt_exit_critical();
}
#else
#if defined(TARGET_E2000D)
#if defined(TARGET_PE2202)
#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
#endif
@@ -274,4 +293,3 @@ void rt_hw_board_init(void)
rt_hw_board_aarch32_init();
#endif
}

46
bsp/phytium/board/board.kconfig
View File

@@ -2,19 +2,19 @@ menu "Board Configuration"
choice
prompt "Board select"
default FIREFLY_DEMO_BOARD
default PHYTIUMPI_FIREFLY_BOARD
config E2000D_DEMO_BOARD
select BSP_USING_IOPAD
bool
prompt "Use E2000D demo board"
depends on TARGET_E2000D
depends on TARGET_PE2202
help
select E2000D demo board config
if E2000D_DEMO_BOARD
config BOARD_NAME
string
default "demo"
default "pe2202_demo"
source "$SDK_DIR/board/e2000d_demo/e2000d_demo.kconfig"
endif
@@ -22,30 +22,56 @@ choice
select BSP_USING_IOPAD
bool
prompt "Use E2000Q demo board"
depends on TARGET_E2000Q
depends on TARGET_PE2204
help
select E2000Q demo board config
if E2000Q_DEMO_BOARD
config BOARD_NAME
string
default "demo"
default "pe2204_demo"
source "$SDK_DIR/board/e2000q_demo/e2000q_demo.kconfig"
endif
config FIREFLY_DEMO_BOARD
config PHYTIUMPI_FIREFLY_BOARD
select BSP_USING_IOPAD
bool
prompt "Use firefly board"
depends on TARGET_PHYTIUMPI
depends on TARGET_PE2204
help
select firefly board config
if FIREFLY_DEMO_BOARD
if PHYTIUMPI_FIREFLY_BOARD
config BOARD_NAME
string
default "firefly"
source "$SDK_DIR/board/firefly/firefly.kconfig"
default "phytiumpi"
source "$SDK_DIR/board/phytiumpi_firefly/firefly.kconfig"
endif
config PD2408_TEST_A_BOARD
select BSP_USING_IOPAD
bool
prompt "Use PD2408 test a board"
depends on TARGET_PD2408
help
select PD2408 test a board config
if PD2408_TEST_A_BOARD
config BOARD_NAME
string
default "pd2408_test_a"
source "$SDK_DIR/board/pd2408_test_a/pd2408_test_a.kconfig"
endif
config PD2408_TEST_B_BOARD
select BSP_USING_IOPAD
bool
prompt "Use PD2408 test b board"
depends on TARGET_PD2408
help
select PD2408 test b board config
if PD2408_TEST_B_BOARD
config BOARD_NAME
string
default "pd2408_test_b"
source "$SDK_DIR/board/pd2408_test_b/pd2408_test_b.kconfig"
endif
config CUS_DEMO_BOARD
select USE_IOMUX
bool

33
bsp/phytium/board/phytium_cpu.c
View File

@@ -14,12 +14,32 @@
#include "rtconfig.h"
#include <rtthread.h>
#include "gicv3.h"
#include "fparameters.h"
#include "fcpu_info.h"
#include "phytium_cpu.h"
rt_uint64_t rt_cpu_mpidr_table[] =
{
#if defined(TARGET_PE2202)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
#elif defined(TARGET_PE2204)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
[2] = RT_CORE_AFF(2),
[3] = RT_CORE_AFF(3),
#elif defined(TARGET_PD2408)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
[2] = RT_CORE_AFF(2),
[3] = RT_CORE_AFF(3),
[4] = RT_CORE_AFF(4),
[5] = RT_CORE_AFF(5),
[6] = RT_CORE_AFF(6),
[7] = RT_CORE_AFF(7),
#endif
[RT_CPUS_NR] = 0
};
/**
@name: phytium_cpu_id_mapping
@msg: Map Phytium CPU ID
@@ -29,7 +49,7 @@
*/
int phytium_cpu_id_mapping(int cpu_id)
{
#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#if defined(TARGET_PE2204)
switch (cpu_id)
{
case 0:
@@ -67,21 +87,19 @@ int rt_hw_cpu_id(void)
rt_uint64_t get_main_cpu_affval(void)
{
#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#if defined(TARGET_PE2204)
return CORE2_AFF;
#else
return CORE0_AFF;
#endif
}
extern u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list);
rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
{
return GetCpuMaskToAffval(cpu_mask, cluster_id, target_list);
}
#ifdef RT_USING_SMP
void send_core_isg(void)
@@ -98,5 +116,4 @@ MSH_CMD_EXPORT(send_core_isg, send_core_isg);
#endif
#endif

10
bsp/phytium/board/phytium_cpu.h
View File

@@ -32,13 +32,17 @@
#define MAX_HANDLERS 160
#endif
#if defined(TARGET_E2000)
#if defined(TARGET_PE220X)
#define MAX_HANDLERS 270
#endif
#if defined(TARGET_PD2408)
#define MAX_HANDLERS 1024
#endif
#define GIC_IRQ_START 0
#define GIC_ACK_INTID_MASK 0x000003ff
#define RT_CORE_AFF(x) (CORE##x##_AFF | 0x80000000)
rt_uint64_t get_main_cpu_affval(void);
@@ -51,7 +55,7 @@ rt_inline rt_uint32_t platform_get_gic_dist_base(void)
rt_inline uintptr_t platform_get_gic_redist_base(void)
{
uintptr_t redis_base, mpidr_aff, gicr_typer_aff;
mpidr_aff = (uintptr_t)(GetAffinity() & 0xfff);
mpidr_aff = (uintptr_t)(GetAffinity() & CORE_AFF_MASK);
for (redis_base = GICV3_RD_BASE_ADDR; redis_base < GICV3_RD_BASE_ADDR + GICV3_RD_SIZE; redis_base += GICV3_RD_OFFSET)
{

50
bsp/phytium/board/phytium_cpu_id.S
View File

@@ -18,7 +18,7 @@
#ifndef __aarch64__
.globl cpu_id_mapping
cpu_id_mapping:
#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#if defined(TARGET_PE2204)
cmp r0, #0 // compare cpu_id with 0
beq map_cpu_id_0
cmp r0, #1 // compare cpu_id with 1
@@ -31,7 +31,7 @@ mov pc, lr // no mapping needed
#endif
mov pc, lr // no mapping needed
// Mapping for E2000Q
// Mapping for PE2204
map_cpu_id_0:
mov r0, #2
mov pc, lr
@@ -105,7 +105,7 @@ return:
.globl cpu_id_mapping
cpu_id_mapping:
#if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
#if defined(TARGET_PE2204)
cmp x0, #0 // compare cpu_id with 0
beq map_cpu_id_0
cmp x0, #1 // compare cpu_id with 1
@@ -118,7 +118,7 @@ RET // no mapping needed
#endif
RET // no mapping needed
// Mapping for E2000Q
// Mapping for PE2204
map_cpu_id_0:
mov x0, #2
RET
@@ -147,7 +147,7 @@ rt_hw_cpu_id_set:
.globl rt_hw_cpu_id
rt_hw_cpu_id:
mrs x0,MPIDR_EL1
ubfx x0, x0, #0, #12
ubfx x0, x0, #0, #20
ldr x1,= CORE0_AFF
cmp x0, x1
beq core0
@@ -170,6 +170,30 @@ rt_hw_cpu_id:
beq core3
#endif
#if defined(CORE4_AFF)
ldr x1,= CORE4_AFF
cmp x0, x1
beq core4
#endif
#if defined(CORE5_AFF)
ldr x1,= CORE5_AFF
cmp x0, x1
beq core5
#endif
#if defined(CORE6_AFF)
ldr x1,= CORE6_AFF
cmp x0, x1
beq core6
#endif
#if defined(CORE7_AFF)
ldr x1,= CORE7_AFF
cmp x0, x1
beq core7
#endif
core0:
mov x0, #0
b return
@@ -186,6 +210,22 @@ core3:
mov x0, #3
b return
core4:
mov x0, #4
b return
core5:
mov x0, #5
b return
core6:
mov x0, #6
b return
core7:
mov x0, #7
b return
return:
b cpu_id_mapping

32
bsp/phytium/board/secondary_cpu.c
View File

@@ -38,20 +38,27 @@
#endif
#include "fpsci.h"
rt_uint64_t rt_cpu_mpidr_early[] =
{
#if defined(TARGET_E2000D)
[0] = 0x80000200,
[1] = 0x80000201,
#elif defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
[0] = 0x80000200,
[1] = 0x80000201,
[2] = 0x80000000,
[3] = 0x80000100,
#if defined(TARGET_PE2202)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
#elif defined(TARGET_PE2204)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
[2] = RT_CORE_AFF(2),
[3] = RT_CORE_AFF(3),
#elif defined(TARGET_PD2408)
[0] = RT_CORE_AFF(0),
[1] = RT_CORE_AFF(1),
[2] = RT_CORE_AFF(2),
[3] = RT_CORE_AFF(3),
[4] = RT_CORE_AFF(4),
[5] = RT_CORE_AFF(5),
[6] = RT_CORE_AFF(6),
[7] = RT_CORE_AFF(7),
#endif
[RT_CPUS_NR] = 0
};
extern int rt_hw_timer_init(void);
@@ -69,11 +76,10 @@ void rt_hw_secondary_cpu_up(void)
{
continue;
}
cpu_mask = 1<<phytium_cpu_id_mapping(i);
cpu_mask = (1 << phytium_cpu_id_mapping(i));
#if defined(TARGET_ARMV8_AARCH64)
/* code */
rt_kprintf("cpu_mask = 0x%x \n", cpu_mask);
char *entry = (char *)_secondary_cpu_entry;
entry += PV_OFFSET;
FPsciCpuMaskOn(cpu_mask, (uintptr)entry);

10
bsp/phytium/board/smp_sgi_test.c
View File

@@ -26,12 +26,16 @@
struct rt_thread core_test_thread[RT_CPUS_NR];
static char *core_thread_name[4] =
static char *core_thread_name[] =
{
"core0_sgi_test",
"core1_sgi_test",
"core2_sgi_test",
"core3_sgi_test",
"core4_sgi_test",
"core5_sgi_test",
"core6_sgi_test",
"core7_sgi_test",
};
static rt_uint8_t core_stack[RT_CPUS_NR][4096];
@@ -82,7 +86,7 @@ static void smp_sgi_test_thread(void *parameter)
{
rt_uint32_t cpu_mask = 0;
for (int i = 0; i < RT_CPUS_NR; i++)
for (rt_uint32_t i = 0; i < RT_CPUS_NR; i++)
{
cpu_mask = (1 << i);
rt_hw_ipi_send(RT_TEST_IPI, cpu_mask);
@@ -95,7 +99,7 @@ void smp_sgi_sample(int argc, char *argv[])
rt_thread_t thread;
rt_err_t res;
demo_core_test();
rt_thread_mdelay(1000);
rt_thread_mdelay(100);
thread = rt_thread_create("smp_test_thread", smp_sgi_test_thread, RT_NULL, 4096, 25, 10);
res = rt_thread_startup(thread);
RT_ASSERT(res == RT_EOK);

122
bsp/phytium/libraries/SConscript
View File

@@ -30,34 +30,26 @@ elif GetDepend(['TARGET_ARMV8_AARCH64']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/common/fcpu_info.c')
path += [PHYTIUM_SDK_DIR + '/soc/common']
if GetDepend(['TARGET_F2000_4']):
src += Glob(cwd+'/port/soc_port/ft2004/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/ft2004']
if GetDepend(['TARGET_PE2204']):
src += Glob(cwd+'/port/soc_port/pe220x/*.c') + Glob(cwd+'/port/soc_port/pe220x/pe2204/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/pe220x'] + [PHYTIUM_SDK_DIR + '/soc/pe220x/pe2204']
if GetDepend(['TARGET_E2000Q']):
src += Glob(cwd+'/port/soc_port/e2000/*.c') + Glob(cwd+'/port/soc_port/e2000/q/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/e2000'] + [PHYTIUM_SDK_DIR + '/soc/e2000/q']
if GetDepend(['TARGET_E2000D']):
src += Glob(cwd+'/port/soc_port/e2000/*.c') + Glob(cwd+'/port/soc_port/e2000/d/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/e2000'] + [PHYTIUM_SDK_DIR + '/soc/e2000/d']
if GetDepend(['TARGET_PE2202']):
src += Glob(cwd+'/port/soc_port/pe220x/*.c') + Glob(cwd+'/port/soc_port/pe220x/pe2202/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/pe220x'] + [PHYTIUM_SDK_DIR + '/soc/pe220x/pe2202']
if GetDepend(['TARGET_PHYTIUMPI']):
src += Glob(cwd+'/port/soc_port/phytiumpi/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/phytiumpi']
if GetDepend(['TARGET_D2000']):
src += Glob(cwd+'/port/soc_port/d2000/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/d2000']
if GetDepend(['TARGET_PD2408']):
src += Glob(cwd+'/port/soc_port/pd2408/*.c')
path += [PHYTIUM_SDK_DIR + '/soc/pd2408']
# board port
if GetDepend(['E2000D_DEMO_BOARD']):
path += cwd + '/fboard_port/e2000d_demo'
if GetDepend(['E2000D_DEMO_BOARD']):
if GetDepend(['E2000Q_DEMO_BOARD']):
path += cwd + '/fboard_port/e2000q_demo'
if GetDepend(['FIREFLY_DEMO_BOARD']):
if GetDepend(['PHYTIUMPI_FIREFLY_BOARD']):
path += cwd + '/fboard_port/firefly'
if GetDepend(['BSP_USING_SDCARD_FATFS']):
@@ -67,8 +59,11 @@ if GetDepend(['BSP_USING_SDCARD_FATFS']):
if GetDepend(['E2000Q_DEMO_BOARD']):
src += Glob(cwd + '/port/fboard_port/e2000q_demo/mnt_sdcard.c')
if GetDepend(['FIREFLY_DEMO_BOARD']):
if GetDepend(['PHYTIUMPI_FIREFLY_BOARD']):
src += Glob(cwd + '/port/fboard_port/firefly/mnt_sdcard.c')
if GetDepend(['PD2408_TEST_A_BOARD']):
src += Glob(cwd + '/port/fboard_port/pd2408_test_a/mnt_sdcard.c')
else:
src += Glob(cwd + '/port/fboard_port/mnt_ramdisk.c')
@@ -78,13 +73,25 @@ path += [PORT_DRV_DIR]
## spim
if GetDepend(['BSP_USING_SPI']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/spi/fspim/*.c') + Glob(PORT_DRV_DIR+'/drv_spi.c')
path += [PHYTIUM_SDK_DIR + '/drivers/spi/fspim']
path += [PHYTIUM_SDK_DIR + '/drivers/spi/fspim']
## spim msg
if GetDepend(['BSP_USING_SPI_MSG']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/spi/fspim_v2_0/*.c') + Glob(PORT_DRV_DIR+'/drv_spi_msg.c')
path += [PHYTIUM_SDK_DIR + '/drivers/spi/fspim_v2_0'] + [PHYTIUM_SDK_DIR + '/drivers/msg']
## serial
if GetDepend(['BSP_USING_UART']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/serial/fpl011/*.c') + Glob(PORT_DRV_DIR+'/drv_usart.c')
path += [PHYTIUM_SDK_DIR + '/drivers/serial/fpl011']
## serial_v2
if GetDepend(['BSP_USING_UART_MSG']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/serial/fpl011/*.c')
src += Glob(PHYTIUM_SDK_DIR+'/drivers/serial/fserial_v2_0/*.c') + Glob(PORT_DRV_DIR+'/drv_usart_msg.c')
path += [PHYTIUM_SDK_DIR + '/drivers/serial/fpl011']
path += [PHYTIUM_SDK_DIR + '/drivers/serial/fserial_v2_0'] + [PHYTIUM_SDK_DIR + '/drivers/msg/']
## can
if GetDepend(['BSP_USING_CAN']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/can/fcan/*.c') + Glob(PORT_DRV_DIR+'/drv_can.c')
@@ -100,32 +107,38 @@ if GetDepend(['BSP_USING_ETH']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/eth/fxmac/*.c') + Glob(PORT_DRV_DIR+'/drv_xmac.c')
path += [PHYTIUM_SDK_DIR + '/drivers/eth/fxmac/'] + [PHYTIUM_SDK_DIR + '/drivers/eth/fxmac/phy/']
## eth_v2
if GetDepend(['BSP_USING_ETH_MSG']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/eth/fxmac_v2_0/*.c') + Glob(PORT_DRV_DIR+'/drv_xmac_msg.c')
path += [PHYTIUM_SDK_DIR + '/drivers/eth/fxmac_v2_0/'] + [PHYTIUM_SDK_DIR + '/drivers/msg']
## sdif
if GetDepend(['BSP_USING_SDIF']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/mmc/fsdif/*.c') + Glob(PORT_DRV_DIR+'/drv_sdif.c')
path += [PHYTIUM_SDK_DIR + '/drivers/mmc/fsdif/']
## sdif_msg
if GetDepend(['BSP_USING_SDIF_MSG']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/mmc/fsdif_v2_0/*.c') + Glob(PORT_DRV_DIR+'/drv_sdif_msg.c')
path += [PHYTIUM_SDK_DIR + '/drivers/mmc/fsdif_v2_0/'] + [PHYTIUM_SDK_DIR + '/drivers/msg/']
## gpio
if GetDepend(['BSP_USING_GPIO']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/pin/fgpio/*.c') + Glob(PORT_DRV_DIR+'/drv_gpio.c')
path += [PHYTIUM_SDK_DIR + '/drivers/pin/fgpio/']
if GetDepend(['TARGET_E2000D']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/e2000/fgpio_table.c')
if GetDepend(['TARGET_E2000Q']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/e2000/fgpio_table.c')
if GetDepend(['TARGET_PHYTIUMPI']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/phytiumpi/fgpio_table.c')
if GetDepend(['TARGET_PE220X']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/pe220x/fgpio_table.c')
if GetDepend(['TARGET_PD2408']):
src += Glob(PHYTIUM_SDK_DIR+'/soc/pd2408/fgpio_table.c')
## i2s
if GetDepend(['BSP_USING_I2S']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/i2s/fi2s/*.c') \
+ Glob(PHYTIUM_SDK_DIR+'/drivers/dma/fddma/*.c') \
+ Glob(PHYTIUM_SDK_DIR+'/drivers/i2s/fes8388/*.c') \
+ Glob(PHYTIUM_SDK_DIR+'/drivers/i2s/fes8336/*.c') \
+ Glob(PORT_DRV_DIR+'/drv_i2s.c')
path += [PHYTIUM_SDK_DIR + '/drivers/i2s/fi2s/'] \
+ [PHYTIUM_SDK_DIR + '/drivers/i2s/fes8336/'] \
+ [PHYTIUM_SDK_DIR + '/drivers/i2s/fes8388/'] \
+ [PHYTIUM_SDK_DIR + '/drivers/dma/fddma/']
## pwm
@@ -133,11 +146,16 @@ if GetDepend(['BSP_USING_PWM']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/pwm/fpwm/*.c') + Glob(PORT_DRV_DIR+'/drv_pwm.c')
path += [PHYTIUM_SDK_DIR + '/drivers/pwm/fpwm/']
## i2C
## i2c
if GetDepend(['BSP_USING_I2C']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/i2c/fi2c/*.c') + Glob(PORT_DRV_DIR+'/drv_i2c.c')
path += [PHYTIUM_SDK_DIR + '/drivers/i2c/fi2c/']
## i2c msg
if GetDepend(['BSP_USING_I2C_MSG']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/i2c/fi2c_v2_0/*.c') + Glob(PORT_DRV_DIR+'/drv_i2c_msg.c')
path += [PHYTIUM_SDK_DIR + '/drivers/i2c/fi2c_v2_0/'] + [PHYTIUM_SDK_DIR + '/drivers/msg/']
# fdriver dc
if GetDepend(['BSP_USING_DC']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/media/fdcdp/*.c') + Glob(PORT_DRV_DIR+'/drv_dc.c')
@@ -153,33 +171,59 @@ if GetDepend(['I2C_USE_MIO']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/mio/fmio/*.c')
path += [PHYTIUM_SDK_DIR + '/drivers/mio/fmio/']
## device
if GetDepend(['BSP_USING_DEVICE']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/device/fdevice/fdevice.c')
path += [PHYTIUM_SDK_DIR + '/drivers/device/fdevice/']
if GetDepend(['BSP_USING_ES8336']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/device/fes8336/fes8336.c') + Glob(PHYTIUM_SDK_DIR+'/drivers/i2c/fi2c/*.c')
path += [PHYTIUM_SDK_DIR + '/drivers/device/fes8336/'] + [PHYTIUM_SDK_DIR + '/drivers/i2c/fi2c/']
if GetDepend(['BSP_USING_ES8388']):
src += Glob(PHYTIUM_SDK_DIR+'/drivers/device/fes8388/fes8388.c') + Glob(PHYTIUM_SDK_DIR+'/drivers/i2c/fi2c/*.c')
path += [PHYTIUM_SDK_DIR + '/drivers/device/fes8388/'] + [PHYTIUM_SDK_DIR + '/drivers/i2c/fi2c/']
## drivers_example
if GetDepend(['BSP_USING_DRIVERS_EXAMPLE']):
src += Glob(DRIVERS_EXAMPLE_DIR+'/*.c')
path += [DRIVERS_EXAMPLE_DIR]
## board
if GetDepend(['E2000D_DEMO_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/e2000d_demo/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/e2000d_demo/']
if GetDepend(['BSP_USING_SDIF']):
if GetDepend(['BSP_USING_SDIF_LAYER']):
src += Glob(PHYTIUM_SDK_DIR+'/board/e2000d_demo/fsdif_timing.c')
if GetDepend(['E2000Q_DEMO_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/e2000q_demo/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/e2000q_demo/']
if GetDepend(['BSP_USING_SDIF']):
if GetDepend(['BSP_USING_SDIF_LAYER']):
src += Glob(PHYTIUM_SDK_DIR+'/board/e2000q_demo/fsdif_timing.c')
if GetDepend(['FIREFLY_DEMO_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/firefly/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/firefly/']
if GetDepend(['PD2408_TEST_A_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/pd2408_test_a/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/pd2408_test_a/']
if GetDepend(['BSP_USING_SDIF']):
src += Glob(PHYTIUM_SDK_DIR+'/board/firefly/fsdif_timing.c')
if GetDepend(['BSP_USING_SDIF_LAYER']):
src += Glob(PHYTIUM_SDK_DIR+'/board/pd2408_test_a/fsdif_timing.c')
if GetDepend(['PD2408_TEST_B_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/pd2408_test_b/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/pd2408_test_b/']
if GetDepend(['BSP_USING_SDIF_LAYER']):
src += Glob(PHYTIUM_SDK_DIR+'/board/pd2408_test_b/fsdif_timing.c')
if GetDepend(['PHYTIUMPI_FIREFLY_BOARD']):
src += Glob(PHYTIUM_SDK_DIR+'/board/phytiumpi_firefly/fio_mux.c')
path += [PHYTIUM_SDK_DIR + '/board/phytiumpi_firefly/']
if GetDepend(['BSP_USING_SDIF_LAYER']):
src += Glob(PHYTIUM_SDK_DIR+'/board/phytiumpi_firefly/fsdif_timing.c')
LIBS = []
LIBPATH = []

45
bsp/phytium/libraries/common/fearly_uart.c
View File

@@ -33,6 +33,44 @@
#include "fio.h"
#include "fparameters.h"
#include "fearly_uart.h"
#if defined(BSP_USING_UART_MSG)
#include "fuart_msg.h"
#include "fio_mux.h"
static FUartMsg early_uart;
void FEarlyUartProbe(void)
{
FUartMsgConfig config;
config = *FUartMsgLookupConfig(EARLY_UART_CTRL_ID);
#ifdef RT_USING_SMART
config.msg.regfile = (uintptr)rt_ioremap((void *)config.msg.regfile, 0x1000);
config.msg.shmem = (uintptr)rt_ioremap((void *)config.msg.shmem, 0x1000);
#endif
FIOPadSetUartMux(EARLY_UART_CTRL_ID);
FUartMsgCfgInitialize(&early_uart, &config);
FUartMsgSetStartUp(&early_uart);
return;
}
void OutByte(s8 byte)
{
while(-1 == FUartMsgTxChar(&(early_uart), byte));
}
char GetByte(void)
{
return (char)(FUartMsgBlockReceive(&early_uart));
}
#else
#include "fpl011.h"
/**************************** Type Definitions *******************************/
@@ -42,6 +80,8 @@ void FEarlyUartProbe(void)
{
FPl011Config config;
config = *FPl011LookupConfig(EARLY_UART_CTRL_ID);
#ifdef RT_USING_SMART
config.base_address = (uintptr)rt_ioremap((void *)config.base_address, 0x2000);
#endif
@@ -55,6 +95,8 @@ void FEarlyUartProbe(void)
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
void OutByte(s8 byte)
{
FPl011BlockSend(&early_uart, (u8 *)&byte, 1);
@@ -63,4 +105,5 @@ void OutByte(s8 byte)
char GetByte(void)
{
return (char)(FPl011BlockReceive(&early_uart));
}
}
#endif

441
bsp/phytium/libraries/drivers/Kconfig
View File

@@ -9,141 +9,129 @@ menu "On-chip Peripheral Drivers"
bool "Enable drivers example"
default n
if BSP_USING_DRIVERS_EXAMPLE
config BSP_USING_DRIVERS_AUTO_TEST
bool "Enable drivers example"
default n
endif
config BSP_USING_IOPAD
bool "Enable IOPAD"
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
menuconfig BSP_USING_UART_LAYER
bool "Enable Uart Layer"
default n
select USE_SERIAL # sdk serial component
select RT_USING_SERIAL
if BSP_USING_UART
config RT_USING_UART0
bool "Enable UART0"
default n
config RT_USING_UART1
bool "Enable UART1"
default y
config RT_USING_UART2
bool "Enable UART2"
default n
config RT_USING_UART3
bool "Enable UART3"
default n
endif
if BSP_USING_UART_LAYER
choice
prompt "Select Uart Mode"
config BSP_USING_UART
bool "Standard Uart"
help
Use standard uart communication mode
config BSP_USING_UART_MSG
bool "message-based Uart"
help
Use message-based uart communication
endchoice
menuconfig BSP_USING_SPI
bool "Enable Spi"
default n
select RT_USING_SPI
if BSP_USING_SPI
config RT_USING_SPIM0
bool "Enable spim0"
default n
config RT_USING_SPIM1
bool "Enable spim1"
default n
config RT_USING_SPIM2
bool "Enable spim2"
default n
config RT_USING_SPIM3
bool "Enable spim3"
default n
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config RT_USING_CANFD
bool "Enable canfd"
select RT_CAN_USING_CANFD
default n
config RT_USING_FILTER
bool "Enable can filter"
select RT_CAN_USING_HDR
default n
config RT_USING_CAN0
bool "Enable can0"
default n
config RT_USING_CAN1
bool "Enable can1"
default n
endif
menuconfig BSP_USING_GPIO
bool "Enable GPIO"
default n
select RT_USING_PIN
menuconfig BSP_USING_QSPI
bool "Enable QSPI"
default n
select RT_USING_QSPI
select RT_USING_SPI
select RT_USING_PIN
if BSP_USING_QSPI
config RT_USING_QSPI0
bool "Enable qspi0"
default n
if RT_USING_QSPI0
config USING_QSPI_CHANNEL0
bool "using qspi channel_0"
if BSP_USING_UART
config RT_USING_UART0
bool "Enable UART0"
default n
config USING_QSPI_CHANNEL1
bool "using qspi channel_1"
config RT_USING_UART1
bool "Enable UART1"
default y
config RT_USING_UART2
bool "Enable UART2"
default n
config RT_USING_UART3
bool "Enable UART3"
default n
endif
if BSP_USING_UART_MSG
config RT_USING_UART0_MSG
bool "Enable UART0_MSG"
default n
config RT_USING_UART1_MSG
bool "Enable UART1_MSG"
default n
config RT_USING_UART2_MSG
bool "Enable UART2_MSG"
default y
endif
endif
menuconfig BSP_USING_SPI_LAYER
menuconfig BSP_USING_SPI_LAYER
bool "Enable SPI Layer"
default n
select RT_USING_SPI
if BSP_USING_SPI_LAYER
choice
prompt "Select SPI Mode"
config BSP_USING_SPI
bool "Standard SPI"
help
Use standard SPI communication mode
config BSP_USING_SPI_MSG
bool "IOP message-based SPI"
help
Use IOP message-based SPI communication
endchoice
if BSP_USING_SPI
config RT_USING_SPIM0
bool "Enable SPIM0"
default n
config RT_USING_SPIM1
bool "Enable SPIM1"
default n
config RT_USING_SPIM2
bool "Enable SPIM2"
default n
config RT_USING_SPIM3
bool "Enable SPIM3"
default n
endif
if BSP_USING_SPI_MSG
config RT_USING_SPIM0_MSG
bool "Enable SPIM0_MSG"
default n
config RT_USING_SPIM1_MSG
bool "Enable SPIM1_MSG"
default n
config RT_USING_SPIM2_MSG
bool "Enable SPIM2_MSG"
default n
config RT_USING_SPIM3_MSG
bool "Enable SPIM3_MSG"
default n
endif
endif
menuconfig BSP_USING_ETH
bool "Enable ETH"
default n
if BSP_USING_ETH
config RT_LWIP_PBUF_POOL_BUFSIZE
int "The size of each pbuf in the pbuf pool"
range 1500 2000
default 1700
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config RT_USING_PWM0
bool "Enable pwm0"
default n
config RT_USING_PWM1
bool "Enable pwm1"
default n
config RT_USING_PWM2
bool "Enable pwm2"
default n
config RT_USING_PWM3
bool "Enable pwm3"
default n
config RT_USING_PWM4
bool "Enable pwm4"
default n
config RT_USING_PWM5
bool "Enable pwm5"
default n
config RT_USING_PWM6
bool "Enable pwm6"
default n
config RT_USING_PWM7
bool "Enable pwm7"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
menuconfig BSP_USING_I2C_LAYER
bool "Enable I2C Layer"
default n
select RT_USING_I2C
if BSP_USING_I2C
if BSP_USING_I2C_LAYER
choice
prompt "Select I2C Mode"
config BSP_USING_I2C
bool "Standard I2C"
help
Use standard I2C communication mode
config BSP_USING_I2C_MSG
bool "IOP message-based I2C"
help
Use IOP message-based I2C communication
endchoice
if BSP_USING_I2C
config I2C_USE_MIO
bool "using i2c mio"
default n
@@ -219,49 +207,209 @@ menu "On-chip Peripheral Drivers"
default n
endif
endif
menuconfig BSP_USING_SDIF
bool "Enable SDIF"
if BSP_USING_I2C_MSG
config RT_USING_I2C0_MSG
bool "Enable i2c0 msg"
default n
config RT_USING_I2C1_MSG
bool "Enable i2c1 msg"
default n
config RT_USING_I2C2_MSG
bool "Enable i2c2 msg"
default n
config RT_USING_I2C3_MSG
bool "Enable i2c3 msg"
default n
endif
endif
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config RT_USING_CANFD
bool "Enable canfd"
select RT_CAN_USING_CANFD
default n
config RT_USING_FILTER
bool "Enable can filter"
select RT_CAN_USING_HDR
default n
config RT_USING_CAN0
bool "Enable can0"
default n
config RT_USING_CAN1
bool "Enable can1"
default n
endif
menuconfig BSP_USING_GPIO
bool "Enable GPIO"
default n
select RT_USING_PIN
menuconfig BSP_USING_QSPI
bool "Enable QSPI"
default n
select RT_USING_QSPI
select RT_USING_SPI
select RT_USING_PIN
if BSP_USING_QSPI
config RT_USING_QSPI0
bool "Enable qspi0"
default n
if RT_USING_QSPI0
config USING_QSPI_CHANNEL0
bool "using qspi channel_0"
default n
config USING_QSPI_CHANNEL1
bool "using qspi channel_1"
default n
endif
endif
menuconfig BSP_USING_ETH_LAYER
bool "Enable ETH Layer"
default n
if BSP_USING_ETH_LAYER
config RT_LWIP_PBUF_POOL_BUFSIZE
int "The size of each pbuf in the pbuf pool"
range 1500 2000
default 1700
choice
prompt "Select ETH Mode"
config BSP_USING_ETH
bool "Standard ETH"
help
Use standard ETH communication mode
config BSP_USING_ETH_MSG
bool "IOP message-based ETH"
help
Use IOP message-based ETH communication
endchoice
if BSP_USING_ETH
config RT_USING_XMAC0
bool "Enable XMAC0"
default n
config RT_USING_XMAC1
bool "Enable XMAC1"
default n
config RT_USING_XMAC2
bool "Enable XMAC2"
default n
config RT_USING_XMAC3
bool "Enable XMAC3"
default n
endif
if BSP_USING_ETH_MSG
config RT_USING_XMAC0_MSG
bool "Enable XMAC0_MSG"
default n
config RT_USING_XMAC1_MSG
bool "Enable XMAC1_MSG"
default n
config RT_USING_XMAC2_MSG
bool "Enable XMAC2_MSG"
default n
config RT_USING_XMAC3_MSG
bool "Enable XMAC3_MSG"
default n
endif
endif
menuconfig BSP_USING_PWM
bool "Enable PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config RT_USING_PWM0
bool "Enable pwm0"
default n
config RT_USING_PWM1
bool "Enable pwm1"
default n
config RT_USING_PWM2
bool "Enable pwm2"
default n
config RT_USING_PWM3
bool "Enable pwm3"
default n
config RT_USING_PWM4
bool "Enable pwm4"
default n
config RT_USING_PWM5
bool "Enable pwm5"
default n
config RT_USING_PWM6
bool "Enable pwm6"
default n
config RT_USING_PWM7
bool "Enable pwm7"
default n
endif
menuconfig BSP_USING_SDIF_LAYER
bool "Enable SDIF Layer"
default n
select RT_USING_SDIO
if BSP_USING_SDIF
config BSP_USING_SDCARD_FATFS
bool "Enable SDCARD (FATFS)"
select RT_USING_DFS_ELMFAT
default n
if BSP_USING_SDIF_LAYER
config BSP_USING_SDCARD_FATFS
bool "Enable SDCARD (FATFS)"
select RT_USING_DFS_ELMFAT
default n
choice
prompt "Select SD Mode"
default BSP_USING_SDIF
config BSP_USING_SDIF
bool "Standard SD"
help
Use standard SD protocol
config BSP_USING_SDIF_MSG
bool "Message-based SD"
help
Use message-based SD communication
endchoice
if (BSP_USING_SDIF || BSP_USING_SDIF_MSG)
config USING_SDIF0
bool "Use SDIF0"
default n
if USING_SDIF0
choice
prompt "Select SD0 Usage"
default USE_SDIF0_TF
prompt "Select SD0 Usage"
default USE_SDIF0_TF
config USE_SDIF0_TF
bool "SD0(TF)"
config USE_SDIF0_EMMC
bool "SD0(eMMC)"
endchoice
endif
endif
if (BSP_USING_SDIF)
config USING_SDIF1
bool "Use SDIF1"
default n
if USING_SDIF1
choice
prompt "Select SD1 Usage"
default USE_SDIF1_TF
prompt "Select SD1 Usage"
default USE_SDIF1_TF
config USE_SDIF1_TF
bool "SD1(TF)"
config USE_SDIF1_EMMC
bool "SD1(eMMC)"
endchoice
endif
endif
endif
menuconfig BSP_USING_DC
@@ -281,6 +429,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable I2S"
default n
select RT_USING_AUDIO
select BSP_USING_DEVICE
if BSP_USING_I2S
config RT_I2S_SAMPLERATE
int "The samplerate param"
@@ -292,6 +441,18 @@ menu "On-chip Peripheral Drivers"
bool "Enable i2s0"
default n
endif
menuconfig BSP_USING_DEVICE
bool "Enable Device"
default n
if BSP_USING_DEVICE
config BSP_USING_ES8336
bool "Enable ES8336"
default n
config BSP_USING_ES8388
bool "Enable ES8388"
default n
endif
endmenu
menu "Board extended module Drivers"

4
bsp/phytium/libraries/drivers/drv_can.c
View File

@@ -44,7 +44,7 @@ static void CanRxIrqCallback(void *args)
struct phytium_can *drv_can = (struct phytium_can *)args;
rt_hw_can_isr(&(drv_can->device), RT_CAN_EVENT_RX_IND);
rt_kprintf("CAN%d irq recv frame callback.", drv_can->can_handle.config.instance_id);
LOG_D("CAN%d irq recv frame callback.", drv_can->can_handle.config.instance_id);
}
static void CanTxIrqCallback(void *args)
@@ -52,7 +52,7 @@ static void CanTxIrqCallback(void *args)
struct phytium_can *drv_can = (struct phytium_can *)args;
rt_hw_can_isr(&(drv_can->device), RT_CAN_EVENT_TX_DONE);
rt_kprintf("CAN%d irq send frame callback.", drv_can->can_handle.config.instance_id);
LOG_D("CAN%d irq send frame callback.", drv_can->can_handle.config.instance_id);
}
static void CanErrorCallback(void *args)

4
bsp/phytium/libraries/drivers/drv_gpio.c
View File

@@ -22,9 +22,7 @@
#include "ioremap.h"
#endif
#if defined(TARGET_E2000)
#include "fparameters.h"
#endif
#include "fparameters.h"
#include "fkernel.h"
#include "fcpu_info.h"
#include "ftypes.h"

71
bsp/phytium/libraries/drivers/drv_i2c.c
View File

@@ -19,8 +19,6 @@
#include "fi2c.h"
#include "fi2c_hw.h"
#include "fio_mux.h"
#include "fmio_hw.h"
#include "fmio.h"
#include "drivers/dev_i2c.h"
#include "fparameters.h"
#ifdef RT_USING_SMART
@@ -29,11 +27,12 @@
/*Please define the length of the mem_addr of the device*/
#ifndef FI2C_DEVICE_MEMADDR_LEN
#define FI2C_DEVICE_MEMADDR_LEN 1
#define FI2C_DEVICE_MEMADDR_LEN 2
#endif
#define FI2C_DEFAULT_ID 0
#define I2C_USE_MIO
#if defined(I2C_USE_MIO)
#include "fmio_hw.h"
#include "fmio.h"
static FMioCtrl mio_handle;
#endif
@@ -68,7 +67,16 @@ static rt_err_t i2c_config(struct phytium_i2c_bus *i2c_bus)
if (ret != FI2C_SUCCESS)
{
LOG_E("Init master I2c failed, ret: 0x%x", ret);
return -RT_ERROR;
}
ret = FI2cSetAddress(&i2c_bus->i2c_handle, FI2C_MASTER, i2c_bus->i2c_handle.config.slave_addr);
if (FI2C_SUCCESS != ret)
{
return -RT_ERROR;
}
ret = FI2cSetSpeed(&i2c_bus->i2c_handle, FI2C_SPEED_STANDARD_RATE, TRUE);
if (FI2C_SUCCESS != ret)
{
return -RT_ERROR;
}
@@ -80,10 +88,10 @@ static rt_err_t i2c_config(struct phytium_i2c_bus *i2c_bus)
static rt_err_t i2c_mio_config(struct phytium_i2c_bus *i2c_bus)
{
RT_ASSERT(i2c_bus);
FI2cConfig input_cfg;
const FI2cConfig *config_p = NULL;
FI2c *instance_p = &i2c_bus->i2c_handle;
FError ret = FI2C_SUCCESS;
FI2cConfig i2c_config;
FI2c *instance_p = &i2c_bus->i2c_handle;
FIOPadSetMioMux(instance_p->config.instance_id);
mio_handle.config = *FMioLookupConfig(instance_p->config.instance_id);
#ifdef RT_USING_SMART
@@ -97,27 +105,35 @@ static rt_err_t i2c_mio_config(struct phytium_i2c_bus *i2c_bus)
return -RT_ERROR;
}
FIOPadSetMioMux(instance_p->config.instance_id);
/* Modify i2c configuration */
rt_memset(&i2c_config, 0, sizeof(i2c_config));
i2c_config.base_addr = FMioFuncGetAddress(&mio_handle, FMIO_FUNC_SET_I2C);
i2c_config.irq_num = FMioFuncGetIrqNum(&mio_handle, FMIO_FUNC_SET_I2C);
i2c_config.irq_prority = 0;
i2c_config.ref_clk_hz = FMIO_CLK_FREQ_HZ;
i2c_config.work_mode = FI2C_MASTER;
i2c_config.use_7bit_addr = TRUE;
i2c_config.speed_rate = FI2C_SPEED_STANDARD_RATE;
i2c_config.auto_calc = TRUE;
config_p = FI2cLookupConfig(FI2C_DEFAULT_ID);
if (NULL == config_p)
{
LOG_E("Config of mio instance %d non found.", instance_p->config.instance_id);
return -RT_ERROR;
}
ret = FI2cCfgInitialize(instance_p, &i2c_config);
input_cfg = *config_p;
input_cfg.instance_id = instance_p->config.instance_id;
input_cfg.base_addr = FMioFuncGetAddress(&mio_handle, FMIO_FUNC_SET_I2C);
input_cfg.irq_num = FMioFuncGetIrqNum(&mio_handle, FMIO_FUNC_SET_I2C);
input_cfg.ref_clk_hz = FMIO_CLK_FREQ_HZ;
input_cfg.speed_rate = FI2C_SPEED_STANDARD_RATE;
ret = FI2cCfgInitialize(&i2c_bus->i2c_handle, &input_cfg);
if (FI2C_SUCCESS != ret)
{
LOG_E("Init mio master failed, ret: 0x%x", ret);
return -RT_ERROR;
}
ret = FI2cSetAddress(instance_p, FI2C_MASTER, instance_p->config.slave_addr);
if (FI2C_SUCCESS != ret)
{
return -RT_ERROR;
}
ret = FI2cSetSpeed(instance_p, FI2C_SPEED_STANDARD_RATE, TRUE);
if (FI2C_SUCCESS != ret)
{
return -RT_ERROR;
}
mio_handle.is_ready = 0;
rt_memset(&mio_handle, 0, sizeof(mio_handle));
@@ -129,9 +145,8 @@ static rt_err_t phytium_i2c_set_speed(struct phytium_i2c_bus *i2c_bus, rt_uint32
{
RT_ASSERT(i2c_bus);
u32 ret;
uintptr base_addr = i2c_bus->i2c_handle.config.base_addr;
ret = FI2cSetSpeed(base_addr, speed, TRUE);
ret = FI2cSetSpeed(&i2c_bus->i2c_handle, speed, TRUE);
if (ret != FI2C_SUCCESS)
{
LOG_E("Set i2c speed failed!\n");
@@ -265,6 +280,9 @@ static int i2c_mio_init(struct phytium_i2c_bus *i2c_mio_bus)
#if defined(RT_USING_I2C2)
static struct phytium_i2c_bus i2c_controller2_bus;
#endif
#if defined(RT_USING_I2C3)
static struct phytium_i2c_bus i2c_controller3_bus;
#endif
#if defined(RT_USING_MIO0)
static struct phytium_i2c_bus i2c_mio0_bus;
@@ -332,6 +350,11 @@ int rt_hw_i2c_init(void)
i2c_controller2_bus.i2c_handle.config.instance_id = FI2C2_ID;
i2c_controller_init(&i2c_controller2_bus);
#endif
#if defined(RT_USING_I2C3)
i2c_controller3_bus.name = "I2C3";
i2c_controller3_bus.i2c_handle.config.instance_id = FI2C3_ID;
i2c_controller_init(&i2c_controller3_bus);
#endif
#if defined(RT_USING_MIO0)
i2c_mio0_bus.name = "MIO0";

246
bsp/phytium/libraries/drivers/drv_i2c_msg.c Normal file
View File

@@ -0,0 +1,246 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-10-23 zhangyan first version
*
*/
#include "rtconfig.h"
#include <rtdevice.h>
#include <string.h>
#define LOG_TAG "i2c_drv_msg"
#include "drv_log.h"
#include "drv_i2c_msg.h"
#include "fi2c_msg.h"
#include "fi2c_msg_hw.h"
#include "fi2c_msg_master.h"
#include "fio_mux.h"
#include "drivers/dev_i2c.h"
#include "fparameters.h"
#ifdef RT_USING_SMART
#include <ioremap.h>
#endif
/*Please define the length of the mem_addr of the device*/
#ifndef FI2C_DEVICE_MEMADDR_LEN
#define FI2C_DEVICE_MEMADDR_LEN 2
#endif
#define I2C_TIMEOUT_MS 1000
struct phytium_i2c_msg_bus
{
struct rt_i2c_bus_device device;
FI2cMsgCtrl i2c_handle;
struct rt_i2c_msg *msg;
const char *name;
};
static rt_err_t i2c_msg_config(struct phytium_i2c_msg_bus *i2c_bus)
{
RT_ASSERT(i2c_bus);
FI2cMsgConfig input_cfg;
const FI2cMsgConfig *config_p = NULL;
FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
rt_uint32_t cpu_id = rt_hw_cpu_id();
FError ret = FI2C_MSG_SUCCESS;
FIOPadSetI2CMux(instance_p->config.instance_id);
/* Lookup default configs by instance id */
config_p = FI2cMsgLookupConfig(instance_p->config.instance_id);
input_cfg = *config_p;
#ifdef RT_USING_SMART
input_cfg.msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.msg.shmem, 0x1000);
input_cfg.msg.regfile= (uintptr)rt_ioremap((void *)input_cfg.msg.regfile, 0x1000);
#endif
/* Initialization */
ret = FI2cMsgCfgInitialize(instance_p, &input_cfg);
if (ret != FI2C_MSG_SUCCESS)
{
LOG_E("FI2cMsgCfgInitialize failed, ret = %d", ret);
return -RT_ERROR;
}
instance_p->speed_mode = FI2C_STANDARD_SPEED;
instance_p->timeout_ms = I2C_TIMEOUT_MS;
instance_p->clk_clock_frequency = FI2C_CLK_FREQ_HZ;
rt_hw_interrupt_set_target_cpus(instance_p->config.irq_num, cpu_id);
rt_hw_interrupt_set_priority(instance_p->config.irq_num, instance_p->config.irq_prority);
rt_hw_interrupt_install(instance_p->config.irq_num, FI2cMsgMasterRegfileIsr, instance_p, i2c_bus->name);
rt_hw_interrupt_umask(instance_p->config.irq_num);
ret = FI2cMsgMasterVirtProbe(instance_p);
if (ret != FI2C_MSG_SUCCESS)
{
LOG_E("FI2cMsgMasterVirtProbe failed, ret = %d", ret);
return ret;
}
return RT_EOK;
}
static rt_err_t phytium_i2c_set_speed(struct phytium_i2c_msg_bus *i2c_bus, rt_uint32_t speed)
{
RT_ASSERT(i2c_bus);
FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
switch (speed)
{
case FI2C_SPEED_STANDARD_RATE:
instance_p->speed_mode = FI2C_STANDARD_SPEED;
break;
case FI2C_SPEED_FAST_RATE:
instance_p->speed_mode = FI2C_FAST_SPEED;
break;
case FI2C_SPEED_HIGH_RATE:
instance_p->speed_mode = FI2C_HIGH_SPEED;
break;
default:
return -RT_EIO;
}
FI2cMsgSetBusSpeed(instance_p, instance_p->speed_mode, TRUE);
return RT_EOK;
}
static rt_err_t i2c_msg_bus_control(struct rt_i2c_bus_device *device, int cmd, void *args)
{
RT_ASSERT(device);
struct phytium_i2c_msg_bus *i2c_bus;
i2c_bus = (struct phytium_i2c_msg_bus *)(device);
FI2cMsgConfig *config_p;
switch (cmd)
{
case RT_I2C_DEV_CTRL_CLK:
phytium_i2c_set_speed(i2c_bus, *(rt_uint32_t *)args);
break;
case RT_I2C_DEV_CTRL_10BIT:
break;
default:
return -RT_EIO;
}
return RT_EOK;
}
static rt_ssize_t i2c_msg_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2c_msg msgs[], rt_uint32_t num)
{
RT_ASSERT(device);
u32 ret;
struct rt_i2c_msg *pmsg;
rt_ssize_t i;
struct phytium_i2c_msg_bus *i2c_bus;
i2c_bus = (struct phytium_i2c_msg_bus *)(device);
FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
for (i = 0; i < num; i++)
{
pmsg = &msgs[i];
if (pmsg->flags & RT_I2C_RD)
{
/*When performing a read operation, first write to the input memaddr, and then read*/
struct FI2cMsg msg[2];
msg[0].addr = pmsg->addr;
msg[0].flags = FI2C_MSG_WD;
msg[0].len = FI2C_DEVICE_MEMADDR_LEN;
msg[0].buf = pmsg->buf;
msg[1].addr = pmsg->addr;
msg[1].flags = FI2C_MSG_RD;
msg[1].len = pmsg->len;
msg[1].buf = pmsg->buf;
ret = FI2cMsgMasterVirtXfer(instance_p, msg, 2);
if (ret != FI2C_MSG_SUCCESS)
{
LOG_E("FI2cMsgMasterVirtProbe read failed, ret = %d", ret);
}
}
else
{
struct FI2cMsg msg;
msg.addr = pmsg->addr;
msg.buf = pmsg->buf;
msg.len = pmsg->len;
msg.flags = FI2C_MSG_WD;
ret = FI2cMsgMasterVirtXfer(instance_p, &msg, 1); /*num = 1 ,只需发送一次写命令*/
if (ret != FI2C_MSG_SUCCESS)
{
LOG_E("FI2cMsgMasterVirtProbe write failed, ret = %d", ret);
}
}
}
return i;
}
static const struct rt_i2c_bus_device_ops _i2c_ops =
{
.master_xfer = i2c_msg_master_xfer,
.slave_xfer = NULL,
.i2c_bus_control = i2c_msg_bus_control
};
static int i2c_msg_controller_init(struct phytium_i2c_msg_bus *i2c_controller_bus)
{
rt_err_t ret = RT_EOK;
ret = i2c_msg_config(i2c_controller_bus);
if (ret != RT_EOK)
{
LOG_E("I2C config failed.\n");
return -RT_ERROR;
}
i2c_controller_bus->device.ops = &_i2c_ops;
ret = rt_i2c_bus_device_register(&i2c_controller_bus->device, i2c_controller_bus->name);
RT_ASSERT(RT_EOK == ret);
LOG_D("I2C bus reg success.\n");
return ret;
}
#if defined(RT_USING_I2C0_MSG)
static struct phytium_i2c_msg_bus i2c_msg_controller0_bus;
#endif
#if defined(RT_USING_I2C1_MSG)
static struct phytium_i2c_msg_bus i2c_msg_controller1_bus;
#endif
#if defined(RT_USING_I2C2_MSG)
static struct phytium_i2c_msg_bus i2c_msg_controller2_bus;
#endif
#if defined(RT_USING_I2C3_MSG)
static struct phytium_i2c_msg_bus i2c_msg_controller3_bus;
#endif
int rt_hw_i2c_msg_init(void)
{
#if defined(RT_USING_I2C0_MSG)
i2c_msg_controller0_bus.name = "I2C0_MSG";
i2c_msg_controller0_bus.i2c_handle.config.instance_id = FI2C0_MSG_ID;
i2c_msg_controller_init(&i2c_msg_controller0_bus);
#endif
#if defined(RT_USING_I2C1_MSG)
i2c_msg_controller1_bus.name = "I2C1_MSG";
i2c_msg_controller1_bus.i2c_handle.config.instance_id = FI2C1_MSG_ID;
i2c_msg_controller_init(&i2c_msg_controller1_bus);
#endif
#if defined(RT_USING_I2C2_MSG)
i2c_msg_controller2_bus.name = "I2C2_MSG";
i2c_msg_controller2_bus.i2c_handle.config.instance_id = FI2C2_MSG_ID;
i2c_msg_controller_init(&i2c_msg_controller2_bus);
#endif
#if defined(RT_USING_I2C3_MSG)
i2c_msg_controller3_bus.name = "I2C3_MSG";
i2c_msg_controller3_bus.i2c_handle.config.instance_id = FI2C3_MSG_ID;
i2c_msg_controller_init(&i2c_msg_controller3_bus);
#endif
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_i2c_msg_init);

29
bsp/phytium/libraries/drivers/drv_i2c_msg.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-10-18 zhangyan first version
*
*/
#ifndef __DRV_I2C_MSG_H__
#define __DRV_I2C_MSG_H__
#include <rtdevice.h>
#ifdef __cplusplus
extern "C"
{
#endif
int rt_hw_i2c_msg_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_CAN_H__ */

115
bsp/phytium/libraries/drivers/drv_i2s.c
View File

@@ -20,6 +20,7 @@
#include "fddma.h"
#include "fddma_hw.h"
#include "fddma_bdl.h"
#include "fdevice.h"
#include "fes8336.h"
#define DBG_TAG "drv.i2s"
@@ -31,9 +32,16 @@
static struct phytium_i2s_device i2s_dev0;
extern FI2c master_device;
extern FMioCtrl es8336;
#define ES8336_MIO FMIO14_ID
#define ES8336_ADDR 0x10
static FEs8336Controller fes8336 =
{
.fes8336_device.name = "es8336",
.dev_type = DEV_TYPE_MIO,
.controller_id = FMIO14_ID,
};
static const u32 ddma_ctrl_id = FDDMA2_I2S_ID;
static const u32 i2s_ctrl_id = FI2S0_ID;
struct phytium_i2s_device
{
@@ -46,8 +54,6 @@ struct phytium_i2s_device
FI2sConfig i2s_config;
FDdma ddmac;
FDdmaConfig ddmac_config;
rt_uint8_t ddma_ctrl_id;
rt_uint8_t i2s_ctrl_id;
rt_uint8_t *rx_fifo;
FDdmaChanConfig rx_config;
@@ -75,84 +81,48 @@ static void FDdmaSetupInterrupt(FDdma *const instance)
return;
}
FError RtEs8336Init(void)
{
FError ret = FES8336_SUCCESS;
FMioCtrl *pctrl = &es8336;
FMioConfig *mioconfig_p ;
FI2c *instance_p = &master_device;
FI2cConfig i2cconfig;
mioconfig_p = FMioLookupConfig(ES8336_MIO);
if (NULL == mioconfig_p)
{
printf("Mio error inval parameters.\r\n");
return FMIO_ERR_INVAL_PARM;
}
pctrl->config = *mioconfig_p;
ret = FMioFuncInit(pctrl, FMIO_FUNC_SET_I2C);
if (ret != FES8336_SUCCESS)
{
printf("ES8336_MIO MioInit error.\r\n");
return ret;
}
/* get standard config of i2c */
i2cconfig = *FI2cLookupConfig(FI2C0_ID);
/* Modify configuration */
i2cconfig.base_addr = FMioFuncGetAddress(pctrl, FMIO_FUNC_SET_I2C);
i2cconfig.irq_num = FMioFuncGetIrqNum(pctrl, FMIO_FUNC_SET_I2C);
FI2cDeInitialize(instance_p);
/* Initialization */
ret = FI2cCfgInitialize(instance_p, &i2cconfig);
if (ret != FES8336_SUCCESS)
{
return ret;
}
/*set the i2c parameters */
ret = FI2cSetAddress(instance_p, FI2C_MASTER, ES8336_ADDR);
if (FI2C_SUCCESS != ret)
{
printf("set mio slave parameters failed, ret: 0x%x\r\n", ret);
return ret;
}
ret = FI2cSetSpeed(instance_p, FI2C_SPEED_STANDARD_RATE, TRUE);
if (FI2C_SUCCESS != ret)
{
printf("set mio slave parameters failed, ret: 0x%x\r\n", ret);
return ret;
}
/* callback function for FI2C_MASTER_INTR_EVT interrupt */
instance_p->master_evt_handlers[FI2C_EVT_MASTER_TRANS_ABORTED] = NULL;
instance_p->master_evt_handlers[FI2C_EVT_MASTER_READ_DONE] = NULL;
instance_p->master_evt_handlers[FI2C_EVT_MASTER_WRITE_DONE] = NULL;
return ret;
}
static FError FI2sEs8336Init(u32 word_length)
{
FError ret = FT_SUCCESS;
u32 volumel = 0x1;
FIOMuxInit();
FIOPadSetI2sMux();
ret = RtEs8336Init(); /* es8336初始化，i2s slave设置 */
ret = FEs8336DevRegister(&fes8336.fes8336_device);
if (FT_SUCCESS != ret)
{
printf("Es8336 init failed.\r\n");
printf("ES8336 dev register failed.\r\n");
return ret;
}
FEs8336RegsProbe(); /* 寄存器默认值 */
FEs8336Startup();
ret = FEs8336SetFormat(word_length); /* 设置ES8336工作模式 */
ret = FDeviceInit(&fes8336.fes8336_device);
if (FT_SUCCESS != ret)
{
printf("Set the es8336 word length failed.\r\n");
printf("ES8336 dev init failed.\r\n");
return ret;
}
ret = FDeviceOpen(&fes8336.fes8336_device, FDEVICE_FLAG_RDWR);
if (FT_SUCCESS != ret)
{
printf("ES8336 dev open failed.\r\n");
return ret;
}
ret = FDeviceControl(&fes8336.fes8336_device, FES8336_SET_FORMAT, &word_length); /* 设置ES8336工作模式 */
if (FT_SUCCESS != ret)
{
printf("Set the ES8336 word length failed.\r\n");
return ret;
}
ret = FDeviceControl(&fes8336.fes8336_device, FES8336_SET_VOLUMEL, &volumel); /* 设置ES8336工作模式 */
if (FT_SUCCESS != ret)
{
printf("Set the ES8336 volumel failed.\r\n");
return ret;
}
FEs8336SetVolumel(0x1);
return ret;
}
@@ -160,12 +130,11 @@ static FError FI2sEs8336Init(u32 word_length)
static FError FI2sRxInit(struct phytium_i2s_device *i2s_dev, u32 word_length)
{
FError ret = FI2S_SUCCESS;
u32 i2s_id = i2s_dev->i2s_ctrl_id;
memset(&i2s_dev->i2s_ctrl, 0, sizeof(FI2s));
memset(&i2s_dev->i2s_ctrl, 0, sizeof(FI2sConfig));
i2s_dev->i2s_ctrl.data_config.word_length = word_length;
i2s_dev->i2s_config = *FI2sLookupConfig(i2s_id);
i2s_dev->i2s_config = *FI2sLookupConfig(i2s_ctrl_id);
ret = FI2sCfgInitialize(&i2s_dev->i2s_ctrl, &i2s_dev->i2s_config);
if (FI2S_SUCCESS != ret)
@@ -182,7 +151,7 @@ static FError FI2sRxInit(struct phytium_i2s_device *i2s_dev, u32 word_length)
static FError FI2sRxDdmaInit(struct phytium_i2s_device *i2s_dev)
{
FError ret = FI2S_SUCCESS;
i2s_dev->ddmac_config = *FDdmaLookupConfig(i2s_dev->ddma_ctrl_id);
i2s_dev->ddmac_config = *FDdmaLookupConfig(ddma_ctrl_id);
ret = FDdmaCfgInitialize(&i2s_dev->ddmac, &i2s_dev->ddmac_config);
if (FI2S_SUCCESS != ret)
@@ -481,8 +450,6 @@ int rt_hw_i2s_init(void)
#if defined(RT_USING_I2S0)
i2s_dev0.name = "I2S0";
i2s_dev0.i2s_ctrl.config.instance_id = FI2S0_ID;
i2s_dev0.i2s_ctrl_id = FI2S0_ID;
i2s_dev0.ddma_ctrl_id = FDDMA2_I2S_ID;
i2s_dev0.config.channels = 1;
i2s_dev0.config.samplerate = RT_I2S_SAMPLERATE;
i2s_dev0.config.samplebits = RT_I2S_SAMPLEBITS;

2
bsp/phytium/libraries/drivers/drv_pwm.c
View File

@@ -34,7 +34,9 @@ static rt_err_t drv_pwm_config(struct phytium_pwm *pwm_dev)
FPwmConfig config;
FPwmCtrl *pwm_handle = &pwm_dev->pwm_handle;
FIOPadSetPwmMux(pwm_handle->config.instance_id, 0);
#if !defined(PD2408_TEST_A_BOARD) || defined(PD2408_TEST_B_BOARD)
FIOPadSetPwmMux(pwm_handle->config.instance_id, 1);
#endif
config = *FPwmLookupConfig(pwm_handle->config.instance_id);
#ifdef RT_USING_SMART
config.lsd_config_addr = (uintptr)rt_ioremap((void *)config.lsd_config_addr, 0x100);

23
bsp/phytium/libraries/drivers/drv_qspi.c
View File

@@ -25,18 +25,10 @@
#include "fiopad.h"
#include "fqspi_hw.h"
#include "fio_mux.h"
#include <string.h>
#define QSPI_ALIGNED_BYTE 4
typedef struct
{
rt_uint32_t fqspi_id;
const char *name;
rt_uint32_t init; /* 0 is init already */
FQspiCtrl fqspi;
struct rt_spi_bus qspi_bus;
} phytium_qspi_bus;
static rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus)
{
FError ret = FT_SUCCESS;
@@ -277,7 +269,7 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
phytium_qspi_bus *qspi_bus;
qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
qspi_bus = (phytium_qspi_bus *) device->bus->parent.user_data;
rt_err_t ret = RT_EOK;
ret = FQspiInit(qspi_bus);
@@ -303,9 +295,12 @@ static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_
rt_uint32_t len = message->length;
const void *rcvb = message->recv_buf;
const void *sndb = message->send_buf;
qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
uintptr addr = qspi_bus->fqspi.config.mem_start + qspi_bus->fqspi.config.channel * qspi_bus->fqspi.flash_size + flash_addr;
qspi_bus = (phytium_qspi_bus *) device->bus->parent.user_data;
uintptr addr = flash_addr;
for (u32 index = 0; index < qspi_bus->fqspi.config.channel; index++)
{
addr = qspi_bus->fqspi.flash_size[index];
}
/*Distinguish the write mode according to different commands*/
if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP)
{
@@ -455,7 +450,7 @@ static int rt_qspi_init(phytium_qspi_bus *phytium_qspi)
if (rt_qspi_bus_register(&phytium_qspi->qspi_bus, phytium_qspi->name, &phytium_qspi_ops) == RT_EOK)
{
LOG_E("Qspi bus register successfully!!!\n");
LOG_D("Qspi bus register successfully!!!\n");
}
else
{

10
bsp/phytium/libraries/drivers/drv_qspi.h
View File

@@ -15,10 +15,20 @@
#define __DRV_QSPI_H__
#include "rtdef.h"
#include "fqspi_flash.h"
#include "fqspi_hw.h"
#ifdef __cplusplus
extern "C"
{
#endif
typedef struct
{
rt_uint32_t fqspi_id;
const char *name;
rt_uint32_t init; /* 0 is init already */
FQspiCtrl fqspi;
struct rt_spi_bus qspi_bus;
} phytium_qspi_bus;
rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name);

78
bsp/phytium/libraries/drivers/drv_sdif.c
View File

@@ -14,8 +14,8 @@
/***************************** Include Files *********************************/
#include "rtconfig.h"
#if defined(BSP_USING_SDIF_LAYER)
#ifdef BSP_USING_SDIF
#include <rthw.h>
#include <rtdef.h>
#include <rtthread.h>
@@ -240,50 +240,54 @@ static void sdif_convert_command_info(struct rt_mmcsd_host *host, struct rt_mmcs
FSdifData *out_data = out_req->data_p;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
out_cmd->flag = 0U;
uint32_t opcode = in_cmd->cmd_code;
out_cmd->rawcmd = FSDIF_CMD_INDX_SET(opcode);
if (in_cmd->cmd_code == GO_IDLE_STATE)
{
out_cmd->flag |= FSDIF_CMD_FLAG_NEED_INIT;
out_cmd->rawcmd |= FSDIF_CMD_INIT;
}
if (in_cmd->cmd_code == GO_INACTIVE_STATE)
{
out_cmd->flag |= FSDIF_CMD_FLAG_NEED_AUTO_STOP | FSDIF_CMD_FLAG_ABORT;
out_cmd->rawcmd |= FSDIF_CMD_STOP_ABORT;
}
if (in_cmd->cmd_code == VOLTAGE_SWITCH)
{
out_cmd->rawcmd |= FSDIF_CMD_VOLT_SWITCH;
}
if (resp_type(in_cmd) != RESP_NONE)
{
out_cmd->flag |= FSDIF_CMD_FLAG_EXP_RESP;
out_cmd->rawcmd |= FSDIF_CMD_RESP_EXP;
if (resp_type(in_cmd) == RESP_R2)
{
/* need 136 bits long response */
out_cmd->flag |= FSDIF_CMD_FLAG_EXP_LONG_RESP;
out_cmd->rawcmd |= FSDIF_CMD_RESP_LONG;
}
if ((resp_type(in_cmd) != RESP_R3) &&
(resp_type(in_cmd) != RESP_R4))
{
/* most cmds need CRC */
out_cmd->flag |= FSDIF_CMD_FLAG_NEED_RESP_CRC;
out_cmd->rawcmd |= FSDIF_CMD_RESP_CRC;
}
}
if (in_data)
{
RT_ASSERT(out_data);
out_cmd->flag |= FSDIF_CMD_FLAG_EXP_DATA;
out_cmd->rawcmd |= FSDIF_CMD_DAT_EXP;
if (in_data->flags & DATA_DIR_READ)
{
out_cmd->flag |= FSDIF_CMD_FLAG_READ_DATA;
out_data->buf = (void *)in_data->buf;
out_data->buf_dma = (uintptr_t)in_data->buf + PV_OFFSET;
}
else if (in_data->flags & DATA_DIR_WRITE)
{
out_cmd->flag |= FSDIF_CMD_FLAG_WRITE_DATA;
out_cmd->rawcmd |= FSDIF_CMD_DAT_WRITE;
out_data->buf = (void *)in_data->buf;
out_data->buf_dma = (uintptr_t)in_data->buf + PV_OFFSET;
}
@@ -339,10 +343,20 @@ static rt_err_t sdif_do_transfer(struct rt_mmcsd_host *host, FSdifCmdData *req_c
wait_event = SDIF_EVENT_COMMAND_DONE | SDIF_EVENT_DATA_DONE;
}
if (req_cmd->data_p)
{
ret = FSdifSetupDMADescriptor(&host_info->sdif, req_cmd->data_p);
if (ret != FT_SUCCESS)
{
LOG_E("FSdifSetupDMADescriptor fail.");
return -RT_ERROR;
}
}
ret = FSdifDMATransfer(&host_info->sdif, req_cmd);
if (ret != FT_SUCCESS)
{
LOG_E("FSdifDMATransfer() fail.");
LOG_E("FSdifDMATransfer() fail. ret = 0x%x", ret);
return -RT_ERROR;
}
@@ -445,14 +459,46 @@ static void sdif_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
static void sdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
FError ret = FT_SUCCESS;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdif *sdif = &host_info->sdif;
uintptr base_addr = sdif->config.base_addr;
if (0 != io_cfg->clock)
{
ret = FSdifSetClkFreq(sdif, io_cfg->clock);
// boolean is_ddr = FALSE;
// if (host->card->type == CARD_TYPE_MMC)
// {
// if (io_cfg->timing == MMCSD_TIMING_MMC_HS400 ||
// io_cfg->timing == MMCSD_TIMING_MMC_HS400_ENH_DS)
// {
// is_ddr = TRUE;
// }
// }
// else if (host->card->type == CARD_TYPE_SD)
// {
// if (io_cfg->timing == MMCSD_TIMING_UHS_DDR50)
// {
// is_ddr = TRUE;
// }
// }
// if (FSDIF_SUCCESS != FSdifSetClkFreqByCalc(&dev->hc, is_ddr, io_cfg->clock))
// {
// LOG_E("FSdifSetClkFreqByCalc fail.")
// }
FSdifTiming timing;
FError ret;
boolean is_ddr = FALSE;
memset(&timing, 0U, sizeof(timing));
/* Get the timing setting based on the clock frequency and device removability */
ret = FSdifGetTimingSetting(io_cfg->clock, sdif->config.non_removable, &timing);
if (ret != FT_SUCCESS)
{
LOG_E("Failed to find timing for clock-%d", io_cfg->clock);
}
/* Set the clock frequency using the obtained timing setting */
ret = FSdifSetClkFreqByDict(sdif, FALSE, &timing, io_cfg->clock);
if (ret != FT_SUCCESS)
{
LOG_E("FSdifSetClkFreq fail.");
@@ -618,8 +664,6 @@ static rt_err_t sdif_host_init(rt_uint32_t id, rt_uint32_t type)
sdif_config.non_removable = TRUE; /* eMMC is unremovable on board */
}
sdif_config.get_tuning = FSdifGetTimingSetting;
if (FSDIF_SUCCESS != FSdifCfgInitialize(&host_info->sdif, &sdif_config))
{
LOG_E("SDIF controller init failed.");
@@ -714,4 +758,4 @@ int rt_hw_sdif_init(void)
return status;
}
INIT_DEVICE_EXPORT(rt_hw_sdif_init);
#endif // #ifdef BSP_USING_SDIF
#endif /* BSP_USING_SDIF_LAYER */

998
bsp/phytium/libraries/drivers/drv_sdif_msg.c Normal file
View File

@@ -0,0 +1,998 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/11 liqiaozhong init SD card and mount file system
* 2023/11/8 zhugengyu add interrupt handling for dma waiting, unify function naming
* 2024/4/7 zhugengyu support use two sdif device
*/
/***************************** Include Files *********************************/
#include "rtconfig.h"
#if defined(BSP_USING_SDIF_LAYER)
#include <rthw.h>
#include <rtdef.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdbg.h>
#include <drivers/dev_mmcsd_core.h>
#ifdef RT_USING_SMART
#include "ioremap.h"
#endif
#include "mm_aspace.h"
#include "interrupt.h"
#define LOG_TAG "sdif_msg_drv"
#include "drv_log.h"
#include "ftypes.h"
#include "fparameters.h"
#include "fcpu_info.h"
#include "fsdif_timing.h"
#include "fsdif_msg.h"
#include "fsdif_msg_hw.h"
#include "drv_sdif_msg.h"
/************************** Constant Definitions *****************************/
#define SDIF_CARD_TYPE_MICRO_SD 1
#define SDIF_CARD_TYPE_EMMC 2
#define SDIF_CARD_TYPE_SDIO 3
#define SDIF_DMA_BLK_SZ 512U
#define SDIF_MAX_BLK_TRANS 1024U
#define SDIF_DMA_ALIGN SDIF_DMA_BLK_SZ
/* preserve pointer to host instance */
static struct rt_mmcsd_host *mmc_host[FSDIF_NUM] = {RT_NULL};
/**************************** Type Definitions *******************************/
typedef struct
{
FSdifMsgCtrl sdif;
rt_int32_t sd_type;
FSdifMsgIDmaDesc *rw_desc;
uintptr_t rw_desc_dma;
rt_size_t rw_desc_num;
struct rt_event event;
#define SDIF_EVENT_CARD_DETECTED (1 << 0)
#define SDIF_EVENT_COMMAND_DONE (1 << 1)
#define SDIF_EVENT_DATA_DONE (1 << 2)
#define SDIF_EVENT_ERROR_OCCUR (1 << 3)
#define SDIF_EVENT_SDIO_IRQ (1 << 4)
void *aligned_buffer;
uintptr_t aligned_buffer_dma;
rt_size_t aligned_buffer_size;
FSdifMsgCommand req_cmd;
FSdifMsgData req_data;
FSdifMsgRequest req;
} sdif_info_t;
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/******************************* Functions *********************************/
void sdif_change(rt_uint32_t id)
{
RT_ASSERT(id < FSDIF_NUM);
if (mmc_host[id])
{
mmcsd_change(mmc_host[id]);
}
}
rt_int32_t sdif_card_inserted(rt_uint32_t id)
{
RT_ASSERT(id < FSDIF_NUM);
if (mmc_host[id])
{
return mmc_host[id]->ops->get_card_status(mmc_host[id]);
}
return 0;
}
static void sdif_card_detect_callback(FSdifMsgCtrl *const instance_p, void *args, void *data)
{
struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
rt_event_send(&host_info->event, SDIF_EVENT_CARD_DETECTED);
sdif_change(host_info->sdif.config.instance_id);
}
static void sdif_command_done_callback(FSdifMsgCtrl *const instance_p, void *args, void *data)
{
struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
rt_event_send(&host_info->event, SDIF_EVENT_COMMAND_DONE);
}
static void sdif_data_done_callback(FSdifMsgCtrl *const instance_p, void *args, void *data)
{
struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
rt_event_send(&host_info->event, SDIF_EVENT_DATA_DONE);
}
static void sdif_error_occur_callback(FSdifMsgCtrl *const instance_p, void *args, void *data)
{
struct rt_mmcsd_host *host = (struct rt_mmcsd_host *)args;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdifMsgDataErrIrq *err_data = (FSdifMsgDataErrIrq *)data;
if (err_data)
{
u32 status = err_data->raw_ints;
u32 dmac_status = err_data->dmac_status;
LOG_E("SDIF ERROR:");
LOG_E("Status: 0x%x, dmac status: 0x%x.", status, dmac_status);
if (status & FSDIF_INT_RE_BIT)
LOG_E("[CMD_FAIL]Response err. 0x%x", FSDIF_INT_RE_BIT);
if (status & FSDIF_INT_RTO_BIT)
LOG_E("[CMD_FAIL]Response timeout. 0x%x", FSDIF_INT_RTO_BIT);
if (dmac_status & FSDIF_DMAC_STATUS_DU)
LOG_E("[DATA_FAIL]Descriptor un-readable. 0x%x", FSDIF_DMAC_STATUS_DU);
if (status & FSDIF_INT_DCRC_BIT)
LOG_E("[DATA_FAIL]Data CRC error. 0x%x", FSDIF_INT_DCRC_BIT);
if (status & FSDIF_INT_RCRC_BIT)
LOG_E("[DATA_FAIL]Data CRC error. 0x%x", FSDIF_INT_RCRC_BIT);
rt_event_send(&host_info->event, SDIF_EVENT_ERROR_OCCUR);
}
}
static rt_err_t sdif_pre_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
rt_err_t err = RT_EOK;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
if (host_info->sd_type != SDIF_CARD_TYPE_SDIO)
{
/* ignore SDIO detect command */
if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) ||
(req->cmd->cmd_code == SD_IO_RW_DIRECT))
{
req->cmd->err = -1;
mmcsd_req_complete(host);
err = RT_EEMPTY;
}
}
if (host_info->sd_type == SDIF_CARD_TYPE_EMMC)
{
/* ignore micro SD detect command, not in eMMC spec. */
if ((req->cmd->cmd_code == SD_APP_OP_COND) ||
(req->cmd->cmd_code == APP_CMD))
{
req->cmd->err = -1;
mmcsd_req_complete(host);
err = RT_EEMPTY;
}
/* ignore mmcsd_send_if_cond(CMD-8) which will failed for eMMC
but check cmd arg to let SEND_EXT_CSD (CMD-8) run */
if ((req->cmd->cmd_code == SD_SEND_IF_COND) &&
(req->cmd->arg == 0x1AA)) /* 0x1AA is the send_if_cond pattern, use it by care */
{
req->cmd->err = -1;
mmcsd_req_complete(host);
err = RT_EEMPTY;
}
}
if ((req->cmd->cmd_code == READ_MULTIPLE_BLOCK) ||
(req->cmd->cmd_code == WRITE_MULTIPLE_BLOCK)) /* set block count */
{
struct rt_mmcsd_req sbc;
struct rt_mmcsd_cmd sbc_cmd;
rt_memset(&sbc, 0, sizeof(sbc));
rt_memset(&sbc_cmd, 0, sizeof(sbc_cmd));
sbc_cmd.cmd_code = SET_BLOCK_COUNT;
RT_ASSERT(req->data);
sbc_cmd.arg = req->data->blks;
sbc_cmd.flags = RESP_R1;
LOG_I("set block_count = %d", req->data->blks);
sbc.data = RT_NULL;
sbc.cmd = &sbc_cmd;
sbc.stop = RT_NULL;
sbc.sbc = RT_NULL;
mmcsd_send_request(host, &sbc);
err = sbc_cmd.err;
if (req->cmd->busy_timeout < 1000) /* in case rt-thread do not give wait timeout */
{
req->cmd->busy_timeout = 5000;
}
}
return err;
}
static rt_err_t sdif_do_transfer(struct rt_mmcsd_host *host, FSdifMsgRequest *request, rt_int32_t timeout_ms)
{
FError ret = FT_SUCCESS;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
rt_uint32_t event = 0U;
rt_uint32_t wait_event = 0U;
if (request->data)
{
wait_event = SDIF_EVENT_COMMAND_DONE | SDIF_EVENT_DATA_DONE;
}
else
{
wait_event = SDIF_EVENT_COMMAND_DONE;
}
ret = FSdifMsgDMATransfer(&host_info->sdif, request);
if (ret != FT_SUCCESS)
{
LOG_E("FSdifMsgDMATransfer() fail. ret = 0x%x", ret);
return -RT_ERROR;
}
while (TRUE)
{
/*
* transfer without data: wait COMMAND_DONE event
* transfer with data: wait COMMAND_DONE and DATA_DONE event
*/
if (rt_event_recv(&host_info->event,
(wait_event),
(RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR),
rt_tick_from_millisecond(1000),
&event) == RT_EOK)
{
break;
}
/*
* transfer with error: check if ERROR_OCCUR event exists, no wait
*/
if (rt_event_recv(&host_info->event,
(SDIF_EVENT_ERROR_OCCUR),
(RT_EVENT_FLAG_AND | RT_WAITING_NO),
0,
&event) == RT_EOK)
{
LOG_E("SDIF dma-transfer endup with error !!!");
return -RT_EIO;
}
timeout_ms -= 1000;
if (timeout_ms <= 0)
{
LOG_E("Sdif DMA transfer endup with timeout !!!");
return -RT_EIO;
}
}
return RT_EOK;
}
static uint32_t sdif_prepare_raw_command(struct rt_mmcsd_req *req)
{
struct rt_mmcsd_cmd *input_cmd = req->cmd;
struct rt_mmcsd_data *input_data = req->data;
uint32_t opcode = input_cmd->cmd_code;
uint32_t raw_cmd = FSDIF_CMD_INDX_SET(opcode);
rt_uint32_t resp_type = resp_type(input_cmd);
if (GO_IDLE_STATE == opcode)
{
raw_cmd |= FSDIF_CMD_INIT;
}
if (GO_INACTIVE_STATE == opcode)
{
raw_cmd |= FSDIF_CMD_STOP_ABORT;
}
if (RESP_NONE != resp_type)
{
raw_cmd |= FSDIF_CMD_RESP_EXP;
if (RESP_R2 == resp_type)
{
/* need 136 bits long response */
raw_cmd |= FSDIF_CMD_RESP_LONG;
}
if ((RESP_R3 != resp_type) && (RESP_R4 != resp_type))
{
/* most cmds need CRC */
raw_cmd |= FSDIF_CMD_RESP_CRC;
}
}
if (VOLTAGE_SWITCH == opcode)
{
/* CMD11 need switch voltage */
raw_cmd |= FSDIF_CMD_VOLT_SWITCH;
}
if (input_data)
{
raw_cmd |= FSDIF_CMD_DAT_EXP;
if (input_data->flags & DATA_DIR_WRITE)
{
raw_cmd |= FSDIF_CMD_DAT_WRITE;
}
}
raw_cmd |= FSDIF_CMD_START;
return raw_cmd;
}
void sdif_prepare_data_transfer(FSdifMsgDataStartData *msg_data, struct rt_mmcsd_req *req)
{
struct rt_mmcsd_cmd *input_cmd = req->cmd;
struct rt_mmcsd_data *input_data = req->data;
rt_memset(msg_data, 0U, sizeof(*msg_data));
msg_data->cmd_arg = input_cmd->arg;
msg_data->raw_cmd = sdif_prepare_raw_command(req);
if ((input_cmd->cmd_code == WRITE_BLOCK) ||
(input_cmd->cmd_code == WRITE_MULTIPLE_BLOCK))
{
msg_data->data_flags = FSDIF_MMC_DATA_WRITE;
}
else
{
msg_data->data_flags = FSDIF_MMC_DATA_READ;
}
msg_data->adtc_type = FSDIF_BLOCK_RW_ADTC;
msg_data->adma_addr = 0U; /* we do not know the descriptor addr here */
msg_data->mrq_data_blksz = input_data->blksize;
msg_data->mrq_data_blocks = input_data->blks;
return;
}
static uint32_t sdif_prepare_sd_command_flags(struct rt_mmcsd_req *req)
{
struct rt_mmcsd_cmd *input_cmd = req->cmd;
uint32_t opcode = input_cmd->cmd_code;
uint32_t argument = input_cmd->arg;
uint32_t flags = 0U;
switch(opcode)
{
case GO_IDLE_STATE: /* MMC_GO_IDLE_STATE 0 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_NONE | FSDIF_MMC_CMD_BC;
break;
case SEND_EXT_CSD: /* SD_SEND_IF_COND 8 */
flags |= FSDIF_MMC_RSP_SPI_R7 | FSDIF_MMC_RSP_R7 | FSDIF_MMC_CMD_BCR;
break;
case SD_APP_OP_COND: /* SD_APP_OP_COND 41 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R3 | FSDIF_MMC_CMD_BCR;
break;
case VOLTAGE_SWITCH: /* SD_SWITCH_VOLTAGE 11 */
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case ALL_SEND_CID: /* MMC_ALL_SEND_CID 2 */
flags |= FSDIF_MMC_RSP_R2 | FSDIF_MMC_CMD_AC;
break;
case SET_RELATIVE_ADDR: /* SD_SEND_RELATIVE_ADDR 3 */
flags |= FSDIF_MMC_RSP_R6 | FSDIF_MMC_CMD_BCR;
break;
case SEND_CSD: /* MMC_SEND_CSD 9 */
flags |= FSDIF_MMC_RSP_R2 | FSDIF_MMC_CMD_AC;
break;
case SELECT_CARD: /* MMC_SELECT_CARD 7 */
if (argument)
{
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
}
else
{
flags |= FSDIF_MMC_RSP_NONE | FSDIF_MMC_CMD_AC;
}
break;
case APP_CMD: /* MMC_APP_CMD 55 */
if (argument)
{
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
}
else
{
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_BCR;
}
break;
case SD_APP_SEND_SCR: /* SD_APP_SEND_SCR 51 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case SD_APP_SET_BUS_WIDTH: /* SD_APP_SET_BUS_WIDTH 6 */
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case SEND_STATUS: /* SD_APP_SD_STATUS 13 */
flags |= FSDIF_MMC_RSP_SPI_R2 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case SET_BLOCKLEN : /* MMC_SET_BLOCKLEN 16 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case SET_BLOCK_COUNT: /* MMC_SET_BLOCK_COUNT 23 */
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case WRITE_BLOCK: /* MMC_WRITE_BLOCK 24 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case WRITE_MULTIPLE_BLOCK: /* MMC_WRITE_MULTIPLE_BLOCK 25 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case READ_SINGLE_BLOCK: /* MMC_READ_SINGLE_BLOCK 17 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case READ_MULTIPLE_BLOCK: /* MMC_READ_MULTIPLE_BLOCK 18 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
default:
LOG_E("unhandled command-%d !!!", opcode);
break;
}
return flags;
}
static uint32_t sdif_prepar_emmc_command_flags(struct rt_mmcsd_req *req)
{
struct rt_mmcsd_cmd *input_cmd = req->cmd;
uint32_t opcode = input_cmd->cmd_code;
uint32_t argument = input_cmd->arg;
uint32_t flags = 0U;
switch(opcode)
{
case GO_IDLE_STATE: /* MMC_GO_IDLE_STATE 0 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_NONE | FSDIF_MMC_CMD_BC;
break;
case SEND_OP_COND: /* MMC_SEND_OP_COND 1 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R3 | FSDIF_MMC_CMD_BCR;
break;
case ALL_SEND_CID: /* MMC_ALL_SEND_CID 2 */
flags |= FSDIF_MMC_RSP_R2 | FSDIF_MMC_CMD_AC;
break;
case SET_RELATIVE_ADDR: /* MMC_SET_RELATIVE_ADDR 3 */
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case SEND_CSD: /* MMC_SEND_CSD 9 */
flags |= FSDIF_MMC_RSP_R2 | FSDIF_MMC_CMD_AC;
break;
case SELECT_CARD: /* MMC_SELECT_CARD 7 */
if (argument)
{
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
}
else
{
flags |= FSDIF_MMC_RSP_NONE | FSDIF_MMC_CMD_AC;
}
break;
case SEND_EXT_CSD: /* MMC_SEND_EXT_CSD 8 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case SWITCH: /* MMC_SWITCH 6 */
flags |= FSDIF_MMC_CMD_AC | FSDIF_MMC_RSP_SPI_R1B | FSDIF_MMC_RSP_R1B;
break;
case SEND_STATUS: /* MMC_SEND_STATUS 13 */
flags |= FSDIF_MMC_RSP_SPI_R2 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case SET_BLOCKLEN: /* MMC_SET_BLOCKLEN 16 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case SET_BLOCK_COUNT: /* MMC_SET_BLOCK_COUNT 23 */
flags |= FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_AC;
break;
case WRITE_BLOCK: /* MMC_WRITE_BLOCK 24 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case WRITE_MULTIPLE_BLOCK: /* MMC_WRITE_MULTIPLE_BLOCK 25 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case READ_SINGLE_BLOCK: /* MMC_READ_SINGLE_BLOCK 17 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
case READ_MULTIPLE_BLOCK: /* MMC_READ_MULTIPLE_BLOCK 18 */
flags |= FSDIF_MMC_RSP_SPI_R1 | FSDIF_MMC_RSP_R1 | FSDIF_MMC_CMD_ADTC;
break;
default:
LOG_E("unhandled command-%d !!!", opcode);
break;
}
return flags;
}
void sdif_prepare_command_trasnfer(FSdifMsgDataStartCmd *msg_cmd, struct rt_mmcsd_req *req, rt_uint32_t type)
{
struct rt_mmcsd_cmd *input_cmd = req->cmd;
rt_memset(msg_cmd, 0U, sizeof(*msg_cmd));
msg_cmd->opcode = input_cmd->cmd_code;
msg_cmd->cmd_arg = input_cmd->arg;
msg_cmd->raw_cmd = sdif_prepare_raw_command(req);
if (type == SDIF_CARD_TYPE_MICRO_SD)
{
msg_cmd->flags = sdif_prepare_sd_command_flags(req);
}
else if (type == SDIF_CARD_TYPE_EMMC)
{
msg_cmd->flags = sdif_prepar_emmc_command_flags(req);
}
return;
}
static void sdif_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdifMsgCtrl *sdif = &host_info->sdif;
FSdifMsgCommand *req_cmd = &host_info->req_cmd;
FSdifMsgData *req_data = &host_info->req_data;
FSdifMsgRequest *request = &host_info->req;
rt_err_t err = sdif_pre_request(host, req);
if (err != RT_EOK)
{
if (err != RT_EEMPTY)
{
LOG_E("sdif_pre_request fail.");
}
return;
}
rt_memset(request, 0U, sizeof(*request));
if (req->data)
{
rt_memset(req_data, 0U, sizeof(*req_data));
req_data->buf = (void *)(req->data->buf);
req_data->buf_dma = (uintptr)req_data->buf + PV_OFFSET;
request->data = req_data;
sdif_prepare_data_transfer(&(req_data->datainfo), req);
err = FSdifMsgSetupDMADescriptor(sdif, req_data);
if (FSDIF_SUCCESS != err)
{
LOG_E("SDIF setup DMA failed, err = 0x%x", err);
return;
}
}
rt_memset(req_cmd, 0, sizeof(*req_cmd));
request->command = req_cmd;
sdif_prepare_command_trasnfer(&(req_cmd->cmdinfo), req, host_info->sd_type);
req->cmd->err = sdif_do_transfer(host, request, req->cmd->busy_timeout);
if (resp_type(req->cmd) & RESP_MASK)
{
if (resp_type(req->cmd) == RESP_R2)
{
req->cmd->resp[3] = req_cmd->response[3];
req->cmd->resp[2] = req_cmd->response[2];
req->cmd->resp[1] = req_cmd->response[1];
req->cmd->resp[0] = req_cmd->response[0];
}
else
{
req->cmd->resp[0] = req_cmd->response[0];
}
}
mmcsd_req_complete(host);
}
static void sdif_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
FError ret = FT_SUCCESS;
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdifMsgCtrl *sdif = &host_info->sdif;
FSdifMsgDataSetIos target_ios;
/* ClockData set */
if (0 != io_cfg->clock)
{
target_ios.ios_clock = io_cfg->clock;
}
/* Timing set */
if (0 != io_cfg->timing)
{
if (host_info->sd_type == SDIF_CARD_TYPE_MICRO_SD)
{
if (io_cfg->signal_voltage == MMCSD_SIGNAL_VOLTAGE_330)
{
if (target_ios.ios_clock == FSDIF_CLK_SPEED_400KHZ)
{
target_ios.ios_timing = FSDIF_MMC_TIMING_LEGACY;
}
else
{
target_ios.ios_timing = FSDIF_MMC_TIMING_SD_HS;
}
}
else
{
switch (io_cfg->timing)
{
case MMCSD_TIMING_UHS_SDR12:
target_ios.ios_timing = FSDIF_MMC_TIMING_UHS_SDR12;
break;
case MMCSD_TIMING_UHS_SDR25:
target_ios.ios_timing = FSDIF_MMC_TIMING_UHS_SDR25;
break;
case MMCSD_TIMING_UHS_SDR50:
target_ios.ios_timing = FSDIF_MMC_TIMING_UHS_SDR50;
break;
case MMCSD_TIMING_UHS_SDR104:
target_ios.ios_timing = FSDIF_MMC_TIMING_UHS_SDR104;
break;
case MMCSD_TIMING_UHS_DDR50:
target_ios.ios_timing = FSDIF_MMC_TIMING_UHS_DDR50;
break;
default:
break;
}
}
}
else if (host_info->sd_type == SDIF_CARD_TYPE_EMMC)
{
switch (io_cfg->timing)
{
case MMCSD_TIMING_LEGACY:
target_ios.ios_timing = FSDIF_MMC_TIMING_LEGACY;
break;
case MMCSD_TIMING_MMC_HS:
target_ios.ios_timing = FSDIF_MMC_TIMING_MMC_HS;
break;
case MMCSD_TIMING_MMC_HS200:
target_ios.ios_timing = FSDIF_MMC_TIMING_MMC_HS200;
break;
case MMCSD_TIMING_MMC_HS400:
case MMCSD_TIMING_MMC_HS400_ENH_DS:
target_ios.ios_timing = FSDIF_MMC_TIMING_MMC_HS400;
break;
default:
break;
}
}
}
/* dataBusWidth set */
switch (io_cfg->bus_width)
{
case MMCSD_BUS_WIDTH_1:
target_ios.ios_bus_width = FSDIF_MMC_BUS_WIDTH_1;
break;
case MMCSD_BUS_WIDTH_4:
target_ios.ios_bus_width = FSDIF_MMC_BUS_WIDTH_4;
break;
case MMCSD_BUS_WIDTH_8:
target_ios.ios_bus_width = FSDIF_MMC_BUS_WIDTH_8;
break;
default:
LOG_E("Invalid bus width %d", io_cfg->bus_width);
break;
}
ret = FSdifMsgSetIos(sdif, &target_ios);
if (FSDIF_SUCCESS != ret)
{
LOG_E("Set card bus width failed.");
}
}
static rt_int32_t sdif_card_status(struct rt_mmcsd_host *host)
{
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdifMsgCtrl *sdif = &host_info->sdif;
return FSdifMsgCheckifCardExists(sdif) ? 1 : 0;
}
static const struct rt_mmcsd_host_ops ops =
{
.request = sdif_send_request,
.set_iocfg = sdif_set_iocfg,
.get_card_status = sdif_card_status,
.enable_sdio_irq = RT_NULL,
.execute_tuning = RT_NULL,
};
static void sdif_ctrl_setup_interrupt(struct rt_mmcsd_host *host)
{
sdif_info_t *host_info = (sdif_info_t *)host->private_data;
FSdifMsgCtrl *sdif = &(host_info->sdif);
FSdifMsgConfig *config_p = &sdif->config;
rt_uint32_t cpu_id = rt_hw_cpu_id();
rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id);
rt_hw_interrupt_set_priority(config_p->irq_num, 0xc);
/* register intr callback */
rt_hw_interrupt_install(config_p->irq_num,
FSdifMsgInterruptHandler,
sdif,
NULL);
/* enable irq */
rt_hw_interrupt_umask(config_p->irq_num);
return;
}
void sdif_msg_prepare_init_data(FSdifMsgDataInit *msg_data_init, rt_uint32_t type)
{
rt_memset(msg_data_init, 0U, sizeof(*msg_data_init));
if (type == SDIF_CARD_TYPE_MICRO_SD)
{
msg_data_init->caps = FSDIF_MMC_CAP_4_BIT_DATA | FSDIF_MMC_CAP_SD_HIGHSPEED |
FSDIF_MMC_CAP_UHS | FSDIF_MMC_CAP_CMD23;
}
else if (type == SDIF_CARD_TYPE_EMMC)
{
msg_data_init->caps = FSDIF_MMC_CAP_4_BIT_DATA | FSDIF_MMC_CAP_8_BIT_DATA |
FSDIF_MMC_CAP_MMC_HIGHSPEED | FSDIF_MMC_CAP_NONREMOVABLE |
FSDIF_MMC_CAP_1_8V_DDR | FSDIF_MMC_CAP_CMD23 | FSDIF_MMC_CAP_HW_RESET;
}
msg_data_init->clk_rate = FSDIF_CLK_FREQ_HZ; /*1.2GHz*/
}
static rt_err_t sdif_prepare_init_ios(FSdifMsgCtrl *const instance)
{
FSdifMsgDataSetIos target_ios;
target_ios.ios_clock = 0U;
target_ios.ios_timing = FSDIF_MMC_TIMING_LEGACY;
target_ios.ios_bus_width = FSDIF_MMC_BUS_WIDTH_1;
target_ios.ios_power_mode = FSDIF_MMC_POWER_UP;
if (FSDIF_SUCCESS != FSdifMsgSetIos(instance, &target_ios))
{
LOG_E("Set init IOS failed.");
return -RT_ERROR;
}
instance->cur_ios.ios_power_mode = FSDIF_MMC_POWER_ON;
return RT_EOK;
}
static rt_err_t sdif_prepare_init_volt(FSdifMsgCtrl *const instance, rt_uint32_t type)
{
FSdifMsgDataSwitchVolt target_volt;
if (type == SDIF_CARD_TYPE_MICRO_SD)
{
target_volt.signal_voltage = FSDIF_MMC_SIGNAL_VOLTAGE_330;
}
else if (type == SDIF_CARD_TYPE_EMMC)
{
target_volt.signal_voltage = FSDIF_MMC_SIGNAL_VOLTAGE_180;
}
if (FSDIF_SUCCESS != FSdifMsgSetVoltage(instance, &target_volt))
{
LOG_E("Set init VOLT failed.");
return -RT_ERROR;
}
return RT_EOK;
}
static rt_err_t sdif_host_init(rt_uint32_t id, rt_uint32_t type)
{
struct rt_mmcsd_host *host = RT_NULL;
sdif_info_t *host_info = RT_NULL;
const FSdifMsgConfig *default_sdif_config = RT_NULL;
FSdifMsgConfig sdif_config;
rt_err_t result = RT_EOK;
host = mmcsd_alloc_host();
if (!host)
{
LOG_E("Alloc host failed");
result = RT_ENOMEM;
goto err_free;
}
host_info = rt_malloc(sizeof(sdif_info_t));
if (!host_info)
{
LOG_E("Malloc host_info failed");
result = RT_ENOMEM;
goto err_free;
}
rt_memset(host_info, 0, sizeof(*host_info));
result = rt_event_init(&host_info->event, "sdif_event", RT_IPC_FLAG_FIFO);
RT_ASSERT(RT_EOK == result);
host_info->aligned_buffer_size = SDIF_DMA_BLK_SZ * SDIF_MAX_BLK_TRANS;
host_info->aligned_buffer = rt_malloc_align(host_info->aligned_buffer_size,
SDIF_DMA_ALIGN);
if (!host_info->aligned_buffer)
{
LOG_E("Malloc aligned buffer failed");
result = RT_ENOMEM;
goto err_free;
}
host_info->aligned_buffer_dma = (uintptr_t)host_info->aligned_buffer + PV_OFFSET;
rt_memset(host_info->aligned_buffer, 0, host_info->aligned_buffer_size);
host_info->rw_desc_num = (SDIF_DMA_BLK_SZ * SDIF_MAX_BLK_TRANS) / FSDIF_IDMAC_MAX_BUF_SIZE + 1;
host_info->rw_desc = rt_malloc_align(host_info->rw_desc_num * sizeof(FSdifMsgIDmaDesc),
SDIF_DMA_ALIGN);
if (!host_info->rw_desc)
{
LOG_E("Malloc rw_desc failed");
result = RT_ENOMEM;
goto err_free;
}
host_info->rw_desc_dma = (uintptr_t)host_info->rw_desc + PV_OFFSET;
rt_memset(host_info->rw_desc, 0, host_info->rw_desc_num * sizeof(FSdifMsgIDmaDesc));
/* host data init */
host->ops = &ops;
host->freq_min = FSDIF_CLK_SPEED_400KHZ;
if (type == SDIF_CARD_TYPE_MICRO_SD)
{
host->freq_max = FSDIF_CLK_SPEED_50_MHZ;
}
else
{
host->freq_max = FSDIF_CLK_SPEED_52_MHZ;
}
host->valid_ocr = VDD_32_33 | VDD_33_34; /* voltage 3.3v */
host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4;
host->max_seg_size = SDIF_DMA_BLK_SZ; /* used in block_dev.c */
host->max_dma_segs = SDIF_MAX_BLK_TRANS; /* physical segment number */
host->max_blk_size = SDIF_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */
host->max_blk_count = SDIF_MAX_BLK_TRANS;
host->private_data = host_info;
host->name[0] = 's';
host->name[1] = 'd';
host->name[2] = '0' + id;
host->name[3] = '\0';
mmc_host[id] = host;
default_sdif_config = FSdifMsgLookupConfig(id);
RT_ASSERT(default_sdif_config != RT_NULL);
sdif_config = *default_sdif_config;
#ifdef RT_USING_SMART
sdif_config.dev_msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.msg.shmem, 0x1000);
sdif_config.dev_msg.regfile = (uintptr)rt_ioremap((void *)input_cfg.msg.regfile, 0x1000);
#endif
if (type == SDIF_CARD_TYPE_MICRO_SD)
{
sdif_config.non_removable = FALSE; /* TF card is removable on board */
}
else if (type == SDIF_CARD_TYPE_EMMC)
{
sdif_config.non_removable = TRUE; /* eMMC is unremovable on board */
}
sdif_msg_prepare_init_data(&(sdif_config.init), type);
FSdifMsgCtrl *sdif = &(host_info->sdif);
if (FSDIF_SUCCESS != FSdifMsgCfgInitialize(sdif, &sdif_config))
{
LOG_E("Sdif v2 ctrl init failed.");
result = RT_EIO;
goto err_free;
}
if (FSDIF_SUCCESS != FSdifMsgSetIDMAList(sdif,
host_info->rw_desc,
host_info->rw_desc_dma,
host_info->rw_desc_num))
{
LOG_E("SDIF controller setup DMA failed.");
result = RT_EIO;
goto err_free;
}
host_info->sd_type = type;
LOG_I("Init sdif-%d as %d", id, type);
/* setup interrupt */
sdif_ctrl_setup_interrupt(host);
FSdifMsgRegisterEvtHandler(sdif, FSDIF_EVT_CARD_DETECTED, sdif_card_detect_callback, host);
FSdifMsgRegisterEvtHandler(sdif, FSDIF_EVT_ERR_OCCURE, sdif_error_occur_callback, host);
FSdifMsgRegisterEvtHandler(sdif, FSDIF_EVT_CMD_DONE, sdif_command_done_callback, host);
FSdifMsgRegisterEvtHandler(sdif, FSDIF_EVT_DATA_DONE, sdif_data_done_callback, host);
if (sdif_prepare_init_ios(sdif) == RT_EOK)
{
result = sdif_prepare_init_volt(sdif, type);
}
return result;
err_free:
if (host)
{
mmcsd_free_host(host);
}
if (host_info)
{
if (host_info->aligned_buffer)
{
rt_free(host_info->aligned_buffer);
host_info->aligned_buffer = RT_NULL;
host_info->aligned_buffer_size = 0U;
}
if (host_info->rw_desc)
{
rt_free(host_info->rw_desc);
host_info->rw_desc = RT_NULL;
host_info->rw_desc_num = 0;
}
rt_free(host_info);
}
return result;
}
int rt_hw_sdif_init(void)
{
int status = RT_EOK;
rt_uint32_t sd_type;
FSdifTimingInit();
#ifdef USING_SDIF0
#if defined(USE_SDIF0_TF)
sd_type = SDIF_CARD_TYPE_MICRO_SD;
#elif defined(USE_SDIF0_EMMC)
sd_type = SDIF_CARD_TYPE_EMMC;
#endif
status = sdif_host_init(FSDIF0_ID, sd_type);
if (status != RT_EOK)
{
LOG_E("SDIF0 init failed, status = %d", status);
return status;
}
#endif
return status;
}
INIT_DEVICE_EXPORT(rt_hw_sdif_init);
#endif

23
bsp/phytium/libraries/drivers/drv_sdif_msg.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023/7/11 liqiaozhong init SD card and mount file system
*
*/
#ifndef __DRV_SDIF_MSG_H__
#define __DRV_SDIF_MSG_H__
/***************************** Include Files *********************************/
#include <rtthread.h>
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*******************************Api Functions*********************************/
#endif

6
bsp/phytium/libraries/drivers/drv_spi.c
View File

@@ -138,7 +138,7 @@ static rt_err_t spim_configure(struct rt_spi_device *device,
{
return -RT_ERROR;
}
FSpimRegisterIntrruptHandler(&user_data_cfg->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
FSpimRegisterInterruptHandler(&user_data_cfg->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
return ret;
}
@@ -229,7 +229,7 @@ static int spi_init(phytium_spi_bus *spi_bus)
{
return -RT_ERROR;
}
FSpimRegisterIntrruptHandler(&spi_bus->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
FSpimRegisterInterruptHandler(&spi_bus->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
rt_spi_bus_register(&spi_bus->spi_bus, spi_bus->name, &spim_ops);
RT_ASSERT((struct rt_spi_device *)rt_device_find(spi_bus->name));
@@ -252,7 +252,7 @@ static int spi_init(phytium_spi_bus *spi_bus)
int rt_hw_spi_init(void)
{
/* event creat */
/* event create */
if (RT_EOK != rt_event_init(&rx_done_event, "rx_done_event", RT_IPC_FLAG_FIFO))
{
rt_kprintf("Create event failed.\n");

202
bsp/phytium/libraries/drivers/drv_spi_msg.c Normal file
View File

@@ -0,0 +1,202 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-10 liqiaozhong first commit
* 2023-03-08 liqiaozhong support 4 spis and qspi working together
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include <rtdevice.h>
#include "interrupt.h"
#define LOG_TAG "spi_msg_drv"
#include "drv_log.h"
#include <string.h>
#include "fparameters.h"
#include "fcpu_info.h"
#include "fkernel.h"
#include "ftypes.h"
#ifdef RT_USING_SMART
#include <ioremap.h>
#endif
#include <dfs_file.h>
#include "fspim_msg.h"
#include "fspim_msg_hw.h" /* include low-level header file for internal probe */
#include "drv_spi_msg.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/************************** Variable Definitions *****************************/
typedef struct
{
struct rt_spi_bus spi_bus;
FSpiMsgCtrl spim_msg_instance;
const char *name;
} phytium_spi_bus;
/***************** Macros (Inline Functions) Definitions *********************/
#define EVENT_RX_DONE (1 << 1)
/*******************************Api Functions*********************************/
static rt_err_t spim_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
static rt_ssize_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
static const struct rt_spi_ops spim_ops =
{
.configure = spim_configure,
.xfer = spim_xfer
};
static rt_err_t spim_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
FError ret = 0;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
phytium_spi_bus *user_data_cfg = device->parent.user_data;
FSpiMsgConfig *set_input_cfg = &user_data_cfg->spim_msg_instance.spi_msg_config;
/* set fspim device according to configuration */
/* Modifying the CPOL and CPHA parameters requires support from relevant documentation*/
if (configuration->data_width == 8)
{
set_input_cfg->n_bytes = FSPIM_1_BYTE;
}
/* send spi_cfg to RT-Thread sys */
ret = FSpiMsgCfgInitialize(&user_data_cfg->spim_msg_instance, set_input_cfg);
if (0 != ret)
{
return -RT_ERROR;
}
return ret;
}
static rt_ssize_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
rt_ssize_t message_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
/* recv spi_cfg from RT-Thread sys */
phytium_spi_bus *user_data_xfer = device->parent.user_data;
FSpiMsgCtrl *xfer_spim_msg_instance = &user_data_xfer->spim_msg_instance;
FError tx_rx_result = 0;
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
if (message->cs_take)
{
FSpiMsgSetChipSelection(xfer_spim_msg_instance, 1);
}
if (message_length > 0)
{
if (send_buf == RT_NULL && recv_buf != RT_NULL)
{
/* receive message */
tx_rx_result = FSpiMsgTransfer(xfer_spim_msg_instance, RT_NULL, recv_buf, message_length);
}
else if (send_buf != RT_NULL && recv_buf == RT_NULL)
{
/* send message */
tx_rx_result = FSpiMsgTransfer(xfer_spim_msg_instance, send_buf, RT_NULL, message_length);
}
else if (send_buf != RT_NULL && recv_buf != RT_NULL)
{
/* send and recv */
tx_rx_result = FSpiMsgTransfer(xfer_spim_msg_instance, send_buf, recv_buf, message_length);
}
}
if (0 != tx_rx_result)
{
rt_kprintf("FSpimTransferByInterrupt() fail!!!");
message_length = 0;
}
if (message->cs_release)
{
FSpiMsgSetChipSelection(xfer_spim_msg_instance, 0);
}
return message_length;
}
static void FSpiMsgIntrInit(FSpiMsgCtrl *ctrl, const FSpiMsgConfig *config)
{
rt_uint32_t cpu_id = rt_hw_cpu_id();
rt_hw_interrupt_set_target_cpus(config->irq_num, cpu_id);
rt_hw_interrupt_set_priority(config->irq_num, config->irq_priority);
ctrl->cmd_completion = CMD_MSG_NOT_COMPLETION;
rt_hw_interrupt_install(config->irq_num, FSpiMsgInterruptHandler, ctrl, NULL);
rt_hw_interrupt_umask(config->irq_num);
}
static int spi_init(phytium_spi_bus *spi_bus)
{
FError ret = 0;
FSpiMsgConfig input_cfg = *FSpiMsgLookupConfig(spi_bus->spim_msg_instance.spi_msg_config.instance_id);
#ifdef RT_USING_SMART
input_cfg.spi_msg.regfile = (uintptr)rt_ioremap((void *)input_cfg.spi_msg.regfile, 0x1000);
input_cfg.spi_msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.spi_msg.shmem, 0x1000);
#endif
FSpiMsgIntrInit(&spi_bus->spim_msg_instance, &input_cfg);
/* send spi_cfg to RT-Thread sys */
ret = FSpiMsgCfgInitialize(&spi_bus->spim_msg_instance, &input_cfg);
if (0 != ret)
{
return -RT_ERROR;
}
rt_spi_bus_register(&spi_bus->spi_bus, spi_bus->name, &spim_ops);
RT_ASSERT((struct rt_spi_device *)rt_device_find(spi_bus->name));
return 0;
}
#ifdef RT_USING_SPIM0_MSG
static phytium_spi_bus spi0_bus;
#endif
#ifdef RT_USING_SPIM1_MSG
static phytium_spi_bus spi1_bus;
#endif
#ifdef RT_USING_SPIM2_MSG
static phytium_spi_bus spi2_bus;
#endif
#ifdef RT_USING_SPIM3_MSG
static phytium_spi_bus spi3_bus;
#endif
int rt_hw_spi_init(void)
{
#ifdef RT_USING_SPIM0_MSG
spi0_bus.name = "SPI0";
spi0_bus.spim_msg_instance.spi_msg_config.instance_id = FSPI0_MSG_ID;
FIOPadSetSpimMux(FSPI0_MSG_ID);
spi_init(&spi0_bus);
#endif
#ifdef RT_USING_SPIM1_MSG
spi1_bus.name = "SPI1";
spi1_bus.spim_msg_instance.spi_msg_config.instance_id = FSPI1_MSG_ID;
FIOPadSetSpimMux(FSPI1_MSG_ID);
spi_init(&spi1_bus);
#endif
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_spi_init);

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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-11-10 liqiaozhong first commit
* 2023-03-08 liqiaozhong support 4 spis and qspi working together
*/
#ifndef __DRV_SPI_MSG_H__
#define __DRV_SPI_MSG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C"
{
#endif
int rt_hw_spi_init(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2025-05-23 liyilun first commit
*/
#include "rtconfig.h"
#include <rtdevice.h>
#include "board.h"
#include <mmu.h>
#include "drv_usart_msg.h"
#include "interrupt.h"
#include "fio_mux.h"
#include "fparameters.h"
#ifdef RT_USING_SMART
#include <ioremap.h>
#endif
#define RING_BUFFER_WAIT_TIMEOUT 10000
#define RING_BUFFER_SIZE 64
struct rt_ringbuffer *recv_ringbuffer = NULL;
rt_inline enum rt_ringbuffer_state rt_ringbuffer_status(struct rt_ringbuffer *rb)
{
if (rb->read_index == rb->write_index)
{
if (rb->read_mirror == rb->write_mirror)
return RT_RINGBUFFER_EMPTY;
else
return RT_RINGBUFFER_FULL;
}
return RT_RINGBUFFER_HALFFULL;
}
static void Ft_Os_Uart_Msg_Callback(void *Args, u32 Event, u32 EventData);
static void rt_hw_uart_msg_isr(int irqno, void *param)
{
FUartMsgInterruptHandler(irqno, param);
}
static rt_err_t uart_msg_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct drv_usart_msg *uart_msg = RT_NULL;
FUartMsg *uart_msg_hw = RT_NULL;
FUartMsgConfig config;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart_msg = rt_container_of(serial, struct drv_usart_msg, serial);
uart_msg_hw = uart_msg->handle;
config = *(const FUartMsgConfig *)FUartMsgLookupConfig(uart_msg->config.uart_instance);
#ifdef RT_USING_SMART
config.msg.regfile = (uintptr)rt_ioremap((void *)config.msg.regfile, 0x1000);
config.msg.shmem = (uintptr)rt_ioremap((void *)config.msg.shmem, 0x1000);
#endif
FIOPadSetUartMux(uart_msg->config.uart_instance);
RT_ASSERT(FUartMsgCfgInitialize(uart_msg_hw, &config) == FT_SUCCESS);
FUartMsgSetStartUp(uart_msg_hw);
FUartMsgSetHandler(uart_msg_hw, Ft_Os_Uart_Msg_Callback, serial);
//<! 打开接收中断
rt_hw_interrupt_set_priority(uart_msg_hw->config.irq_num, uart_msg->config.isr_priority);
rt_hw_interrupt_install(uart_msg_hw->config.irq_num, rt_hw_uart_msg_isr, uart_msg_hw, "uart");
rt_hw_interrupt_umask(uart_msg_hw->config.irq_num);
FUartMsgEnableInterrups(uart_msg_hw);
return RT_EOK;
}
static rt_err_t uart_msg_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct drv_usart_msg *uart_msg = RT_NULL;
FUartMsg *uart_msg_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_msg = rt_container_of(serial, struct drv_usart_msg, serial);
uart_msg_ptr = uart_msg->handle;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
rt_hw_interrupt_mask(uart_msg_ptr->config.irq_num);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
rt_hw_interrupt_umask(uart_msg_ptr->config.irq_num);
break;
}
return RT_EOK;
}
static int uart_msg_putc(struct rt_serial_device *serial, char c)
{
struct drv_usart_msg *uart_msg = RT_NULL;
FUartMsg *uart_msg_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_msg = rt_container_of(serial, struct drv_usart_msg, serial);
uart_msg_ptr = uart_msg->handle;
while(-1 == FUartMsgTxChar(&(uart_msg_ptr->config.msg), (u8)c))
{
}
return 1;
}
void FUartMsgRecvBufferNoBlocking(FUartMsg *uart_p)
{
u8 data[16] = {0};
rt_size_t write_length = 0;
u32 received_count = 0;
while (!FUartMsgRxRingBufferIsEmpty(uart_p->config.msg.regfile))
{
received_count += FUartMsgRxChars(&(uart_p->config.msg), data, 16);
}
if(received_count > 0)
{
write_length = rt_ringbuffer_put(recv_ringbuffer, data, received_count);
RT_ASSERT(write_length == received_count);
}
}
static int uart_msg_getc(struct rt_serial_device *serial)
{
int ch;
struct drv_usart_msg *uart_msg = RT_NULL;
FUartMsg *uart_msg_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart_msg = rt_container_of(serial, struct drv_usart_msg, serial);
uart_msg_ptr = uart_msg->handle;
if(RT_RINGBUFFER_EMPTY == rt_ringbuffer_status(recv_ringbuffer))
{
FUartMsgRecvBufferNoBlocking(uart_msg_ptr);
}
if(0 == rt_ringbuffer_getchar(recv_ringbuffer, (rt_uint8_t *)&ch))
{
return -1;
}
if (ch == 0xffff)
{
ch = -1;
}
else
{
ch &= 0xff;
}
return ch;
}
static void Ft_Os_Uart_Msg_Callback(void *Args, u32 Event, u32 EventData)
{
struct rt_serial_device *serial = (struct rt_serial_device *)Args;
if(FUART_EVENT_RECV_DATA == Event)
{
if(serial->serial_rx)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
}
else if(FUART_EVENT_SENT_DATA == Event)
{
}
else
{
}
}
static const struct rt_uart_ops _uart_ops =
{
uart_msg_configure,
uart_msg_control,
uart_msg_putc,
uart_msg_getc,
NULL
};
static int uart_msg_init(struct drv_usart_msg *uart_msg_dev)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
config.bufsz = RT_SERIAL_RB_BUFSZ;
uart_msg_dev->serial.ops = &_uart_ops;
uart_msg_dev->serial.config = config;
uart_msg_dev->config.isr_priority = 0xd0;
uart_msg_dev->config.isr_event_mask = RTOS_UART_MSG_RX_ISR_MASK | RTOS_UART_MSG_TX_ISR_MASK;
uart_msg_dev->config.uart_baudrate = BAUD_RATE_115200;
recv_ringbuffer = rt_ringbuffer_create(RING_BUFFER_SIZE);
RT_ASSERT(recv_ringbuffer != RT_NULL);
rt_hw_serial_register(&uart_msg_dev->serial, uart_msg_dev->name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart_msg_dev);
return 0;
}
#ifdef RT_USING_UART0_MSG
static FUartMsg Ft_Uart0_Msg;
static struct drv_usart_msg drv_uart0_msg;
#endif
#ifdef RT_USING_UART1_MSG
static FUartMsg Ft_Uart1_Msg;
static struct drv_usart_msg drv_uart1_msg;
#endif
#ifdef RT_USING_UART2_MSG
static FUartMsg Ft_Uart2_Msg;
static struct drv_usart_msg drv_uart2_msg;
#endif
int rt_hw_uart_init(void)
{
#ifdef RT_USING_UART0_MSG
drv_uart0_msg.name = "uart0";
drv_uart0_msg.handle = &Ft_Uart0_Msg;
drv_uart0_msg.config.uart_instance = FUART0_MSG_ID;
uart_msg_init(&drv_uart0_msg);
#endif
#ifdef RT_USING_UART1_MSG
drv_uart1_msg.name = "uart1";
drv_uart1_msg.handle = &Ft_Uart1_Msg;
drv_uart1_msg.config.uart_instance = FUART1_MSG_ID;
uart_msg_init(&drv_uart1_msg);
#endif
#ifdef RT_USING_UART2_MSG
drv_uart2_msg.name = "uart2";
drv_uart2_msg.handle = &Ft_Uart2_Msg;
drv_uart2_msg.config.uart_instance = FUART2_MSG_ID;
uart_msg_init(&drv_uart2_msg);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);

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bsp/phytium/libraries/drivers/drv_usart_msg.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2025-05-23 liyilun first commit
*/
#ifndef __DRV_USART_MSG_H__
#define __DRV_USART_MSG_H__
#include <rtthread.h>
#include "rtdevice.h"
#include "fuart_msg.h"
#include "fuart_msg_hw.h"
#define RTOS_UART_MSG_RX_ISR_MASK 0x01
#define RTOS_UART_MSG_TX_ISR_MASK 0x02
typedef struct
{
u32 uart_instance; /* select uart global object */
u32 isr_priority; /* irq Priority */
u32 isr_event_mask; /* followed by RTOS_UART_ISR_XX */
u32 uart_baudrate;
} FtRtthreadUartMsgConfig;
struct drv_usart_msg
{
const char *name;
FUartMsg *handle;
FtRtthreadUartMsgConfig config;
struct rt_serial_device serial;
};
#endif // !

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bsp/phytium/libraries/drivers/drv_xmac_msg.c Normal file
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148
bsp/phytium/libraries/drivers/drv_xmac_msg.h Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2025-05-28 huangjin first commit
*/
#ifndef __DRV_XMAC_MSG_H__
#define __DRV_XMAC_MSG_H__
#include <rtthread.h>
#include <rtdevice.h>
#ifdef BSP_USING_ETH_MSG
#include <netif/ethernetif.h>
#include "fxmac_msg.h"
#include "fkernel.h"
#include "ferror_code.h"
#include "fassert.h"
#include "fxmac_msg_bdring.h"
#include "eth_ieee_reg.h"
#include "fcpu_info.h"
#include "fxmac_msg_phy.h"
#ifdef __cplusplus
extern "C" {
#endif
#define RTTHREAD_XMAC_MSG_INIT_ERROR FT_CODE_ERR(ErrModPort, 0, 0x1)
#define RTTHREAD_XMAC_MSG_PARAM_ERROR FT_CODE_ERR(ErrModPort, 0, 0x2)
#define RTTHREAD_XMAC_MSG_NO_VALID_SPACE FT_CODE_ERR(ErrModPort, 0, 0x3)
#define FXMAC_MSG_RX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
#define FXMAC_MSG_TX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/
#define FXMAC_MSG_RX_PBUFS_LENGTH 64
#define FXMAC_MSG_TX_PBUFS_LENGTH 64
#define FXMAC_MSG_MAX_HARDWARE_ADDRESS_LENGTH 6
#define XMAC_MSG_PHY_RESET_ENABLE 1
#define XMAC_MSG_PHY_RESET_DISABLE 0
/* configuration */
#define FXMAC_MSG_OS_CONFIG_JUMBO BIT(0)
#define FXMAC_MSG_OS_CONFIG_MULTICAST_ADDRESS_FILITER BIT(1) /* Allow multicast address filtering */
#define FXMAC_MSG_OS_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */
#define FXMAC_MSG_OS_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */
#define FXMAC_MSG_OS_CONFIG_RX_POLL_RECV BIT(4) /* select poll mode */
#define FXMAC_MSG_OS_CONFIG_UNICAST_ADDRESS_FILITER BIT(5) /* Allow unicast address filtering */
/* Phy */
#define FXMAC_MSG_PHY_SPEED_10M 10
#define FXMAC_MSG_PHY_SPEED_100M 100
#define FXMAC_MSG_PHY_SPEED_1000M 1000
#define FXMAC_MSG_PHY_HALF_DUPLEX 0
#define FXMAC_MSG_PHY_FULL_DUPLEX 1
#define MAX_FRAME_SIZE_JUMBO (FXMAC_MSG_MTU_JUMBO + FXMAC_MSG_HDR_SIZE + FXMAC_MSG_TRL_SIZE)
/* Byte alignment of BDs */
#define BD_ALIGNMENT (FXMAC_MSG_DMABD_MINIMUM_ALIGNMENT*2)
/* frame queue */
#define PQ_QUEUE_SIZE 4096
#define LINK_THREAD_STACK_LENGTH 0x20400
typedef struct
{
uintptr data[PQ_QUEUE_SIZE];
int head, tail, len;
} PqQueue;
typedef enum
{
FXMAC_MSG_OS_INTERFACE_SGMII = 0,
FXMAC_MSG_OS_INTERFACE_RMII,
FXMAC_MSG_OS_INTERFACE_RGMII,
FXMAC_MSG_OS_INTERFACE_LENGTH
} FXmacMsgRtThreadInterface;
typedef struct
{
u8 rx_bdspace[FXMAC_MSG_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 接收bd 缓冲区 */
u8 tx_bdspace[FXMAC_MSG_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 发送bd 缓冲区 */
uintptr rx_pbufs_storage[FXMAC_MSG_RX_PBUFS_LENGTH];
uintptr tx_pbufs_storage[FXMAC_MSG_TX_PBUFS_LENGTH];
} FXmacMsgNetifBuffer;
typedef struct
{
u32 instance_id;
FXmacMsgRtThreadInterface interface;
u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
u32 phy_speed; /* FXMAC_PHY_SPEED_XXX */
u32 phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */
} FXmacMsgOsControl;
typedef struct
{
struct eth_device parent; /* inherit from ethernet device */
FXmacMsgCtrl instance; /* Xmac controller */
FXmacMsgOsControl mac_config;
FXmacMsgNetifBuffer buffer; /* DMA buffer */
/* queue to store overflow packets */
PqQueue recv_q;
PqQueue send_q;
/* configuration */
u32 config;
u32 is_link_up;
rt_uint8_t hwaddr[FXMAC_MSG_MAX_HARDWARE_ADDRESS_LENGTH]; /* MAC address */
struct rt_thread _link_thread; /* link detect thread */
rt_uint8_t _link_thread_stack[LINK_THREAD_STACK_LENGTH];/* link detect thread stack*/
} FXmacMsgOs;
enum lwip_port_link_status
{
ETH_LINK_UNDEFINED = 0,
ETH_LINK_UP,
ETH_LINK_DOWN,
ETH_LINK_NEGOTIATING
};
#ifdef __cplusplus
}
#endif
#endif // !
#endif

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#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "auto_test.h"
#include "rtconfig.h"
#define MAX_TESTS 100
typedef int (*TestFunc)(void);
typedef struct {
const char* name;
TestFunc func;
rt_err_t passed;
} TestCase;
TestCase test_cases[MAX_TESTS];
int test_count = 0;
// 注册测试用例
void register_test(const char* name, TestFunc func) {
if (test_count < MAX_TESTS) {
test_cases[test_count].name = name;
test_cases[test_count].func = func;
test_cases[test_count].passed = 0;
test_count++;
} else {
rt_kprintf("Exceeded the maximum number of test cases(%d)\n", MAX_TESTS);
}
}
// 运行所有测试
void run_all_tests() {
int passed_count = 0;
rt_kprintf("Run tests...\n");
for (int i = 0; i < test_count; i++) {
rt_err_t result = test_cases[i].func();
test_cases[i].passed = result;
if (result == RT_EOK) {
rt_kprintf("[PASS] %s\n", test_cases[i].name);
passed_count++;
} else {
rt_kprintf("[FAIL] %s %d\n", test_cases[i].name, result);
}
}
#if defined(TARGET_ARMV8_AARCH64)
rt_kprintf("\n%s aarch64 test results: \n", BOARD_NAME);
#else
rt_kprintf("\n%s aarch32 test results: \n", BOARD_NAME);
#endif
rt_kprintf("PASS: %d / %d\n", passed_count, test_count);
if (passed_count < test_count)
{
rt_kprintf("[test_failure] example:\n");
for (int i = 0; i < test_count; i++) {
if (test_cases[i].passed != RT_EOK) {
rt_kprintf(" - %s\n", test_cases[i].name);
}
}
}
else
{
rt_kprintf("[test_success]\n");
}
rt_kprintf("[rtthread_test_end]\n");
}
int auto_test() {
#if defined BSP_USING_CAN
register_test("can_loopback_sample", can_loopback_sample);
#endif
#if defined BSP_USING_SPI
register_test("spi_sample", fspim_test_sample);
#endif
#if defined BSP_USING_GPIO
register_test("gpio_sample", gpio_toggle_sample);
#endif
#if defined BSP_USING_I2C
#if defined (PD2408_TEST_A_BOARD) || defined (PD2408_TEST_B_BOARD)
register_test("i2c_msg_sample", i2c_msg_sample);
#else
register_test("i2c_sample", i2c_sample);
#endif
#endif
#if defined BSP_USING_QSPI
#if !defined(TARGET_PD2408)
register_test("qspi_sample", qspi_sample);
#endif
#endif
// 运行测试
run_all_tests();
return 0;
}

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bsp/phytium/libraries/drivers_example/auto_test.h Normal file
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#include <rtthread.h>
#include <rtdevice.h>
#include "rtconfig.h"
#if defined BSP_USING_CAN
rt_err_t can_loopback_sample();
#endif
#if defined BSP_USING_GPIO
rt_err_t gpio_toggle_sample();
#endif
#if defined BSP_USING_I2C
rt_err_t i2c_sample();
#endif
#if defined BSP_USING_SPI
rt_err_t fspim_test_sample();
#endif
#if defined BSP_USING_QSPI
rt_err_t qspi_sample();
#endif

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bsp/phytium/libraries/drivers_example/can_loopback_sample.c Normal file
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#include "rtconfig.h"
#ifdef BSP_USING_CAN
#include <rtdevice.h>
#include "drv_can.h"
#define LOG_TAG "can_drv"
#include "drv_log.h"
#include "fcan.h"
#include "fio_mux.h"
#include "interrupt.h"
#include "fcpu_info.h"
/*can test example*/
static rt_device_t can0_dev; /* CAN device handle */
static rt_device_t can1_dev; /* CAN device handle */
static struct rt_semaphore can0_rx_sem;
static struct rt_semaphore can1_rx_sem;
static struct rt_can_msg rxmsg = {0};
static rt_err_t can0_rx_call(rt_device_t dev, rt_size_t size)
{
/* The CAN generates an interrupt after receiving data, calls this callback function, and then sends the received semaphore */
rt_sem_release(&can0_rx_sem);
return RT_EOK;
}
static void can0_rx_thread(void *parameter)
{
int i;
rt_err_t res = RT_EOK;
rt_device_set_rx_indicate(can0_dev, can0_rx_call);
while (1)
{
/* The hdr value is - 1, which means reading data directly from the uselist */
rxmsg.hdr_index = -1;
/* Blocking waiting to receive semaphore */
res = rt_sem_take(&can0_rx_sem, RT_WAITING_FOREVER);
RT_ASSERT(res == RT_EOK);
/* Read a frame of data from CAN */
rt_device_read(can0_dev, 0, &rxmsg, sizeof(rxmsg));
/* Print data ID and conten */
LOG_D("ID:%x\n", rxmsg.id);
LOG_D("DATA: ");
for (i = 0; i < 8; i++)
{
LOG_D("%2x ", rxmsg.data[i]);
}
LOG_D("\n");
}
}
static rt_err_t can1_rx_call(rt_device_t dev, rt_size_t size)
{
/* The CAN generates an interrupt after receiving data, calls this callback function, and then sends the received semaphore */
rt_sem_release(&can1_rx_sem);
return RT_EOK;
}
static void can1_rx_thread(void *parameter)
{
int i;
rt_err_t res = RT_EOK;
rt_device_set_rx_indicate(can1_dev, can1_rx_call);
while (1)
{
/* The hdr value is - 1, which means reading data directly from the uselist */
rxmsg.hdr_index = -1;
/* Blocking waiting to receive semaphore */
res = rt_sem_take(&can1_rx_sem, RT_WAITING_FOREVER);
RT_ASSERT(res == RT_EOK);
/* Read a frame of data from CAN */
rt_device_read(can1_dev, 0, &rxmsg, sizeof(rxmsg));
/* Print data ID and conten */
LOG_D("ID:%x\n", rxmsg.id);
LOG_D("DATA: ");
for (i = 0; i < 8; i++)
{
LOG_D("%2x ", rxmsg.data[i]);
}
LOG_D("\n");
}
}
rt_err_t can_loopback_sample()
{
struct rt_can_msg msg = {0};
rt_err_t res = RT_EOK;;
rt_thread_t thread;
/* Find CAN device */
can0_dev = rt_device_find("CAN0");
if (!can0_dev)
{
rt_kprintf("Find CAN0 failed.\n");
return -RT_ERROR;
}
/* Find CAN device */
can1_dev = rt_device_find("CAN1");
if (!can1_dev)
{
rt_kprintf("Find CAN1 failed.\n");
return -RT_ERROR;
}
/* Initialize CAN receive signal quantity */
res = rt_sem_init(&can0_rx_sem, "can0_rx_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(res == RT_EOK);
res = rt_sem_init(&can1_rx_sem, "can1_rx_sem", 0, RT_IPC_FLAG_FIFO);
RT_ASSERT(res == RT_EOK);
/* Open the CAN device in the way of interrupt reception and transmission */
res = rt_device_open(can0_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
rt_device_control(can0_dev, RT_CAN_CMD_SET_BAUD, CAN800kBaud);
RT_ASSERT(res == RT_EOK);
res = rt_device_open(can1_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
rt_device_control(can1_dev, RT_CAN_CMD_SET_BAUD, CAN800kBaud);
RT_ASSERT(res == RT_EOK);
/* Create data receiving thread */
thread = rt_thread_create("can0_rx", can0_rx_thread, RT_NULL, 4096, 10, 10);
if (thread != RT_NULL)
{
res = rt_thread_startup(thread);
RT_ASSERT(res == RT_EOK);
}
else
{
rt_kprintf("Create can0_rx thread failed.\n");
}
thread = rt_thread_create("can1_rx", can1_rx_thread, RT_NULL, 4096, 10, 10);
if (thread != RT_NULL)
{
res = rt_thread_startup(thread);
RT_ASSERT(res == RT_EOK);
}
else
{
rt_kprintf("Create can1_rx thread failed.\n");
}
msg.id = 0x78; /* ID = 0x78 */
msg.ide = RT_CAN_STDID; /* Standard format */
msg.rtr = RT_CAN_DTR; /* Data frame */
msg.len = 8; /* Data length is 8 */
/* Send CAN data */
for (int i = 0; i < 5; i++)
{
/* 8-byte data to be sent */
msg.data[0] = 0x0;
msg.data[1] = 0x1;
msg.data[2] = 0x2;
msg.data[3] = 0x3;
msg.data[4] = 0x4;
msg.data[5] = 0x5;
msg.data[6] = 0x6;
msg.data[7] = 0x7;
rt_device_write(can0_dev, 0, &msg, sizeof(msg));
rt_thread_mdelay(100);
for (int i = 0; i < 8; i++)
{
if (msg.data[i] != rxmsg.data[i])
{
res = RT_ERROR;
goto exit;
}
}
}
/* Send CAN data */
for (int i = 0; i < 5; i++)
{
/* 8-byte data to be sent */
msg.data[0] = 0x0;
msg.data[1] = 0x1;
msg.data[2] = 0x2;
msg.data[3] = 0x3;
msg.data[4] = 0x4;
msg.data[5] = 0x5;
msg.data[6] = 0x6;
msg.data[7] = 0x7;
rt_device_write(can1_dev, 0, &msg, sizeof(msg));
rt_thread_mdelay(100);
for (int i = 0; i < 8; i++)
{
if (msg.data[i] != rxmsg.data[i])
{
res = RT_ERROR;
goto exit;
}
}
}
exit:
/* print message on example run result */
if (res == RT_EOK)
{
rt_kprintf("%s@%d:Can loopback test example [success].\r\n", __func__, __LINE__);
}
else
{
rt_kprintf("%s@%d:Can loopback test example [failure], res = %d\r\n", __func__, __LINE__, res);
}
return res;
}
/* Enter can_sample command for testing */
MSH_CMD_EXPORT(can_loopback_sample, can device sample);
#endif

8
bsp/phytium/libraries/drivers_example/gpio_sample.c
View File

@@ -47,9 +47,9 @@ static void gpio_irq_test(s32 vector, void *param)
gpio_instance->config.pin);
}
/* this function will toggle output pin and test intr of input pin */
static int gpio_toggle_sample(uint8_t argc, char **argv)
rt_err_t gpio_toggle_sample()
{
int res = 0;
rt_err_t res = RT_EOK;
static u32 set_level = FGPIO_OPS_LEVEL_LOW;
u32 get_level;
@@ -79,7 +79,7 @@ static int gpio_toggle_sample(uint8_t argc, char **argv)
if (set_level != get_level)
{
rt_kprintf(" input level not equals to output level!!!\r\n");
res = -1;
res = RT_ERROR;
goto exit;
}
else
@@ -95,7 +95,7 @@ static int gpio_toggle_sample(uint8_t argc, char **argv)
}
exit:
/* print message on example run result */
if (res == 0)
if (res == RT_EOK)
{
rt_kprintf("%s@%d:rtthread gpio test example [success].\r\n", __func__, __LINE__);
}

57
bsp/phytium/libraries/drivers_example/i2c_msg_sample.c Normal file
View File

@@ -0,0 +1,57 @@
#include "rtconfig.h"
#if defined BSP_USING_I2C_MSG
#include "drv_log.h"
#include "drv_i2c.h"
#define TEST_DEVICE_ADDR 0x53
static struct rt_i2c_bus_device *i2c_test_bus = RT_NULL;
int i2c_msg_sample(int argc, char *argv[])
{
rt_uint8_t write_content[] = {"Phytium Rt-thread I2C Msg Driver Test Successfully !!"};
rt_uint8_t write_addr[2] = {0x0, 0x0};
rt_uint8_t write_buf[2 + sizeof(write_content)];
rt_memcpy(write_buf, write_addr, 2);
rt_memcpy(write_buf + 2, write_content, sizeof(write_content));
rt_uint8_t read_buf[2 + sizeof(write_content)];
rt_memcpy(read_buf, write_addr, 2);
char name[RT_NAME_MAX];
rt_strncpy(name, "I2C3_MSG", RT_NAME_MAX);
i2c_test_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
if (i2c_test_bus == RT_NULL)
{
rt_kprintf("can't find %s device!\n", name);
}
else
{
rt_kprintf("find %s device!!!!\n", name);
}
struct rt_i2c_msg write_msgs;
write_msgs.addr = TEST_DEVICE_ADDR;
write_msgs.flags = RT_I2C_WR;
write_msgs.buf = write_buf;
write_msgs.len = sizeof(write_buf);
rt_i2c_transfer(i2c_test_bus, &write_msgs, 1);
struct rt_i2c_msg read_msgs;
read_msgs.addr = TEST_DEVICE_ADDR;
read_msgs.flags = RT_I2C_RD;
read_msgs.buf = read_buf;
read_msgs.len = sizeof(read_buf);
rt_i2c_transfer(i2c_test_bus, &read_msgs, 1);
for (rt_uint8_t i = 0; i < sizeof(write_content); i++)
{
if (read_buf[i] != write_content[i])
{
return -RT_ERROR;
}
}
printf("%s\n", read_buf);
return RT_EOK;
}
MSH_CMD_EXPORT(i2c_msg_sample, i2c msg device sample);
#endif

57
bsp/phytium/libraries/drivers_example/i2c_sample.c
View File

@@ -1,30 +1,31 @@
#include "rtconfig.h"
#if defined BSP_USING_I2C
#include "drv_log.h"
#include "drv_i2c.h"
#include "fi2c.h"
#include "fi2c_hw.h"
#include "fio_mux.h"
#include "fmio_hw.h"
#include "fmio.h"
#include "fparameters.h"
#define TEST_DEVICE_ADDR 0x53
static struct rt_i2c_bus_device *i2c_test_bus = RT_NULL;
int i2c_sample(int argc, char *argv[])
rt_err_t i2c_sample()
{
rt_uint8_t write_content[] = {"Phytium Rt-thread I2C Driver Test Successfully !!"};
rt_uint8_t write_addr[2] = {0x0, 0x0};
rt_uint8_t write_buf[2 + sizeof(write_content)];
rt_memcpy(write_buf, write_addr, 2);
rt_memcpy(write_buf + 2, write_content, sizeof(write_content));
rt_uint8_t read_buf[2 + sizeof(write_content)];
rt_memcpy(read_buf, write_addr, 2);
char name[RT_NAME_MAX];
#if defined(FIREFLY_DEMO_BOARD)
rt_strncpy(name, "MIO1", RT_NAME_MAX);
#endif
#if defined(E2000D_DEMO_BOARD)||defined(E2000Q_DEMO_BOARD)
rt_strncpy(name, "MIO15", RT_NAME_MAX);
#endif
#if defined(TARGET_PD2408)
rt_strncpy(name, "I2C3", RT_NAME_MAX);
#endif
i2c_test_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
rt_uint8_t read_buf[2] = {0x0, 0x0};
rt_uint8_t write_buf[2] = {0x0, 0x1};
if (i2c_test_bus == RT_NULL)
{
rt_kprintf("can't find %s device!\n", name);
@@ -34,24 +35,28 @@ int i2c_sample(int argc, char *argv[])
rt_kprintf("find %s device!!!!\n", name);
}
struct rt_i2c_msg read_msgs;
read_msgs.addr = 0x50;
read_msgs.flags = RT_I2C_RD;
read_msgs.buf = read_buf;
read_msgs.len = 1;
rt_i2c_transfer(i2c_test_bus, &read_msgs, 1);
rt_kprintf("read_buf = %x\n", *read_msgs.buf);
struct rt_i2c_msg write_msgs;
write_msgs.addr = 0x50;
write_msgs.addr = TEST_DEVICE_ADDR;
write_msgs.flags = RT_I2C_WR;
write_msgs.buf = write_buf;
write_msgs.len = 1;
write_msgs.len = sizeof(write_buf);
rt_i2c_transfer(i2c_test_bus, &write_msgs, 1);
read_buf[0] = 0x02;
rt_i2c_transfer(i2c_test_bus, &read_msgs, 1);
rt_kprintf("read_buf = %x\n", *read_msgs.buf);
struct rt_i2c_msg read_msgs;
read_msgs.addr = TEST_DEVICE_ADDR;
read_msgs.flags = RT_I2C_RD;
read_msgs.buf = read_buf;
read_msgs.len = sizeof(read_buf);
rt_i2c_transfer(i2c_test_bus, &read_msgs, 1);
for (rt_uint8_t i = 0; i < sizeof(write_content); i++)
{
if (read_buf[i] != write_content[i])
{
return -RT_ERROR;
}
}
rt_kprintf("%s\n", read_buf);
return RT_EOK;
}
MSH_CMD_EXPORT(i2c_sample, i2c device sample);

110
bsp/phytium/libraries/drivers_example/i2s_mic_example.c
View File

@@ -1,68 +1,62 @@
/* pcm_record.c */
#include "rtconfig.h"
#if defined(BSP_USING_I2S)||defined(BSP_USING_SDIF)
#include <rtthread.h>
#include <rtdevice.h>
#include <dfs_posix.h>
// /* pcm_record.c */
// #include "rtconfig.h"
// #if defined(BSP_USING_I2S)||defined(BSP_USING_SDIF)
// #include <rtthread.h>
// #include <rtdevice.h>
// #include <dfs_posix.h>
#define RECORD_TIME_MS 5000
#define RT_I2S_SAMPLERATE 8000
#define RECORD_CHANNEL 2
#define RECORD_CHUNK_SZ ((RT_I2S_SAMPLERATE * RECORD_CHANNEL * 2) * 20 / 1000)
// #define RECORD_TIME_MS 5000
// #define RT_I2S_SAMPLERATE 8000
// #define RECORD_CHANNEL 2
// #define RECORD_CHUNK_SZ ((RT_I2S_SAMPLERATE * RECORD_CHANNEL * 2) * 20 / 1000)
#define SOUND_DEVICE_NAME "I2S0" /* Audio 设备名称 */
static rt_device_t mic_dev; /* Audio 设备句柄 */
// #define SOUND_DEVICE_NAME "I2S0" /* Audio 设备名称 */
// static rt_device_t mic_dev; /* Audio 设备句柄 */
int pcm_record()
{
int fd = -1;
uint8_t *buffer = NULL;
int length, total_length = 0;
// int pcm_record()
// {
// int fd = -1;
// uint8_t *buffer = NULL;
// int length, total_length = 0;
fd = open("file.pcm", O_WRONLY | O_CREAT);
if (fd < 0)
{
rt_kprintf("open file for recording failed!\n");
return -1;
}
rt_kprintf("1\n");
buffer = rt_malloc(RECORD_CHUNK_SZ);
if (buffer == RT_NULL)
goto __exit;
rt_kprintf("2\n");
mic_dev = rt_device_find(SOUND_DEVICE_NAME);
if (mic_dev == RT_NULL)
goto __exit;
rt_kprintf("3\n");
rt_device_open(mic_dev, RT_DEVICE_OFLAG_RDONLY);
rt_kprintf("4\n");
while (1)
{
rt_kprintf("6\n");
length = rt_device_read(mic_dev, 0, buffer, RECORD_CHUNK_SZ);
rt_kprintf("7\n");
if (length)
{
write(fd, buffer, length);
total_length += length;
}
// fd = open("file.pcm", O_WRONLY | O_CREAT);
// if (fd < 0)
// {
// rt_kprintf("open file for recording failed!\n");
// return -1;
// }
// buffer = rt_malloc(RECORD_CHUNK_SZ);
// if (buffer == RT_NULL)
// goto __exit;
// mic_dev = rt_device_find(SOUND_DEVICE_NAME);
// if (mic_dev == RT_NULL)
// goto __exit;
// rt_device_open(mic_dev, RT_DEVICE_OFLAG_RDONLY);
// while (1)
// {
// length = rt_device_read(mic_dev, 0, buffer, RECORD_CHUNK_SZ);
// if (length)
// {
// write(fd, buffer, length);
// total_length += length;
// }
if ((total_length / RECORD_CHUNK_SZ) > (RECORD_TIME_MS / 20))
break;
}
// if ((total_length / RECORD_CHUNK_SZ) > (RECORD_TIME_MS / 20))
// break;
// }
close(fd);
// close(fd);
rt_device_close(mic_dev);
// rt_device_close(mic_dev);
__exit:
if (fd >= 0)
close(fd);
// __exit:
// if (fd >= 0)
// close(fd);
if (buffer)
rt_free(buffer);
// if (buffer)
// rt_free(buffer);
return 0;
}
MSH_CMD_EXPORT(pcm_record, record voice to a pcm file); // 修改命令描述
#endif
// return 0;
// }
// MSH_CMD_EXPORT(pcm_record, record voice to a pcm file); // 修改命令描述
// #endif

43
bsp/phytium/libraries/drivers_example/qspi_sample.c
View File

@@ -5,11 +5,13 @@
#ifdef RT_USING_SMART
#include <ioremap.h>
#endif
#include "auto_test.h"
#include "rtdevice.h"
#include "drv_qspi.h"
#include "fqspi_flash.h"
#include "fiopad.h"
#include "fqspi_hw.h"
#include "drv_qspi.h"
/*example*/
struct rt_qspi_message qspi_write_message;
struct rt_qspi_message qspi_read_message;
@@ -26,26 +28,32 @@ rt_err_t qspi_init()
}
/*write cmd example message improvement*/
void qspi_thread(void *parameter)
rt_err_t qspi_sample()
{
rt_size_t res;
qspi_init();
rt_err_t res = RT_EOK;
rt_size_t trans_res = 0;
res = qspi_init();
phytium_qspi_bus *qspi_bus;
qspi_bus = (phytium_qspi_bus *) qspi_test_device->parent.bus->parent.user_data;
/*Read and write flash chip fixed area repeatedly*/
qspi_write_message.address.content = 0x360000 ;/*Flash address*/
qspi_write_message.address.content = qspi_bus->fqspi.flash_size[0] - 0x100;/*Flash address*/
qspi_write_message.instruction.content = 0x02 ;/*write cmd*/
qspi_write_message.parent.send_buf = "phytium hello world!";
qspi_write_message.parent.length = strlen((char *)qspi_write_message.parent.send_buf) + 1;
res = rt_qspi_transfer_message(qspi_test_device, &qspi_write_message);
rt_qspi_transfer_message(qspi_test_device, &qspi_write_message);
qspi_read_message.address.content = 0x360000 ;/*Flash address*/
qspi_read_message.address.content = qspi_bus->fqspi.flash_size[0] - 0x100;/*Flash address*/
qspi_read_message.instruction.content = 0x03 ;/*write cmd*/
qspi_read_message.parent.length = 128;/*write cmd*/
qspi_read_message.parent.recv_buf = (rt_uint8_t *)rt_malloc(sizeof(rt_uint8_t) * qspi_read_message.parent.length);
res = rt_qspi_transfer_message(qspi_test_device, &qspi_read_message);
trans_res = rt_qspi_transfer_message(qspi_test_device, &qspi_read_message);
if (res != qspi_read_message.parent.length)
if (trans_res != qspi_read_message.parent.length)
{
LOG_E("The qspi read data length is incorrect.\r\n");
res = RT_ERROR;
goto exit;
}
@@ -57,23 +65,24 @@ void qspi_thread(void *parameter)
if (send_ptr[i] != recv_ptr[i])
{
LOG_E("The qspi read and write data is inconsistent.\r\n");
res = RT_ERROR;
goto exit;
}
}
rt_uint8_t recv;
rt_uint8_t cmd = 0x9F;/*read the flash status reg2*/
res = rt_qspi_send_then_recv(qspi_test_device, &cmd, sizeof(cmd), &recv, sizeof(recv));
if (recv == 0x0 || res != 0)
rt_qspi_send_then_recv(qspi_test_device, &cmd, sizeof(cmd), &recv, sizeof(recv));
if (recv == 0x0)
{
LOG_E("The status reg is incorrect\n");
LOG_E("The status reg is incorrect, recv = %x, res = %x\n", recv, res);
res = RT_ERROR;
goto exit;
}
exit:
/* print message on example run result */
if (res != 0)
if (res == RT_EOK)
{
rt_kprintf("%s@%d:rtthread qspi flash test example [success].\r\n", __func__, __LINE__);
}
@@ -81,18 +90,10 @@ exit:
{
rt_kprintf("%s@%d:rtthread qspi flash test example [failure], res = %d\r\n", __func__, __LINE__, res);
}
}
rt_err_t qspi_sample(int argc, char *argv[])
{
rt_thread_t thread;
rt_err_t res;
thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 4096, 25, 10);
res = rt_thread_startup(thread);
RT_ASSERT(res == RT_EOK);
return res;
}
/* Enter qspi_sample command for testing */
MSH_CMD_EXPORT(qspi_sample, qspi sample);
#endif

48
bsp/phytium/libraries/drivers_example/spi_sample.c
View File

@@ -1,24 +1,36 @@
#include"rtconfig.h"
#ifdef BSP_USING_SPI
#include"rtconfig.h"
#include <rtthread.h>
#include <rtdevice.h>
#include "interrupt.h"
#define LOG_TAG "spi_drv"
#include "drv_log.h"
#include <string.h>
#include "fparameters.h"
#include "fcpu_info.h"
#include "fkernel.h"
#include "ftypes.h"
#if defined(BSP_USING_SPI_LAYER)
#include"rtconfig.h"
#include <rtthread.h>
#include <rtdevice.h>
#include "auto_test.h"
#include "interrupt.h"
#if defined(BSP_USING_SPI)
#define LOG_TAG "spi_drv"
#elif defined(BSP_USING_SPI_MSG)
#define LOG_TAG "spi_msg_drv"
#endif
#include "drv_log.h"
#include <string.h>
#include "fparameters.h"
#include "fcpu_info.h"
#include "fkernel.h"
#include "ftypes.h"
#include <dfs_file.h>
#if defined(BSP_USING_SPI)
#include "fspim.h"
#include "fspim_hw.h" /* include low-level header file for internal probe */
#include "drv_spi.h"
#elif defined(BSP_USING_SPI_MSG)
#include "fspim_msg.h"
#include "fspim_msg_hw.h" /* include low-level header file for internal probe */
#include "drv_spi_msg.h"
#endif
#include <dfs_file.h>
#include "fspim.h"
#include "fspim_hw.h" /* include low-level header file for internal probe */
#include "drv_spi.h"
static struct rt_spi_device spi_flash_device;
/* spi test example */
static void fspim_test_sample(int argc, char *argv[])
rt_err_t fspim_test_sample()
{
static struct rt_spi_device *spi_device = RT_NULL;
static struct rt_spi_device *spi_bus = RT_NULL;
@@ -29,7 +41,7 @@ static void fspim_test_sample(int argc, char *argv[])
rt_spi_bus_attach_device(&spi_flash_device, "flash", "SPI2", spi_bus);
#endif
#if defined(FIREFLY_DEMO_BOARD)
#if defined(FIREFLY_DEMO_BOARD)||defined(CUS_DEMO_BOARD)
spi_bus = (struct rt_spi_device *)rt_device_find("SPI0");
rt_spi_bus_attach_device(&spi_flash_device, "flash", "SPI0", spi_bus);
#endif

4
bsp/phytium/libraries/phytium_standalone_sdk_install.py
View File

@@ -19,6 +19,6 @@ def clone_repository(branch, commit_hash):
if __name__ == "__main__":
branch_to_clone = "master"
commit_to_clone = "ebb6a635fcc5145592636ce24cecd91807104d35"
commit_to_clone = "20d40083fb3b1b328a2b750938123999d6c12262"
clone_repository(branch_to_clone, commit_to_clone)
clone_repository(branch_to_clone, commit_to_clone)

2
bsp/phytium/libraries/port/fboard_port/e2000d_demo/mnt_sdcard.c
View File

@@ -113,7 +113,7 @@ static void sd_mount(void)
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
4096, RT_THREAD_PRIORITY_MAX - 2, 20);
8192, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);

2
bsp/phytium/libraries/port/fboard_port/e2000q_demo/mnt_sdcard.c
View File

@@ -113,7 +113,7 @@ static void sd_mount(void)
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
4096, RT_THREAD_PRIORITY_MAX - 2, 20);
8192, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);

139
bsp/phytium/libraries/port/fboard_port/pd2408_test_a/mnt_sdcard.c Normal file
View File

@@ -0,0 +1,139 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2023-04-27 huanghe first version
* 2023-07-14 liqiaozhong add SD file sys mount func
* 2024-04-08 zhugengyu define mount table by board
*/
#include <rtthread.h>
#include <dfs_fs.h>
#define DBG_TAG "mnt.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#if defined(USE_SDIF0_TF)
#define FS_SD_MOUNT_POINT "/"
#define FS_SD_DEVICE_NAME "sd0"
#define FS_SD_DEVICE_INDEX 0
#elif defined(USE_SDIF0_EMMC)
#define FS_EMMC_MOUNT_POINT "/"
#define FS_EMMC_DEVICE_NAME "sd0"
#define FS_EMMC_DEVICE_INDEX 0
#endif
extern void sdif_change(rt_uint32_t id);
#if defined(USE_SDIF0_TF)
extern rt_int32_t sdif_card_inserted(rt_uint32_t id);
static rt_int32_t card_inserted = 0;
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find(FS_SD_DEVICE_NAME);
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdif_change(FS_SD_DEVICE_INDEX);
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find(FS_SD_DEVICE_NAME);
}
if (device != RT_NULL)
{
if (dfs_mount(FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT, "elm", 0, 0) == RT_EOK)
{
LOG_I("%s mount to '%s'", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT);
card_inserted = 1;
}
else
{
LOG_W("%s mount to '%s' failed!", FS_SD_DEVICE_NAME, FS_SD_MOUNT_POINT);
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount(FS_SD_MOUNT_POINT);
LOG_I("Unmount %s", FS_SD_MOUNT_POINT);
mmcsd_wait_cd_changed(0);
sdif_change(FS_SD_DEVICE_INDEX);
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
card_inserted = 0;
}
#endif
static void sd_auto_mount(void *parameter)
{
rt_thread_mdelay(20);
#if defined(USE_SDIF0_TF)
if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1))
{
_sdcard_mount();
}
while (RT_TRUE)
{
rt_thread_mdelay(200);
if ((card_inserted == 0) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 1))
{
_sdcard_mount();
}
if ((card_inserted == 1) && (sdif_card_inserted(FS_SD_DEVICE_INDEX) == 0))
{
_sdcard_unmount();
}
}
#elif defined(USE_SDIF0_EMMC)
mmcsd_wait_cd_changed(0);
sdif_change(FS_EMMC_DEVICE_INDEX);
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
if (dfs_mount(FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT, "elm", 0, 0) == RT_EOK)
{
LOG_I("%s mount to '%s'", FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT);
}
else
{
LOG_W("%s mount to '%s' failed!", FS_EMMC_DEVICE_NAME, FS_EMMC_MOUNT_POINT);
}
#endif
}
static void sd_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
8192, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
return;
}
}
int filesystem_mount(void)
{
sd_mount();
return RT_EOK;
}
INIT_APP_EXPORT(filesystem_mount);

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