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[driver/usb]Update dwc2/usb_glue_infineon.c to add the missing header file. (#11158)

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R b b666
2026-01-28 10:54:30 +08:00
committed by GitHub
parent cdc50db570
commit 3e2d924e9d
1 changed files with 6 additions and 2 deletions
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8
components/drivers/usb/cherryusb/port/dwc2/usb_glue_infineon.c
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@@ -8,13 +8,13 @@
#include "usb_dwc2_param.h" #include "usb_dwc2_param.h"
#include "rtthread.h" #include "rtthread.h"
#include "cybsp.h" #include "cybsp.h"
#include "cy_device.h"
#if defined (COMPONENT_CM55) #if defined (COMPONENT_CM55)
#if defined(CONFIG_USB_DWC2_DMA_ENABLE) && !defined(CONFIG_USB_DCACHE_ENABLE) #if !defined(CONFIG_USB_DCACHE_ENABLE)
#error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" when using DMA" #error "Please enable CONFIG_USB_DCACHE_ENABLE and put USB_NOCACHE_RAM_SECTION to section ".cy_socmem_data" when using DMA"
#endif #endif
#else #else
#define CONFIG_USB_DWC2_DMA_ENABLE #define CONFIG_USB_DWC2_DMA_ENABLE
#endif #endif
@@ -83,6 +83,8 @@ void usb_dc_low_level_init(uint8_t busid)
USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos);
USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk);
rt_thread_mdelay(200); /* Wait for PHY stable */
cy_stc_sysint_t usb_int_cfg = { cy_stc_sysint_t usb_int_cfg = {
.intrSrc = usbhs_interrupt_usbhsctrl_IRQn, .intrSrc = usbhs_interrupt_usbhsctrl_IRQn,
.intrPriority = 3 .intrPriority = 3
@@ -120,6 +122,8 @@ void usb_hc_low_level_init(struct usbh_bus *bus)
USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos); USBHS_SS->PHY_FUNC_CTL_1 |= (7 << USBHS_SS_PHY_FUNC_CTL_1_PLL_FSEL_Pos);
USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk); USBHS_SS->PHY_FUNC_CTL_2 |= (USBHS_SS_PHY_FUNC_CTL_2_RES_TUNING_SEL_Msk | USBHS_SS_PHY_FUNC_CTL_2_EFUSE_SEL_Msk);
rt_thread_mdelay(200); /* Wait for PHY stable */
cy_stc_sysint_t usb_int_cfg = { cy_stc_sysint_t usb_int_cfg = {
.intrSrc = usbhs_interrupt_usbhsctrl_IRQn, .intrSrc = usbhs_interrupt_usbhsctrl_IRQn,
.intrPriority = 3 .intrPriority = 3