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support ch32f10x family, add ch32f103c8-core bsp

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charlown
2021-08-31 14:41:35 +08:00
parent 14d0001c2b
commit 2e74dd8e2d
85 changed files with 36313 additions and 0 deletions
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5737
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Include/ch32f10x.h Normal file
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bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Include/system_ch32f10x.h Normal file
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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_system.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
*******************************************************************************/
#ifndef __SYSTEM_CH32F10X_H
#define __SYSTEM_CH32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/* CH32F10x_System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_SYSTEM_H */

295
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Source/ARM/startup_ch32f10x.s Normal file
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;/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
;* File Name : startup_ch32f10x.s
;* Author : WCH
;* Version : V1.0.0
;* Date : 2019/10/15
;* Description : CH32F10x vector table for MDK-ARM toolchain.
;*******************************************************************************/
;/*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;*******************************************************************************/
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
;/*******************************************************************************
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;*******************************************************************************/
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
;/*******************************************************************************
; Vector Table Mapped to Address 0 at Reset
;*******************************************************************************/
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
;/*******************************************************************************
; External Interrupts
;*******************************************************************************/
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD USB_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/*******************************************************************************
; Reset handler
;*******************************************************************************/
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/*******************************************************************************
; Dummy Exception Handlers (infinite loops which can be modified)
;*******************************************************************************/
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
USB_IRQHandler
B .
ENDP
ALIGN
;/*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************/
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

554
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Source/system_ch32f10x.c Normal file
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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_system.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
****************************************************************************************/
#include "ch32f10x.h"
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
// #define SYSCLK_FREQ_HSE HSE_VALUE
/* #define SYSCLK_FREQ_24MHz 24000000 */
// #define SYSCLK_FREQ_48MHz 48000000
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
/* #define VECT_TAB_SRAM */
/* Vector Table base offset field This value must be a multiple of 0x200 */
#define VECT_TAB_OFFSET 0x0
/* Clock Definitions */
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* ch32f10x_system_private_functionprototypes */
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/******************************************************************************************
* Function Name : SystemInit
* Description : Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
* Input : None
* Return : None
*******************************************************************************************/
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/******************************************************************************************
* Function Name : SystemCoreClockUpdate
* Description : Update SystemCoreClock variable according to Clock Register Values.
* Input : None
* Return : None
*******************************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
{
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
SystemCoreClock >>= tmp;
}
/******************************************************************************************
* Function Name : SetSysClock
* Description : Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
* source (default after reset)
*/
}
#ifdef DATA_IN_ExtSRAM
/******************************************************************************************
* Function Name : SystemInit_ExtMemCtl
* Description : Setup the external memory controller.
* Input : None
* Return : None
*******************************************************************************************/
void SystemInit_ExtMemCtl(void)
{
RCC->AHBENR = 0x00000114;
RCC->APB2ENR = 0x000001E0;
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#ifdef SYSCLK_FREQ_HSE
/******************************************************************************************
* Function Name : SetSysClockToHSE
* Description : elects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
/* Select HSE as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_24MHz
/******************************************************************************************
* Function Name : SetSysClockTo24
* Description : Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo24(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz
/******************************************************************************************
* Function Name : SetSysClockTo48
* Description : Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo48(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_56MHz
/******************************************************************************************
* Function Name : SetSysClockTo56
* Description : Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo56(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_72MHz
/******************************************************************************************
* Function Name : SetSysClockTo72
* Description : Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#endif

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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n\t"
"BX lr \n\t" : : "r" (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r" (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n\t"
"BX lr \n\t" : : "r" (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif

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bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/SConscript Normal file
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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
src = Split("""
StdPeriph_Driver/src/ch32f10x_adc.c
StdPeriph_Driver/src/ch32f10x_bkp.c
StdPeriph_Driver/src/ch32f10x_can.c
StdPeriph_Driver/src/ch32f10x_crc.c
StdPeriph_Driver/src/ch32f10x_dac.c
StdPeriph_Driver/src/ch32f10x_dbgmcu.c
StdPeriph_Driver/src/ch32f10x_dma.c
StdPeriph_Driver/src/ch32f10x_exti.c
StdPeriph_Driver/src/ch32f10x_flash.c
StdPeriph_Driver/src/ch32f10x_gpio.c
StdPeriph_Driver/src/ch32f10x_i2c.c
StdPeriph_Driver/src/ch32f10x_iwdg.c
StdPeriph_Driver/src/ch32f10x_misc.c
StdPeriph_Driver/src/ch32f10x_pwr.c
StdPeriph_Driver/src/ch32f10x_rcc.c
StdPeriph_Driver/src/ch32f10x_rtc.c
StdPeriph_Driver/src/ch32f10x_spi.c
StdPeriph_Driver/src/ch32f10x_tim.c
StdPeriph_Driver/src/ch32f10x_usart.c
StdPeriph_Driver/src/ch32f10x_wwdg.c
""")
path = [
cwd + '/CMSIS',
cwd + '/CMSIS/WCH/CH32F10x/Include',
cwd + '/StdPeriph_Driver/inc']
group = DefineGroup('ch32f10x_lib', src, depend = [''], CPPPATH = path)
Return('group')

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bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32f10x_adc.h Normal file
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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
*******************************************************************************/
#ifndef __CH32F10x_ADC_H
#define __CH32F10x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* ADC Init structure definition */
typedef struct
{
uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
}ADC_InitTypeDef;
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
/* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
/* ADC_sampling_time */
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
/* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_StartCalibration(ADC_TypeDef* ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_ADC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_bkp.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* BKP firmware library.
*******************************************************************************/
#ifndef __CH32F10x_BKP_H
#define __CH32F10x_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* Tamper_Pin_active_level */
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
/* RTC_output_source_to_output_on_the_Tamper_pin */
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
/* Data_Backup_Register */
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
void BKP_DeInit(void);
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
void BKP_TamperPinCmd(FunctionalState NewState);
void BKP_ITConfig(FunctionalState NewState);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
FlagStatus BKP_GetFlagStatus(void);
void BKP_ClearFlag(void);
ITStatus BKP_GetITStatus(void);
void BKP_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_BKP_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_can.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* CAN firmware library.
*******************************************************************************/
#ifndef __CH32F10x_CAN_H
#define __CH32F10x_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* CAN init structure definition */
typedef struct
{
uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
It ranges from 1 to 1024. */
uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of
@ref CAN_operating_mode */
uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of
@ref CAN_synchronisation_jump_width */
uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
Segment 1. This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_1 */
uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit
Segment 2.
This parameter can be a value of
@ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered
communication mode. This parameter can be set
either to ENABLE or DISABLE. */
FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off
management. This parameter can be set either
to ENABLE or DISABLE. */
FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set either to ENABLE or
DISABLE. */
FunctionalState CAN_NART; /*!< Enable or disable the no-automatic
retransmission mode. This parameter can be
set either to ENABLE or DISABLE. */
FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set either to ENABLE
or DISABLE. */
FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set either to ENABLE
or DISABLE. */
} CAN_InitTypeDef;
/* CAN filter init structure definition */
typedef struct
{
uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter can be a value between 0x0000 and 0xFFFF */
uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
This parameter can be set either to ENABLE or DISABLE. */
} CAN_FilterInitTypeDef;
/* CAN Tx message structure definition */
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanTxMsg;
/* CAN Rx message structure definition */
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t IDE; /*!< Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of
@ref CAN_remote_transmission_request */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
0xFF. */
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
the mailbox passes through. This parameter can be a
value between 0 to 0xFF */
} CanRxMsg;
/* CAN_sleep_constants */
#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
/* CAN_Mode */
#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
/* CAN_Operating_Mode */
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
/* CAN_Mode_Status */
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
/* CAN_synchronisation_jump_width */
#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
/* CAN_time_quantum_in_bit_segment_1 */
#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
/* CAN_time_quantum_in_bit_segment_2 */
#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
/* CAN_filter_mode */
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
/* CAN_filter_scale */
#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
/* CAN_filter_FIFO */
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
/* CAN_identifier_type */
#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
/* CAN_remote_transmission_request */
#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
/* CAN_transmit_constants */
#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
/* CAN_receive_FIFO_number_constants */
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
/* CAN_sleep_constants */
#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
/* CAN_wake_up_constants */
#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
/* CAN_Error_Code_constants */
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
/* -------------------------- CAN_flags ---------------------------- */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
/* Receive Flags */
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
/* Operating Mode Flags */
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
/* -------------------------- CAN_interrupts ---------------------------- */
#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
/* Flags named as Interrupts : kept only for FW compatibility */
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
/* CAN_Legacy */
#define CANINITFAILED CAN_InitStatus_Failed
#define CANINITOK CAN_InitStatus_Success
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
#define CAN_ID_STD CAN_Id_Standard
#define CAN_ID_EXT CAN_Id_Extended
#define CAN_RTR_DATA CAN_RTR_Data
#define CAN_RTR_REMOTE CAN_RTR_Remote
#define CANTXFAILE CAN_TxStatus_Failed
#define CANTXOK CAN_TxStatus_Ok
#define CANTXPENDING CAN_TxStatus_Pending
#define CAN_NO_MB CAN_TxStatus_NoMailBox
#define CANSLEEPFAILED CAN_Sleep_Failed
#define CANSLEEPOK CAN_Sleep_Ok
#define CANWAKEUPFAILED CAN_WakeUp_Failed
#define CANWAKEUPOK CAN_WakeUp_Ok
void CAN_DeInit(CAN_TypeDef* CANx);
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_CAN_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_crc.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* CRC firmware library.
*******************************************************************************/
#ifndef __CH32F10x_CRC_H
#define __CH32F10x_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
void CRC_ResetDR(void);
uint32_t CRC_CalcCRC(uint32_t Data);
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC_GetCRC(void);
void CRC_SetIDRegister(uint8_t IDValue);
uint8_t CRC_GetIDRegister(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_CRC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_dac.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* DAC firmware library.
*******************************************************************************/
#ifndef __CH32F10x_DAC_H
#define __CH32F10x_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* DAC Init structure definition */
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
}DAC_InitTypeDef;
/* DAC_trigger_selection */
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in High-density devices*/
#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
only in Connectivity line, Medium-density and Low-density Value Line devices */
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
only in Medium-density and Low-density Value Line devices*/
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
/* DAC_wave_generation */
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
/* DAC_lfsrunmask_triangleamplitude */
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
/* DAC_output_buffer */
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
/* DAC_Channel_selection */
#define DAC_Channel_1 ((uint32_t)0x00000000)
#define DAC_Channel_2 ((uint32_t)0x00000010)
/* DAC_data_alignment */
#define DAC_Align_12b_R ((uint32_t)0x00000000)
#define DAC_Align_12b_L ((uint32_t)0x00000004)
#define DAC_Align_8b_R ((uint32_t)0x00000008)
/* DAC_wave_generation */
#define DAC_Wave_Noise ((uint32_t)0x00000040)
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
/* DAC_Exported_Functions */
void DAC_DeInit(void);
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_DAC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_dbgmcu.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
*******************************************************************************/
#ifndef __CH32F10x_DBGMCU_H
#define __CH32F10x_DBGMCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)
#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)
#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)
#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)
#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)
#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)
#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)
#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)
#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)
#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)
uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_DBGMCU_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
*******************************************************************************/
#ifndef __CH32F10x_DMA_H
#define __CH32F10x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* DMA Init structure definition */
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
}DMA_InitTypeDef;
/* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
/* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
/* DMA_Exported_Functions */
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_DMA_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_exti.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
*******************************************************************************/
#ifndef __CH32F10x_EXTI_H
#define __CH32F10x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* EXTI mode enumeration */
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
/* EXTI Trigger enumeration */
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
/* EXTI Init Structure definition */
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
}EXTI_InitTypeDef;
/* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
/* EXTI_Exported_Functions */
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_EXTI_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
*******************************************************************************/
#ifndef __CH32F10x_FLASH_H
#define __CH32F10x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/* Flash_Latency */
#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
/* Half_Cycle_Enable_Disable */
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */
/* Prefetch_Buffer_Enable_Disable */
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
/* Values to be used with CH32F10x Low and Medium density devices */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< CH32 Low and Medium density devices: Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< CH32 Low and Medium density devices: Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< CH32 Low and Medium density devices: Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< CH32 Low and Medium density devices: Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< CH32 Low and Medium density devices: Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< CH32 Low and Medium density devices: Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< CH32 Low and Medium density devices: Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< CH32 Low and Medium density devices: Write protection of page 28 to 31 */
/* Values to be used with CH32F10x Medium-density devices */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< CH32 Medium-density devices: Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< CH32 Medium-density devices: Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< CH32 Medium-density devices: Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< CH32 Medium-density devices: Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< CH32 Medium-density devices: Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< CH32 Medium-density devices: Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< CH32 Medium-density devices: Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< CH32 Medium-density devices: Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< CH32 Medium-density devices: Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< CH32 Medium-density devices: Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< CH32 Medium-density devices: Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< CH32 Medium-density devices: Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< CH32 Medium-density devices: Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< CH32 Medium-density devices: Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< CH32 Medium-density devices: Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< CH32 Medium-density devices: Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< CH32 Medium-density devices: Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< CH32 Medium-density devices: Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< CH32 Medium-density devices: Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< CH32 Medium-density devices: Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< CH32 Medium-density devices: Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< CH32 Medium-density devices: Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< CH32 Medium-density devices: Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< CH32 Medium-density devices: Write protection of page 124 to 127 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< CH32 Medium-density devices: Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
/* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */
/*Functions used for all CH32F10x devices*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
/* New function used for all CH32F10x devices */
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_FLASH_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*******************************************************************************/
#ifndef __CH32F10x_GPIO_H
#define __CH32F10x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* Output Maximum frequency selection */
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */
typedef enum
{ GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
}GPIOMode_TypeDef;
/* GPIO Init structure definition */
typedef struct
{
uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
}GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
/* GPIO_pins_define */
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
/* GPIO_Remap_define */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected
to TIM2 Internal Trigger 1 for calibration
(only for Connectivity line devices) */
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
only for High density Value line devices) */
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_GPIO_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_i2c.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
*******************************************************************************/
#ifndef __CH32F10x_I2C_H
#define __CH32F10x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* I2C Init structure definition */
typedef struct
{
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
}I2C_InitTypeDef;
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
/* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_SMBus_alert_pin_level */
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
/* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NCAK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001)
/* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001)
/*========================================
I2C Master Events (Events grouped in order of communication)
==========================================*/
/**
* @brief Communication start
*
* After sending the START condition (I2C_GenerateSTART() function) the master
* has to wait for this event. It means that the Start condition has been correctly
* released on the I2C bus (the bus is free, no other devices is communicating).
*
*/
/* --EV5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/**
* @brief Address Acknowledge
*
* After checking on EV5 (start condition correctly released on the bus), the
* master sends the address of the slave(s) with which it will communicate
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will
* be set:
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
* function). Then master should wait on EV9. It means that the 10-bit addressing
* header has been correctly sent on the bus. Then master should send the second part of
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
* should wait for event EV6.
*
*/
/* --EV6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/* --EV9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/**
* @brief Communication events
*
* If a communication is established (START condition generated and slave address
* acknowledged) then the master has to check on one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
* the data received from the slave (I2C_ReceiveData() function).
*
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
* function) then to wait on event EV8 or EV8_2.
* These two events are similar:
* - EV8 means that the data has been written in the data register and is
* being shifted out.
* - EV8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EV8 is sufficient for the application.
* Using EV8_2 leads to a slower communication but ensure more reliable test.
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
* (before Stop condition generation).
*
* @note In case the user software does not guarantee that this event EV7 is
* managed before the current byte end of transfer, then user may check on EV7
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* --EV8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/*========================================
I2C Slave Events (Events grouped in order of communication)
==========================================*/
/**
* @brief Communication start events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a Start condition on the bus (generated by master
* device) followed by the peripheral address. The peripheral generates an ACK
* condition on the bus (if the acknowledge feature is enabled through function
* I2C_AcknowledgeConfig()) and the events listed above are set :
*
* 1) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* 2) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* 3) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* 2) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* 3) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/**
* @brief Communication events
*
* Wait on one of these events when EV1 has already been checked and:
*
* - Slave RECEIVER mode:
* - EV2: When the application is expecting a data byte to be received.
* - EV4: When the application is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EV3: When a byte has been transmitted by the slave and the application is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
* used when the user software doesn't guarantee the EV3 is managed before the
* current byte end of transfer.
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
* shall end (before sending the STOP condition). In this case slave has to stop sending
* data bytes and expect a Stop condition on the bus.
*
* @note In case the user software does not guarantee that the event EV2 is
* managed before the current byte end of transfer, then user may check on EV2
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
* In this case the communication may be slower.
*
*/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* --EV4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/* --EV3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
/*=========================== End of Events Description ==========================================*/
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
/**
* @brief
****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* depending on the application requirements and constraints:
*
*
* 1) Basic state monitoring:
* Using I2C_CheckEvent() function:
* It compares the status registers (SR1 and SR2) content to a given event
* (can be the combination of one or more flags).
* It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs (ie. error flags are set besides to the monitored flags),
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* hold or corrupted real state.
* In this case, it is advised to use error interrupts to monitor the error
* events and handle them in the interrupt IRQ handler.
*
* @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occurred.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
*
*
* 2) Advanced state monitoring:
* Using the function I2C_GetLastEvent() which returns the image of both status
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
* by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
* overcome the limitations of I2C_GetFlagStatus() function (see below).
* The returned value could be compared to events already defined in the
* library (ch32f10x_i2c.h) or to custom values defined by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
* other flags are set or just when the needed flags are set like
* I2C_CheckEvent() function).
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* 3) Flag-based state monitoring:
* Using the function I2C_GetFlagStatus() which simply returns the status of
* one single flag (ie. I2C_FLAG_RXNE ...).
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed (most I2C events
* are monitored through multiple flags).
* - Limitations:
* - When calling this function, the Status register is accessed. Some flags are
* cleared when the status register is accessed. So checking the status
* of one Flag, may clear other ones.
* - Function may need to be called twice or more in order to monitor one
* single event.
*
*/
/**
*
* 1) Basic state monitoring
*******************************************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/**
*
* 2) Advanced state monitoring
*******************************************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/**
*
* 3) Flag-based state monitoring
*******************************************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
/**
*
*******************************************************************************
*/
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_I2C_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_iwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
*******************************************************************************/
#ifndef __CH32F10x_IWDG_H
#define __CH32F10x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_IWDG_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_misc.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : CThis file contains all the functions prototypes for the
* miscellaneous firmware library functions (add-on to CMSIS functions).
*******************************************************************************/
#ifndef __CH32F10X_MISC_H
#define __CH32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* NVIC Init Structure definition */
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete ch32 Devices IRQ Channels list, please
refer to ch32f10x.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
/*
* NVIC_Priority_Table:
* The table below gives the allowed values of the pre-emption priority and subpriority according
* to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
* ============================================================================================================================
* NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
* ============================================================================================================================
* NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
* | | | 4 bits for subpriority
* ----------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
* | | | 3 bits for subpriority
* ----------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
* | | | 2 bits for subpriority
* ----------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
* | | | 1 bits for subpriority
* ----------------------------------------------------------------------------------------------------------------------------
* NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
* | | | 0 bits for subpriority
* ============================================================================================================================
*
*/
/* Vector_Table_Base */
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
/* System_Low_Power */
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
/* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/* MISC_Exported_Functions */
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_MISC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
*******************************************************************************/
#ifndef __CH32F10x_PWR_H
#define __CH32F10x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* PVD_detection_level */
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)
#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)
#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)
/* Regulator_state_is_STOP_mode */
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_PWR_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the RCC firmware functions.
*******************************************************************************/
#ifndef __CH32F10x_RCC_H
#define __CH32F10x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* RCC_Exported_Types */
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
}RCC_ClocksTypeDef;
/* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
/* PLL_multiplication_factor */
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
/* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
/* APB1_APB2_clock_source */
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
/* USB_Device_clock_source */
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
/* LSE_configuration */
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
/* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
/* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
/* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_RCC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_rtc.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the RTC
* firmware library.
*******************************************************************************/
#ifndef __CH32F10x_RTC_H
#define __CH32F10x_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* RTC_interrupts_define */
#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */
/* RTC_interrupts_flags */
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetDivider(void);
void RTC_WaitForLastTask(void);
void RTC_WaitForSynchro(void);
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
void RTC_ClearFlag(uint16_t RTC_FLAG);
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
void RTC_ClearITPendingBit(uint16_t RTC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_RTC_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
*******************************************************************************/
#ifndef __CH32F10x_SPI_H
#define __CH32F10x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* SPI Init structure definition */
typedef struct
{
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
}SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
/* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
/* I2S_Standard */
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
/* I2S_Data_Format */
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
/* I2S_MCLK_Output */
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
/* I2S_Audio_Frequency */
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
/* I2S_Clock_Polarity */
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
/* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_SPI_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*******************************************************************************/
#ifndef __CH32F10x_TIM_H
#define __CH32F10x_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* TIM Time Base Init structure definition */
typedef struct
{
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
uint16_t TIM_Channel; /*!< Specifies the TIM channel.
This parameter can be a value of @ref TIM_Channel */
uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint16_t TIM_ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
This parameter can be a value of @ref Lock_level */
uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between 0x00 and 0xFF */
uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref Break_Input_enable_disable */
uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref Break_Polarity */
uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BDTRInitTypeDef;
/* TIM_Output_Compare_and_PWM_modes */
#define TIM_OCMode_Timing ((uint16_t)0x0000)
#define TIM_OCMode_Active ((uint16_t)0x0010)
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
/* TIM_One_Pulse_Mode */
#define TIM_OPMode_Single ((uint16_t)0x0008)
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
/* TIM_Channel */
#define TIM_Channel_1 ((uint16_t)0x0000)
#define TIM_Channel_2 ((uint16_t)0x0004)
#define TIM_Channel_3 ((uint16_t)0x0008)
#define TIM_Channel_4 ((uint16_t)0x000C)
/* TIM_Clock_Division_CKD */
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
/* TIM_Counter_Mode */
#define TIM_CounterMode_Up ((uint16_t)0x0000)
#define TIM_CounterMode_Down ((uint16_t)0x0010)
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
/* TIM_Output_Compare_Polarity */
#define TIM_OCPolarity_High ((uint16_t)0x0000)
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
/* TIM_Output_Compare_N_Polarity */
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
/* TIM_Output_Compare_state */
#define TIM_OutputState_Disable ((uint16_t)0x0000)
#define TIM_OutputState_Enable ((uint16_t)0x0001)
/* TIM_Output_Compare_N_state */
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
/* TIM_Capture_Compare_state */
#define TIM_CCx_Enable ((uint16_t)0x0001)
#define TIM_CCx_Disable ((uint16_t)0x0000)
/* TIM_Capture_Compare_N_state */
#define TIM_CCxN_Enable ((uint16_t)0x0004)
#define TIM_CCxN_Disable ((uint16_t)0x0000)
/* Break_Input_enable_disable */
#define TIM_Break_Enable ((uint16_t)0x1000)
#define TIM_Break_Disable ((uint16_t)0x0000)
/* Break_Polarity */
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
/* TIM_AOE_Bit_Set_Reset */
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
/* Lock_level */
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
/* OSSI_Off_State_Selection_for_Idle_mode_state */
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
/* OSSR_Off_State_Selection_for_Run_mode_state */
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Idle_State */
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
/* TIM_Output_Compare_N_Idle_State */
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
/* TIM_Input_Capture_Polarity */
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
/* TIM_Input_Capture_Selection */
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
/* TIM_Input_Capture_Prescaler */
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
/* TIM_interrupt_sources */
#define TIM_IT_Update ((uint16_t)0x0001)
#define TIM_IT_CC1 ((uint16_t)0x0002)
#define TIM_IT_CC2 ((uint16_t)0x0004)
#define TIM_IT_CC3 ((uint16_t)0x0008)
#define TIM_IT_CC4 ((uint16_t)0x0010)
#define TIM_IT_COM ((uint16_t)0x0020)
#define TIM_IT_Trigger ((uint16_t)0x0040)
#define TIM_IT_Break ((uint16_t)0x0080)
/* TIM_DMA_Base_address */
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
#define TIM_DMABase_DIER ((uint16_t)0x0003)
#define TIM_DMABase_SR ((uint16_t)0x0004)
#define TIM_DMABase_EGR ((uint16_t)0x0005)
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define TIM_DMABase_CCER ((uint16_t)0x0008)
#define TIM_DMABase_CNT ((uint16_t)0x0009)
#define TIM_DMABase_PSC ((uint16_t)0x000A)
#define TIM_DMABase_ARR ((uint16_t)0x000B)
#define TIM_DMABase_RCR ((uint16_t)0x000C)
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
#define TIM_DMABase_DCR ((uint16_t)0x0012)
/* TIM_DMA_Burst_Length */
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
/* TIM_DMA_sources */
#define TIM_DMA_Update ((uint16_t)0x0100)
#define TIM_DMA_CC1 ((uint16_t)0x0200)
#define TIM_DMA_CC2 ((uint16_t)0x0400)
#define TIM_DMA_CC3 ((uint16_t)0x0800)
#define TIM_DMA_CC4 ((uint16_t)0x1000)
#define TIM_DMA_COM ((uint16_t)0x2000)
#define TIM_DMA_Trigger ((uint16_t)0x4000)
/* TIM_External_Trigger_Prescaler */
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
/* TIM_Internal_Trigger_Selection */
#define TIM_TS_ITR0 ((uint16_t)0x0000)
#define TIM_TS_ITR1 ((uint16_t)0x0010)
#define TIM_TS_ITR2 ((uint16_t)0x0020)
#define TIM_TS_ITR3 ((uint16_t)0x0030)
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define TIM_TS_ETRF ((uint16_t)0x0070)
/* TIM_TIx_External_Clock_Source */
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
/* TIM_External_Trigger_Polarity */
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
/* TIM_Prescaler_Reload_Mode */
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
/* TIM_Forced_Action */
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
/* TIM_Encoder_Mode */
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
/* TIM_Event_Source */
#define TIM_EventSource_Update ((uint16_t)0x0001)
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
#define TIM_EventSource_COM ((uint16_t)0x0020)
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
#define TIM_EventSource_Break ((uint16_t)0x0080)
/* TIM_Update_Source */
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
or the setting of UG bit, or an update generation
through the slave mode controller. */
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
/* TIM_Output_Compare_Preload_State */
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Fast_State */
#define TIM_OCFast_Enable ((uint16_t)0x0004)
#define TIM_OCFast_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Clear_State */
#define TIM_OCClear_Enable ((uint16_t)0x0080)
#define TIM_OCClear_Disable ((uint16_t)0x0000)
/* TIM_Trigger_Output_Source */
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
/* TIM_Slave_Mode */
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
/* TIM_Master_Slave_Mode */
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
/* TIM_Flags */
#define TIM_FLAG_Update ((uint16_t)0x0001)
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
#define TIM_FLAG_COM ((uint16_t)0x0020)
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
#define TIM_FLAG_Break ((uint16_t)0x0080)
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
/* TIM_Legacy */
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
void TIM_DeInit(TIM_TypeDef* TIMx);
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity, uint16_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32F10x_TIM_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*******************************************************************************/
#ifndef __CH32F10x_USART_H
#define __CH32F10x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* USART Init Structure definition */
typedef struct
{
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
/* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef* USARTx);
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
void USART_SendBreak(USART_TypeDef* USARTx);
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_USART_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the USB
* firmware library.
*******************************************************************************/
#ifndef __CH32F10x_USB_H
#define __CH32F10x_USB_H
#include "stdio.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef VOID
#define VOID (void)
#endif
#ifndef CONST
#define CONST const
#endif
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef BOOLEAN
typedef unsigned char BOOLEAN;
#endif
#ifndef CHAR
typedef char CHAR;
#endif
#ifndef INT8
typedef char INT8;
#endif
#ifndef INT16
typedef short INT16;
#endif
#ifndef INT32
typedef long INT32;
#endif
#ifndef UINT8
typedef unsigned char UINT8;
#endif
#ifndef UINT16
typedef unsigned short UINT16;
#endif
#ifndef UINT32
typedef unsigned long UINT32;
#endif
#ifndef UINT8V
typedef unsigned char volatile UINT8V;
#endif
#ifndef UINT16V
typedef unsigned short volatile UINT16V;
#endif
#ifndef UINT32V
typedef unsigned long volatile UINT32V;
#endif
#ifndef PVOID
typedef void *PVOID;
#endif
#ifndef PCHAR
typedef char *PCHAR;
#endif
#ifndef PCHAR
typedef const char *PCCHAR;
#endif
#ifndef PINT8
typedef char *PINT8;
#endif
#ifndef PINT16
typedef short *PINT16;
#endif
#ifndef PINT32
typedef long *PINT32;
#endif
#ifndef PUINT8
typedef unsigned char *PUINT8;
#endif
#ifndef PUINT16
typedef unsigned short *PUINT16;
#endif
#ifndef PUINT32
typedef unsigned long *PUINT32;
#endif
#ifndef PUINT8V
typedef volatile unsigned char *PUINT8V;
#endif
#ifndef PUINT16V
typedef volatile unsigned short *PUINT16V;
#endif
#ifndef PUINT32V
typedef volatile unsigned long *PUINT32V;
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* usb addresses
// USB: +8000H - 83FFH */
#define USB_BASE_ADDR (0x40023400)
#define EXTEN_CTRL (*((PUINT32V)(0x40023800)))
#define USBD_LOWSPEED ((UINT32)0x0001)
#define USBD_PU_EN ((UINT32)0x0002)
#define USBHD_IO_EN ((UINT32)0x0004)
#define USB_5V_SEL ((UINT32)0x0008)
#define RCC_AHBPeriph_USBHD ((UINT32)0x00001000)
/* USB */
#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address
#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control
#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode
#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps
#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable
#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit
#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit
#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control
// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
// 0 00: disable USB device and disable internal pullup resistance
// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
// 0 1x: enable USB device and enable internal pullup resistance
// 1 00: enable USB host and normal status
// 1 01: enable USB host and force UDP/UDM output SE0 state
// 1 10: enable USB host and force UDP/UDM output J state
// 1 11: enable USB host and force UDP/UDM output resume or K state
#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear
#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB
#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB
#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control
#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
#define RB_UD_GP_BIT 0x02 // general purpose bit
#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control
#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable
#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode
#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode
#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow
#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode
#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event
#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion
#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode
#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode
#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address
#define RB_UDA_GP_BIT 0x80 // general purpose bit
#define MASK_USB_ADDR 0x7F // bit mask for USB device address
#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status
#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status
#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status
#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host
#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty)
#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status
#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status
#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host
#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host
#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag
#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status
#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode
#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode
#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode
#define UIS_TOKEN_OUT 0x00
#define UIS_TOKEN_SOF 0x10
#define UIS_TOKEN_IN 0x20
#define UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
#define R8_USB_RX_LEN (*((PUINT8V)(0x40023408))) // USB receiving length
#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode
#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode
#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
// 0 0 x: disable endpoint and disable buffer
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode
#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode
#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for receiving (IN endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address
#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address
#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address
#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address
#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address
#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address
#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023420))) // endpoint 0 control & transmittal length
#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023420))) // endpoint 0 transmittal length
#define R8_UEP0_CTRL (*((PUINT8V)(0x40023422))) // endpoint 0 control
#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023424))) // endpoint 1 control & transmittal length
#define R8_UEP1_T_LEN (*((PUINT8V)(0x40023424))) // endpoint 1 transmittal length
#define R8_UEP1_CTRL (*((PUINT8V)(0x40023426))) // endpoint 1 control
#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT)
#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT)
#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT)
#define UEP_R_RES_ACK 0x00
#define UEP_R_RES_TOUT 0x04
#define UEP_R_RES_NAK 0x08
#define UEP_R_RES_STALL 0x0C
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
// 00: ACK (ready)
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
#define UEP_T_RES_ACK 0x00
#define UEP_T_RES_TOUT 0x01
#define UEP_T_RES_NAK 0x02
#define UEP_T_RES_STALL 0x03
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
// 00: DATA0 or DATA1 then expecting ACK (ready)
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup
#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable
#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023428))) // endpoint 2 control & transmittal length
#define R8_UEP2_T_LEN (*((PUINT8V)(0x40023428))) // endpoint 2 transmittal length
#define R8_UEP2_CTRL (*((PUINT8V)(0x4002342a))) // endpoint 2 control
#define R8_UH_EP_PID R8_UEP2_T_LEN // host endpoint and PID
#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer
#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer
#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control
#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002342c))) // endpoint 3 control & transmittal length
#define R8_UEP3_T_LEN (*((PUINT8V)(0x4002342c))) // endpoint 3 transmittal length
#define R8_UEP3_CTRL (*((PUINT8V)(0x4002342e))) // endpoint 3 control
#define R8_UH_TX_LEN R8_UEP3_T_LEN // host transmittal endpoint transmittal length
#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control
#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023430))) // endpoint 4 control & transmittal length
#define R8_UEP4_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 4 transmittal length
#define R8_UEP4_CTRL (*((PUINT8V)(0x40023432))) // endpoint 4 control
#define R8_USB_TYPE_C_CTRL (*((PUINT8V)(0x40023438))) // USB type-C control
#define RB_UTCC_GP_BIT 0x80 // USB general purpose bit
#define RB_UCC2_PD_EN 0x40 // USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown
#define RB_UCC2_PU1_EN 0x20 // USB CC2 pullup resistance control high bit
#define RB_UCC2_PU0_EN 0x10 // USB CC2 pullup resistance control low bit
#define RB_VBUS_PD_EN 0x08 // USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup
#define RB_UCC1_PD_EN 0x04 // USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown
#define RB_UCC1_PU1_EN 0x02 // USB CC1 pullup resistance control high bit
#define RB_UCC1_PU0_EN 0x01 // USB CC1 pullup resistance control low bit
// RB_UCC?_PU1_EN & RB_UCC?_PU0_EN: USB CC pullup resistance selection
// 00: disable pullup resistance
// 01: enable 36K pullup resistance for default USB power
// 10: enable 12K pullup resistance for 1.5A USB power
// 11: enable 4.7K pullup resistance for 3A USB power
#ifdef __cplusplus
}
#endif
#endif //__CH32F10x_USB_H
#ifndef __USB_TYPE__
#define __USB_TYPE__
#ifdef __cplusplus
extern "C" {
#endif
/*----- USB constant and structure define --------------------------------*/
/* USB PID */
#ifndef USB_PID_SETUP
#define USB_PID_NULL 0x00 /* reserved PID */
#define USB_PID_SOF 0x05
#define USB_PID_SETUP 0x0D
#define USB_PID_IN 0x09
#define USB_PID_OUT 0x01
#define USB_PID_ACK 0x02
#define USB_PID_NAK 0x0A
#define USB_PID_STALL 0x0E
#define USB_PID_DATA0 0x03
#define USB_PID_DATA1 0x0B
#define USB_PID_PRE 0x0C
#endif
/* USB standard device request code */
#ifndef USB_GET_DESCRIPTOR
#define USB_GET_STATUS 0x00
#define USB_CLEAR_FEATURE 0x01
#define USB_SET_FEATURE 0x03
#define USB_SET_ADDRESS 0x05
#define USB_GET_DESCRIPTOR 0x06
#define USB_SET_DESCRIPTOR 0x07
#define USB_GET_CONFIGURATION 0x08
#define USB_SET_CONFIGURATION 0x09
#define USB_GET_INTERFACE 0x0A
#define USB_SET_INTERFACE 0x0B
#define USB_SYNCH_FRAME 0x0C
#endif
/* USB hub class request code */
#ifndef HUB_GET_DESCRIPTOR
#define HUB_GET_STATUS 0x00
#define HUB_CLEAR_FEATURE 0x01
#define HUB_GET_STATE 0x02
#define HUB_SET_FEATURE 0x03
#define HUB_GET_DESCRIPTOR 0x06
#define HUB_SET_DESCRIPTOR 0x07
#endif
/* USB HID class request code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* Bit define for USB request type */
#ifndef USB_REQ_TYP_MASK
#define USB_REQ_TYP_IN 0x80 /* control IN, device to host */
#define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */
#define USB_REQ_TYP_READ 0x80 /* control read, device to host */
#define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */
#define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */
#define USB_REQ_TYP_STANDARD 0x00
#define USB_REQ_TYP_CLASS 0x20
#define USB_REQ_TYP_VENDOR 0x40
#define USB_REQ_TYP_RESERVED 0x60
#define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */
#define USB_REQ_RECIP_DEVICE 0x00
#define USB_REQ_RECIP_INTERF 0x01
#define USB_REQ_RECIP_ENDP 0x02
#define USB_REQ_RECIP_OTHER 0x03
#endif
/* USB request type for hub class request */
#ifndef HUB_GET_HUB_DESCRIPTOR
#define HUB_CLEAR_HUB_FEATURE 0x20
#define HUB_CLEAR_PORT_FEATURE 0x23
#define HUB_GET_BUS_STATE 0xA3
#define HUB_GET_HUB_DESCRIPTOR 0xA0
#define HUB_GET_HUB_STATUS 0xA0
#define HUB_GET_PORT_STATUS 0xA3
#define HUB_SET_HUB_DESCRIPTOR 0x20
#define HUB_SET_HUB_FEATURE 0x20
#define HUB_SET_PORT_FEATURE 0x23
#endif
/* Hub class feature selectors */
#ifndef HUB_PORT_RESET
#define HUB_C_HUB_LOCAL_POWER 0
#define HUB_C_HUB_OVER_CURRENT 1
#define HUB_PORT_CONNECTION 0
#define HUB_PORT_ENABLE 1
#define HUB_PORT_SUSPEND 2
#define HUB_PORT_OVER_CURRENT 3
#define HUB_PORT_RESET 4
#define HUB_PORT_POWER 8
#define HUB_PORT_LOW_SPEED 9
#define HUB_C_PORT_CONNECTION 16
#define HUB_C_PORT_ENABLE 17
#define HUB_C_PORT_SUSPEND 18
#define HUB_C_PORT_OVER_CURRENT 19
#define HUB_C_PORT_RESET 20
#endif
/* USB descriptor type */
#ifndef USB_DESCR_TYP_DEVICE
#define USB_DESCR_TYP_DEVICE 0x01
#define USB_DESCR_TYP_CONFIG 0x02
#define USB_DESCR_TYP_STRING 0x03
#define USB_DESCR_TYP_INTERF 0x04
#define USB_DESCR_TYP_ENDP 0x05
#define USB_DESCR_TYP_QUALIF 0x06
#define USB_DESCR_TYP_SPEED 0x07
#define USB_DESCR_TYP_OTG 0x09
#define USB_DESCR_TYP_HID 0x21
#define USB_DESCR_TYP_REPORT 0x22
#define USB_DESCR_TYP_PHYSIC 0x23
#define USB_DESCR_TYP_CS_INTF 0x24
#define USB_DESCR_TYP_CS_ENDP 0x25
#define USB_DESCR_TYP_HUB 0x29
#endif
/* USB device class */
#ifndef USB_DEV_CLASS_HUB
#define USB_DEV_CLASS_RESERVED 0x00
#define USB_DEV_CLASS_AUDIO 0x01
#define USB_DEV_CLASS_COMMUNIC 0x02
#define USB_DEV_CLASS_HID 0x03
#define USB_DEV_CLASS_MONITOR 0x04
#define USB_DEV_CLASS_PHYSIC_IF 0x05
#define USB_DEV_CLASS_POWER 0x06
#define USB_DEV_CLASS_PRINTER 0x07
#define USB_DEV_CLASS_STORAGE 0x08
#define USB_DEV_CLASS_HUB 0x09
#define USB_DEV_CLASS_VEN_SPEC 0xFF
#endif
/* USB endpoint type and attributes */
#ifndef USB_ENDP_TYPE_MASK
#define USB_ENDP_DIR_MASK 0x80
#define USB_ENDP_ADDR_MASK 0x0F
#define USB_ENDP_TYPE_MASK 0x03
#define USB_ENDP_TYPE_CTRL 0x00
#define USB_ENDP_TYPE_ISOCH 0x01
#define USB_ENDP_TYPE_BULK 0x02
#define USB_ENDP_TYPE_INTER 0x03
#endif
#ifndef USB_DEVICE_ADDR
#define USB_DEVICE_ADDR 0x02
#endif
#ifndef DEFAULT_ENDP0_SIZE
#define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */
#endif
#ifndef MAX_PACKET_SIZE
#define MAX_PACKET_SIZE 64 /* maximum packet size */
#endif
#ifndef USB_BO_CBW_SIZE
#define USB_BO_CBW_SIZE 0x1F
#define USB_BO_CSW_SIZE 0x0D
#endif
#ifndef USB_BO_CBW_SIG0
#define USB_BO_CBW_SIG0 0x55
#define USB_BO_CBW_SIG1 0x53
#define USB_BO_CBW_SIG2 0x42
#define USB_BO_CBW_SIG3 0x43
#define USB_BO_CSW_SIG0 0x55
#define USB_BO_CSW_SIG1 0x53
#define USB_BO_CSW_SIG2 0x42
#define USB_BO_CSW_SIG3 0x53
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
__PACKED typedef struct _USB_SETUP_REQ {
UINT8 bRequestType;
UINT8 bRequest;
UINT16 wValue;
UINT16 wIndex;
UINT16 wLength;
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
__PACKED typedef struct _USB_DEVICE_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 bcdUSB;
UINT8 bDeviceClass;
UINT8 bDeviceSubClass;
UINT8 bDeviceProtocol;
UINT8 bMaxPacketSize0;
UINT16 idVendor;
UINT16 idProduct;
UINT16 bcdDevice;
UINT8 iManufacturer;
UINT8 iProduct;
UINT8 iSerialNumber;
UINT8 bNumConfigurations;
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
__PACKED typedef struct _USB_CONFIG_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 wTotalLength;
UINT8 bNumInterfaces;
UINT8 bConfigurationValue;
UINT8 iConfiguration;
UINT8 bmAttributes;
UINT8 MaxPower;
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
__PACKED typedef struct _USB_INTERF_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bInterfaceNumber;
UINT8 bAlternateSetting;
UINT8 bNumEndpoints;
UINT8 bInterfaceClass;
UINT8 bInterfaceSubClass;
UINT8 bInterfaceProtocol;
UINT8 iInterface;
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
__PACKED typedef struct _USB_ENDPOINT_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT8 bEndpointAddress;
UINT8 bmAttributes;
UINT16 wMaxPacketSize;
UINT8 bInterval;
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
__packed typedef struct _USB_CONFIG_DESCR_LONG {
USB_CFG_DESCR cfg_descr;
USB_ITF_DESCR itf_descr;
USB_ENDP_DESCR endp_descr[1];
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
__PACKED typedef struct _USB_HUB_DESCR {
UINT8 bDescLength;
UINT8 bDescriptorType;
UINT8 bNbrPorts;
UINT8 wHubCharacteristicsL;
UINT8 wHubCharacteristicsH;
UINT8 bPwrOn2PwrGood;
UINT8 bHubContrCurrent;
UINT8 DeviceRemovable;
UINT8 PortPwrCtrlMask;
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
__PACKED typedef struct _USB_HID_DESCR {
UINT8 bLength;
UINT8 bDescriptorType;
UINT16 bcdHID;
UINT8 bCountryCode;
UINT8 bNumDescriptors;
UINT8 bDescriptorTypeX;
UINT8 wDescriptorLengthL;
UINT8 wDescriptorLengthH;
} USB_HID_DESCR, *PUSB_HID_DESCR;
__PACKED typedef struct _UDISK_BOC_CBW {/* command of BulkOnly USB-FlashDisk */
UINT32 mCBW_Sig;
UINT32 mCBW_Tag;
UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */
UINT8 mCBW_Flag; /* transfer direction and etc. */
UINT8 mCBW_LUN;
UINT8 mCBW_CB_Len; /* length of command block */
UINT8 mCBW_CB_Buf[16]; /* command block buffer */
} UDISK_BOC_CBW, *PUDISK_BOC_CBW;
__PACKED typedef struct _UDISK_BOC_CSW {/* status of BulkOnly USB-FlashDisk */
UINT32 mCBW_Sig;
UINT32 mCBW_Tag;
UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */
UINT8 mCSW_Status; /* return: result status */
} UDISK_BOC_CSW, *PUDISK_BOC_CSW;
extern PUINT8 pEP0_RAM_Addr; //ep0(64)+ep4_out(64)+ep4_in(64)
extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64)
extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64)
extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64)
#define pSetupReqPak ((PUSB_SETUP_REQ)pEP0_RAM_Addr)
#define pEP0_DataBuf (pEP0_RAM_Addr)
#define pEP1_OUT_DataBuf (pEP1_RAM_Addr)
#define pEP1_IN_DataBuf (pEP1_RAM_Addr+64)
#define pEP2_OUT_DataBuf (pEP2_RAM_Addr)
#define pEP2_IN_DataBuf (pEP2_RAM_Addr+64)
#define pEP3_OUT_DataBuf (pEP3_RAM_Addr)
#define pEP3_IN_DataBuf (pEP3_RAM_Addr+64)
#define pEP4_OUT_DataBuf (pEP0_RAM_Addr+64)
#define pEP4_IN_DataBuf (pEP0_RAM_Addr+128)
void USB_DeviceInit( void );
void USB_DevTransProcess( void );
void DevEP1_OUT_Deal( UINT8 l );
void DevEP2_OUT_Deal( UINT8 l );
void DevEP3_OUT_Deal( UINT8 l );
void DevEP4_OUT_Deal( UINT8 l );
void DevEP1_IN_Deal( UINT8 l );
void DevEP2_IN_Deal( UINT8 l );
void DevEP3_IN_Deal( UINT8 l );
void DevEP4_IN_Deal( UINT8 l );
void Set_USBClock(void);
#define EP1_GetINSta() (R8_UEP1_CTRL&UEP_T_RES_NAK)
#define EP2_GetINSta() (R8_UEP2_CTRL&UEP_T_RES_NAK)
#define EP3_GetINSta() (R8_UEP3_CTRL&UEP_T_RES_NAK)
#define EP4_GetINSta() (R8_UEP4_CTRL&UEP_T_RES_NAK)
#ifdef __cplusplus
}
#endif
#endif // __USB_TYPE__
#ifndef __CH32F10x_USBHOST_H__
#define __CH32F10x_USBHOST_H__
#ifdef __cplusplus
extern "C" {
#endif
#define ERR_SUCCESS 0x00
#define ERR_USB_CONNECT 0x15
#define ERR_USB_DISCON 0x16
#define ERR_USB_BUF_OVER 0x17
#define ERR_USB_DISK_ERR 0x1F
#define ERR_USB_TRANSFER 0x20
#define ERR_USB_UNSUPPORT 0xFB
#define ERR_USB_UNKNOWN 0xFE
#define ERR_AOA_PROTOCOL 0x41
#define ROOT_DEV_DISCONNECT 0
#define ROOT_DEV_CONNECTED 1
#define ROOT_DEV_FAILED 2
#define ROOT_DEV_SUCCESS 3
#define DEV_TYPE_KEYBOARD ( USB_DEV_CLASS_HID | 0x20 )
#define DEV_TYPE_MOUSE ( USB_DEV_CLASS_HID | 0x30 )
#define DEF_AOA_DEVICE 0xF0
#define DEV_TYPE_UNKNOW 0xFF
#define HUB_MAX_PORTS 4
#define WAIT_USB_TOUT_200US 800
typedef struct
{
UINT8 DeviceStatus;
UINT8 DeviceAddress;
UINT8 DeviceSpeed;
UINT8 DeviceType;
UINT16 DeviceVID;
UINT16 DevicePID;
UINT8 GpVar[4];
UINT8 GpHUBPortNum[4];
} _RootHubDev;
extern _RootHubDev ThisUsbDev;
extern UINT8 UsbDevEndp0Size;
extern UINT8 FoundNewDev;
extern PUINT8 pHOST_RX_RAM_Addr;
extern PUINT8 pHOST_TX_RAM_Addr;
#define pSetupReq ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr)
extern const UINT8 SetupGetDevDescr[];
extern const UINT8 SetupGetCfgDescr[];
extern const UINT8 SetupSetUsbAddr[];
extern const UINT8 SetupSetUsbConfig[];
extern const UINT8 SetupSetUsbInterface[];
extern const UINT8 SetupClrEndpStall[];
void DisableRootHubPort(void) ;
UINT8 AnalyzeRootHub( void ) ;
void SetHostUsbAddr( UINT8 addr );
void SetUsbSpeed( UINT8 FullSpeed );
void ResetRootHubPort(void);
UINT8 EnableRootHubPort(void);
void SelectHubPort( UINT8 HubPortIndex );
UINT8 WaitUSB_Interrupt( void );
UINT8 USBHostTransact( UINT8 endp_pid, UINT8 tog, UINT16 timeout );
UINT8 HostCtrlTransfer( PUINT8 DataBuf, PUINT16 RetLen );
void CopySetupReqPkg( const UINT8 *pReqPkt );
UINT8 CtrlGetDeviceDescr( PUINT8 DataBuf );
UINT8 CtrlGetConfigDescr( PUINT8 DataBuf );
UINT8 CtrlSetUsbAddress( UINT8 addr );
UINT8 CtrlSetUsbConfig( UINT8 cfg );
UINT8 CtrlClearEndpStall( UINT8 endp ) ;
UINT8 CtrlSetUsbIntercace( UINT8 cfg );
void DelsyMs( UINT16 t );
void USB_HostInit( void );
UINT8 InitRootDevice( PUINT8 DataBuf );
#ifdef DEBUG
#define PRINT(X...) printf(X)
#else
#define PRINT(X...)
#endif
#define mDelaymS DelsyMs
#define mDelayuS DelsyUs
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_USBHOST_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_wwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file contains all the functions prototypes for the WWDG
* firmware library.
*******************************************************************************/
#ifndef __CH32F10x_WWDG_H
#define __CH32F10x_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32f10x.h"
/* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#ifdef __cplusplus
}
#endif
#endif /* __CH32F10x_WWDG_H */

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_bkp.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the BKP firmware functions.
*******************************************************************************/
#include "ch32f10x_bkp.h"
#include "ch32f10x_rcc.h"
/* ------------ BKP registers bit address in the alias region --------------- */
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
/* --- TPCTLR Register ----*/
/* Alias word address of TPAL bit */
#define TPCTLR_OFFSET (BKP_OFFSET + 0x30)
#define TPAL_BitNumber 0x01
#define TPCTLR_TPAL_BB (PERIPH_BB_BASE + (TPCTLR_OFFSET * 32) + (TPAL_BitNumber * 4))
/* Alias word address of TPE bit */
#define TPE_BitNumber 0x00
#define TPCTLR_TPE_BB (PERIPH_BB_BASE + (TPCTLR_OFFSET * 32) + (TPE_BitNumber * 4))
/* --- TPCSR Register ---*/
/* Alias word address of TPIE bit */
#define TPCSR_OFFSET (BKP_OFFSET + 0x34)
#define TPIE_BitNumber 0x02
#define TPCSR_TPIE_BB (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TPIE_BitNumber * 4))
/* Alias word address of TIF bit */
#define TIF_BitNumber 0x09
#define TPCSR_TIF_BB (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TIF_BitNumber * 4))
/* Alias word address of TEF bit */
#define TEF_BitNumber 0x08
#define TPCSR_TEF_BB (PERIPH_BB_BASE + (TPCSR_OFFSET * 32) + (TEF_BitNumber * 4))
/* ---------------------- BKP registers bit mask ------------------------ */
/* OCTLR register bit mask */
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
#define OCTLR_MASK ((uint16_t)0xFC7F)
/*******************************************************************************
* Function Name : BKP_DeInit
* Description : Deinitializes the BKP peripheral registers to their default
* reset values.
* Input : None
* Return : None
*******************************************************************************/
void BKP_DeInit(void)
{
RCC_BackupResetCmd(ENABLE);
RCC_BackupResetCmd(DISABLE);
}
/*******************************************************************************
* Function Name : BKP_TamperPinLevelConfig
* Description : Configures the Tamper Pin active level.
* Input : BKP_TamperPinLevel: specifies the Tamper Pin active level.
* BKP_TamperPinLevel_High: Tamper pin active on high level.
* BKP_TamperPinLevel_Low: Tamper pin active on low level.
* Return : None
*******************************************************************************/
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
{
*(__IO uint32_t *) TPCTLR_TPAL_BB = BKP_TamperPinLevel;
}
/*******************************************************************************
* Function Name : BKP_TamperPinCmd
* Description : Configures the Tamper Pin active level.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void BKP_TamperPinCmd(FunctionalState NewState)
{
*(__IO uint32_t *) TPCTLR_TPE_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : BKP_ITConfig
* Description : Enables or disables the Tamper Pin Interrupt.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void BKP_ITConfig(FunctionalState NewState)
{
*(__IO uint32_t *) TPCSR_TPIE_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : BKP_RTCOutputConfig
* Description : Select the RTC output source to output on the Tamper pin.
* Input : BKP_RTCOutputSource: specifies the RTC output source.
* BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
* BKP_RTCOutputSource_CalibClock: output the RTC clock with
* frequency divided by 64 on the Tamper pin.
* BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal
* on the Tamper pin.
* BKP_RTCOutputSource_Second: output the RTC Second pulse
* signal on the Tamper pin.
* Return : None
*******************************************************************************/
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_MASK;
tmpreg |= BKP_RTCOutputSource;
BKP->OCTLR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_SetRTCCalibrationValue
* Description : Sets RTC Clock Calibration value.
* Input : CalibrationValue: specifies the RTC Clock Calibration value.
* This parameter must be a number between 0 and 0x1F.
* Return : None
*******************************************************************************/
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
{
uint16_t tmpreg = 0;
tmpreg = BKP->OCTLR;
tmpreg &= OCTLR_CAL_MASK;
tmpreg |= CalibrationValue;
BKP->OCTLR = tmpreg;
}
/*******************************************************************************
* Function Name : BKP_WriteBackupRegister
* Description : Writes user data to the specified Data Backup Register.
* Input : BKP_DR: specifies the Data Backup Register.
* Data: data to write.
* Return : None
*******************************************************************************/
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
*(__IO uint32_t *) tmp = Data;
}
/*******************************************************************************
* Function Name : BKP_ReadBackupRegister
* Description : Reads data from the specified Data Backup Register.
* Input : BKP_DR: specifies the Data Backup Register.
* This parameter can be BKP_DRx where x:[1, 42].
* Return : None
*******************************************************************************/
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)BKP_BASE;
tmp += BKP_DR;
return (*(__IO uint16_t *) tmp);
}
/*******************************************************************************
* Function Name : BKP_GetFlagStatus
* Description : Checks whether the Tamper Pin Event flag is set or not.
* Input : None
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
FlagStatus BKP_GetFlagStatus(void)
{
return (FlagStatus)(*(__IO uint32_t *) TPCSR_TEF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearFlag
* Description : Clears Tamper Pin Event pending flag.
* Input : None
* Return : None
*******************************************************************************/
void BKP_ClearFlag(void)
{
BKP->TPCSR |= BKP_CTE;
}
/*******************************************************************************
* Function Name : BKP_GetITStatus
* Description : Checks whether the Tamper Pin Interrupt has occurred or not.
* Input : None
* Return : ITStatus: SET or RESET.
*******************************************************************************/
ITStatus BKP_GetITStatus(void)
{
return (ITStatus)(*(__IO uint32_t *) TPCSR_TIF_BB);
}
/*******************************************************************************
* Function Name : BKP_ClearITPendingBit
* Description : Clears Tamper Pin Interrupt pending bit.
* Input : None
* Return : None
*******************************************************************************/
void BKP_ClearITPendingBit(void)
{
BKP->TPCSR |= BKP_CTI;
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_crc.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the CRC firmware functions.
*******************************************************************************/
#include "ch32f10x_crc.h"
/*******************************************************************************
* Function Name : CRC_ResetDR
* Description : Resets the CRC Data register (DR).
* Input : None
* Return : None
*******************************************************************************/
void CRC_ResetDR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/*******************************************************************************
* Function Name : CRC_CalcCRC
* Description : Computes the 32-bit CRC of a given data word(32-bit).
* Input : Data: data word(32-bit) to compute its CRC.
* Return : 32-bit CRC.
*******************************************************************************/
uint32_t CRC_CalcCRC(uint32_t Data)
{
CRC->DATAR = Data;
return (CRC->DATAR);
}
/*******************************************************************************
* Function Name : CRC_CalcBlockCRC
* Description : Computes the 32-bit CRC of a given buffer of data word(32-bit).
* Input : pBuffer: pointer to the buffer containing the data to be computed.
* BufferLength: length of the buffer to be computed.
* Return : 32-bit CRC.
*******************************************************************************/
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0;
for(index = 0; index < BufferLength; index++)
{
CRC->DATAR = pBuffer[index];
}
return (CRC->DATAR);
}
/*******************************************************************************
* Function Name : CRC_GetCRC
* Description : Returns the current CRC value.
* Input : None
* Return : 32-bit CRC.
*******************************************************************************/
uint32_t CRC_GetCRC(void)
{
return (CRC->IDATAR);
}
/*******************************************************************************
* Function Name : CRC_SetIDRegister
* Description : Stores a 8-bit data in the Independent Data(ID) register.
* Input : IDValue: 8-bit value to be stored in the ID register.
* Return : None
*******************************************************************************/
void CRC_SetIDRegister(uint8_t IDValue)
{
CRC->IDATAR = IDValue;
}
/*******************************************************************************
* Function Name : CRC_GetIDRegister
* Description : Returns the 8-bit data stored in the Independent Data(ID) register.
* Input : None
* Return : 8-bit value of the ID register.
*******************************************************************************/
uint8_t CRC_GetIDRegister(void)
{
return (CRC->IDATAR);
}

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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_dac.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the DAC firmware functions.
****************************************************************************************/
#include "ch32f10x_dac.h"
#include "ch32f10x_rcc.h"
/* CTLR register Mask */
#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE)
/* DAC Dual Channels SWTR masks */
#define DUAL_SWTR_SET ((uint32_t)0x00000003)
#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC)
/* DHR registers offsets */
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
/* DOR register offset */
#define DOR_OFFSET ((uint32_t)0x0000002C)
/******************************************************************************************
* Function Name : DAC_DeInit
* Description : Deinitializes the DAC peripheral registers to their default reset values.
* Input : None
* Return : None
*******************************************************************************************/
void DAC_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
}
/******************************************************************************************
* Function Name : DAC_Init
* Description : Initializes the DAC peripheral according to the specified parameters in
* the DAC_InitStruct.
* Input : DAC_Channel:the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* DAC_InitStruct:pointer to a DAC_InitTypeDef structure.
* Return : None
*******************************************************************************************/
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
tmpreg1 = DAC->CTLR;
tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
tmpreg1 |= tmpreg2 << DAC_Channel;
DAC->CTLR = tmpreg1;
}
/******************************************************************************************
* Function Name : DAC_StructInit
* Description : Fills each DAC_InitStruct member with its default value.
* Input : DAC_InitStruct:pointer to a DAC_InitTypeDef structure which will be initialized.
* Return : None
*******************************************************************************************/
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
{
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
}
/******************************************************************************************
* Function Name : DAC_Cmd
* Description : Enables or disables the specified DAC channel.
* Input : DAC_Channel: the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* NewState:new state of the DAC channel(ENABLE or DISABLE).
* Return : None
*******************************************************************************************/
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DAC->CTLR |= (DAC_EN1 << DAC_Channel);
}
else
{
DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
}
}
/******************************************************************************************
* Function Name : DAC_DMACmd
* Description : Enables or disables the specified DAC channel DMA request.
* Input : DAC_Channel: the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* NewState:new state of the DAC channel(ENABLE or DISABLE).
* Return : None
*******************************************************************************************/
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
}
else
{
DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
}
}
/******************************************************************************************
* Function Name : DAC_SoftwareTriggerCmd
* Description : Enables or disables the selected DAC channel software trigger.
* Input : DAC_Channel: the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* NewState:new state of the DAC channel(ENABLE or DISABLE).
* Return : None
*******************************************************************************************/
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
}
else
{
DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
}
}
/******************************************************************************************
* Function Name : DAC_WaveGenerationCmd
* Description : Enables or disables the selected DAC channel wave generation.
* Input : DAC_Channel: the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* DAC_Wave: Specifies the wave type to enable or disable.
* DAC_Wave_Noise: noise wave generation
* DAC_Wave_Triangle: triangle wave generation
* NewState:new state of the DAC channel(ENABLE or DISABLE).
* Return : None
*******************************************************************************************/
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DAC->CTLR |= DAC_Wave << DAC_Channel;
}
else
{
DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
}
}
/******************************************************************************************
* Function Name : DAC_SetChannel1Data
* Description : Set the specified data holding register value for DAC channel1.
* Input : DAC_Align: Specifies the data alignment for DAC channel1.
* DAC_Align_8b_R: 8bit right data alignment selected
* DAC_Align_12b_L: 12bit left data alignment selected
* DAC_Align_12b_R: 12bit right data alignment selected
* Data : Data to be loaded in the selected data holding register.
* Return : None
*******************************************************************************************/
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R1_OFFSET + DAC_Align;
*(__IO uint32_t *) tmp = Data;
}
/******************************************************************************************
* Function Name : DAC_SetChannel2Data
* Description : Set the specified data holding register value for DAC channel2.
* Input : DAC_Align: Specifies the data alignment for DAC channel1.
* DAC_Align_8b_R: 8bit right data alignment selected
* DAC_Align_12b_L: 12bit left data alignment selected
* DAC_Align_12b_R: 12bit right data alignment selected
* Data : Data to be loaded in the selected data holding register.
* Return : None
*******************************************************************************************/
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t)DAC_BASE;
tmp += DHR12R2_OFFSET + DAC_Align;
*(__IO uint32_t *)tmp = Data;
}
/******************************************************************************************
* Function Name : DAC_GetDataOutputValue
* Description : Returns the last data output value of the selected DAC channel.
* Input : DAC_Channel: the selected DAC channel.
* DAC_Channel_1: DAC Channel1 selected
* DAC_Channel_2: DAC Channel2 selected
* Return : The selected DAC channel data output value.
*******************************************************************************************/
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t) DAC_BASE ;
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
return (uint16_t) (*(__IO uint32_t*) tmp);
}

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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_dbgmcu.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the DBGMCU firmware functions.
****************************************************************************************/
#include "ch32f10x_dbgmcu.h"
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/*******************************************************************************
* Function Name : DBGMCU_GetREVID
* Description : Returns the device revision identifier.
* Input : None
* Return : Revision identifier.
*******************************************************************************/
uint32_t DBGMCU_GetREVID(void)
{
return(DBGMCU->IDCODE >> 16);
}
/*******************************************************************************
* Function Name : DBGMCU_GetDEVID
* Description : Returns the device identifier.
* Input : None
* Return : Device identifier.
*******************************************************************************/
uint32_t DBGMCU_GetDEVID(void)
{
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
}
/*******************************************************************************
* Function Name : DBGMCU_Config
* Description : Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* Input : DBGMCU_Periph: specifies the peripheral and low power mode.
* DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
* DBGMCU_STOP: Keep debugger connection during STOP mode
* DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
* DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
* DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
* DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
* DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted
* DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
* DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
* DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
* DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
* DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
* DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
* DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
* DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
* DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DBGMCU->CFGR |= DBGMCU_Periph;
}
else
{
DBGMCU->CFGR &= ~DBGMCU_Periph;
}
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_dma.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the DMA firmware functions.
*******************************************************************************/
#include "ch32f10x_dma.h"
#include "ch32f10x_rcc.h"
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
/* DMA registers Masks */
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/********************************************************************************
* Function Name : DMA_DeInit
* Description : Deinitializes the DMAy Channelx registers to their default reset
* values.
* Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* Return : None
*********************************************************************************/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->CFGR = 0;
DMAy_Channelx->CNTR = 0;
DMAy_Channelx->PADDR = 0;
DMAy_Channelx->MADDR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel2)
{
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel3)
{
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel4)
{
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel5)
{
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel6)
{
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel7)
{
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel1)
{
DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel2)
{
DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel3)
{
DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel4)
{
DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
}
else
{
if (DMAy_Channelx == DMA2_Channel5)
{
DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
}
}
}
/********************************************************************************
* Function Name : DMA_Init
* Description : Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* Input : DMAy_Channelx:here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* DMA_InitStruct:pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the
* specified DMA Channel.
* Return : None
*********************************************************************************/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
tmpreg = DMAy_Channelx->CFGR;
tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/********************************************************************************
* Function Name : DMA_StructInit
* Description : Fills each DMA_InitStruct member with its default value.
* Input : DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* be initialized.
* Return : None
*********************************************************************************/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/********************************************************************************
* Function Name : DMA_Cmd
* Description : Enables or disables the specified DMAy Channelx.
* Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
* be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
* the DMA Channel.
* NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
* Return : None
*********************************************************************************/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
}
else
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
}
}
/********************************************************************************
* Function Name : DMA_ITConfig
* Description : Enables or disables the specified DMAy Channelx interrupts.
* Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
* be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
* the DMA Channel.
* DMA_IT : specifies the DMA interrupts sources to be enabled
* or disabled.
* DMA_IT_TC : Transfer complete interrupt mask
* DMA_IT_HT : Half transfer interrupt mask
* DMA_IT_TE : Transfer error interrupt mask
* NewState : new state of the DMAy Channelx(ENABLE or DISABLE).
* Return : None
*********************************************************************************/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
if (NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_IT;
}
else
{
DMAy_Channelx->CFGR &= ~DMA_IT;
}
}
/********************************************************************************
* Function Name : DMA_SetCurrDataCounter
* Description : Sets the number of data units in the current DMAy Channelx transfer.
* Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
* be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
* the DMA Channel.
* DataNumber : The number of data units in the current DMAy Channelx
* transfer.
* Return : None
*********************************************************************************/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
DMAy_Channelx->CNTR = DataNumber;
}
/********************************************************************************
* Function Name : DMA_SetCurrDataCounter
* Description : Sets the number of data units in the current DMAy Channelx transfer.
* Input : DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can
* be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select
* the DMA Channel.
* Return : DataNumber : The number of remaining data units in the current
* DMAy Channelx transfer.
*********************************************************************************/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
return ((uint16_t)(DMAy_Channelx->CNTR));
}
/********************************************************************************
* Function Name : DMA_GetFlagStatus
* Description : Checks whether the specified DMAy Channelx flag is set or not.
* Input : DMAy_FLAG: specifies the flag to check.
* DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* Return : The new state of DMAy_FLAG (SET or RESET).
*********************************************************************************/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
tmpreg = DMA2->INTFR ;
}
else
{
tmpreg = DMA1->INTFR ;
}
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : DMA_ClearFlag
* Description : Clears the DMAy Channelx's pending flags.
* Input : DMAy_FLAG: specifies the flag to check.
* DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* Return : NONE
*********************************************************************************/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
DMA2->INTFCR = DMAy_FLAG;
}
else
{
DMA1->INTFCR = DMAy_FLAG;
}
}
/********************************************************************************
* Function Name : DMA_GetITStatus
* Description : Checks whether the specified DMAy Channelx interrupt has occurred
* or not.
* Input : DMAy_IT: specifies the DMAy interrupt source to check.
* DMA1_IT_GL1: DMA1 Channel1 global flag.
* DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2: DMA1 Channel2 global flag.
* DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3: DMA1 Channel3 global flag.
* DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4: DMA1 Channel4 global flag.
* DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5: DMA1 Channel5 global flag.
* DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6: DMA1 Channel6 global flag.
* DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7: DMA1 Channel7 global flag.
* DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1: DMA2 Channel1 global flag.
* DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
* DMA2_IT_GL2: DMA2 Channel2 global flag.
* DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
* DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
* DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
* DMA2_IT_GL3: DMA2 Channel3 global flag.
* DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
* DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
* DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
* DMA2_IT_GL4: DMA2 Channel4 global flag.
* DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
* DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
* DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
* DMA2_IT_GL5: DMA2 Channel5 global flag.
* DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
* DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
* DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
* Return : The new state of DMAy_IT (SET or RESET).
*********************************************************************************/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
tmpreg = DMA2->INTFR;
}
else
{
tmpreg = DMA1->INTFR;
}
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : DMA_ClearITPendingBit
* Description : Clears the DMAy Channelx's interrupt pending bits.
* Input : DMAy_IT: specifies the DMAy interrupt source to check.
* DMA1_IT_GL1: DMA1 Channel1 global flag.
* DMA1_IT_TC1: DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1: DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1: DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2: DMA1 Channel2 global flag.
* DMA1_IT_TC2: DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2: DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2: DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3: DMA1 Channel3 global flag.
* DMA1_IT_TC3: DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3: DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3: DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4: DMA1 Channel4 global flag.
* DMA1_IT_TC4: DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4: DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4: DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5: DMA1 Channel5 global flag.
* DMA1_IT_TC5: DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5: DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5: DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6: DMA1 Channel6 global flag.
* DMA1_IT_TC6: DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6: DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6: DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7: DMA1 Channel7 global flag.
* DMA1_IT_TC7: DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7: DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7: DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1: DMA2 Channel1 global flag.
* DMA2_IT_TC1: DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1: DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1: DMA2 Channel1 transfer error flag.
* DMA2_IT_GL2: DMA2 Channel2 global flag.
* DMA2_IT_TC2: DMA2 Channel2 transfer complete flag.
* DMA2_IT_HT2: DMA2 Channel2 half transfer flag.
* DMA2_IT_TE2: DMA2 Channel2 transfer error flag.
* DMA2_IT_GL3: DMA2 Channel3 global flag.
* DMA2_IT_TC3: DMA2 Channel3 transfer complete flag.
* DMA2_IT_HT3: DMA2 Channel3 half transfer flag.
* DMA2_IT_TE3: DMA2 Channel3 transfer error flag.
* DMA2_IT_GL4: DMA2 Channel4 global flag.
* DMA2_IT_TC4: DMA2 Channel4 transfer complete flag.
* DMA2_IT_HT4: DMA2 Channel4 half transfer flag.
* DMA2_IT_TE4: DMA2 Channel4 transfer error flag.
* DMA2_IT_GL5: DMA2 Channel5 global flag.
* DMA2_IT_TC5: DMA2 Channel5 transfer complete flag.
* DMA2_IT_HT5: DMA2 Channel5 half transfer flag.
* DMA2_IT_TE5: DMA2 Channel5 transfer error flag.
* Return : None
*********************************************************************************/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
DMA2->INTFCR = DMAy_IT;
}
else
{
DMA1->INTFCR = DMAy_IT;
}
}

158
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_exti.c Normal file
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@@ -0,0 +1,158 @@
/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_exti.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the EXTI firmware functions.
***************************************************************************************/
#include "ch32f10x_exti.h"
/* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000)
/********************************************************************************
* Function Name : EXTI_DeInit
* Description : Deinitializes the EXTI peripheral registers to their default
* reset values.
* Input : None
* Return : None
*********************************************************************************/
void EXTI_DeInit(void)
{
EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
}
/********************************************************************************
* Function Name : EXTI_Init
* Description : Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* Input : EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* Return : None
*********************************************************************************/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/********************************************************************************
* Function Name : EXTI_StructInit
* Description : Fills each EXTI_InitStruct member with its reset value.
* Input : EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* Return : None
*********************************************************************************/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/********************************************************************************
* Function Name : EXTI_GenerateSWInterrupt
* Description : Generates a Software interrupt.
* Input : EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* Return : None
*********************************************************************************/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
EXTI->SWIEVR |= EXTI_Line;
}
/********************************************************************************
* Function Name : EXTI_GetFlagStatus
* Description : Checks whether the specified EXTI line flag is set or not.
* Input : EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* Return : The new state of EXTI_Line (SET or RESET).
*********************************************************************************/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
if ((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : EXTI_ClearFlag
* Description : Clears the EXTI's line pending flags.
* Input : EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* Return : None
*********************************************************************************/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
/********************************************************************************
* Function Name : EXTI_GetITStatus
* Description : Checks whether the specified EXTI line is asserted or not.
* Input : EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* Return : The new state of EXTI_Line (SET or RESET).
*********************************************************************************/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line;
if (((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : EXTI_ClearITPendingBit
* Description : Clears the EXTI's line pending bits.
* Input : EXTI_Line: specifies the EXTI lines to be enabled or disabled.
* Return : None
*********************************************************************************/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}

775
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_flash.c Normal file
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@@ -0,0 +1,775 @@
/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_flash.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the FLASH firmware functions.
***************************************************************************************/
#include "ch32f10x_flash.h"
/* Flash Access Control Register bits */
#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
/* Flash Access Control Register bits */
#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
/* Flash Control Register bits */
#define CR_PG_Set ((uint32_t)0x00000001)
#define CR_PG_Reset ((uint32_t)0x00001FFE)
#define CR_PER_Set ((uint32_t)0x00000002)
#define CR_PER_Reset ((uint32_t)0x00001FFD)
#define CR_MER_Set ((uint32_t)0x00000004)
#define CR_MER_Reset ((uint32_t)0x00001FFB)
#define CR_OPTPG_Set ((uint32_t)0x00000010)
#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
#define CR_OPTER_Set ((uint32_t)0x00000020)
#define CR_OPTER_Reset ((uint32_t)0x00001FDF)
#define CR_STRT_Set ((uint32_t)0x00000040)
#define CR_LOCK_Set ((uint32_t)0x00000080)
/* FLASH Mask */
#define RDPRT_Mask ((uint32_t)0x00000002)
#define WRP0_Mask ((uint32_t)0x000000FF)
#define WRP1_Mask ((uint32_t)0x0000FF00)
#define WRP2_Mask ((uint32_t)0x00FF0000)
#define WRP3_Mask ((uint32_t)0xFF000000)
#define OB_USER_BFB2 ((uint16_t)0x0008)
/* FLASH Keys */
#define RDP_Key ((uint16_t)0x00A5)
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
/* FLASH BANK address */
#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00002000)
/********************************************************************************
* Function Name : FLASH_SetLatency
* Description : Sets the code latency value.
* Input : FLASH_Latency: specifies the FLASH Latency value.
* FLASH_Latency_0: FLASH Zero Latency cycle
* FLASH_Latency_1: FLASH One Latency cycle
* FLASH_Latency_2: FLASH Two Latency cycles
* Return : None
*********************************************************************************/
void FLASH_SetLatency(uint32_t FLASH_Latency)
{
uint32_t tmpreg = 0;
tmpreg = FLASH->ACTLR;
tmpreg &= ACR_LATENCY_Mask;
tmpreg |= FLASH_Latency;
FLASH->ACTLR = tmpreg;
}
/********************************************************************************
* Function Name : FLASH_HalfCycleAccessCmd
* Description : Enables or disables the Half cycle flash access.
* Input : FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
* FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
* FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
* Return : None
*********************************************************************************/
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
{
FLASH->ACTLR &= ACR_HLFCYA_Mask;
FLASH->ACTLR |= FLASH_HalfCycleAccess;
}
/********************************************************************************
* Function Name : FLASH_PrefetchBufferCmd
* Description : Enables or disables the Prefetch Buffer.
* Input : FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
* FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
* FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
* Return : None
*********************************************************************************/
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
{
FLASH->ACTLR &= ACR_PRFTBE_Mask;
FLASH->ACTLR |= FLASH_PrefetchBuffer;
}
/********************************************************************************
* Function Name : FLASH_Unlock
* Description : Unlocks the FLASH Program Erase Controller.
* Input : None
* Return : None
*********************************************************************************/
void FLASH_Unlock(void)
{
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/********************************************************************************
* Function Name : FLASH_UnlockBank1
* Description : Unlocks the FLASH Bank1 Program Erase Controller.
* equivalent to FLASH_Unlock function.
* Input : None
* Return : None
*********************************************************************************/
void FLASH_UnlockBank1(void)
{
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
/********************************************************************************
* Function Name : FLASH_Lock
* Description : Locks the FLASH Program Erase Controller.
* Input : None
* Return : None
*********************************************************************************/
void FLASH_Lock(void)
{
FLASH->CTLR |= CR_LOCK_Set;
}
/********************************************************************************
* Function Name : FLASH_LockBank1
* Description : Locks the FLASH Bank1 Program Erase Controller.
* Input : None
* Return : None
*********************************************************************************/
void FLASH_LockBank1(void)
{
FLASH->CTLR |= CR_LOCK_Set;
}
/********************************************************************************
* Function Name : FLASH_ErasePage
* Description : Erases a specified FLASH page.
* Input : Page_Address: The page address to be erased.
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR|= CR_PER_Set;
FLASH->ADDR = Page_Address;
FLASH->CTLR|= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
FLASH->CTLR &= CR_PER_Reset;
}
return status;
}
/********************************************************************************
* Function Name : FLASH_EraseAllPages
* Description : Erases all FLASH pages.
* Input : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_EraseAllPages(void)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_MER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
FLASH->CTLR &= CR_MER_Reset;
}
return status;
}
/********************************************************************************
* Function Name : FLASH_EraseAllBank1Pages
* Description : Erases all Bank1 FLASH pages.
* Input : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_EraseAllBank1Pages(void)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_MER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastBank1Operation(EraseTimeout);
FLASH->CTLR &= CR_MER_Reset;
}
return status;
}
/********************************************************************************
* Function Name : FLASH_EraseOptionBytes
* Description : Erases the FLASH option bytes.
* Input : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_EraseOptionBytes(void)
{
uint16_t rdptmp = RDP_Key;
FLASH_Status status = FLASH_COMPLETE;
if(FLASH_GetReadOutProtectionStatus() != RESET)
{
rdptmp = 0x00;
}
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR &= CR_OPTER_Reset;
FLASH->CTLR |= CR_OPTPG_Set;
OB->RDPR = (uint16_t)rdptmp;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
else
{
if (status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_ProgramWord
* Description : Programs a word at a specified address.
* Input : Address: specifies the address to be programmed.
* Data: specifies the data to be programmed.
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
__IO uint32_t tmp = 0;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_PG_Set;
*(__IO uint16_t*)Address = (uint16_t)Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
tmp = Address + 2;
*(__IO uint16_t*) tmp = Data >> 16;
status = FLASH_WaitForLastOperation(ProgramTimeout);
FLASH->CTLR &= CR_PG_Reset;
}
else
{
FLASH->CTLR &= CR_PG_Reset;
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_ProgramHalfWord
* Description : Programs a half word at a specified address.
* Input : Address: specifies the address to be programmed.
* Data: specifies the data to be programmed.
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_PG_Set;
*(__IO uint16_t*)Address = Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
FLASH->CTLR &= CR_PG_Reset;
}
return status;
}
/********************************************************************************
* Function Name : FLASH_ProgramOptionByteData
* Description : Programs a half word at a specified Option Byte Data address.
* Input : Address: specifies the address to be programmed.
* Data: specifies the data to be programmed.
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR |= CR_OPTPG_Set;
*(__IO uint16_t*)Address = Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_EnableWriteProtection
* Description : Write protects the desired pages
* Input : FLASH_Pages: specifies the address of the pages to be write protected.
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
{
uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
FLASH_Status status = FLASH_COMPLETE;
FLASH_Pages = (uint32_t)(~FLASH_Pages);
WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR |= CR_OPTPG_Set;
if(WRP0_Data != 0xFF)
{
OB->WRPR0 = WRP0_Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
{
OB->WRPR1 = WRP1_Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
{
OB->WRPR2 = WRP2_Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))
{
OB->WRPR3 = WRP3_Data;
status = FLASH_WaitForLastOperation(ProgramTimeout);
}
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_ReadOutProtection
* Description : Enables or disables the read out protection.
* Input : Newstate: new state of the ReadOut Protection(ENABLE or DISABLE).
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR &= CR_OPTER_Reset;
FLASH->CTLR |= CR_OPTPG_Set;
if(NewState != DISABLE)
{
OB->RDPR = 0x00;
}
else
{
OB->RDPR = RDP_Key;
}
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
else
{
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTER_Reset;
}
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_UserOptionByteConfig
* Description : Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
* Input : OB_IWDG: Selects the IWDG mode
* OB_IWDG_SW: Software IWDG selected
* OB_IWDG_HW: Hardware IWDG selected
* OB_STOP: Reset event when entering STOP mode.
* OB_STOP_NoRST: No reset generated when entering in STOP
* OB_STOP_RST: Reset generated when entering in STOP
* OB_STDBY: Reset event when entering Standby mode.
* OB_STDBY_NoRST: No reset generated when entering in STANDBY
* OB_STDBY_RST: Reset generated when entering in STANDBY
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
{
FLASH_Status status = FLASH_COMPLETE;
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR |= CR_OPTPG_Set;
OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
{
FLASH->CTLR &= CR_OPTPG_Reset;
}
}
return status;
}
/********************************************************************************
* Function Name : FLASH_GetUserOptionByte
* Description : Returns the FLASH User Option Bytes values.
* Input : None
* Return : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*********************************************************************************/
uint32_t FLASH_GetUserOptionByte(void)
{
return (uint32_t)(FLASH->OBR >> 2);
}
/********************************************************************************
* Function Name : FLASH_GetWriteProtectionOptionByte
* Description : Returns the FLASH Write Protection Option Bytes Register value.
* Input : None
* Return : The FLASH Write Protection Option Bytes Register value
*********************************************************************************/
uint32_t FLASH_GetWriteProtectionOptionByte(void)
{
return (uint32_t)(FLASH->WPR);
}
/********************************************************************************
* Function Name : FLASH_GetReadOutProtectionStatus
* Description : Checks whether the FLASH Read Out Protection Status is set or not.
* Input : None
* Return : FLASH ReadOut Protection Status(SET or RESET)
*********************************************************************************/
FlagStatus FLASH_GetReadOutProtectionStatus(void)
{
FlagStatus readoutstatus = RESET;
if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
{
readoutstatus = SET;
}
else
{
readoutstatus = RESET;
}
return readoutstatus;
}
/********************************************************************************
* Function Name : FLASH_GetPrefetchBufferStatus
* Description : Checks whether the FLASH Prefetch Buffer status is set or not.
* Input : None
* Return : FLASH Prefetch Buffer Status (SET or RESET).
*********************************************************************************/
FlagStatus FLASH_GetPrefetchBufferStatus(void)
{
FlagStatus bitstatus = RESET;
if ((FLASH->ACTLR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : FLASH_ITConfig
* Description : Enables or disables the specified FLASH interrupts.
* Input : FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
* FLASH_IT_ERROR: FLASH Error Interrupt
* FLASH_IT_EOP: FLASH end of operation Interrupt
* NewState: new state of the specified Flash interrupts(ENABLE or DISABLE).
* Return : FLASH Prefetch Buffer Status (SET or RESET).
*********************************************************************************/
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
FLASH->CTLR |= FLASH_IT;
}
else
{
FLASH->CTLR &= ~(uint32_t)FLASH_IT;
}
}
/********************************************************************************
* Function Name : FLASH_GetFlagStatus
* Description : Checks whether the specified FLASH flag is set or not.
* Input : FLASH_FLAG: specifies the FLASH flag to check.
* FLASH_FLAG_BSY: FLASH Busy flag
* FLASH_FLAG_PGERR: FLASH Program error flag
* FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* FLASH_FLAG_EOP: FLASH End of Operation flag
* FLASH_FLAG_OPTERR: FLASH Option Byte error flag
* Return : The new state of FLASH_FLAG (SET or RESET).
*********************************************************************************/
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
{
FlagStatus bitstatus = RESET;
if(FLASH_FLAG == FLASH_FLAG_OPTERR)
{
if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
else
{
if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
}
return bitstatus;
}
/********************************************************************************
* Function Name : FLASH_ClearFlag
* Description : Clears the FLASH's pending flags.
* Input : FLASH_FLAG: specifies the FLASH flags to clear.
* FLASH_FLAG_PGERR: FLASH Program error flag
* FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
* FLASH_FLAG_EOP: FLASH End of Operation flag
* Return : None
*********************************************************************************/
void FLASH_ClearFlag(uint32_t FLASH_FLAG)
{
FLASH->STATR = FLASH_FLAG;
}
/********************************************************************************
* Function Name : FLASH_GetStatus
* Description : Returns the FLASH Status.
* Input : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*********************************************************************************/
FLASH_Status FLASH_GetStatus(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0 )
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
return flashstatus;
}
/********************************************************************************
* Function Name : FLASH_GetBank1Status
* Description : Returns the FLASH Bank1 Status.
* Input : None
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*********************************************************************************/
FLASH_Status FLASH_GetBank1Status(void)
{
FLASH_Status flashstatus = FLASH_COMPLETE;
if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
{
flashstatus = FLASH_BUSY;
}
else
{
if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
{
flashstatus = FLASH_ERROR_PG;
}
else
{
if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )
{
flashstatus = FLASH_ERROR_WRP;
}
else
{
flashstatus = FLASH_COMPLETE;
}
}
}
return flashstatus;
}
/********************************************************************************
* Function Name : FLASH_WaitForLastOperation
* Description : Waits for a Flash operation to complete or a TIMEOUT to occur.
* Input : Timeout: FLASH programming Timeout
* Return : FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP or FLASH_COMPLETE.
*********************************************************************************/
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_GetBank1Status();
while((status == FLASH_BUSY) && (Timeout != 0x00))
{
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
return status;
}
/********************************************************************************
* Function Name : FLASH_WaitForLastBank1Operation
* Description : Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
* Input : Timeout: FLASH programming Timeout
* Return : FLASH Status: The returned value can be: FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*********************************************************************************/
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
{
FLASH_Status status = FLASH_COMPLETE;
status = FLASH_GetBank1Status();
while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
{
status = FLASH_GetBank1Status();
Timeout--;
}
if(Timeout == 0x00 )
{
status = FLASH_TIMEOUT;
}
return status;
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the GPIO firmware functions.
*******************************************************************************/
#include "ch32f10x_gpio.h"
#include "ch32f10x_rcc.h"
/* ------------ RCC registers bit address in the alias region ----------------*/
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- ECR Register -----*/
/* Alias word address of EVOE bit */
#define ECR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((uint8_t)0x07)
#define ECR_EVOE_BB (PERIPH_BB_BASE + (ECR_OFFSET * 32) + (EVOE_BitNumber * 4))
/* --- PCFR1 Register ---*/
/* Alias word address of MII_RMII_SEL bit */
#define PCFR1_OFFSET (AFIO_OFFSET + 0x04)
#define MII_RMII_SEL_BitNumber ((u8)0x17)
#define PCFR1_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PCFR1_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
/*******************************************************************************
* Function Name : GPIO_DeInit
* Description : Deinitializes the GPIOx peripheral registers to their default reset values.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Return : None
*******************************************************************************/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
if (GPIOx == GPIOA)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
}
else if (GPIOx == GPIOB)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
}
else if (GPIOx == GPIOC)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
}
else if (GPIOx == GPIOD)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
else if (GPIOx == GPIOE)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
}
else if (GPIOx == GPIOF)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
}
else
{
if (GPIOx == GPIOG)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
}
}
}
/*******************************************************************************
* Function Name : GPIO_AFIODeInit
* Description : Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset values.
* Input : None
* Return : None
*******************************************************************************/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*******************************************************************************
* Function Name : GPIO_Init
* Description : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Input : GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO peripheral.
* Return : None
*******************************************************************************/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
{
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
}
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CFGLR;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
}
else
{
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOx->CFGLR = tmpreg;
}
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CFGHR;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x08));
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
}
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CFGHR = tmpreg;
}
}
/*******************************************************************************
* Function Name : GPIO_StructInit
* Description : Fills each GPIO_InitStruct member with its default
* Input : GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* Return : None
*******************************************************************************/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputDataBit
* Description : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Input : GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Return : The input port pin value.
*******************************************************************************/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
if ((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadInputData
* Description : Reads the specified GPIO input data port.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Return : The output port pin value.
*******************************************************************************/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
return ((uint16_t)GPIOx->INDR);
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputDataBit
* Description : Reads the specified output data port bit.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* Return : The output port pin value.
*******************************************************************************/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
if ((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : GPIO_ReadOutputData
* Description : Reads the specified GPIO output data port.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* Return : GPIO output port pin value.
*******************************************************************************/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
return ((uint16_t)GPIOx->OUTDR);
}
/*******************************************************************************
* Function Name : GPIO_SetBits
* Description : Sets the selected data port bits.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* Return : None
*******************************************************************************/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIOx->BSHR = GPIO_Pin;
}
/*******************************************************************************
* Function Name : GPIO_ResetBits
* Description : Clears the selected data port bits.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* Return : None
*******************************************************************************/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIOx->BCR = GPIO_Pin;
}
/*******************************************************************************
* Function Name : GPIO_WriteBit
* Description : Sets or clears the selected data port bit.
* Input : GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* BitVal: specifies the value to be written to the selected bit.
* Bit_SetL: to clear the port pin.
* Bit_SetH: to set the port pin.
* Return : None
*******************************************************************************/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
if (BitVal != Bit_RESET)
{
GPIOx->BSHR = GPIO_Pin;
}
else
{
GPIOx->BCR = GPIO_Pin;
}
}
/*******************************************************************************
* Function Name : GPIO_Write
* Description : Writes data to the specified GPIO data port.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* PortVal: specifies the value to be written to the port output data register.
* Return : None
*******************************************************************************/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
GPIOx->OUTDR = PortVal;
}
/*******************************************************************************
* Function Name : GPIO_PinLockConfig
* Description : Locks GPIO Pins configuration registers.
* Input : GPIOx: where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* Return : None
*******************************************************************************/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
tmp |= GPIO_Pin;
GPIOx->LCKR = tmp;
GPIOx->LCKR = GPIO_Pin;
GPIOx->LCKR = tmp;
tmp = GPIOx->LCKR;
tmp = GPIOx->LCKR;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputConfig
* Description : Selects the GPIO pin used as Event output.
* Input : GPIO_PortSource: selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
* GPIO_PinSource: specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Return : None
*******************************************************************************/
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmpreg = 0x00;
tmpreg = AFIO->ECR;
tmpreg &= ECR_PORTPINCONFIG_MASK;
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->ECR = tmpreg;
}
/*******************************************************************************
* Function Name : GPIO_EventOutputCmd
* Description : Enables or disables the Event Output.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
*(__IO uint32_t *) ECR_EVOE_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : GPIO_PinRemapConfig
* Description : Changes the mapping of the specified pin.
* Input : GPIO_Remap: selects the pin to remap.
* GPIO_Remap_SPI1: SPI1 Alternate Function mapping
* GPIO_Remap_I2C1: I2C1 Alternate Function mapping
* GPIO_Remap_USART1: USART1 Alternate Function mapping
* GPIO_Remap_USART2: USART2 Alternate Function mapping
* GPIO_PartialRemap_USART3: USART3 Partial Alternate Function mapping
* GPIO_FullRemap_USART3: USART3 Full Alternate Function mapping
* GPIO_PartialRemap_TIM1: TIM1 Partial Alternate Function mapping
* GPIO_FullRemap_TIM1: TIM1 Full Alternate Function mapping
* GPIO_PartialRemap1_TIM2: TIM2 Partial1 Alternate Function mapping
* GPIO_PartialRemap2_TIM2: TIM2 Partial2 Alternate Function mapping
* GPIO_FullRemap_TIM2: TIM2 Full Alternate Function mapping
* GPIO_PartialRemap_TIM3: TIM3 Partial Alternate Function mapping
* GPIO_FullRemap_TIM3: TIM3 Full Alternate Function mapping
* GPIO_Remap_TIM4: TIM4 Alternate Function mapping
* GPIO_Remap1_CAN1: CAN1 Alternate Function mapping
* GPIO_Remap2_CAN1: CAN1 Alternate Function mapping
* GPIO_Remap_PD01: PD01 Alternate Function mapping
* GPIO_Remap_ADC1_ETRGINJ: ADC1 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC1_ETRGREG: ADC1 External Trigger Regular Conversion remapping
* GPIO_Remap_SWJ_NoJTRST: Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
* GPIO_Remap_SWJ_JTAGDisable: JTAG-DP Disabled and SW-DP Enabled
* GPIO_Remap_SWJ_Disable: Full SWJ Disabled (JTAG-DP + SW-DP)
* GPIO_Remap_TIM2ITR1_PTP_SOF: Ethernet PTP output or USB OTG SOF (Start of Frame)
* connected to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices).If the
* is enabled the TIM2 ITR1 is connected to Ethernet PTP output. When Reset TIM2 ITR1 is connected
* to USB OTG SOF output.
* GPIO_Remap_TIM1_DMA: TIM1 DMA requests mapping (only for Value line devices)
* GPIO_Remap_TIM67_DAC_DMA: TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
* GPIO_Remap_MISC: Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
* only for High density Value line devices)
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
{
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
tmpreg = AFIO->PCFR2;
}
else
{
tmpreg = AFIO->PCFR1;
}
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
{
tmpreg &= DBGAFR_SWJCFG_MASK;
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
}
else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
else
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
if (NewState != DISABLE)
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
}
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
AFIO->PCFR2 = tmpreg;
}
else
{
AFIO->PCFR1 = tmpreg;
}
}
/*******************************************************************************
* Function Name : GPIO_EXTILineConfig
* Description : Selects the GPIO pin used as EXTI Line.
* Input : GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* GPIO_PinSource: specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
* Return : None
*******************************************************************************/
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_i2c.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the I2C firmware functions.
*******************************************************************************/
#include "ch32f10x_i2c.h"
#include "ch32f10x_rcc.h"
/* I2C SPE mask */
#define CTLR1_PE_Set ((uint16_t)0x0001)
#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
/* I2C START mask */
#define CTLR1_START_Set ((uint16_t)0x0100)
#define CTLR1_START_Reset ((uint16_t)0xFEFF)
/* I2C STOP mask */
#define CTLR1_STOP_Set ((uint16_t)0x0200)
#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
/* I2C ACK mask */
#define CTLR1_ACK_Set ((uint16_t)0x0400)
#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
/* I2C ENGC mask */
#define CTLR1_ENGC_Set ((uint16_t)0x0040)
#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
/* I2C SWRST mask */
#define CTLR1_SWRST_Set ((uint16_t)0x8000)
#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
/* I2C PEC mask */
#define CTLR1_PEC_Set ((uint16_t)0x1000)
#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
/* I2C ENPEC mask */
#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
/* I2C ENARP mask */
#define CTLR1_ENARP_Set ((uint16_t)0x0010)
#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
/* I2C NOSTRETCH mask */
#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
/* I2C registers Masks */
#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
/* I2C DMAEN mask */
#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
/* I2C LAST mask */
#define CTLR2_LAST_Set ((uint16_t)0x1000)
#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
/* I2C FREQ mask */
#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
/* I2C ADD0 mask */
#define OADDR1_ADD0_Set ((uint16_t)0x0001)
#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
/* I2C ENDUAL mask */
#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
/* I2C ADD2 mask */
#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
/* I2C F/S mask */
#define CKCFGR_FS_Set ((uint16_t)0x8000)
/* I2C CCR mask */
#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
/* I2C FLAG mask */
#define FLAG_Mask ((uint32_t)0x00FFFFFF)
/* I2C Interrupt Enable mask */
#define ITEN_Mask ((uint32_t)0x07000000)
/*******************************************************************************
* Function Name : I2C_DeInit
* Description : Deinitializes the I2Cx peripheral registers to their default
* reset values.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Return : None
*******************************************************************************/
void I2C_DeInit(I2C_TypeDef* I2Cx)
{
if (I2Cx == I2C1)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
}
else
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
}
}
/*******************************************************************************
* Function Name : I2C_Init
* Description : Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
* contains the configuration information for the specified I2C peripheral.
* Return : None
*******************************************************************************/
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
{
uint16_t tmpreg = 0, freqrange = 0;
uint16_t result = 0x04;
uint32_t pclk1 = 8000000;
RCC_ClocksTypeDef rcc_clocks;
/*---------------------------- I2Cx CR2 Configuration ------------------------*/
tmpreg = I2Cx->CTLR2;
tmpreg &= CTLR2_FREQ_Reset;
RCC_GetClocksFreq(&rcc_clocks);
pclk1 = rcc_clocks.PCLK1_Frequency;
freqrange = (uint16_t)(pclk1 / 1000000);
tmpreg |= freqrange;
I2Cx->CTLR2 = tmpreg;
/*---------------------------- I2Cx CCR Configuration ------------------------*/
I2Cx->CTLR1 &= CTLR1_PE_Reset;
tmpreg = 0;
if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
if (result < 0x04)
{
result = 0x04;
}
tmpreg |= result;
I2Cx->RTR = freqrange + 1;
}
else
{
if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
}
else
{
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
result |= I2C_DutyCycle_16_9;
}
if ((result & CKCFGR_CCR_Set) == 0)
{
result |= (uint16_t)0x0001;
}
tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
}
I2Cx->CKCFGR = tmpreg;
I2Cx->CTLR1 |= CTLR1_PE_Set;
/*---------------------------- I2Cx CR1 Configuration ------------------------*/
tmpreg = I2Cx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
I2Cx->CTLR1 = tmpreg;
/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
}
/*******************************************************************************
* Function Name : I2C_StructInit
* Description : Fills each I2C_InitStruct member with its default value.
* Input : I2C_InitStruct: pointer to an I2C_InitTypeDef structure which
* will be initialized.
* Return : None
*******************************************************************************/
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
{
/*---------------- Reset I2C init structure parameters values ----------------*/
I2C_InitStruct->I2C_ClockSpeed = 5000;
I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
I2C_InitStruct->I2C_OwnAddress1 = 0;
I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
}
/*******************************************************************************
* Function Name : I2C_Cmd
* Description : Enables or disables the specified I2C peripheral.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_PE_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_PE_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_DMACmd
* Description : Enables or disables the specified I2C DMA requests.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
}
else
{
I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_DMALastTransferCmd
* Description : Specifies if the next DMA transfer will be the last one.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR2 |= CTLR2_LAST_Set;
}
else
{
I2Cx->CTLR2 &= CTLR2_LAST_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_GenerateSTART
* Description : Generates I2Cx communication START condition.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_START_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_START_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_GenerateSTOP
* Description : Generates I2Cx communication STOP condition.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_STOP_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_STOP_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_AcknowledgeConfig
* Description : Enables or disables the specified I2C acknowledge feature.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ACK_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ACK_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_OwnAddress2Config
* Description : Configures the specified I2C own address2.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Address: specifies the 7bit I2C own address2.
* Return : None
*******************************************************************************/
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
{
uint16_t tmpreg = 0;
tmpreg = I2Cx->OADDR2;
tmpreg &= OADDR2_ADD2_Reset;
tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
I2Cx->OADDR2 = tmpreg;
}
/*******************************************************************************
* Function Name : I2C_DualAddressCmd
* Description : Enables or disables the specified I2C dual addressing mode.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
}
else
{
I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_GeneralCallCmd
* Description : Enables or disables the specified I2C general call feature.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENGC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_ITConfig
* Description : Enables or disables the specified I2C interrupts.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
* I2C_IT_BUF: Buffer interrupt mask.
* I2C_IT_EVT: Event interrupt mask.
* I2C_IT_ERR: Error interrupt mask.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR2 |= I2C_IT;
}
else
{
I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
}
}
/*******************************************************************************
* Function Name : I2C_SendData
* Description : Sends a data byte through the I2Cx peripheral.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Data: Byte to be transmitted.
* Return : None
*******************************************************************************/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
{
I2Cx->DATAR = Data;
}
/*******************************************************************************
* Function Name : I2C_ReceiveData
* Description : Returns the most recent received data by the I2Cx peripheral.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Return : The value of the received data.
*******************************************************************************/
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
{
return (uint8_t)I2Cx->DATAR;
}
/*******************************************************************************
* Function Name : I2C_Send7bitAddress
* Description : Transmits the address byte to select the slave device.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Address: specifies the slave address which will be transmitted.
* I2C_Direction: specifies whether the I2C device will be a
* Transmitter or a Receiver.
* I2C_Direction_Transmitter: Transmitter mode.
* I2C_Direction_Receiver: Receiver mode.
* Return : None
*******************************************************************************/
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
{
if (I2C_Direction != I2C_Direction_Transmitter)
{
Address |= OADDR1_ADD0_Set;
}
else
{
Address &= OADDR1_ADD0_Reset;
}
I2Cx->DATAR = Address;
}
/*******************************************************************************
* Function Name : I2C_ReadRegister
* Description : Reads the specified I2C register and returns its value.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_Register: specifies the register to read.
* I2C_Register_CTLR1.
* I2C_Register_CTLR2.
* I2C_Register_OADDR1.
* I2C_Register_OADDR2.
* I2C_Register_DATAR.
* I2C_Register_STAR1.
* I2C_Register_STAR2.
* I2C_Register_CKCFGR.
* I2C_Register_RTR.
* Return : The value of the received data.
*******************************************************************************/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t) I2Cx;
tmp += I2C_Register;
return (*(__IO uint16_t *) tmp);
}
/*******************************************************************************
* Function Name : I2C_SoftwareResetCmd
* Description : Enables or disables the specified I2C software reset.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_SWRST_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_NACKPositionConfig
* Description : Selects the specified I2C NACK position in master receiver mode.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_NACKPosition: specifies the NACK position.
* I2C_NACKPosition_Next: indicates that the next byte will be
* the last received byte.
* I2C_NACKPosition_Current: indicates that current byte is the
* last received byte.
* Return : None
*******************************************************************************/
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
{
if (I2C_NACKPosition == I2C_NACKPosition_Next)
{
I2Cx->CTLR1 |= I2C_NACKPosition_Next;
}
else
{
I2Cx->CTLR1 &= I2C_NACKPosition_Current;
}
}
/*******************************************************************************
* Function Name : I2C_SMBusAlertConfig
* Description : Drives the SMBusAlert pin high or low for the specified I2C.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_SMBusAlert: specifies SMBAlert pin level.
* I2C_SMBusAlert_Low: SMBAlert pin driven low.
* I2C_SMBusAlert_High: SMBAlert pin driven high.
* Return : None
*******************************************************************************/
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
{
if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
{
I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
}
else
{
I2Cx->CTLR1 &= I2C_SMBusAlert_High;
}
}
/*******************************************************************************
* Function Name : I2C_TransmitPEC
* Description : Enables or disables the specified I2C PEC transfer.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_PEC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_PEC_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_PECPositionConfig
* Description : Selects the specified I2C PEC position.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_PECPosition: specifies the PEC position.
* I2C_PECPosition_Next: indicates that the next byte is PEC.
* I2C_PECPosition_Current: indicates that current byte is PEC.
* Return : None
*******************************************************************************/
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
{
if (I2C_PECPosition == I2C_PECPosition_Next)
{
I2Cx->CTLR1 |= I2C_PECPosition_Next;
}
else
{
I2Cx->CTLR1 &= I2C_PECPosition_Current;
}
}
/*******************************************************************************
* Function Name : I2C_CalculatePEC
* Description : Enables or disables the PEC value calculation of the transferred bytes.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_GetPEC
* Description : Returns the PEC value for the specified I2C.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Return : The PEC value.
*******************************************************************************/
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
{
return ((I2Cx->STAR2) >> 8);
}
/*******************************************************************************
* Function Name : I2C_ARPCmd
* Description : Enables or disables the specified I2C ARP.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : The PEC value.
*******************************************************************************/
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
I2Cx->CTLR1 |= CTLR1_ENARP_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_StretchClockCmd
* Description : Enables or disables the specified I2C Clock stretching.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if (NewState == DISABLE)
{
I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
}
else
{
I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
}
}
/*******************************************************************************
* Function Name : I2C_FastModeDutyCycleConfig
* Description : Selects the specified I2C fast mode duty cycle.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_DutyCycle: specifies the fast mode duty cycle.
* I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2.
* I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9.
* Return : None
*******************************************************************************/
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
{
if (I2C_DutyCycle != I2C_DutyCycle_16_9)
{
I2Cx->CKCFGR &= I2C_DutyCycle_2;
}
else
{
I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
}
}
/**
****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* depending on the application requirements and constraints:
*
*
* 1) Basic state monitoring:
* Using I2C_CheckEvent() function:
* It compares the status registers (SR1 and SR2) content to a given event
* (can be the combination of one or more flags).
* It returns SUCCESS if the current status includes the given flags
* and returns ERROR if one or more flags are missing in the current status.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (RM0008).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs (ie. error flags are set besides to the monitored flags),
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* hold or corrupted real state.
* In this case, it is advised to use error interrupts to monitor the error
* events and handle them in the interrupt IRQ handler.
*
* @note
* For error management, it is advised to use the following functions:
* - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()
* in order to determine which error occured.
* - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
* and/or I2C_GenerateStop() in order to clear the error flag and source,
* and return to correct communication status.
*
*
* 2) Advanced state monitoring:
* Using the function I2C_GetLastEvent() which returns the image of both status
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
* by 16 bits and concatenated to Status Register 1).
* - When to use:
* - This function is suitable for the same applications above but it allows to
* overcome the mentioned limitation of I2C_GetFlagStatus() function.
* The returned value could be compared to events already defined in the
* library (ch32f10x_i2c.h) or to custom values defined by user.
* - This function is suitable when multiple flags are monitored at the same time.
* - At the opposite of I2C_CheckEvent() function, this function allows user to
* choose when an event is accepted (when all events flags are set and no
* other flags are set or just when the needed flags are set like
* I2C_CheckEvent() function).
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* 3) Flag-based state monitoring:
* Using the function I2C_GetFlagStatus() which simply returns the status of
* one single flag (ie. I2C_FLAG_RXNE ...).
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed (most I2C events
* are monitored through multiple flags).
* - Limitations:
* - When calling this function, the Status register is accessed. Some flags are
* cleared when the status register is accessed. So checking the status
* of one Flag, may clear other ones.
* - Function may need to be called twice or more in order to monitor one
* single event.
*
* For detailed description of Events, please refer to section I2C_Events in
* ch32f10x_i2c.h file.
*
*/
/**
*
* 1) Basic state monitoring
*******************************************************************************
*/
/*******************************************************************************
* Function Name : I2C_CheckEvent
* Description : Checks whether the last I2Cx Event is equal to the one passed
* as parameter.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_EVENT: specifies the event to be checked.
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1.
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1.
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1.
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1.
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1.
* I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2.
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3.
* I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2.
* I2C_EVENT_SLAVE_STOP_DETECTED : EV4.
* I2C_EVENT_MASTER_MODE_SELECT : EV5.
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6.
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6.
* I2C_EVENT_MASTER_BYTE_RECEIVED : EV7.
* I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8.
* I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2.
* I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9.
* Return : ErrorStatus: SUCCESS or ERROR.
*******************************************************************************/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
ErrorStatus status = ERROR;
flag1 = I2Cx->STAR1;
flag2 = I2Cx->STAR2;
flag2 = flag2 << 16;
lastevent = (flag1 | flag2) & FLAG_Mask;
if ((lastevent & I2C_EVENT) == I2C_EVENT)
{
status = SUCCESS;
}
else
{
status = ERROR;
}
return status;
}
/**
*
* 2) Advanced state monitoring
*******************************************************************************
*/
/*******************************************************************************
* Function Name : I2C_GetLastEvent
* Description : Returns the last I2Cx Event.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* Return : The last event.
*******************************************************************************/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0, flag2 = 0;
flag1 = I2Cx->STAR1;
flag2 = I2Cx->STAR2;
flag2 = flag2 << 16;
lastevent = (flag1 | flag2) & FLAG_Mask;
return lastevent;
}
/**
*
* 3) Flag-based state monitoring
*******************************************************************************
*/
/*******************************************************************************
* Function Name : I2C_GetFlagStatus
* Description : Checks whether the last I2Cx Event is equal to the one passed
* as parameter.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_FLAG: specifies the flag to check.
* I2C_FLAG_DUALF: Dual flag (Slave mode).
* I2C_FLAG_SMBHOST: SMBus host header (Slave mode).
* I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode).
* I2C_FLAG_GENCALL: General call header flag (Slave mode).
* I2C_FLAG_TRA: Transmitter/Receiver flag.
* I2C_FLAG_BUSY: Bus busy flag.
* I2C_FLAG_MSL: Master/Slave flag.
* I2C_FLAG_SMBALERT: SMBus Alert flag.
* I2C_FLAG_TIMEOUT: Timeout or Tlow error flag.
* I2C_FLAG_PECERR: PEC error in reception flag.
* I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode).
* I2C_FLAG_AF: Acknowledge failure flag.
* I2C_FLAG_ARLO: Arbitration lost flag (Master mode).
* I2C_FLAG_BERR: Bus error flag.
* I2C_FLAG_TXE: Data register empty flag (Transmitter).
* I2C_FLAG_RXNE: Data register not empty (Receiver) flag.
* I2C_FLAG_STOPF: Stop detection flag (Slave mode).
* I2C_FLAG_ADD10: 10-bit header sent flag (Master mode).
* I2C_FLAG_BTF: Byte transfer finished flag.
* I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
* Address matched flag (Slave mode)"ENDA".
* I2C_FLAG_SB: Start bit flag (Master mode).
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
{
FlagStatus bitstatus = RESET;
__IO uint32_t i2creg = 0, i2cxbase = 0;
i2cxbase = (uint32_t)I2Cx;
i2creg = I2C_FLAG >> 28;
I2C_FLAG &= FLAG_Mask;
if(i2creg != 0)
{
i2cxbase += 0x14;
}
else
{
I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
i2cxbase += 0x18;
}
if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : I2C_ClearFlag
* Description : Clears the I2Cx's pending flags.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_FLAG: specifies the flag to clear.
* I2C_FLAG_SMBALERT: SMBus Alert flag.
* I2C_FLAG_TIMEOUT: Timeout or Tlow error flag.
* I2C_FLAG_PECERR: PEC error in reception flag.
* I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode).
* I2C_FLAG_AF: Acknowledge failure flag.
* I2C_FLAG_ARLO: Arbitration lost flag (Master mode).
* I2C_FLAG_BERR: Bus error flag.
* Return : None
*******************************************************************************/
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
{
uint32_t flagpos = 0;
flagpos = I2C_FLAG & FLAG_Mask;
I2Cx->STAR1 = (uint16_t)~flagpos;
}
/*******************************************************************************
* Function Name : I2C_GetITStatus
* Description : Checks whether the specified I2C interrupt has occurred or not.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* II2C_IT: specifies the interrupt source to check.
* I2C_IT_SMBALERT: SMBus Alert flag.
* I2C_IT_TIMEOUT: Timeout or Tlow error flag.
* I2C_IT_PECERR: PEC error in reception flag.
* I2C_IT_OVR: Overrun/Underrun flag (Slave mode).
* I2C_IT_AF: Acknowledge failure flag.
* I2C_IT_ARLO: Arbitration lost flag (Master mode).
* I2C_IT_BERR: Bus error flag.
* I2C_IT_TXE: Data register empty flag (Transmitter).
* I2C_IT_RXNE: Data register not empty (Receiver) flag.
* I2C_IT_STOPF: Stop detection flag (Slave mode).
* I2C_IT_ADD10: 10-bit header sent flag (Master mode).
* I2C_IT_BTF: Byte transfer finished flag.
* I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" Address matched
* flag (Slave mode)"ENDAD".
* I2C_IT_SB: Start bit flag (Master mode).
* Return : None
*******************************************************************************/
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)) ;
I2C_IT &= FLAG_Mask;
if (((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : I2C_ClearITPendingBit
* Description : Clears the I2Cx<43>s interrupt pending bits.
* Input : I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* I2C_IT: specifies the interrupt pending bit to clear.
* I2C_IT_SMBALERT: SMBus Alert interrupt.
* I2C_IT_TIMEOUT: Timeout or Tlow error interrupt.
* I2C_IT_PECERR: PEC error in reception interrupt.
* I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode).
* I2C_IT_AF: Acknowledge failure interrupt.
* I2C_IT_ARLO: Arbitration lost interrupt (Master mode).
* I2C_IT_BERR: Bus error interrupt.
* Return : None
*******************************************************************************/
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
uint32_t flagpos = 0;
flagpos = I2C_IT & FLAG_Mask;
I2Cx->STAR1 = (uint16_t)~flagpos;
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the IWDG firmware functions.
*******************************************************************************/
#include "ch32f10x_iwdg.h"
/* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/*******************************************************************************
* Function Name : IWDG_WriteAccessCmd
* Description : Enables or disables write access to IWDG_PR and IWDG_RLR registers.
* Input : WDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and
* IWDG_RLR registers.
* IWDG_WriteAccess_Disable: Disable write access to IWDG_PR
* and IWDG_RLR registers.
* Return : None
*******************************************************************************/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/*******************************************************************************
* Function Name : IWDG_SetPrescaler
* Description : Sets IWDG Prescaler value.
* Input : IWDG_Prescaler: specifies the IWDG Prescaler value.
* IWDG_Prescaler_4: IWDG prescaler set to 4.
* IWDG_Prescaler_8: IWDG prescaler set to 8.
* IWDG_Prescaler_16: IWDG prescaler set to 16.
* IWDG_Prescaler_32: IWDG prescaler set to 32.
* IWDG_Prescaler_64: IWDG prescaler set to 64.
* IWDG_Prescaler_128: IWDG prescaler set to 128.
* IWDG_Prescaler_256: IWDG prescaler set to 256.
* Return : None
*******************************************************************************/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
IWDG->PSCR = IWDG_Prescaler;
}
/*******************************************************************************
* Function Name : IWDG_SetReload
* Description : Sets IWDG Reload value.
* Input : Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* Return : None
*******************************************************************************/
void IWDG_SetReload(uint16_t Reload)
{
IWDG->RLDR = Reload;
}
/*******************************************************************************
* Function Name : IWDG_ReloadCounter
* Description : Reloads IWDG counter with value defined in the reload register.
* Input : None
* Return : None
*******************************************************************************/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_Reload;
}
/*******************************************************************************
* Function Name : IWDG_Enable
* Description : Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
* Input : None
* Return : None
*******************************************************************************/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
}
/*******************************************************************************
* Function Name : IWDG_GetFlagStatus
* Description : Checks whether the specified IWDG flag is set or not.
* Input : IWDG_FLAG: specifies the flag to check.
* IWDG_FLAG_PVU: Prescaler Value Update on going.
* IWDG_FLAG_RVU: Reload Value Update on going.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
if ((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}

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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_misc.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
****************************************************************************************/
#include "ch32f10x_misc.h"
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/******************************************************************************************
* Function Name : NVIC_PriorityGroupConfig
* Description : Configures the priority grouping: pre-emption priority and subpriority.
* Input : NVIC_PriorityGroup: specifies the priority grouping bits length.
* NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* Return : None
*******************************************************************************************/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/******************************************************************************************
* Function Name : NVIC_Init
* Description : Initializes the NVIC peripheral according to the specified parameters in
* the NVIC_InitStruct.
* Input : NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
* Return : None
*******************************************************************************************/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority */
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels */
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels */
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/******************************************************************************************
* Function Name : NVIC_SetVectorTable
* Description : ISets the vector table location and Offset.
* Input : NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.The
* value can be NVIC_VectTab_RAM or NVIC_VectTab_FLASH.
* Offset : Vector Table base offset field. This value must be a multiple
* of 0x200.
* Return : None
*******************************************************************************************/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/******************************************************************************************
* Function Name : NVIC_SystemLPConfig
* Description : Selects the condition for the system to enter low power mode.
* Input : LowPowerMode: Specifies the new mode for the system to enter low power mode.
* NVIC_LP_SEVONPEND
* NVIC_LP_SLEEPDEEP
* NVIC_LP_SLEEPONEXIT
* NewState : new state of LP condition. This parameter can be: ENABLE or DISABLE.
* Return : None
*******************************************************************************************/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/******************************************************************************************
* Function Name : SysTick_CLKSourceConfig
* Description : Configures the SysTick clock source.
* Input : SysTick_CLKSource: Specifies the new mode for the system to enter low power mode.
* ysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* Return : None
*******************************************************************************************/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}

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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_pwr.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the PWR firmware functions.
***************************************************************************************/
#include "ch32f10x_pwr.h"
#include "ch32f10x_rcc.h"
/* PWR registers bit address in the alias region */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* CTLR Register */
/* Alias word address of DBP bit */
#define CTLR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CTLR_DBP_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CTLR_PVDE_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* CSR Register */
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* PWR registers bit mask */
/* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/********************************************************************************
* Function Name : PWR_DeInit
* Description : Deinitializes the PWR peripheral registers to their default
* reset values.
* Input : None
* Return : None
*********************************************************************************/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/********************************************************************************
* Function Name : PWR_BackupAccessCmd
* Description : Enables or disables access to the RTC and backup registers.
* Input : NewState: new state of the access to the RTC and backup registers,
* This parameter can be: ENABLE or DISABLE.
* Return : None
*********************************************************************************/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
*(__IO uint32_t *) CTLR_DBP_BB = (uint32_t)NewState;
}
/********************************************************************************
* Function Name : PWR_PVDCmd
* Description : Enables or disables the Power Voltage Detector(PVD).
* Input : NewState: new state of the PVD(ENABLE or DISABLE).
* Return : None
*********************************************************************************/
void PWR_PVDCmd(FunctionalState NewState)
{
*(__IO uint32_t *) CTLR_PVDE_BB = (uint32_t)NewState;
}
/********************************************************************************
* Function Name : PWR_PVDLevelConfig
* Description : Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
* Input : PWR_PVDLevel: specifies the PVD detection level
* PWR_PVDLevel_2V2: PVD detection level set to 2.2V
* PWR_PVDLevel_2V3: PVD detection level set to 2.3V
* PWR_PVDLevel_2V4: PVD detection level set to 2.4V
* PWR_PVDLevel_2V5: PVD detection level set to 2.5V
* PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* PWR_PVDLevel_2V7: PVD detection level set to 2.7V
* PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* PWR_PVDLevel_2V9: PVD detection level set to 2.9V
* Return : None
*********************************************************************************/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_PLS_MASK;
tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg;
}
/********************************************************************************
* Function Name : PWR_WakeUpPinCmd
* Description : Enables or disables the WakeUp Pin functionality.
* Input : NewState: new state of the WakeUp Pin functionality(ENABLE or DISABLE).
* Return : None
*********************************************************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
}
/********************************************************************************
* Function Name : PWR_EnterSTOPMode
* Description : Enters STOP mode.
* Input : PWR_Regulator: specifies the regulator state in STOP mode.
* PWR_Regulator_ON: STOP mode with regulator ON
* PWR_Regulator_LowPower: STOP mode with regulator in low power mode
* PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* Return : None
*********************************************************************************/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK;
tmpreg |= PWR_Regulator;
PWR->CTLR = tmpreg;
SCB->SCR |= SCB_SCR_SLEEPDEEP;
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
__WFI();
}
else
{
__WFE();
}
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
}
/********************************************************************************
* Function Name : PWR_EnterSTANDBYMode
* Description : Enters STANDBY mode.
* Input : None
* Return : None
*********************************************************************************/
void PWR_EnterSTANDBYMode(void)
{
PWR->CTLR |= PWR_CTLR_CWUF;
PWR->CTLR |= PWR_CTLR_PDDS;
SCB->SCR |= SCB_SCR_SLEEPDEEP;
#if defined ( __CC_ARM )
__force_stores();
#endif
__WFI();
}
/********************************************************************************
* Function Name : PWR_GetFlagStatus
* Description : Checks whether the specified PWR flag is set or not.
* Input : PWR_FLAG: specifies the flag to check.
* PWR_FLAG_WU: Wake Up flag
* PWR_FLAG_SB: StandBy flag
* PWR_FLAG_PVDO: PVD Output
* Return : The new state of PWR_FLAG (SET or RESET).
*********************************************************************************/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : PWR_ClearFlag
* Description : Clears the PWR's pending flags.
* Input : PWR_FLAG: specifies the flag to clear.
* PWR_FLAG_WU: Wake Up flag
* PWR_FLAG_SB: StandBy flag
* Return : None
*********************************************************************************/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
PWR->CTLR |= PWR_FLAG << 2;
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_rcc.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the RCC firmware functions.
*******************************************************************************/
#include "ch32f10x_rcc.h"
/* ------------ RCC registers bit address in the alias region ----------- */
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
/* --- CTLR Register ---*/
/* Alias word address of HSION bit */
#define CTLR_OFFSET (RCC_OFFSET + 0x00)
#define HSION_BitNumber 0x00
#define CTLR_HSION_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (HSION_BitNumber * 4))
/* Alias word address of PLLON bit */
#define PLLON_BitNumber 0x18
#define CTLR_PLLON_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (PLLON_BitNumber * 4))
/* Alias word address of CSSON bit */
#define CSSON_BitNumber 0x13
#define CTLR_CSSON_BB (PERIPH_BB_BASE + (CTLR_OFFSET * 32) + (CSSON_BitNumber * 4))
/* --- CFGR0 Register ---*/
/* Alias word address of USBPRE bit */
#define CFGR0_OFFSET (RCC_OFFSET + 0x04)
#define USBPRE_BitNumber 0x16
#define CFGR0_USBPRE_BB (PERIPH_BB_BASE + (CFGR0_OFFSET * 32) + (USBPRE_BitNumber * 4))
/* --- BDCTLR Register ---*/
/* Alias word address of RTCEN bit */
#define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
#define RTCEN_BitNumber 0x0F
#define BDCTLR_RTCEN_BB (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (RTCEN_BitNumber * 4))
/* Alias word address of BDRST bit */
#define BDRST_BitNumber 0x10
#define BDCTLR_BDRST_BB (PERIPH_BB_BASE + (BDCTLR_OFFSET * 32) + (BDRST_BitNumber * 4))
/* --- RSTSCKR Register ---*/
/* Alias word address of LSION bit */
#define RSTSCKR_OFFSET (RCC_OFFSET + 0x24)
#define LSION_BitNumber 0x00
#define RSTSCKR_LSION_BB (PERIPH_BB_BASE + (RSTSCKR_OFFSET * 32) + (LSION_BitNumber * 4))
/* ---------------------- RCC registers bit mask ------------------------ */
/* CTLR register bit mask */
#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
#define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
#define CTLR_HSEON_Set ((uint32_t)0x00010000)
#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
#define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
/* RSTSCKR register bit mask */
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
/* RCC Flag Mask */
#define FLAG_Mask ((uint8_t)0x1F)
/* INTR register byte 2 (Bits[15:8]) base address */
#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
/* INTR register byte 3 (Bits[23:16]) base address */
#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
/* CFGR0 register byte 4 (Bits[31:24]) base address */
#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
/* BDCTLR register base address */
#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
/*******************************************************************************
* Function Name : RCC_DeInit
* Description : Resets the RCC clock configuration to the default reset state.
* Input : None
* Return : None
*******************************************************************************/
void RCC_DeInit(void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->INTR = 0x009F0000;
}
/*******************************************************************************
* Function Name : RCC_HSEConfig
* Description : Configures the External High Speed oscillator (HSE).
* Input : RCC_HSE:
* RCC_HSE_OFF: HSE oscillator OFF.
* RCC_HSE_ON: HSE oscillator ON.
* RCC_HSE_Bypass: HSE oscillator bypassed with external clock.
* Return : None
*******************************************************************************/
void RCC_HSEConfig(uint32_t RCC_HSE)
{
RCC->CTLR &= CTLR_HSEON_Reset;
RCC->CTLR &= CTLR_HSEBYP_Reset;
switch(RCC_HSE)
{
case RCC_HSE_ON:
RCC->CTLR |= CTLR_HSEON_Set;
break;
case RCC_HSE_Bypass:
RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : RCC_WaitForHSEStartUp
* Description : Configures the External High Speed oscillator (HSE).
* Input : None
* Return : SUCCESS: HSE oscillator is stable and ready to use.
* ERROR: HSE oscillator not yet ready.
*******************************************************************************/
ErrorStatus RCC_WaitForHSEStartUp(void)
{
__IO uint32_t StartUpCounter = 0;
ErrorStatus status = ERROR;
FlagStatus HSEStatus = RESET;
do
{
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
StartUpCounter++;
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
{
status = SUCCESS;
}
else
{
status = ERROR;
}
return (status);
}
/*******************************************************************************
* Function Name : RCC_AdjustHSICalibrationValue
* Description : Adjusts the Internal High Speed oscillator (HSI) calibration value.
* Input : HSICalibrationValue: specifies the calibration trimming value.
* This parameter must be a number between 0 and 0x1F.
* Return : None
*******************************************************************************/
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CTLR;
tmpreg &= CTLR_HSITRIM_Mask;
tmpreg |= (uint32_t)HSICalibrationValue << 3;
RCC->CTLR = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_HSICmd
* Description : Enables or disables the Internal High Speed oscillator (HSI).
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_HSICmd(FunctionalState NewState)
{
*(__IO uint32_t *) CTLR_HSION_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_PLLConfig
* Description : Configures the PLL clock source and multiplication factor.
* Input : RCC_PLLSource: specifies the PLL entry clock source.
* RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2
* selected as PLL clock entry.
* RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL
* clock entry.
* RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2
* selected as PLL clock entry.
* RCC_PLLMul: specifies the PLL multiplication factor.
* This parameter can be RCC_PLLMul_x where x:[2,16].
* Return : None
*******************************************************************************/
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_PLL_Mask;
tmpreg |= RCC_PLLSource | RCC_PLLMul;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_PLLCmd
* Description : Enables or disables the PLL.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_PLLCmd(FunctionalState NewState)
{
*(__IO uint32_t *) CTLR_PLLON_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_SYSCLKConfig
* Description : Configures the system clock (SYSCLK).
* Input : RCC_SYSCLKSource: specifies the clock source used as system clock.
* RCC_SYSCLKSource_HSI: HSI selected as system clock.
* RCC_SYSCLKSource_HSE: HSE selected as system clock.
* RCC_SYSCLKSource_PLLCLK: PLL selected as system clock.
* Return : None
*******************************************************************************/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_SW_Mask;
tmpreg |= RCC_SYSCLKSource;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_GetSYSCLKSource
* Description : Configures the system clock (SYSCLK).
* Input : None
* Return : 0x00: HSI used as system clock.
* 0x04: HSE used as system clock.
* 0x08: PLL used as system clock.
*******************************************************************************/
uint8_t RCC_GetSYSCLKSource(void)
{
return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
}
/*******************************************************************************
* Function Name : RCC_HCLKConfig
* Description : Configures the AHB clock (HCLK).
* Input : RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
* the system clock (SYSCLK).
* RCC_SYSCLK_Div1: AHB clock = SYSCLK.
* RCC_SYSCLK_Div2: AHB clock = SYSCLK/2.
* RCC_SYSCLK_Div4: AHB clock = SYSCLK/4.
* RCC_SYSCLK_Div8: AHB clock = SYSCLK/8.
* RCC_SYSCLK_Div16: AHB clock = SYSCLK/16.
* RCC_SYSCLK_Div64: AHB clock = SYSCLK/64.
* RCC_SYSCLK_Div128: AHB clock = SYSCLK/128.
* RCC_SYSCLK_Div256: AHB clock = SYSCLK/256.
* RCC_SYSCLK_Div512: AHB clock = SYSCLK/512.
* Return : None
*******************************************************************************/
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_HPRE_Reset_Mask;
tmpreg |= RCC_SYSCLK;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_PCLK1Config
* Description : Configures the Low Speed APB clock (PCLK1).
* Input : RCC_HCLK: defines the APB1 clock divider. This clock is derived from
* the AHB clock (HCLK).
* RCC_HCLK_Div1: APB1 clock = HCLK.
* RCC_HCLK_Div2: APB1 clock = HCLK/2.
* RCC_HCLK_Div4: APB1 clock = HCLK/4.
* RCC_HCLK_Div8: APB1 clock = HCLK/8.
* RCC_HCLK_Div16: APB1 clock = HCLK/16.
* Return : None
*******************************************************************************/
void RCC_PCLK1Config(uint32_t RCC_HCLK)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_PPRE1_Reset_Mask;
tmpreg |= RCC_HCLK;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_PCLK2Config
* Description : Configures the High Speed APB clock (PCLK2).
* Input : RCC_HCLK: defines the APB2 clock divider. This clock is derived from
* the AHB clock (HCLK).
* RCC_HCLK_Div1: APB2 clock = HCLK.
* RCC_HCLK_Div2: APB2 clock = HCLK/2.
* RCC_HCLK_Div4: APB2 clock = HCLK/4.
* RCC_HCLK_Div8: APB2 clock = HCLK/8.
* RCC_HCLK_Div16: APB2 clock = HCLK/16.
* Return : None
*******************************************************************************/
void RCC_PCLK2Config(uint32_t RCC_HCLK)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_PPRE2_Reset_Mask;
tmpreg |= RCC_HCLK << 3;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_ITConfig
* Description : Enables or disables the specified RCC interrupts.
* Input : RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
* RCC_IT_LSIRDY: LSI ready interrupt.
* RCC_IT_LSERDY: LSE ready interrupt.
* RCC_IT_HSIRDY: HSI ready interrupt.
* RCC_IT_HSERDY: HSE ready interrupt.
* RCC_IT_PLLRDY: PLL ready interrupt.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
{
if (NewState != DISABLE)
{
*(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT;
}
else
{
*(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
}
}
/*******************************************************************************
* Function Name : RCC_USBCLKConfig
* Description : Configures the USB clock (USBCLK).
* Input : RCC_USBCLKSource: specifies the USB clock source. This clock is
* derived from the PLL output.
* RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
* clock source.
* RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source.
* Return : None
*******************************************************************************/
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
{
*(__IO uint32_t *) CFGR0_USBPRE_BB = RCC_USBCLKSource;
}
/*******************************************************************************
* Function Name : RCC_ADCCLKConfig
* Description : Configures the ADC clock (ADCCLK).
* Input : RCC_PCLK2: defines the ADC clock divider. This clock is derived from
* the APB2 clock (PCLK2).
* RCC_PCLK2_Div2: ADC clock = PCLK2/2.
* RCC_PCLK2_Div4: ADC clock = PCLK2/4.
* RCC_PCLK2_Div6: ADC clock = PCLK2/6.
* RCC_PCLK2_Div8: ADC clock = PCLK2/8.
* Return : None
********************************************************************************/
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_ADCPRE_Reset_Mask;
tmpreg |= RCC_PCLK2;
RCC->CFGR0 = tmpreg;
}
/*******************************************************************************
* Function Name : RCC_LSEConfig
* Description : Configures the External Low Speed oscillator (LSE).
* Input : RCC_LSE: specifies the new state of the LSE.
* RCC_LSE_OFF: LSE oscillator OFF.
* RCC_LSE_ON: LSE oscillator ON.
* RCC_LSE_Bypass: LSE oscillator bypassed with external clock.
* Return : None
********************************************************************************/
void RCC_LSEConfig(uint8_t RCC_LSE)
{
*(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
*(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
switch(RCC_LSE)
{
case RCC_LSE_ON:
*(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON;
break;
case RCC_LSE_Bypass:
*(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
break;
default:
break;
}
}
/*******************************************************************************
* Function Name : RCC_LSICmd
* Description : Enables or disables the Internal Low Speed oscillator (LSI).
* Input : NewState: ENABLE or DISABLE.
* Return : None
********************************************************************************/
void RCC_LSICmd(FunctionalState NewState)
{
*(__IO uint32_t *) RSTSCKR_LSION_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_RTCCLKConfig
* Description : Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
* Input : RCC_RTCCLKSource: specifies the RTC clock source.
* RCC_RTCCLKSource_LSE: LSE selected as RTC clock.
* RCC_RTCCLKSource_LSI: LSI selected as RTC clock.
* RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock.
* Return : None
********************************************************************************/
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{
RCC->BDCTLR |= RCC_RTCCLKSource;
}
/*******************************************************************************
* Function Name : RCC_RTCCLKCmd
* Description : This function must be used only after the RTC clock was selected
* using the RCC_RTCCLKConfig function.
* Input : NewState: ENABLE or DISABLE.
* Return : None
********************************************************************************/
void RCC_RTCCLKCmd(FunctionalState NewState)
{
*(__IO uint32_t *) BDCTLR_RTCEN_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_GetClocksFreq
* Description : RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
* the clocks frequencies.
* Input : The result of this function could be not correct when using
* fractional value for HSE crystal.
* Return : None
********************************************************************************/
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
switch (tmp)
{
case 0x00:
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
break;
case 0x04:
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
}
else
{
if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
{
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
}
else
{
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
}
}
break;
default:
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
break;
}
tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
tmp = tmp >> 4;
presc = APBAHBPrescTable[tmp];
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
tmp = tmp >> 8;
presc = APBAHBPrescTable[tmp];
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
tmp = tmp >> 11;
presc = APBAHBPrescTable[tmp];
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
tmp = tmp >> 14;
presc = ADCPrescTable[tmp];
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
}
/*******************************************************************************
* Function Name : RCC_AHBPeriphClockCmd
* Description : Enables or disables the AHB peripheral clock.
* Input : RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
* RCC_AHBPeriph_DMA1.
* RCC_AHBPeriph_DMA2.
* RCC_AHBPeriph_SRAM.
* RCC_AHBPeriph_FLITF.
* RCC_AHBPeriph_CRC.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RCC->AHBPCENR |= RCC_AHBPeriph;
}
else
{
RCC->AHBPCENR &= ~RCC_AHBPeriph;
}
}
/*******************************************************************************
* Function Name : RCC_APB2PeriphClockCmd
* Description : Enables or disables the High Speed APB (APB2) peripheral clock.
* Input : RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
* RCC_APB2Periph_AFIO.
* RCC_APB2Periph_GPIOA.
* RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_GPIOD.
* RCC_APB2Periph_ADC1.
* RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1.
* RCC_APB2Periph_USART1.
* NewState: ENABLE or DISABLE
* Return : None
*******************************************************************************/
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RCC->APB2PCENR |= RCC_APB2Periph;
}
else
{
RCC->APB2PCENR &= ~RCC_APB2Periph;
}
}
/*******************************************************************************
* Function Name : RCC_APB1PeriphClockCmd
* Description : Enables or disables the Low Speed APB (APB1) peripheral clock.
* Input : RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
* RCC_APB1Periph_TIM2.
* RCC_APB1Periph_TIM3.
* RCC_APB1Periph_TIM4.
* RCC_APB1Periph_WWDG.
* RCC_APB1Periph_SPI2.
* RCC_APB1Periph_USART2.
* RCC_APB1Periph_USART3.
* RCC_APB1Periph_I2C1.
* RCC_APB1Periph_I2C2.
* RCC_APB1Periph_USB.
* RCC_APB1Periph_CAN1.
* RCC_APB1Periph_BKP.
* RCC_APB1Periph_PWR.
* RCC_APB1Periph_DAC.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RCC->APB1PCENR |= RCC_APB1Periph;
}
else
{
RCC->APB1PCENR &= ~RCC_APB1Periph;
}
}
/*******************************************************************************
* Function Name : RCC_APB2PeriphResetCmd
* Description : Forces or releases High Speed APB (APB2) peripheral reset.
* Input : RCC_APB2Periph: specifies the APB2 peripheral to reset.
* RCC_APB2Periph_AFIO.
* RCC_APB2Periph_GPIOA.
* RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_GPIOD.
* RCC_APB2Periph_ADC1.
* RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1.
* RCC_APB2Periph_USART1.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RCC->APB2PRSTR |= RCC_APB2Periph;
}
else
{
RCC->APB2PRSTR &= ~RCC_APB2Periph;
}
}
/*******************************************************************************
* Function Name : RCC_APB1PeriphResetCmd
* Description : Forces or releases Low Speed APB (APB1) peripheral reset.
* Input : RCC_APB1Periph: specifies the APB1 peripheral to reset.
* RCC_APB1Periph_TIM2.
* RCC_APB1Periph_TIM3.
* RCC_APB1Periph_TIM4.
* RCC_APB1Periph_WWDG.
* RCC_APB1Periph_SPI2.
* RCC_APB1Periph_USART2.
* RCC_APB1Periph_USART3.
* RCC_APB1Periph_I2C1.
* RCC_APB1Periph_I2C2.
* RCC_APB1Periph_USB.
* RCC_APB1Periph_CAN1.
* RCC_APB1Periph_BKP.
* RCC_APB1Periph_PWR.
* RCC_APB1Periph_DAC.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RCC->APB2PRSTR |= RCC_APB1Periph;
}
else
{
RCC->APB2PRSTR &= ~RCC_APB1Periph;
}
}
/*******************************************************************************
* Function Name : RCC_BackupResetCmd
* Description : Forces or releases the Backup domain reset.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_BackupResetCmd(FunctionalState NewState)
{
*(__IO uint32_t *) BDCTLR_BDRST_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_ClockSecuritySystemCmd
* Description : Enables or disables the Clock Security System.
* Input : NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
{
*(__IO uint32_t *) CTLR_CSSON_BB = (uint32_t)NewState;
}
/*******************************************************************************
* Function Name : RCC_MCOConfig
* Description : Selects the clock source to output on MCO pin.
* Input : RCC_MCO: specifies the clock source to output.
* RCC_MCO_NoClock: No clock selected.
* RCC_MCO_SYSCLK: System clock selected.
* RCC_MCO_HSI: HSI oscillator clock selected.
* RCC_MCO_HSE: HSE oscillator clock selected.
* RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected.
* Return : None
*******************************************************************************/
void RCC_MCOConfig(uint8_t RCC_MCO)
{
*(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
}
/*******************************************************************************
* Function Name : RCC_GetFlagStatus
* Description : Checks whether the specified RCC flag is set or not.
* Input : RCC_FLAG: specifies the flag to check.
* RCC_FLAG_HSIRDY: HSI oscillator clock ready.
* RCC_FLAG_HSERDY: HSE oscillator clock ready.
* RCC_FLAG_PLLRDY: PLL clock ready.
* RCC_FLAG_LSERDY: LSE oscillator clock ready.
* RCC_FLAG_LSIRDY: LSI oscillator clock ready.
* RCC_FLAG_PINRST: Pin reset.
* RCC_FLAG_PORRST: POR/PDR reset.
* RCC_FLAG_SFTRST: Software reset.
* RCC_FLAG_IWDGRST: Independent Watchdog reset.
* RCC_FLAG_WWDGRST: Window Watchdog reset.
* RCC_FLAG_LPWRRST: Low Power reset.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
{
uint32_t tmp = 0;
uint32_t statusreg = 0;
FlagStatus bitstatus = RESET;
tmp = RCC_FLAG >> 5;
if (tmp == 1)
{
statusreg = RCC->CTLR;
}
else if (tmp == 2)
{
statusreg = RCC->BDCTLR;
}
else
{
statusreg = RCC->RSTSCKR;
}
tmp = RCC_FLAG & FLAG_Mask;
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RCC_ClearFlag
* Description : Clears the RCC reset flags.
* Input : None
* Return : None
*******************************************************************************/
void RCC_ClearFlag(void)
{
RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
}
/*******************************************************************************
* Function Name : RCC_GetITStatus
* Description : Checks whether the specified RCC interrupt has occurred or not.
* Input : RCC_IT: specifies the RCC interrupt source to check.
* RCC_IT_LSIRDY: LSI ready interrupt.
* RCC_IT_LSERDY: LSE ready interrupt.
* RCC_IT_HSIRDY: HSI ready interrupt.
* RCC_IT_HSERDY: HSE ready interrupt.
* RCC_IT_PLLRDY: PLL ready interrupt.
* RCC_IT_CSS: Clock Security System interruptt.
* Return : ITStatus: SET or RESET.
*******************************************************************************/
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
{
ITStatus bitstatus = RESET;
if ((RCC->INTR & RCC_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : RCC_ClearITPendingBit
* Description : Clears the RCC's interrupt pending bits.
* Input : RCC_IT: specifies the interrupt pending bit to clear.
* RCC_IT_LSIRDY: LSI ready interrupt.
* RCC_IT_LSERDY: LSE ready interrupt.
* RCC_IT_HSIRDY: HSI ready interrupt.
* RCC_IT_HSERDY: HSE ready interrupt.
* RCC_IT_PLLRDY: PLL ready interrupt.
* RCC_IT_CSS: Clock Security System interruptt.
* Return : None
*******************************************************************************/
void RCC_ClearITPendingBit(uint8_t RCC_IT)
{
*(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT;
}

243
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_rtc.c Normal file
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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_rtc.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the RTC firmware functions.
***************************************************************************************/
#include "ch32f10x_rtc.h"
/* RTC_Private_Defines */
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */
/********************************************************************************
* Function Name : RTC_ITConfig
* Description : Enables or disables the specified RTC interrupts.
* Input : RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
* RTC_IT_OW: Overflow interrupt
* RTC_IT_ALR: Alarm interrupt
* RTC_IT_SEC: Second interrupt
* Return : NewState: new state of the specified RTC interrupts(ENABLE or DISABLE).
*********************************************************************************/
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
{
if (NewState != DISABLE)
{
RTC->CTLRH |= RTC_IT;
}
else
{
RTC->CTLRH &= (uint16_t)~RTC_IT;
}
}
/********************************************************************************
* Function Name : RTC_EnterConfigMode
* Description : Enters the RTC configuration mode.
* Input : None
* Return : None
*********************************************************************************/
void RTC_EnterConfigMode(void)
{
RTC->CTLRL |= RTC_CTLRL_CNF;
}
/********************************************************************************
* Function Name : RTC_ExitConfigMode
* Description : Exits from the RTC configuration mode.
* Input : None
* Return : None
*********************************************************************************/
void RTC_ExitConfigMode(void)
{
RTC->CTLRL &= (uint16_t)~((uint16_t)RTC_CTLRL_CNF);
}
/********************************************************************************
* Function Name : RTC_GetCounter
* Description : Gets the RTC counter value
* Input : None
* Return : RTC counter value
*********************************************************************************/
uint32_t RTC_GetCounter(void)
{
uint16_t tmp = 0;
tmp = RTC->CNTL;
return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
}
/********************************************************************************
* Function Name : RTC_SetCounter
* Description : Sets the RTC counter value.
* Input : CounterValue: RTC counter new value.
* Return : None
*********************************************************************************/
void RTC_SetCounter(uint32_t CounterValue)
{
RTC_EnterConfigMode();
RTC->CNTH = CounterValue >> 16;
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/********************************************************************************
* Function Name : RTC_SetPrescaler
* Description : Sets the RTC prescaler value
* Input : PrescalerValue: RTC prescaler new value
* Return : None
*********************************************************************************/
void RTC_SetPrescaler(uint32_t PrescalerValue)
{
RTC_EnterConfigMode();
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/********************************************************************************
* Function Name : RTC_SetAlarm
* Description : Sets the RTC alarm value
* Input : AlarmValue: RTC alarm new value
* Return : None
*********************************************************************************/
void RTC_SetAlarm(uint32_t AlarmValue)
{
RTC_EnterConfigMode();
RTC->ALRMH = AlarmValue >> 16;
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
RTC_ExitConfigMode();
}
/********************************************************************************
* Function Name : RTC_GetDivider
* Description : Gets the RTC divider value
* Input : None
* Return : RTC Divider value
*********************************************************************************/
uint32_t RTC_GetDivider(void)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
tmp |= RTC->DIVL;
return tmp;
}
/********************************************************************************
* Function Name : RTC_WaitForLastTask
* Description : Waits until last write operation on RTC registers has finished
* Input : None
* Return : None
*********************************************************************************/
void RTC_WaitForLastTask(void)
{
while ((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
{
}
}
/********************************************************************************
* Function Name : RTC_WaitForSynchro
* Description : Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
* are synchronized with RTC APB clock
* Input : None
* Return : None
*********************************************************************************/
void RTC_WaitForSynchro(void)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
while ((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
{
}
}
/********************************************************************************
* Function Name : RTC_GetFlagStatus
* Description : Checks whether the specified RTC flag is set or not
* Input : RTC_FLAG: specifies the flag to check
* RTC_FLAG_RTOFF: RTC Operation OFF flag
* RTC_FLAG_RSF: Registers Synchronized flag
* RTC_FLAG_OW: Overflow flag
* RTC_FLAG_ALR: Alarm flag
* RTC_FLAG_SEC: Second flag
* Return : The new state of RTC_FLAG (SET or RESET)
*********************************************************************************/
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
{
FlagStatus bitstatus = RESET;
if ((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : RTC_ClearFlag
* Description : Clears the RTC's pending flags
* Input : RTC_FLAG: specifies the flag to clear
* RTC_FLAG_RSF: Registers Synchronized flag
* RTC_FLAG_OW: Overflow flag
* RTC_FLAG_ALR: Alarm flag
* RTC_FLAG_SEC: Second flag
* Return : None
*********************************************************************************/
void RTC_ClearFlag(uint16_t RTC_FLAG)
{
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
}
/********************************************************************************
* Function Name : RTC_GetITStatus
* Description : Checks whether the specified RTC interrupt has occurred or not
* Input : RTC_IT: specifies the RTC interrupts sources to check
* RTC_FLAG_OW: Overflow interrupt
* RTC_FLAG_ALR: Alarm interrupt
* RTC_FLAG_SEC: Second interrupt
* Return : The new state of the RTC_IT (SET or RESET)
*********************************************************************************/
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
{
ITStatus bitstatus = RESET;
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
if (((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/********************************************************************************
* Function Name : RTC_ClearITPendingBit
* Description : Clears the RTC's interrupt pending bits
* Input : RTC_IT: specifies the interrupt pending bit to clear
* RTC_FLAG_OW: Overflow interrupt
* RTC_FLAG_ALR: Alarm interrupt
* RTC_FLAG_SEC: Second interrupt
* Return : None
*********************************************************************************/
void RTC_ClearITPendingBit(uint16_t RTC_IT)
{
RTC->CTLRL &= (uint16_t)~RTC_IT;
}

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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_spi.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the SPI firmware functions.
***************************************************************************************/
#include "ch32f10x_spi.h"
#include "ch32f10x_rcc.h"
/* SPI SPE mask */
#define CTLR1_SPE_Set ((uint16_t)0x0040)
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
/* SPI CRCNext mask */
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
/* SPI CRCEN mask */
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
/* SPI SSOE mask */
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
/* SPI registers Masks */
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((uint16_t)0xF7FF)
#define I2S_Mode_Select ((uint16_t)0x0800)
/* I2S clock source selection masks */
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
/*******************************************************************************
* Function Name : SPI_I2S_DeInit
* Description : Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Return : None
*******************************************************************************/
void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
{
if (SPIx == SPI1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
}
else if (SPIx == SPI2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
}
else
{
if (SPIx == SPI3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
}
}
}
/*******************************************************************************
* Function Name : SPI_Init
* Description : Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral.
* Return : None
*******************************************************************************/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
uint16_t tmpreg = 0;
tmpreg = SPIx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
SPIx->CTLR1 = tmpreg;
SPIx->I2SCFGR &= SPI_Mode_Select;
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
}
/*******************************************************************************
* Function Name : I2S_Init
* Description : Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* (configured in I2S mode).
* I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral
* configured in I2S mode.
* Return : None
*******************************************************************************/
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
{
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0;
RCC_ClocksTypeDef RCC_Clocks;
uint32_t sourceclock = 0;
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
SPIx->I2SPR = 0x0002;
tmpreg = SPIx->I2SCFGR;
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
{
i2sodd = (uint16_t)0;
i2sdiv = (uint16_t)2;
}
else
{
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
{
packetlength = 1;
}
else
{
packetlength = 2;
}
if(((uint32_t)SPIx) == SPI2_BASE)
{
tmp = I2S2_CLOCK_SRC;
}
else
{
tmp = I2S3_CLOCK_SRC;
}
RCC_GetClocksFreq(&RCC_Clocks);
sourceclock = RCC_Clocks.SYSCLK_Frequency;
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
else
{
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
tmp = tmp / 10;
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
i2sodd = (uint16_t) (i2sodd << 8);
}
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
{
i2sdiv = 2;
i2sodd = 0;
}
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
(uint16_t)I2S_InitStruct->I2S_CPOL))));
SPIx->I2SCFGR = tmpreg;
}
/*******************************************************************************
* Function Name : SPI_StructInit
* Description : Fills each SPI_InitStruct member with its default value.
* Input : SPI_InitStruct : pointer to a SPI_InitTypeDef structure which
* will be initialized.
* Return : None
*******************************************************************************/
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
/*******************************************************************************
* Function Name : I2S_StructInit
* Description : Fills each I2S_InitStruct member with its default value.
* Input : I2S_InitStruct : pointer to a I2S_InitTypeDef structure which
* will be initialized.
* Return : None
*******************************************************************************/
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
{
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
}
/*******************************************************************************
* Function Name : SPI_Cmd
* Description : Enables or disables the specified SPI peripheral.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_SPE_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_SPE_Reset;
}
}
/*******************************************************************************
* Function Name : I2S_Cmd
* Description : Enables or disables the specified SPI peripheral (in I2S mode).
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
}
else
{
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_ITConfig
* Description : Enables or disables the specified SPI/I2S interrupts.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT: specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* SPI_I2S_IT_TXE: Tx buffer empty interrupt mask.
* SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask.
* SPI_I2S_IT_ERR: Error interrupt mask.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
{
uint16_t itpos = 0, itmask = 0 ;
itpos = SPI_I2S_IT >> 4;
itmask = (uint16_t)1 << (uint16_t)itpos;
if (NewState != DISABLE)
{
SPIx->CTLR2 |= itmask;
}
else
{
SPIx->CTLR2 &= (uint16_t)~itmask;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_DMACmd
* Description : Enables or disables the SPIx/I2Sx DMA interface.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to
* be enabled or disabled.
* SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request.
* SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx->CTLR2 |= SPI_I2S_DMAReq;
}
else
{
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_SendData
* Description : Transmits a Data through the SPIx/I2Sx peripheral.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data : Data to be transmitted.
* Return : None
*******************************************************************************/
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
{
SPIx->DATAR = Data;
}
/*******************************************************************************
* Function Name : SPI_I2S_ReceiveData
* Description : Returns the most recent received data by the SPIx/I2Sx peripheral.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data : Data to be transmitted.
* Return : SPIx->DATAR: The value of the received data.
*******************************************************************************/
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
{
return SPIx->DATAR;
}
/*******************************************************************************
* Function Name : SPI_NSSInternalSoftwareConfig
* Description : Configures internally by software the NSS pin for the selected SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_NSSInternalSoft:
* SPI_NSSInternalSoft_Set: Set NSS pin internally.
* SPI_NSSInternalSoft_Reset: Reset NSS pin internally.
* Return : None
*******************************************************************************/
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
{
if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
{
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
}
else
{
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_SSOutputCmd
* Description : Enables or disables the SS output for the selected SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState: new state of the SPIx SS output.
* Return : None
*******************************************************************************/
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx->CTLR2 |= CTLR2_SSOE_Set;
}
else
{
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_DataSizeConfig
* Description : Configures the data size for the selected SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_DataSize: specifies the SPI data size.
* SPI_DataSize_16b: Set data frame format to 16bit.
* SPI_DataSize_8b: Set data frame format to 8bit.
* Return : None
*******************************************************************************/
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
{
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
SPIx->CTLR1 |= SPI_DataSize;
}
/*******************************************************************************
* Function Name : SPI_TransmitCRC
* Description : Transmit the SPIx CRC value.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Return : None
*******************************************************************************/
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
{
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
}
/*******************************************************************************
* Function Name : SPI_CalculateCRC
* Description : Enables or disables the CRC value calculation of the transferred bytes.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState: new state of the SPIx CRC value calculation.
* Return : None
*******************************************************************************/
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
}
}
/*******************************************************************************
* Function Name : SPI_GetCRC
* Description : Returns the transmit or the receive CRC register value for the specified SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_CRC: specifies the CRC register to be read.
* SPI_CRC_Tx: Selects Tx CRC register.
* SPI_CRC_Rx: Selects Rx CRC register.
* Return : crcreg: The selected CRC register value.
*******************************************************************************/
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
{
uint16_t crcreg = 0;
if (SPI_CRC != SPI_CRC_Rx)
{
crcreg = SPIx->TCRCR;
}
else
{
crcreg = SPIx->RCRCR;
}
return crcreg;
}
/*******************************************************************************
* Function Name : SPI_GetCRCPolynomial
* Description : Returns the CRC Polynomial register value for the specified SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* Return : SPIx->CRCR: The CRC Polynomial register value.
*******************************************************************************/
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
{
return SPIx->CRCR;
}
/*******************************************************************************
* Function Name : SPI_BiDirectionalLineConfig
* Description : Selects the data transfer direction in bi-directional mode
* for the specified SPI.
* Input : SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_Direction: specifies the data transfer direction in
* bi-directional mode.
* SPI_Direction_Tx: Selects Tx transmission direction.
* SPI_Direction_Rx: Selects Rx receive direction.
* Return : None
*******************************************************************************/
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
{
if (SPI_Direction == SPI_Direction_Tx)
{
SPIx->CTLR1 |= SPI_Direction_Tx;
}
else
{
SPIx->CTLR1 &= SPI_Direction_Rx;
}
}
/*******************************************************************************
* Function Name : SPI_I2S_GetFlagStatus
* Description : Checks whether the specified SPI/I2S flag is set or not.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
* SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
* SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
* SPI_I2S_FLAG_BSY: Busy flag.
* SPI_I2S_FLAG_OVR: Overrun flag.
* SPI_FLAG_MODF: Mode Fault flag.
* SPI_FLAG_CRCERR: CRC Error flag.
* I2S_FLAG_UDR: Underrun Error flag.
* I2S_FLAG_CHSIDE: Channel Side flag.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
FlagStatus bitstatus = RESET;
if ((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : SPI_I2S_ClearFlag
* Description : Clears the SPIx CRC Error (CRCERR) flag.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG: specifies the SPI flag to clear.
* SPI_FLAG_CRCERR: CRC Error flag.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
{
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
}
/*******************************************************************************
* Function Name : SPI_I2S_GetITStatus
* Description : Clears the SPIx CRC Error (CRCERR) flag.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT: specifies the SPI/I2S interrupt source to check..
* SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
* SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
* SPI_I2S_IT_OVR: Overrun interrupt.
* SPI_IT_MODF: Mode Fault interrupt.
* SPI_IT_CRCERR: CRC Error interrupt.
* I2S_IT_UDR: Underrun Error interrupt.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
{
ITStatus bitstatus = RESET;
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
itmask = SPI_I2S_IT >> 4;
itmask = 0x01 << itmask;
enablestatus = (SPIx->CTLR2 & itmask) ;
if (((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : SPI_I2S_ClearITPendingBit
* Description : Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
* Input : SPIx: where x can be
* - 1, 2 or 3 in SPI mode.
* SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
* SPI_IT_CRCERR: CRC Error interrupt.
* Return : FlagStatus: SET or RESET.
*******************************************************************************/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
{
uint16_t itpos = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
SPIx->STATR = (uint16_t)~itpos;
}

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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_usart.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the USART firmware functions.
*******************************************************************************/
#include "ch32f10x_usart.h"
#include "ch32f10x_rcc.h"
/* USART_Private_Defines */
#define CTLR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */
#define CTLR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */
#define CTLR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */
#define CTLR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */
#define CTLR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */
#define GPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */
#define GPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */
#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */
/* USART OverSampling-8 Mask */
#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
/* USART One Bit Sampling Mask */
#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
/*******************************************************************************
* Function Name : USART_DeInit
* Description : Deinitializes the USARTx peripheral registers to their default
* reset values.
* Input : USARTx: where x can be 1, 2 or 3 to select the UART peripheral.
* Return : None
*******************************************************************************/
void USART_DeInit(USART_TypeDef* USARTx)
{
if (USARTx == USART1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
}
else if (USARTx == USART2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
}
else if (USARTx == USART3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
}
else if (USARTx == UART4)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
}
else
{
if (USARTx == UART5)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
}
}
}
/*******************************************************************************
* Function Name : USART_Init
* Description : Initializes the USARTx peripheral according to the specified
* parameters in the USART_InitStruct.
* Input : USARTx: where x can be 1, 2 or 3 to select the UART peripheral.
* USART_InitStruct: pointer to a USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* Return : None
*******************************************************************************/
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
{
uint32_t tmpreg = 0x00, apbclock = 0x00;
uint32_t integerdivider = 0x00;
uint32_t fractionaldivider = 0x00;
uint32_t usartxbase = 0;
RCC_ClocksTypeDef RCC_ClocksStatus;
if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
{
}
usartxbase = (uint32_t)USARTx;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_STOP_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
USARTx->CTLR2 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
USART_InitStruct->USART_Mode;
USARTx->CTLR1 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR3;
tmpreg &= CTLR3_CLEAR_Mask;
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
USARTx->CTLR3 = (uint16_t)tmpreg;
RCC_GetClocksFreq(&RCC_ClocksStatus);
if (usartxbase == USART1_BASE)
{
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
}
else
{
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
}
if ((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
}
else
{
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
}
tmpreg = (integerdivider / 100) << 4;
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
if ((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
{
tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
}
else
{
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
}
USARTx->BRR = (uint16_t)tmpreg;
}
/*******************************************************************************
* Function Name : USART_StructInit
* Description : Fills each USART_InitStruct member with its default value.
* Input : USART_InitStruct: pointer to a USART_InitTypeDef structure
* which will be initialized.
* Return : None
*******************************************************************************/
void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
{
USART_InitStruct->USART_BaudRate = 9600;
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
USART_InitStruct->USART_StopBits = USART_StopBits_1;
USART_InitStruct->USART_Parity = USART_Parity_No ;
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
}
/*******************************************************************************
* Function Name : USART_ClockInit
* Description : Initializes the USARTx peripheral Clock according to the
* specified parameters in the USART_ClockInitStruct .
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
* structure that contains the configuration information for the specified
* USART peripheral.
* Return : None
*******************************************************************************/
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
{
uint32_t tmpreg = 0x00;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
USARTx->CTLR2 = (uint16_t)tmpreg;
}
/*******************************************************************************
* Function Name : USART_ClockStructInit
* Description : Fills each USART_InitStruct member with its default value.
* Input : USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
* structure which will be initialized.
* Return : None
*******************************************************************************/
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
{
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
}
/*******************************************************************************
* Function Name : USART_Cmd
* Description : Enables or disables the specified USART peripheral.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_UE_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_UE_Reset;
}
}
/*******************************************************************************
* Function Name : USART_ITConfig
* Description : Enables or disables the specified USART interrupts.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT: specifies the USART interrupt sources to be enabled or disabled.
* USART_IT_CTS: CTS change interrupt.
* USART_IT_LBD: LIN Break detection interrupt.
* USART_IT_TXE: Transmit Data Register empty interrupt.
* USART_IT_TC: Transmission complete interrupt.
* USART_IT_RXNE: Receive Data register not empty interrupt.
* USART_IT_IDLE: Idle line detection interrupt.
* USART_IT_PE: Parity Error interrupt.
* USART_IT_ERR: Error interrupt.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
{
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
uint32_t usartxbase = 0x00;
if (USART_IT == USART_IT_CTS)
{
}
usartxbase = (uint32_t)USARTx;
usartreg = (((uint8_t)USART_IT) >> 0x05);
itpos = USART_IT & IT_Mask;
itmask = (((uint32_t)0x01) << itpos);
if (usartreg == 0x01)
{
usartxbase += 0x0C;
}
else if (usartreg == 0x02)
{
usartxbase += 0x10;
}
else
{
usartxbase += 0x14;
}
if (NewState != DISABLE)
{
*(__IO uint32_t*)usartxbase |= itmask;
}
else
{
*(__IO uint32_t*)usartxbase &= ~itmask;
}
}
/*******************************************************************************
* Function Name : USART_DMACmd
* Description : Enables or disables the USART DMA interface.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_DMAReq: specifies the DMA request.
* USART_DMAReq_Tx: USART DMA transmit request.
* USART_DMAReq_Rx: USART DMA receive request.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= USART_DMAReq;
}
else
{
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
}
}
/*******************************************************************************
* Function Name : USART_SetAddress
* Description : Sets the address of the USART node.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_Address: Indicates the address of the USART node.
* Return : None
*******************************************************************************/
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
{
USARTx->CTLR2 &= CTLR2_Address_Mask;
USARTx->CTLR2 |= USART_Address;
}
/*******************************************************************************
* Function Name : USART_WakeUpConfig
* Description : Selects the USART WakeUp method.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_WakeUp: specifies the USART wakeup method.
* USART_WakeUp_IdleLine: WakeUp by an idle line detection.
* USART_WakeUp_AddressMark: WakeUp by an address mark.
* Return : None
*******************************************************************************/
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
{
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
USARTx->CTLR1 |= USART_WakeUp;
}
/*******************************************************************************
* Function Name : USART_ReceiverWakeUpCmd
* Description : Determines if the USART is in mute mode or not.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_RWU_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_RWU_Reset;
}
}
/*******************************************************************************
* Function Name : USART_LINBreakDetectLengthConfig
* Description : Sets the USART LIN Break detection length.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_LINBreakDetectLength: specifies the LIN break detection length.
* USART_LINBreakDetectLength_10b: 10-bit break detection.
* USART_LINBreakDetectLength_11b: 11-bit break detection.
* Return : None
*******************************************************************************/
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
{
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
USARTx->CTLR2 |= USART_LINBreakDetectLength;
}
/*******************************************************************************
* Function Name : USART_LINCmd
* Description : Enables or disables the USART LIN mode.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR2 |= CTLR2_LINEN_Set;
}
else
{
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
}
}
/*******************************************************************************
* Function Name : USART_SendData
* Description : Transmits single data through the USARTx peripheral.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* Data: the data to transmit..
* Return : None
*******************************************************************************/
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
{
USARTx->DATAR = (Data & (uint16_t)0x01FF);
}
/*******************************************************************************
* Function Name : USART_ReceiveData
* Description : Returns the most recent received data by the USARTx peripheral.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* Return : The received data.
*******************************************************************************/
uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
{
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
}
/*******************************************************************************
* Function Name : USART_SendBreak
* Description : Transmits break characters.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* Return : None
*******************************************************************************/
void USART_SendBreak(USART_TypeDef* USARTx)
{
USARTx->CTLR1 |= CTLR1_SBK_Set;
}
/*******************************************************************************
* Function Name : USART_SetGuardTime
* Description : Sets the specified USART guard time.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_GuardTime: specifies the guard time.
* Return : None
*******************************************************************************/
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
{
USARTx->GPR &= GPR_LSB_Mask;
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
}
/*******************************************************************************
* Function Name : USART_SetPrescaler
* Description : Sets the system clock prescaler.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_Prescaler: specifies the prescaler clock.
* Return : None
*******************************************************************************/
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
{
USARTx->GPR &= GPR_MSB_Mask;
USARTx->GPR |= USART_Prescaler;
}
/*******************************************************************************
* Function Name : USART_SmartCardCmd
* Description : Enables or disables the USART Smart Card mode.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_SCEN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
}
}
/*******************************************************************************
* Function Name : USART_SmartCardNACKCmd
* Description : Enables or disables NACK transmission.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_NACK_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_NACK_Reset;
}
}
/*******************************************************************************
* Function Name : USART_HalfDuplexCmd
* Description : Enables or disables the USART Half Duplex communication.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
}
}
/*******************************************************************************
* Function Name : USART_OverSampling8Cmd
* Description : Enables or disables the USART's 8x oversampling mode.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_OVER8_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_OVER8_Reset;
}
}
/*******************************************************************************
* Function Name : USART_OneBitMethodCmd
* Description : Enables or disables the USART's one bit sampling method.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
}
}
/*******************************************************************************
* Function Name : USART_IrDAConfig
* Description : Configures the USART's IrDA interface.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_IrDAMode: specifies the IrDA mode.
* USART_IrDAMode_LowPower.
* USART_IrDAMode_Normal.
* Return : None
*******************************************************************************/
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
{
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
USARTx->CTLR3 |= USART_IrDAMode;
}
/*******************************************************************************
* Function Name : USART_IrDACmd
* Description : Enables or disables the USART's IrDA interface.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
* Return : None
*******************************************************************************/
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
{
if (NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_IREN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_IREN_Reset;
}
}
/*******************************************************************************
* Function Name : USART_GetFlagStatus
* Description : Checks whether the specified USART flag is set or not.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG: specifies the flag to check.
* USART_FLAG_CTS: CTS Change flag.
* USART_FLAG_LBD: LIN Break detection flag.
* USART_FLAG_TXE: Transmit data register empty flag.
* USART_FLAG_TC: Transmission Complete flag.
* USART_FLAG_RXNE: Receive data register not empty flag.
* USART_FLAG_IDLE: Idle Line detection flag.
* USART_FLAG_ORE: OverRun Error flag.
* USART_FLAG_NE: Noise Error flag.
* USART_FLAG_FE: Framing Error flag.
* USART_FLAG_PE: Parity Error flag.
* Return : bitstatus: SET or RESET.
*******************************************************************************/
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
{
FlagStatus bitstatus = RESET;
if (USART_FLAG == USART_FLAG_CTS)
{
}
if ((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : USART_ClearFlag
* Description : Clears the USARTx's pending flags.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG: specifies the flag to clear.
* USART_FLAG_CTS: CTS Change flag.
* USART_FLAG_LBD: LIN Break detection flag.
* USART_FLAG_TC: Transmission Complete flag.
* USART_FLAG_RXNE: Receive data register not empty flag.
* Return : None
*******************************************************************************/
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
{
if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
{
}
USARTx->STATR = (uint16_t)~USART_FLAG;
}
/*******************************************************************************
* Function Name : USART_GetITStatus
* Description : Checks whether the specified USART interrupt has occurred or not.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT: specifies the USART interrupt source to check.
* USART_IT_CTS: CTS change interrupt.
* USART_IT_LBD: LIN Break detection interrupt.
* USART_IT_TXE: Tansmit Data Register empty interrupt.
* USART_IT_TC: Transmission complete interrupt.
* USART_IT_RXNE: Receive Data register not empty interrupt.
* USART_IT_IDLE: Idle line detection interrupt.
* USART_IT_ORE: OverRun Error interrupt.
* USART_IT_NE: Noise Error interrupt.
* USART_IT_FE: Framing Error interrupt.
* USART_IT_PE: Parity Error interrupt.
* Return : bitstatus: SET or RESET.
*******************************************************************************/
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
{
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
ITStatus bitstatus = RESET;
if (USART_IT == USART_IT_CTS)
{
}
usartreg = (((uint8_t)USART_IT) >> 0x05);
itmask = USART_IT & IT_Mask;
itmask = (uint32_t)0x01 << itmask;
if (usartreg == 0x01)
{
itmask &= USARTx->CTLR1;
}
else if (usartreg == 0x02)
{
itmask &= USARTx->CTLR2;
}
else
{
itmask &= USARTx->CTLR3;
}
bitpos = USART_IT >> 0x08;
bitpos = (uint32_t)0x01 << bitpos;
bitpos &= USARTx->STATR;
if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*******************************************************************************
* Function Name : USART_ClearITPendingBit
* Description : Clears the USARTx's interrupt pending bits.
* Input : USARTx: where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT: specifies the interrupt pending bit to clear.
* USART_IT_CTS: CTS change interrupt.
* USART_IT_LBD: LIN Break detection interrupt.
* USART_IT_TC: Transmission complete interrupt.
* USART_IT_RXNE: Receive Data register not empty interrupt.
* Return : None
*******************************************************************************/
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
{
uint16_t bitpos = 0x00, itmask = 0x00;
if (USART_IT == USART_IT_CTS)
{
}
bitpos = USART_IT >> 0x08;
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
USARTx->STATR = (uint16_t)~itmask;
}

813
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_usb.c Normal file
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/***************COPYRIGHT(C) 2019 WCH. A11 rights reserved*********************
* File Name : ch32f10x_usb.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the USB firmware functions.
*******************************************************************************/
#include "ch32f10x_usb.h"
#include "ch32f10x_rcc.h"
/******************************** USB DEVICE **********************************/
/* Endpoint address */
PUINT8 pEP0_RAM_Addr;
PUINT8 pEP1_RAM_Addr;
PUINT8 pEP2_RAM_Addr;
PUINT8 pEP3_RAM_Addr;
/*******************************************************************************
* Function Name : DelsyUs
* Description : Microsecond Delay Time.
* Input : t<><74>Microsecond number.
* Return : None
*******************************************************************************/
void DelsyUs( UINT16 t )
{
UINT16 j,i;
for(j=0; j<t; j++)
{
for(i=0; i<4; i++)
{
__nop();
__nop();
}
}
}
/*******************************************************************************
* Function Name : DelsyMs
* Description : Millisecond Delay Time.
* Input : t<><74>Millisecond number.
* Return : None
*******************************************************************************/
void DelsyMs( UINT16 t )
{
UINT16 i;
for(i=0; i<t; i++)
{
DelsyUs(1000);
}
}
/*******************************************************************************
* Function Name : USB_DeviceInit
* Description : Initializes USB device.
* Input : None
* Return : None
*******************************************************************************/
void USB_DeviceInit( void )
{
R8_USB_CTRL = 0x00;
EXTEN_CTRL = USBHD_IO_EN ;//| USB_5V_SEL;
R8_UEP4_1_MOD = RB_UEP4_RX_EN|RB_UEP4_TX_EN|RB_UEP1_RX_EN|RB_UEP1_TX_EN;
R8_UEP2_3_MOD = RB_UEP2_RX_EN|RB_UEP2_TX_EN|RB_UEP3_RX_EN|RB_UEP3_TX_EN;
R16_UEP0_DMA = (UINT16)(UINT32)pEP0_RAM_Addr;
R16_UEP1_DMA = (UINT16)(UINT32)pEP1_RAM_Addr;
R16_UEP2_DMA = (UINT16)(UINT32)pEP2_RAM_Addr;
R16_UEP3_DMA = (UINT16)(UINT32)pEP3_RAM_Addr;
R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK | RB_UEP_AUTO_TOG;
R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
R8_USB_INT_FG = 0xFF;
R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
R8_USB_DEV_AD = 0x00;
R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
R8_UDEV_CTRL = RB_UD_PD_DIS|RB_UD_PORT_EN;
}
/*******************************************************************************
* Function Name : Set_USBClock
* Description : Set USB clock.
* Input : None
* Return : None
*******************************************************************************/
void Set_USBClock(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5); //USBclk=PLLclk/1.5=48Mhz
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHD,ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
}
/*******************************************************************************
* Function Name : DevEP1_IN_Deal
* Description : Device endpoint1 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP1_IN_Deal( UINT8 l )
{
R8_UEP1_T_LEN = l;
R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES)| UEP_T_RES_ACK;
}
/*******************************************************************************
* Function Name : DevEP2_IN_Deal
* Description : Device endpoint2 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP2_IN_Deal( UINT8 l )
{
R8_UEP2_T_LEN = l;
R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES)| UEP_T_RES_ACK;
}
/*******************************************************************************
* Function Name : DevEP3_IN_Deal
* Description : Device endpoint3 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP3_IN_Deal( UINT8 l )
{
R8_UEP3_T_LEN = l;
R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES)| UEP_T_RES_ACK;
}
/*******************************************************************************
* Function Name : DevEP4_IN_Deal
* Description : Device endpoint4 IN.
* Input : l: IN length(<64B)
* Return : None
*******************************************************************************/
void DevEP4_IN_Deal( UINT8 l )
{
R8_UEP4_T_LEN = l;
R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES)| UEP_T_RES_ACK;
}
/******************************** HOST DEVICE **********************************/
UINT8 UsbDevEndp0Size;
UINT8 FoundNewDev;
_RootHubDev ThisUsbDev;
PUINT8 pHOST_RX_RAM_Addr;
PUINT8 pHOST_TX_RAM_Addr;
__align(4) const UINT8 SetupGetDevDescr[] = { USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof( USB_DEV_DESCR ), 0x00 };
__align(4) const UINT8 SetupGetCfgDescr[] = { USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00 };
__align(4) const UINT8 SetupSetUsbAddr[] = { USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00 };
__align(4) const UINT8 SetupSetUsbConfig[] = { USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
__align(4) const UINT8 SetupSetUsbInterface[] = { USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
__align(4) const UINT8 SetupClrEndpStall[] = { USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
/*******************************************************************************
* Function Name : DisableRootHubPort( )
* Description : Disable root hub.
* Input : None
* Return : None
*******************************************************************************/
void DisableRootHubPort(void)
{
#ifdef FOR_ROOT_UDISK_ONLY
CH579DiskStatus = DISK_DISCONNECT;
#endif
#ifndef DISK_BASE_BUF_LEN
ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT;
ThisUsbDev.DeviceAddress = 0x00;
#endif
}
/*******************************************************************************
* Function Name : AnalyzeRootHub
* Description : Analyze root hub state.
* Input : None
* Return : Error
*******************************************************************************/
//extern __align(4) UINT8 LED_HOST_MODE;
UINT8 AnalyzeRootHub( void )
{
UINT8 s;
s = ERR_SUCCESS;
if ( R8_USB_MIS_ST & RB_UMS_DEV_ATTACH ) {
#ifdef DISK_BASE_BUF_LEN
if ( CH579DiskStatus == DISK_DISCONNECT
#else
if ( ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT
#endif
|| ( R8_UHOST_CTRL & RB_UH_PORT_EN ) == 0x00 ) {
DisableRootHubPort( );
#ifdef DISK_BASE_BUF_LEN
CH579DiskStatus = DISK_CONNECT;
#else
ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1;
ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
#endif
PRINT( "USB dev in\n" );
s = ERR_USB_CONNECT;
}
}
#ifdef DISK_BASE_BUF_LEN
else if ( CH579DiskStatus >= DISK_CONNECT ) {
#else
else if ( ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED ) {
#endif
DisableRootHubPort( );
PRINT( "USB dev out\n" );
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, DISABLE); //ʱ<>ӹر<D3B9>ʹ<EFBFBD><CAB9>
// LED_HOST_MODE = 0;
if(s == ERR_SUCCESS) s = ERR_USB_DISCON;
}
return( s );
}
/*******************************************************************************
* Function Name : SetHostUsbAddr
* Description : Set USB host address.
* Input : addr; host address.
* Return : None
*******************************************************************************/
void SetHostUsbAddr( UINT8 addr )
{
R8_USB_DEV_AD = (R8_USB_DEV_AD&RB_UDA_GP_BIT) | (addr&MASK_USB_ADDR);
}
#ifndef FOR_ROOT_UDISK_ONLY
/*******************************************************************************
* Function Name : SetUsbSpeed
* Description : Set USB speed.
* Input : FullSpeed: USB speed.
* Return : None
*******************************************************************************/
void SetUsbSpeed( UINT8 FullSpeed )
{
if ( FullSpeed )
{
R8_USB_CTRL &= ~ RB_UC_LOW_SPEED;
R8_UH_SETUP &= ~ RB_UH_PRE_PID_EN;
}
else
{
R8_USB_CTRL |= RB_UC_LOW_SPEED;
}
}
#endif
/*******************************************************************************
* Function Name : ResetRootHubPort( )
* Description : Reset root hub.
* Input : None
* Return : None
*******************************************************************************/
void ResetRootHubPort( void )
{
UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
SetHostUsbAddr( 0x00 );
R8_UHOST_CTRL &= ~RB_UH_PORT_EN;
SetUsbSpeed( 1 );
R8_UHOST_CTRL = (R8_UHOST_CTRL & ~RB_UH_LOW_SPEED) | RB_UH_BUS_RESET;
mDelaymS( 15 );
R8_UHOST_CTRL = R8_UHOST_CTRL & ~ RB_UH_BUS_RESET;
mDelayuS( 250 );
R8_USB_INT_FG = RB_UIF_DETECT;
}
/*******************************************************************************
* Function Name : EnableRootHubPort( )
* Description : Enable root hub.
* Input : None
* Return : ERROR
*******************************************************************************/
UINT8 EnableRootHubPort(void)
{
#ifdef DISK_BASE_BUF_LEN
if ( CH579DiskStatus < DISK_CONNECT ) CH579DiskStatus = DISK_CONNECT;
#else
if ( ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED ) ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
#endif
if ( R8_USB_MIS_ST & RB_UMS_DEV_ATTACH ) {
#ifndef DISK_BASE_BUF_LEN
if ( ( R8_UHOST_CTRL & RB_UH_PORT_EN ) == 0x00 ) {
ThisUsbDev.DeviceSpeed = (R8_USB_MIS_ST & RB_UMS_DM_LEVEL) ? 0 : 1;
if ( ThisUsbDev.DeviceSpeed == 0 ) R8_UHOST_CTRL |= RB_UH_LOW_SPEED;
}
#endif
R8_UHOST_CTRL |= RB_UH_PORT_EN;
return( ERR_SUCCESS );
}
return( ERR_USB_DISCON );
}
/*******************************************************************************
* Function Name : WaitUSB_Interrupt
* Description : Wait USB Interrput.
* Input : None
* Return : EEROR
*******************************************************************************/
UINT8 WaitUSB_Interrupt( void )
{
UINT16 i;
for ( i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG&RB_UIF_TRANSFER) == 0; i -- ){;}
return( (R8_USB_INT_FG&RB_UIF_TRANSFER) ? ERR_SUCCESS : ERR_USB_UNKNOWN );
}
/*******************************************************************************
* Function Name : USBHostTransact
* Description : USB host transport transaction.
* Input : endp_pid: endpoint and PID.
* tog: Synchronization flag.
* timeout: timeout times.
* Return : EEROR:
* ERR_USB_UNKNOWN
* ERR_USB_DISCON
* ERR_USB_CONNECT
* ERR_SUCCESS
*******************************************************************************/
UINT8 USBHostTransact( UINT8 endp_pid, UINT8 tog, UINT16 timeout )
{
UINT8 TransRetry;
UINT8 s, r;
UINT16 i;
R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog;
TransRetry = 0;
do {
R8_UH_EP_PID = endp_pid;
R8_USB_INT_FG = RB_UIF_TRANSFER;
for ( i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG&RB_UIF_TRANSFER) == 0; i -- );
R8_UH_EP_PID = 0x00;
if ( (R8_USB_INT_FG&RB_UIF_TRANSFER) == 0 ) {PRINT("1");return( ERR_USB_UNKNOWN );}
if ( R8_USB_INT_FG & RB_UIF_DETECT ) {
R8_USB_INT_FG = RB_UIF_DETECT;
s = AnalyzeRootHub( );
if ( s == ERR_USB_CONNECT ) FoundNewDev = 1;
#ifdef DISK_BASE_BUF_LEN
if ( CH579DiskStatus == DISK_DISCONNECT ) return( ERR_USB_DISCON );
if ( CH579DiskStatus == DISK_CONNECT ) return( ERR_USB_CONNECT );
#else
if ( ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT ) return( ERR_USB_DISCON );
if ( ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED ) return( ERR_USB_CONNECT );
#endif
mDelayuS( 200 );
}
if ( R8_USB_INT_FG & RB_UIF_TRANSFER )
{
if ( R8_USB_INT_ST & RB_UIS_TOG_OK ) return( ERR_SUCCESS );
r = R8_USB_INT_ST & MASK_UIS_H_RES;
if ( r == USB_PID_STALL ) return( r | ERR_USB_TRANSFER );
if ( r == USB_PID_NAK )
{
if ( timeout == 0 ) return( r | ERR_USB_TRANSFER );
if ( timeout < 0xFFFF ) timeout --;
-- TransRetry;
}
else switch ( endp_pid >> 4 ) {
case USB_PID_SETUP:
case USB_PID_OUT:
if ( r ) return( r | ERR_USB_TRANSFER );
break;
case USB_PID_IN:
if ( r == USB_PID_DATA0 && r == USB_PID_DATA1 ) {
}
else if ( r ) return( r | ERR_USB_TRANSFER );
break;
default:
return( ERR_USB_UNKNOWN );
break;
}
}
else {
R8_USB_INT_FG = 0xFF;
}
mDelayuS( 15 );
} while ( ++ TransRetry < 3 );
return( ERR_USB_TRANSFER );
}
/*******************************************************************************
* Function Name : HostCtrlTransfer
* Description : Host control transport.
* Input : DataBuf : Receive or send data buffer.
* RetLen : Data length.
* Return : ERR_USB_BUF_OVER IN
* ERR_SUCCESS
*******************************************************************************/
UINT8 HostCtrlTransfer( PUINT8 DataBuf, PUINT16 RetLen )
{
UINT16 RemLen = 0;
UINT8 s, RxLen, RxCnt, TxCnt;
PUINT8 pBuf;
PUINT16 pLen;
pBuf = DataBuf;
pLen = RetLen;
mDelayuS( 200 );
if ( pLen ) *pLen = 0;
R8_UH_TX_LEN = sizeof( USB_SETUP_REQ );
s = USBHostTransact( USB_PID_SETUP << 4 | 0x00, 0x00, 200000/20 );
if ( s != ERR_SUCCESS ) return( s );
R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG;
R8_UH_TX_LEN = 0x01;
RemLen = pSetupReq -> wLength;
if ( RemLen && pBuf )
{
if ( pSetupReq -> bRequestType & USB_REQ_TYP_IN )
{
while ( RemLen )
{
mDelayuS( 200 );
s = USBHostTransact( USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000/20 );
if ( s != ERR_SUCCESS ) return( s );
RxLen = R8_USB_RX_LEN < RemLen ? R8_USB_RX_LEN : RemLen;
RemLen -= RxLen;
if ( pLen ) *pLen += RxLen;
for ( RxCnt = 0; RxCnt != RxLen; RxCnt ++ )
{
*pBuf = pHOST_RX_RAM_Addr[ RxCnt ];
pBuf ++;
}
if ( R8_USB_RX_LEN == 0 || ( R8_USB_RX_LEN & ( UsbDevEndp0Size - 1 ) ) ) break;
}
R8_UH_TX_LEN = 0x00;
}
else
{
while ( RemLen )
{
mDelayuS( 200 );
R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen;
for ( TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt ++ )
{
pHOST_TX_RAM_Addr[ TxCnt ] = *pBuf;
pBuf ++;
}
s = USBHostTransact( USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000/20 );
if ( s != ERR_SUCCESS ) return( s );
RemLen -= R8_UH_TX_LEN;
if ( pLen ) *pLen += R8_UH_TX_LEN;
}
}
}
mDelayuS( 200 );
s = USBHostTransact( ( R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00: USB_PID_OUT << 4 | 0x00 ), RB_UH_R_TOG | RB_UH_T_TOG, 200000/20 );
if ( s != ERR_SUCCESS ) return( s );
if ( R8_UH_TX_LEN == 0 ) return( ERR_SUCCESS );
if ( R8_USB_RX_LEN == 0 ) return( ERR_SUCCESS );
return( ERR_USB_BUF_OVER );
}
/*******************************************************************************
* Function Name : CopySetupReqPkg
* Description : Copy setup request package.
* Input : pReqPkt: setup request package address.
* Return : None
*******************************************************************************/
void CopySetupReqPkg( const UINT8 *pReqPkt )
{
UINT8 i;
for ( i = 0; i != sizeof( USB_SETUP_REQ ); i ++ )
{
((PUINT8)pSetupReq)[ i ] = *pReqPkt;
pReqPkt++;
}
}
/*******************************************************************************
* Function Name : CtrlGetDeviceDescr
* Description : Get device descrptor
* Input : DataBuf: Data buffer.
* Return : ERR_USB_BUF_OVER
* ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlGetDeviceDescr( PUINT8 DataBuf )
{
UINT8 s;
UINT16 len;
UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
CopySetupReqPkg( SetupGetDevDescr );
s = HostCtrlTransfer( DataBuf, &len );
if ( s != ERR_SUCCESS ) return( s );
UsbDevEndp0Size = ( (PUSB_DEV_DESCR)DataBuf ) -> bMaxPacketSize0;
if ( len < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength ) return( ERR_USB_BUF_OVER );
return( ERR_SUCCESS );
}
/*******************************************************************************
* Function Name : CtrlGetConfigDescr
* Description : Get configration descrptor.
* Input : DataBuf: Data buffer.
* Return : ERR_USB_BUF_OVER
* ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlGetConfigDescr( PUINT8 DataBuf )
{
UINT8 s;
UINT16 len;
CopySetupReqPkg( SetupGetCfgDescr );
s = HostCtrlTransfer( DataBuf, &len );
if ( s != ERR_SUCCESS ) return( s );
if ( len < ( (PUSB_SETUP_REQ)SetupGetCfgDescr ) -> wLength ) return( ERR_USB_BUF_OVER );
len = ( (PUSB_CFG_DESCR)DataBuf ) -> wTotalLength;
CopySetupReqPkg( SetupGetCfgDescr );
pSetupReq ->wLength = len;
s = HostCtrlTransfer( DataBuf, &len );
if ( s != ERR_SUCCESS ) return( s );
return( ERR_SUCCESS );
}
/*******************************************************************************
* Function Name : CtrlSetUsbAddress
* Description : Set USB device address.
* Input : addr: Device address.
* Return : ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlSetUsbAddress( UINT8 addr )
{
UINT8 s;
CopySetupReqPkg( SetupSetUsbAddr );
pSetupReq -> wValue = addr;
s = HostCtrlTransfer( NULL, NULL );
if ( s != ERR_SUCCESS ) return( s );
SetHostUsbAddr( addr );
mDelaymS( 10 );
return( ERR_SUCCESS );
}
/*******************************************************************************
* Function Name : CtrlSetUsbConfig
* Description : Set usb configration.
* Input : cfg: Configration Value.
* Return : ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlSetUsbConfig( UINT8 cfg )
{
CopySetupReqPkg( SetupSetUsbConfig );
pSetupReq -> wValue = cfg;
return( HostCtrlTransfer( NULL, NULL ) );
}
/*******************************************************************************
* Function Name : CtrlClearEndpStall
* Description : Clear endpoint STALL.
* Input : endp: Endpoint address.
* Return : ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlClearEndpStall( UINT8 endp )
{
CopySetupReqPkg( SetupClrEndpStall );
pSetupReq -> wIndex = endp;
return( HostCtrlTransfer( NULL, NULL ) );
}
/*******************************************************************************
* Function Name : CtrlSetUsbIntercace
* Description : Set USB Interface configration.
* Input : cfg: Configration value.
* Return : ERR_SUCCESS
*******************************************************************************/
UINT8 CtrlSetUsbIntercace( UINT8 cfg )
{
CopySetupReqPkg( SetupSetUsbInterface );
pSetupReq -> wValue = cfg;
return( HostCtrlTransfer( NULL, NULL ) );
}
/*******************************************************************************
* Function Name : USB_HostInit
* Description : Initializes USB host mode.
* Input : None
* Return : None
*******************************************************************************/
void USB_HostInit( void )
{
R8_USB_CTRL = RB_UC_HOST_MODE;
R8_UHOST_CTRL = 0;
R8_USB_DEV_AD = 0x00;
EXTEN_CTRL = USBHD_IO_EN|USBD_LOWSPEED|USBD_PU_EN;//| USB_5V_SEL;
R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN;
R16_UH_RX_DMA = (UINT16)(UINT32)pHOST_RX_RAM_Addr;
R16_UH_TX_DMA = (UINT16)(UINT32)pHOST_TX_RAM_Addr;
R8_UH_RX_CTRL = 0x00;
R8_UH_TX_CTRL = 0x00;
R8_USB_CTRL = RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN;
R8_UH_SETUP = RB_UH_SOF_EN;
R8_USB_INT_FG = 0xFF;
DisableRootHubPort( );
R8_USB_INT_EN = RB_UIE_TRANSFER|RB_UIE_DETECT;
FoundNewDev = 0;
}
/*****************************************************************************
* Function Name : InitRootDevice
* Description : Initializes USB root hub.
* Input : DataBuf: Data buffer.
* Return : ERROR
*******************************************************************************/
UINT8 InitRootDevice( PUINT8 DataBuf )
{
UINT8 i, s;
UINT8 cfg, dv_cls, if_cls;
PRINT( "Reset host port\n" );
ResetRootHubPort( );
for ( i = 0, s = 0; i < 100; i ++ )
{
mDelaymS( 1 );
if ( EnableRootHubPort( ) == ERR_SUCCESS ) {
i = 0;
s ++;
if ( s > 100 ) break;
}
}
if ( i )
{
DisableRootHubPort( );
PRINT( "Disable host port because of disconnect\n" );
return( ERR_USB_DISCON );
}
SetUsbSpeed( ThisUsbDev.DeviceSpeed );
PRINT( "GetDevDescr: " );
s = CtrlGetDeviceDescr( DataBuf );
if ( s == ERR_SUCCESS )
{
for ( i = 0; i < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength; i ++ )
PRINT( "x%02X ", (UINT16)( DataBuf[i] ) );
PRINT( "\n" );
ThisUsbDev.DeviceVID = ((PUSB_DEV_DESCR)DataBuf)->idVendor;
ThisUsbDev.DevicePID = ((PUSB_DEV_DESCR)DataBuf)->idProduct;
dv_cls = ( (PUSB_DEV_DESCR)DataBuf ) -> bDeviceClass;
s = CtrlSetUsbAddress( ((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue );
if ( s == ERR_SUCCESS )
{
ThisUsbDev.DeviceAddress = ( (PUSB_SETUP_REQ)SetupSetUsbAddr )->wValue;
PRINT( "GetCfgDescr: " );
s = CtrlGetConfigDescr( DataBuf );
if ( s == ERR_SUCCESS )
{
for ( i = 0; i < ( (PUSB_CFG_DESCR)DataBuf )->wTotalLength; i ++ )
PRINT( "x%02X ", (UINT16)( DataBuf[i] ) );
PRINT("\n");
cfg = ( (PUSB_CFG_DESCR)DataBuf )->bConfigurationValue;
if_cls = ( (PUSB_CFG_DESCR_LONG)DataBuf )->itf_descr.bInterfaceClass;
if ( (dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_STORAGE)) {
#ifdef FOR_ROOT_UDISK_ONLY
CH579DiskStatus = DISK_USB_ADDR;
return( ERR_SUCCESS );
}
else return( ERR_USB_UNSUPPORT );
#else
s = CtrlSetUsbConfig( cfg );
if ( s == ERR_SUCCESS )
{
ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE;
PRINT( "USB-Disk Ready\n" );
SetUsbSpeed( 1 );
return( ERR_SUCCESS );
}
}
else if ( (dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_PRINTER) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass == 0x01 ) {
s = CtrlSetUsbConfig( cfg );
if ( s == ERR_SUCCESS ) {
ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER;
PRINT( "USB-Print Ready\n" );
SetUsbSpeed( 1 );
return( ERR_SUCCESS );
}
}
else if ( (dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass <= 0x01 ) {
if_cls = ( (PUSB_CFG_DESCR_LONG)DataBuf ) -> itf_descr.bInterfaceProtocol;
s = CtrlSetUsbConfig( cfg );
if ( s == ERR_SUCCESS ) {
ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
if ( if_cls == 1 ) {
ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD;
PRINT( "USB-Keyboard Ready\n" );
SetUsbSpeed( 1 );
return( ERR_SUCCESS );
}
else if ( if_cls == 2 ) {
ThisUsbDev.DeviceType = DEV_TYPE_MOUSE;
PRINT( "USB-Mouse Ready\n" );
SetUsbSpeed( 1 );
return( ERR_SUCCESS );
}
s = ERR_USB_UNSUPPORT;
}
}
else {
s = CtrlSetUsbConfig( cfg );
if ( s == ERR_SUCCESS ) {
ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW;
SetUsbSpeed( 1 );
return( ERR_SUCCESS );
}
}
#endif
}
}
}
PRINT( "InitRootDev Err = %02X\n", (UINT16)s );
#ifdef FOR_ROOT_UDISK_ONLY
CH579DiskStatus = DISK_CONNECT;
#else
ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED;
#endif
SetUsbSpeed( 1 );
return( s );
}

133
bsp/wch/arm/Libraries/CH32F10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32f10x_wwdg.c Normal file
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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_wwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : This file provides all the WWDG firmware functions.
***************************************************************************************/
#include "ch32f10x_wwdg.h"
#include "ch32f10x_rcc.h"
/* WWDG registers bit address in the alias region */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFGR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFGR_EWI_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (EWI_BitNumber * 4))
/* CTLR register bit mask */
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
/* CFGR register bit mask */
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F)
/********************************************************************************
* Function Name : WWDG_DeInit
* Description : Deinitializes the WWDG peripheral registers to their default reset values
* Input : None
* Return : None
*********************************************************************************/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/********************************************************************************
* Function Name : WWDG_SetPrescaler
* Description : Sets the WWDG Prescaler
* Input : WWDG_Prescaler: specifies the WWDG Prescaler
* WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* Return : None
*********************************************************************************/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
tmpreg |= WWDG_Prescaler;
WWDG->CFGR = tmpreg;
}
/********************************************************************************
* Function Name : WWDG_SetWindowValue
* Description : Sets the WWDG window value
* Input : WindowValue: specifies the window value to be compared to the
* downcounter,which must be lower than 0x80
* Return : None
*********************************************************************************/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_W_Mask;
tmpreg |= WindowValue & (uint32_t) BIT_Mask;
WWDG->CFGR = tmpreg;
}
/********************************************************************************
* Function Name : WWDG_EnableIT
* Description : Enables the WWDG Early Wakeup interrupt(EWI)
* Input : None
* Return : None
*********************************************************************************/
void WWDG_EnableIT(void)
{
*(__IO uint32_t *) CFGR_EWI_BB = (uint32_t)ENABLE;
}
/********************************************************************************
* Function Name : WWDG_SetCounter
* Description : Sets the WWDG counter value
* Input : Counter: specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
* Return : None
*********************************************************************************/
void WWDG_SetCounter(uint8_t Counter)
{
WWDG->CTLR = Counter & BIT_Mask;
}
/********************************************************************************
* Function Name : WWDG_Enable
* Description : Enables WWDG and load the counter value
* Input : Counter: specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F
* Return : None
*********************************************************************************/
void WWDG_Enable(uint8_t Counter)
{
WWDG->CTLR = CTLR_WDGA_Set | Counter;
}
/********************************************************************************
* Function Name : WWDG_GetFlagStatus
* Description : Checks whether the Early Wakeup interrupt flag is set or not
* Input : None
* Return : The new state of the Early Wakeup interrupt flag (SET or RESET)
*********************************************************************************/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->STATR);
}
/********************************************************************************
* Function Name : WWDG_ClearFlag
* Description : Clears Early Wakeup interrupt flag
* Input : None
* Return : None
*********************************************************************************/
void WWDG_ClearFlag(void)
{
WWDG->STATR = (uint32_t)RESET;
}

23
bsp/wch/arm/Libraries/Kconfig Normal file
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config SOC_ARM_FAMILY_CH32
bool
config SOC_ARM_SERIES_CH32F103
bool
select ARCH_ARM_CORTEX_M3
select SOC_ARM_FAMILY_CH32
config SOC_ARM_SERIES_CH32F203
bool
select ARCH_ARM_CORTEX_M3
select SOC_ARM_FAMILY_CH32
config SOC_ARM_SERIES_CH32F205
bool
select ARCH_ARM_CORTEX_M3
select SOC_ARM_FAMILY_CH32
config SOC_ARM_SERIES_CH32F207
bool
select ARCH_ARM_CORTEX_M3
select SOC_ARM_FAMILY_CH32

39
bsp/wch/arm/Libraries/ch32_drivers/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend('SOC_ARM_SERIES_CH32F103'):
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio_ch32f10x.c']
if GetDepend(['RT_USING_SERIAL', 'BSP_USING_UART']):
src += ['drv_uart_ch32f10x.c']
if GetDepend(['RT_USING_SPI', 'BSP_USING_SPI']):
src += ['drv_spi_ch32f10x.c']
if GetDepend(['RT_USING_I2C', 'BSP_USING_HWI2C']):
src += ['drv_hwi2c_ch32f10x.c']
if GetDepend(['RT_USING_RTC', 'BSP_USING_RTC']):
src += ['drv_rtc_ch32f10x.c']
if GetDepend(['RT_USING_WDT', 'BSP_USING_IWDT']):
src += ['drv_iwdt_ch32f10x.c']
src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

112
bsp/wch/arm/Libraries/ch32_drivers/drv_common.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "board.h"
#include "drv_common.h"
#ifdef RT_USING_PIN
#include "drv_gpio.h"
#endif
#ifdef RT_USING_SERIAL
#include "drv_uart.h"
#endif
#ifdef RT_USING_FINSH
#include <finsh.h>
static void reboot(uint8_t argc, char **argv)
{
rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reboot, Reboot System)
#endif /* RT_USING_FINSH */
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t start, now, delta, reload, us_tick;
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = SystemCoreClock / 1000000UL;
do
{
now = SysTick->VAL;
delta = start > now ? start - now : reload + start - now;
} while (delta < us_tick * us);
}
void SystemClock_Config(void)
{
SysTick_Config(ch32_get_sysclock_frequency() / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void _Error_Handler(char *s, int num)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
void rt_hw_board_init()
{
/* System clock initialization */
SystemClock_Config();
/* Heap initialization */
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* Pin driver initialization is open by default */
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
/* USART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
/* Set the shell console output device */
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

32
bsp/wch/arm/Libraries/ch32_drivers/drv_common.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-7 SummerGift first version
*/
#ifndef __DRV_COMMON_H__
#define __DRV_COMMON_H__
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *s, int num);
#ifndef Error_Handler
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#endif
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif

16
bsp/wch/arm/Libraries/ch32_drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
int rt_hw_pin_init(void);
#endif

587
bsp/wch/arm/Libraries/ch32_drivers/drv_gpio_ch32f10x.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "board.h"
#include "ch32f10x_gpio.h"
#ifdef RT_USING_PIN
#ifndef ITEM_NUM
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#endif
struct pin_info
{
rt_base_t pin;
rt_uint32_t gpio_pin;
rt_uint32_t portsource;
rt_uint32_t pinsource;
GPIO_TypeDef *gpio;
};
/*
*pin: assign number, start 0
*group: such GPIOA, use 'A'
*gpio_pin: such GPIO_PIN_0, use '0'
*/
#define ASSIGN_PIN(pin, group, gpio_pin) \
{ \
pin, GPIO_Pin_##gpio_pin, GPIO_PortSourceGPIO##group, GPIO_PinSource##gpio_pin, GPIO##group \
}
#define NOT_USE_PIN \
{ \
-1, 0, 0, 0, 0 \
}
static const struct pin_info pin_info_list[] = {
#if defined(GPIOA)
ASSIGN_PIN(0, A, 0),
ASSIGN_PIN(1, A, 1),
ASSIGN_PIN(2, A, 2),
ASSIGN_PIN(3, A, 3),
ASSIGN_PIN(4, A, 4),
ASSIGN_PIN(5, A, 5),
ASSIGN_PIN(6, A, 6),
ASSIGN_PIN(7, A, 7),
ASSIGN_PIN(8, A, 8),
ASSIGN_PIN(9, A, 9),
ASSIGN_PIN(10, A, 10),
ASSIGN_PIN(11, A, 11),
ASSIGN_PIN(12, A, 12),
ASSIGN_PIN(13, A, 13),
ASSIGN_PIN(14, A, 14),
ASSIGN_PIN(15, A, 15),
#endif
#if defined(GPIOB)
ASSIGN_PIN(16, B, 0),
ASSIGN_PIN(17, B, 1),
ASSIGN_PIN(18, B, 2),
ASSIGN_PIN(19, B, 3),
ASSIGN_PIN(20, B, 4),
ASSIGN_PIN(21, B, 5),
ASSIGN_PIN(22, B, 6),
ASSIGN_PIN(23, B, 7),
ASSIGN_PIN(24, B, 8),
ASSIGN_PIN(25, B, 9),
ASSIGN_PIN(26, B, 10),
ASSIGN_PIN(27, B, 11),
ASSIGN_PIN(28, B, 12),
ASSIGN_PIN(29, B, 13),
ASSIGN_PIN(30, B, 14),
ASSIGN_PIN(31, B, 15),
#endif
#if defined(GPIOC)
ASSIGN_PIN(32, C, 0),
ASSIGN_PIN(33, C, 1),
ASSIGN_PIN(34, C, 2),
ASSIGN_PIN(35, C, 3),
ASSIGN_PIN(36, C, 4),
ASSIGN_PIN(37, C, 5),
ASSIGN_PIN(38, C, 6),
ASSIGN_PIN(39, C, 7),
ASSIGN_PIN(40, C, 8),
ASSIGN_PIN(41, C, 9),
ASSIGN_PIN(42, C, 10),
ASSIGN_PIN(43, C, 11),
ASSIGN_PIN(44, C, 12),
ASSIGN_PIN(45, C, 13),
ASSIGN_PIN(46, C, 14),
ASSIGN_PIN(47, C, 15),
#endif
#if defined(GPIOD)
ASSIGN_PIN(48, D, 0),
ASSIGN_PIN(49, D, 1),
ASSIGN_PIN(50, D, 2)
#endif
};
static const struct pin_info *pin_info_list_find(rt_base_t pin)
{
const struct pin_info *item = RT_NULL;
if ((pin != -1) && (pin < ITEM_NUM(pin_info_list)))
{
item = pin_info_list[pin].pin == -1 ? RT_NULL : &pin_info_list[pin];
}
return item;
}
static rt_base_t pin_info_list_find_pin(rt_uint16_t portsource, rt_uint16_t pinsource)
{
rt_base_t pin = -1;
int index;
for (index = 0; index < ITEM_NUM(pin_info_list); index++)
{
if (pin_info_list[index].portsource == portsource && pin_info_list[index].pinsource == pinsource)
{
pin = pin_info_list[index].pin;
break;
}
}
return pin;
}
/*
*use: 0 using the exti line, -1 do not using
*/
struct exti_line_irq
{
rt_uint16_t nvic_priority;
rt_uint16_t nvic_subpriority;
rt_uint32_t exit_line;
IRQn_Type irqn;
int use;
struct rt_pin_irq_hdr bind_irq_hdr;
};
static struct exti_line_irq exti_line_irq_list[] = {
{5, 0, EXTI_Line0, EXTI0_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line1, EXTI1_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line2, EXTI2_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line3, EXTI3_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line4, EXTI4_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line5, EXTI9_5_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line6, EXTI9_5_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line7, EXTI9_5_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line8, EXTI9_5_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line9, EXTI9_5_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line10, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line11, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line12, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line13, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line14, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
{5, 0, EXTI_Line15, EXTI15_10_IRQn, 0, {
.pin = -1,
}},
};
static struct exti_line_irq *exti_line_irq_list_find(rt_int16_t pin)
{
struct exti_line_irq *item = RT_NULL;
int index;
for (index = 0; index < ITEM_NUM(exti_line_irq_list); index++)
{
if (exti_line_irq_list[index].bind_irq_hdr.pin == pin)
{
item = &exti_line_irq_list[index];
break;
}
}
return item;
}
static rt_err_t exti_line_irq_list_bind(struct rt_pin_irq_hdr *irq_hdr)
{
rt_err_t ret = RT_EFULL;
rt_base_t level;
struct exti_line_irq *item;
int index;
for (index = 0; index < ITEM_NUM(exti_line_irq_list); index++)
{
if (exti_line_irq_list[index].bind_irq_hdr.pin == -1 && exti_line_irq_list[index].use != -1)
{
item = &exti_line_irq_list[index];
break;
}
}
if (item != RT_NULL)
{
level = rt_hw_interrupt_disable();
item->bind_irq_hdr.pin = irq_hdr->pin;
item->bind_irq_hdr.mode = irq_hdr->mode;
item->bind_irq_hdr.hdr = irq_hdr->hdr;
item->bind_irq_hdr.args = irq_hdr->args;
rt_hw_interrupt_enable(level);
ret = RT_EOK;
}
return ret;
}
static rt_err_t exti_line_irq_list_unbind(rt_int16_t pin)
{
rt_err_t ret = RT_EEMPTY;
rt_base_t level;
struct exti_line_irq *item;
item = exti_line_irq_list_find(pin);
if (item != RT_NULL)
{
level = rt_hw_interrupt_disable();
item->bind_irq_hdr.pin = -1;
rt_hw_interrupt_enable(level);
ret = RT_EOK;
}
return ret;
}
void ch32f1_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_info *item;
GPIO_InitTypeDef gpio_initstruct;
item = pin_info_list_find(pin);
if (item == RT_NULL)
{
return;
}
gpio_initstruct.GPIO_Pin = item->gpio_pin;
gpio_initstruct.GPIO_Mode = GPIO_Mode_Out_PP;
gpio_initstruct.GPIO_Speed = GPIO_Speed_50MHz;
if (mode == PIN_MODE_OUTPUT)
{
gpio_initstruct.GPIO_Mode = GPIO_Mode_Out_PP;
}
else if (mode == PIN_MODE_INPUT)
{
gpio_initstruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
gpio_initstruct.GPIO_Mode = GPIO_Mode_IPU;
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
gpio_initstruct.GPIO_Mode = GPIO_Mode_IPD;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
gpio_initstruct.GPIO_Mode = GPIO_Mode_Out_OD;
}
GPIO_Init(item->gpio, &gpio_initstruct);
}
void ch32f1_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_info *item;
item = pin_info_list_find(pin);
if (item == RT_NULL)
{
return;
}
GPIO_WriteBit(item->gpio, item->gpio_pin, (BitAction)value);
}
int ch32f1_pin_read(rt_device_t dev, rt_base_t pin)
{
const struct pin_info *item;
item = pin_info_list_find(pin);
if (item == RT_NULL)
{
return PIN_LOW;
}
return GPIO_ReadInputDataBit(item->gpio, item->gpio_pin);
}
rt_err_t ch32f1_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args),
void *args)
{
struct rt_pin_irq_hdr bind_item;
bind_item.pin = pin;
bind_item.mode = mode;
bind_item.hdr = hdr;
bind_item.args = args;
return exti_line_irq_list_bind(&bind_item);
}
rt_err_t ch32f1_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
return exti_line_irq_list_unbind(pin);
}
rt_err_t ch32f1_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
struct exti_line_irq *find;
const struct pin_info *item;
rt_base_t level;
EXTI_InitTypeDef EXTI_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
find = exti_line_irq_list_find(pin);
if (find == RT_NULL)
return RT_EINVAL;
item = pin_info_list_find(pin);
if (item == RT_NULL)
return RT_EINVAL;
if (enabled == PIN_IRQ_ENABLE)
{
level = rt_hw_interrupt_disable();
GPIO_EXTILineConfig(item->portsource, item->pinsource);
EXTI_InitStructure.EXTI_Line = find->exit_line;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
switch (find->bind_irq_hdr.mode)
{
case PIN_IRQ_MODE_RISING:
{
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
}
case PIN_IRQ_MODE_FALLING:
{
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
}
case PIN_IRQ_MODE_RISING_FALLING:
{
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
default:
break;
}
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel = find->irqn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = find->nvic_priority;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = find->nvic_subpriority;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
rt_hw_interrupt_enable(level);
}
else
{
level = rt_hw_interrupt_disable();
EXTI_InitStructure.EXTI_Line = find->exit_line;
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
EXTI_Init(&EXTI_InitStructure);
NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE;
NVIC_Init(&NVIC_InitStructure);
rt_hw_interrupt_enable(level);
}
return RT_EOK;
}
/*PX.XX*/
rt_base_t ch32f1_pin_get(const char *name)
{
rt_uint16_t portsource, pinsource;
int sz;
sz = rt_strlen(name);
if (sz == 4)
{
portsource = name[1] - 0x41;
pinsource = name[3] - 0x30;
return pin_info_list_find_pin(portsource, pinsource);
}
if (sz == 5)
{
portsource = name[1];
pinsource = (name[3] - 0x30) * 10 + (name[4] - 0x30);
return pin_info_list_find_pin(portsource, pinsource);
}
return -1;
}
const static struct rt_pin_ops pin_ops = {
.pin_mode = ch32f1_pin_mode,
.pin_write = ch32f1_pin_write,
.pin_read = ch32f1_pin_read,
.pin_attach_irq = ch32f1_pin_attach_irq,
.pin_detach_irq = ch32f1_pin_detach_irq,
.pin_irq_enable = ch32f1_pin_irq_enable,
.pin_get = ch32f1_pin_get,
};
int rt_hw_pin_init(void)
{
#ifdef GPIOA
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
#endif
#ifdef GPIOB
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
#endif
#ifdef GPIOC
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
#endif
#ifdef GPIOD
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
#endif
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
return rt_device_pin_register("pin", &pin_ops, RT_NULL);
}
rt_inline void exti_irq_handler(rt_uint16_t seq)
{
if (EXTI_GetITStatus(exti_line_irq_list[seq].exit_line) == SET)
{
EXTI_ClearITPendingBit(exti_line_irq_list[seq].exit_line);
if (exti_line_irq_list[seq].use != -1 &&
exti_line_irq_list[seq].bind_irq_hdr.pin != -1 &&
exti_line_irq_list[seq].bind_irq_hdr.hdr != RT_NULL)
{
exti_line_irq_list[seq].bind_irq_hdr.hdr(exti_line_irq_list[seq].bind_irq_hdr.args);
}
}
}
void EXTI0_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(0);
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(1);
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(2);
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(3);
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(4);
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(5);
exti_irq_handler(6);
exti_irq_handler(7);
exti_irq_handler(8);
exti_irq_handler(9);
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
rt_interrupt_enter();
exti_irq_handler(10);
exti_irq_handler(11);
exti_irq_handler(12);
exti_irq_handler(13);
exti_irq_handler(14);
exti_irq_handler(15);
rt_interrupt_leave();
}
#endif /* RT_USING_PIN */

16
bsp/wch/arm/Libraries/ch32_drivers/drv_hwi2c.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef DRV_HWI2C_H__
#define DRV_HWI2C_H__
int rt_hw_i2c_init(void);
#endif

371
bsp/wch/arm/Libraries/ch32_drivers/drv_hwi2c_ch32f10x.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "board.h"
#include "drv_hwi2c.h"
#ifdef BSP_USING_HWI2C
#define LOG_TAG "drv.hwi2c"
#include "drv_log.h"
#define TIMEOUT 0x0FF
struct i2c_bus_device
{
struct rt_i2c_bus_device parent;
I2C_TypeDef *periph;
};
#ifdef BSP_USING_HWI2C1
struct i2c_bus_device i2c_bus1;
#endif
#ifdef BSP_USING_HWI2C2
struct i2c_bus_device i2c_bus2;
#endif
static int ch32f1_i2c_read(I2C_TypeDef *i2c_periph,
rt_uint8_t flags,
rt_uint16_t slave_address,
rt_uint8_t *p_buffer,
rt_uint16_t data_byte)
{
rt_uint32_t try;
if (flags & RT_I2C_ADDR_10BIT)
{
//fixme
}
else
{
//7 bit address
try = 0;
while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_BUSY) != RESET)
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read getflag timeout! \n");
return -1;
}
try++;
};
I2C_GenerateSTART(i2c_periph, ENABLE);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
};
I2C_Send7bitAddress(i2c_periph, (slave_address << 1), I2C_Direction_Transmitter);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
};
I2C_GenerateSTART(i2c_periph, ENABLE);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
};
I2C_Send7bitAddress(i2c_periph, (slave_address << 1), I2C_Direction_Receiver);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
};
if (data_byte == 1)
{
try = 0;
while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_RXNE) == RESET)
{
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
};
I2C_AcknowledgeConfig(i2c_periph, DISABLE);
*p_buffer = I2C_ReceiveData(i2c_periph);
I2C_GenerateSTOP(i2c_periph, ENABLE);
}
else
{
try = 0;
while (data_byte)
{
if (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_RXNE) == RESET)
{
*p_buffer = I2C_ReceiveData(i2c_periph);
p_buffer++;
data_byte--;
try = 0;
if (data_byte == 1)
{
I2C_AcknowledgeConfig(i2c_periph, DISABLE);
I2C_GenerateSTOP(i2c_periph, ENABLE);
}
}
if (try == TIMEOUT)
{
LOG_E("i2c bus read checkevent timeout! \n");
return -1;
}
try++;
}
}
}
return 0;
}
static int ch32f1_i2c_write(I2C_TypeDef *i2c_periph,
rt_uint8_t flags,
rt_uint16_t slave_address,
rt_uint8_t *p_buffer,
rt_uint16_t data_byte)
{
rt_uint32_t try;
if (flags & RT_I2C_ADDR_10BIT)
{
//fixme
}
else
{
//7 bit address
try = 0;
while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_BUSY) != RESET)
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write getflag timeout! \n");
return -1;
}
try++;
};
I2C_GenerateSTART(i2c_periph, ENABLE);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
I2C_Send7bitAddress(i2c_periph, (slave_address << 1), I2C_Direction_Transmitter);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
I2C_GenerateSTART(i2c_periph, ENABLE);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_MODE_SELECT))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
I2C_Send7bitAddress(i2c_periph, (slave_address << 1), I2C_Direction_Transmitter);
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
try = 0;
while (I2C_GetFlagStatus(i2c_periph, I2C_FLAG_TXE) == RESET)
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
while (data_byte)
{
I2C_SendData(i2c_periph, *p_buffer);
p_buffer++;
data_byte--;
try = 0;
while (!I2C_CheckEvent(i2c_periph, I2C_EVENT_MASTER_BYTE_TRANSMITTED))
{
if (try == TIMEOUT)
{
LOG_E("i2c bus write checkevent timeout! \n");
return -1;
}
try++;
};
}
I2C_GenerateSTOP(i2c_periph, ENABLE);
}
return 0;
}
static rt_size_t ch32f1_master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
{
struct rt_i2c_msg *msg;
struct i2c_bus_device *i2c_bus_dev;
rt_uint32_t index;
i2c_bus_dev = (struct i2c_bus_device *)bus;
for (index = 0; index < num; index++)
{
msg = &msgs[index];
if (msg->flags & RT_I2C_RD)
{
if (ch32f1_i2c_read(i2c_bus_dev->periph, msg->flags, msg->addr, msg->buf, msg->len) != 0)
{
LOG_E("i2c bus write failed,i2c bus stop!");
return 0;
}
}
else
{
if (ch32f1_i2c_write(i2c_bus_dev->periph, msg->flags, msg->addr, msg->buf, msg->len) != 0)
{
LOG_E("i2c bus write failed,i2c bus stop!");
return 0;
}
}
}
return index;
}
const struct rt_i2c_bus_device_ops ch32f1_i2c_ops = {
.master_xfer = ch32f1_master_xfer,
.slave_xfer = RT_NULL,
.i2c_bus_control = RT_NULL,
};
int rt_hw_i2c_init(void)
{
int result = RT_EOK;
#ifdef BSP_USING_HWI2C1
i2c_bus1.periph = I2C1;
ch32f1_i2c_clock_and_io_init(i2c_bus1.periph);
ch32f1_i2c_config(i2c_bus1.periph);
i2c_bus1.parent.ops = &ch32f1_i2c_ops;
result = rt_i2c_bus_device_register(&i2c_bus1.parent, "hwi2c1");
if (result != RT_EOK)
{
return result;
}
#endif
#ifdef BSP_USING_HWI2C2
i2c_bus2.periph = I2C2;
ch32f1_i2c_clock_and_io_init(i2c_bus2.periph);
ch32f1_i2c_config(i2c_bus2.periph);
i2c_bus2.parent.ops = &ch32f1_i2c_ops;
rt_i2c_bus_device_register(&i2c_bus2.parent, "hwi2c2");
if (result != RT_EOK)
{
return result;
}
#endif
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
#endif /* BSP_USING_HWI2C */

139
bsp/wch/arm/Libraries/ch32_drivers/drv_iwdt_ch32f10x.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include "ch32f10x_iwdg.h"
#ifdef BSP_USING_IWDT
#define LOG_TAG "drv.wdt"
#include "drv_log.h"
struct watchdog_device
{
rt_watchdog_t parent;
IWDG_TypeDef *instance;
rt_uint32_t Prescaler;
rt_uint32_t Reload;
rt_uint16_t is_start;
};
static struct watchdog_device watchdog_dev;
static rt_err_t ch32_wdt_init(rt_watchdog_t *wdt)
{
return RT_EOK;
}
static rt_err_t ch32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
struct watchdog_device *wdt_dev;
wdt_dev = (struct watchdog_device *)wdt;
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
IWDG_ReloadCounter();
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
#if defined(LSI_VALUE)
if (LSI_VALUE)
{
wdt_dev->Reload = (*((rt_uint32_t *)arg)) * LSI_VALUE / 256;
}
else
{
LOG_E("Please define the value of LSI_VALUE!");
}
if (wdt_dev->Reload > 0xFFF)
{
LOG_E("wdg set timeout parameter too large, please less than %ds", 0xFFF * 256 / LSI_VALUE);
return -RT_EINVAL;
}
#else
#error "Please define the value of LSI_VALUE!"
#endif
if (wdt_dev->is_start)
{
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
IWDG_SetPrescaler(wdt_dev->Prescaler);
IWDG_SetReload(wdt_dev->Reload);
IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);
IWDG_Enable();
}
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
#if defined(LSI_VALUE)
if (LSI_VALUE)
{
(*((rt_uint32_t *)arg)) = wdt_dev->Reload * 256 / LSI_VALUE;
}
else
{
LOG_E("Please define the value of LSI_VALUE!");
}
#else
#error "Please define the value of LSI_VALUE!"
#endif
break;
case RT_DEVICE_CTRL_WDT_START:
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
IWDG_SetPrescaler(wdt_dev->Prescaler);
IWDG_SetReload(wdt_dev->Reload);
IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);
IWDG_Enable();
wdt_dev->is_start = 1;
break;
default:
LOG_W("This command is not supported.");
return -RT_ERROR;
}
return RT_EOK;
}
static struct rt_watchdog_ops watchdog_ops =
{
.init = ch32_wdt_init,
.control = ch32_wdt_control,
};
int rt_hw_wdt_init(void)
{
watchdog_dev.instance = IWDG;
watchdog_dev.Prescaler = IWDG_Prescaler_256;
watchdog_dev.Reload = 0x0000FFF;
watchdog_dev.is_start = 0;
watchdog_dev.parent.ops = &watchdog_ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&watchdog_dev.parent, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;
}
LOG_D("wdt device register success.");
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_wdt_init);
#endif /* BSP_USING_IWDT */

27
bsp/wch/arm/Libraries/ch32_drivers/drv_log.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

16
bsp/wch/arm/Libraries/ch32_drivers/drv_rtc.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef DRV_RTC_H__
#define DRV_RTC_H__
int rt_hw_rtc_init(void);
#endif

131
bsp/wch/arm/Libraries/ch32_drivers/drv_rtc_ch32f10x.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <sys/time.h>
#include "board.h"
#ifdef BSP_USING_RTC
#define LOG_TAG "drv.rtc"
#include "drv_log.h"
#ifndef BKP_DR1
#define BKP_DR1 RT_NULL
#endif
#define BKUP_REG_DATA 0xA5A5
static struct rt_rtc_device rtc;
static void rt_rtc_config(void)
{
/* Allow access to BKP Domain */
PWR_BackupAccessCmd(ENABLE);
#if defined(BSP_USING_RTC_LSI) && defined(LSI_VALUE)
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);
#else
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
#endif
RCC_RTCCLKCmd(ENABLE);
RTC_WaitForLastTask();
RTC_WaitForSynchro();
if (BKP_ReadBackupRegister(BKP_DR1) != BKUP_REG_DATA)
{
LOG_I("RTC hasn't been configured, please use <date> command to config.");
/* Set RTC prescaler: set RTC period to 1sec */
RTC_SetPrescaler(32767);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
}
}
static rt_err_t ch32f1_rt_rtc_init(void)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
PWR_BackupAccessCmd(ENABLE);
#if defined(BSP_USING_RTC_LSI) && defined(LSI_VALUE)
RCC_LSICmd(ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET)
;
#else
RCC_LSEConfig(RCC_LSE_ON);
while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
;
#endif
rt_rtc_config();
return RT_EOK;
}
static rt_err_t ch32f1_get_secs(void *args)
{
*(rt_uint32_t *)args = RTC_GetCounter();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
return RT_EOK;
}
static rt_err_t ch32f1_set_secs(void *args)
{
/* Set the RTC counter value */
RTC_SetCounter(*(rt_uint32_t *)args);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
LOG_D("set rtc time.");
BKP_WriteBackupRegister(BKP_DR1, BKUP_REG_DATA);
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
return RT_EOK;
}
const static struct rt_rtc_ops rtc_ops =
{
.init = ch32f1_rt_rtc_init,
.get_secs = ch32f1_get_secs,
.set_secs = ch32f1_set_secs,
.get_alarm = RT_NULL,
.set_alarm = RT_NULL,
.get_usecs = RT_NULL,
.set_usecs = RT_NULL};
int rt_hw_rtc_init(void)
{
rt_err_t result;
rtc.ops = &rtc_ops;
result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
if (result != RT_EOK)
{
LOG_E("rtc register err code: %d", result);
return result;
}
LOG_D("rtc init success");
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /* BSP_USING_RTC */

18
bsp/wch/arm/Libraries/ch32_drivers/drv_spi.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef __DRV_SPI__
#define __DRV_SPI__
int rt_hw_spi_init(void);
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t cs_pin);
#endif

313
bsp/wch/arm/Libraries/ch32_drivers/drv_spi_ch32f10x.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <drivers/spi.h>
#include "board.h"
#include "drv_spi.h"
#include "ch32f10x_spi.h"
#include "ch32f10x_rcc.h"
#ifdef BSP_USING_SPI
#define LOG_TAG "drv.spi"
#include "drv_log.h"
#ifndef ITEM_NUM
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#endif
struct spi_bus_device
{
struct rt_spi_bus parent;
char *name;
SPI_TypeDef *periph;
rt_base_t cs_pin;
struct rt_spi_device spi_device;
};
static struct spi_bus_device spi_bus_device_list[] = {
#ifdef BSP_USING_SPI1
{.periph = SPI1,
.name = "spi1"},
#endif
#ifdef BSP_USING_SPI2
{.periph = SPI2,
.name = "spi2"},
#endif
};
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
{
rt_err_t result;
struct rt_spi_bus *spi_bus;
struct spi_bus_device *spi_bus_dev;
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
spi_bus = (struct rt_spi_bus *)rt_device_find(bus_name);
RT_ASSERT(spi_bus != RT_NULL);
spi_bus_dev = (struct spi_bus_device *)spi_bus;
spi_bus_dev->cs_pin = pin;
//often active low, output from master
rt_pin_mode(spi_bus_dev->cs_pin, PIN_MODE_OUTPUT);
rt_pin_write(spi_bus_dev->cs_pin, PIN_HIGH);
result = rt_spi_bus_attach_device(&spi_bus_dev->spi_device, device_name, bus_name, RT_NULL);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
static rt_err_t ch32f1_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
{
struct rt_spi_bus *spi_bus;
struct spi_bus_device *spi_bus_dev;
rt_uint32_t spi_clock;
SPI_InitTypeDef SPI_InitStruct;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
//device is not RT_NULL, so spi_bus not need check
spi_bus = (struct rt_spi_bus *)device->bus;
spi_bus_dev = (struct spi_bus_device *)spi_bus;
ch32f1_spi_clock_and_io_init(spi_bus_dev->periph);
spi_clock = ch32f1_spi_clock_get(spi_bus_dev->periph);
if (configuration->data_width <= 8)
{
SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b;
}
else if (configuration->data_width <= 16)
{
SPI_InitStruct.SPI_DataSize = SPI_DataSize_16b;
}
else
{
return RT_EIO;
}
if (configuration->max_hz >= spi_clock / 2)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
}
else if (configuration->max_hz >= spi_clock / 4)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4;
}
else if (configuration->max_hz >= spi_clock / 8)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
}
else if (configuration->max_hz >= spi_clock / 16)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
}
else if (configuration->max_hz >= spi_clock / 32)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;
}
else if (configuration->max_hz >= spi_clock / 64)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
}
else if (configuration->max_hz >= spi_clock / 128)
{
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_128;
}
else
{
/* min prescaler 256 */
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
}
switch (configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;
break;
case RT_SPI_MODE_1:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;
break;
case RT_SPI_MODE_2:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
break;
case RT_SPI_MODE_3:
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
break;
}
/* MSB or LSB */
if (configuration->mode & RT_SPI_MSB)
{
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
}
else
{
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_LSB;
}
SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct.SPI_Mode = SPI_Mode_Master;
SPI_InitStruct.SPI_NSS = SPI_NSS_Soft;
SPI_Init(spi_bus_dev->periph, &SPI_InitStruct);
/* Enable SPI_MASTER */
SPI_Cmd(spi_bus_dev->periph, ENABLE);
return RT_EOK;
};
static rt_uint32_t ch32f1_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
struct rt_spi_bus *spi_bus;
struct spi_bus_device *spi_bus_dev;
struct rt_spi_configuration *config;
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
//device is not RT_NULL, so spi_bus not need check
spi_bus = (struct rt_spi_bus *)device->bus;
spi_bus_dev = (struct spi_bus_device *)spi_bus;
config = &device->config;
/* take CS */
if (message->cs_take)
{
rt_pin_write(spi_bus_dev->cs_pin, PIN_LOW);
LOG_D("spi take cs\n");
}
if (config->data_width <= 8)
{
const rt_uint8_t *send_ptr = message->send_buf;
rt_uint8_t *recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
rt_uint8_t data;
LOG_D("spi poll transfer start: %d\n", size);
while (size--)
{
data = 0xFF;
if (send_ptr != RT_NULL)
{
data = *send_ptr++;
}
//Wait until the transmit buffer is empty
while (RESET == SPI_I2S_GetFlagStatus(spi_bus_dev->periph, SPI_I2S_FLAG_TXE))
;
// Send the byte
SPI_I2S_SendData(spi_bus_dev->periph, data);
//Wait until a data is received
while (RESET == SPI_I2S_GetFlagStatus(spi_bus_dev->periph, SPI_I2S_FLAG_RXNE))
;
// Get the received data
data = SPI_I2S_ReceiveData(spi_bus_dev->periph);
if (recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
LOG_D("spi poll transfer finsh\n");
}
else if (config->data_width <= 16)
{
const rt_uint16_t *send_ptr = message->send_buf;
rt_uint16_t *recv_ptr = message->recv_buf;
rt_uint32_t size = message->length;
rt_uint16_t data;
while (size--)
{
data = 0xFF;
if (send_ptr != RT_NULL)
{
data = *send_ptr++;
}
//Wait until the transmit buffer is empty
while (RESET == SPI_I2S_GetFlagStatus(spi_bus_dev->periph, SPI_I2S_FLAG_TXE))
;
// Send the byte
SPI_I2S_SendData(spi_bus_dev->periph, data);
//Wait until a data is received
while (RESET == SPI_I2S_GetFlagStatus(spi_bus_dev->periph, SPI_I2S_FLAG_RXNE))
;
// Get the received data
data = SPI_I2S_ReceiveData(spi_bus_dev->periph);
if (recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
}
}
/* release CS */
if (message->cs_release)
{
rt_pin_write(spi_bus_dev->cs_pin, PIN_HIGH);
LOG_D("spi release cs\n");
}
return message->length;
};
static struct rt_spi_ops spi_ops = {
.configure = ch32f1_spi_configure,
.xfer = ch32f1_spi_xfer};
int rt_hw_spi_init(void)
{
int index;
for (index = 0; index < ITEM_NUM(spi_bus_device_list); index++)
{
rt_spi_bus_register(&spi_bus_device_list[index].parent, spi_bus_device_list[index].name, &spi_ops);
}
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
#endif /* BSP_USING_SPI */

16
bsp/wch/arm/Libraries/ch32_drivers/drv_uart.h Normal file
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@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
int rt_hw_uart_init(void);
#endif

295
bsp/wch/arm/Libraries/ch32_drivers/drv_uart_ch32f10x.c Normal file
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@@ -0,0 +1,295 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
#include "ch32f10x_usart.h"
#include "ch32f10x_misc.h"
#ifdef BSP_USING_UART
#ifndef ITEM_NUM
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#endif
struct usart_device
{
struct rt_serial_device parent;
char *name;
USART_TypeDef *periph;
IRQn_Type irqn;
};
#ifdef BSP_USING_UART1
static struct usart_device usart_device1 =
{
.name = "uart1",
.periph = USART1,
.irqn = USART1_IRQn,
};
#endif
#ifdef BSP_USING_UART2
static struct usart_device usart_device2 =
{
.name = "uart2",
.periph = USART2,
.irqn = USART2_IRQn,
};
#endif
#ifdef BSP_USING_UART3
static struct usart_device usart_device3 =
{
.name = "uart3",
.periph = USART3,
.irqn = USART3_IRQn,
};
#endif
static rt_err_t ch32f1_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct usart_device *usart_dev;
USART_InitTypeDef USART_InitStructure;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
usart_dev = (struct usart_device *)serial;
RT_ASSERT(usart_dev != RT_NULL);
ch32f1_usart_clock_and_io_init(usart_dev->periph);
USART_StructInit(&USART_InitStructure);
USART_InitStructure.USART_BaudRate = cfg->baud_rate;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
switch (cfg->data_bits)
{
case DATA_BITS_8:
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
break;
case DATA_BITS_9:
USART_InitStructure.USART_WordLength = USART_WordLength_9b;
break;
default:
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
USART_InitStructure.USART_StopBits = USART_StopBits_1;
break;
case STOP_BITS_2:
USART_InitStructure.USART_StopBits = USART_StopBits_2;
break;
default:
USART_InitStructure.USART_StopBits = USART_StopBits_1;
break;
}
switch (cfg->parity)
{
case PARITY_NONE:
USART_InitStructure.USART_Parity = USART_Parity_No;
break;
case PARITY_ODD:
USART_InitStructure.USART_Parity = USART_Parity_Odd;
break;
case PARITY_EVEN:
USART_InitStructure.USART_Parity = USART_Parity_Even;
break;
default:
USART_InitStructure.USART_Parity = USART_Parity_No;
break;
}
USART_Init(usart_dev->periph, &USART_InitStructure);
USART_Cmd(usart_dev->periph, ENABLE);
return RT_EOK;
}
static rt_err_t ch32f1_usart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct usart_device *usart_dev;
NVIC_InitTypeDef NVIC_InitStruct;
RT_ASSERT(serial != RT_NULL);
usart_dev = (struct usart_device *)serial;
RT_ASSERT(usart_dev != RT_NULL);
NVIC_InitStruct.NVIC_IRQChannel = usart_dev->irqn;
NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStruct.NVIC_IRQChannelSubPriority = 1;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
NVIC_InitStruct.NVIC_IRQChannelCmd = DISABLE;
NVIC_Init(&NVIC_InitStruct);
USART_ITConfig(usart_dev->periph, USART_IT_RXNE, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStruct);
USART_ITConfig(usart_dev->periph, USART_IT_RXNE, ENABLE);
break;
}
return RT_EOK;
}
static int ch32f1_usart_putc(struct rt_serial_device *serial, char ch)
{
struct usart_device *usart_dev;
RT_ASSERT(serial != RT_NULL);
usart_dev = (struct usart_device *)serial;
RT_ASSERT(usart_dev != RT_NULL);
USART_SendData(usart_dev->periph, (uint8_t)ch);
while (USART_GetFlagStatus(usart_dev->periph, USART_FLAG_TXE) == RESET)
;
return 1;
}
static int ch32f1_usart_getc(struct rt_serial_device *serial)
{
struct usart_device *usart_dev;
int ch;
RT_ASSERT(serial != RT_NULL);
usart_dev = (struct usart_device *)serial;
RT_ASSERT(usart_dev != RT_NULL);
ch = -1;
if (RESET != USART_GetFlagStatus(usart_dev->periph, USART_FLAG_RXNE))
{
ch = USART_ReceiveData(usart_dev->periph) & 0xff;
}
return ch;
}
static const struct rt_uart_ops usart_ops = {
.configure = ch32f1_usart_configure,
.control = ch32f1_usart_control,
.putc = ch32f1_usart_putc,
.getc = ch32f1_usart_getc,
.dma_transmit = RT_NULL};
static void usart_isr(struct usart_device *usart_dev)
{
RT_ASSERT(usart_dev != RT_NULL);
if ((USART_GetITStatus(usart_dev->periph, USART_IT_RXNE) != RESET) && (RESET != USART_GetFlagStatus(usart_dev->periph, USART_FLAG_RXNE)))
{
rt_hw_serial_isr(&usart_dev->parent, RT_SERIAL_EVENT_RX_IND);
USART_ClearITPendingBit(usart_dev->periph, USART_IT_RXNE);
USART_ClearFlag(usart_dev->periph, USART_FLAG_RXNE);
}
else
{
if (USART_GetFlagStatus(usart_dev->periph, USART_FLAG_CTS) != RESET)
{
USART_ClearFlag(usart_dev->periph, USART_FLAG_CTS);
}
if (USART_GetFlagStatus(usart_dev->periph, USART_FLAG_LBD) != RESET)
{
USART_ClearFlag(usart_dev->periph, USART_FLAG_LBD);
}
if (USART_GetFlagStatus(usart_dev->periph, USART_FLAG_TC) != RESET)
{
USART_ClearFlag(usart_dev->periph, USART_FLAG_TC);
}
}
}
#ifdef BSP_USING_UART1
void USART1_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&usart_device1);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART2
void USART2_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&usart_device2);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART3
void USART3_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&usart_device3);
rt_interrupt_leave();
}
#endif
int rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART1
usart_device1.parent.ops = &usart_ops;
usart_device1.parent.config = config;
rt_hw_serial_register(&usart_device1.parent, usart_device1.name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX,
RT_NULL);
#endif
#ifdef BSP_USING_UART2
usart_device2.parent.ops = &usart_ops;
usart_device2.parent.config = config;
rt_hw_serial_register(&usart_device2.parent, usart_device2.name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX,
RT_NULL);
#endif
#ifdef BSP_USING_UART3
usart_device3.parent.ops = &usart_ops;
usart_device3.parent.config = config;
rt_hw_serial_register(&usart_device3.parent, usart_device3.name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX,
RT_NULL);
#endif
return RT_EOK;
}
#endif /* BSP_USING_UART */

609
bsp/wch/arm/ch32f103c8-core/.config Normal file
View File

@@ -0,0 +1,609 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M3=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
CONFIG_RT_I2C_DEBUG=y
# CONFIG_RT_USING_I2C_BITOPS is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_LIBC_USING_TIME=y
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_WCWIDTH is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_TERMBOX is not set
CONFIG_SOC_ARM_FAMILY_CH32=y
CONFIG_SOC_ARM_SERIES_CH32F103=y
#
# Hardware Drivers Config
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
CONFIG_BSP_USING_UART2=y
CONFIG_BSP_USING_UART3=y
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI1=y
CONFIG_BSP_USING_SPI2=y
CONFIG_BSP_USING_HWI2C=y
CONFIG_BSP_USING_HWI2C1=y
CONFIG_BSP_USING_HWI2C2=y
CONFIG_BSP_USING_IWDT=y
CONFIG_BSP_USING_RTC=y
CONFIG_BSP_USING_RTC_LSI=y
CONFIG_LSI_VALUE=40000
#
# Onboard Peripheral Drivers
#
#
# Board extended module Drivers
#

21
bsp/wch/arm/ch32f103c8-core/Kconfig Normal file
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@@ -0,0 +1,21 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../Libraries/Kconfig"
source "board/Kconfig"

99
bsp/wch/arm/ch32f103c8-core/README.md Normal file
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# ch32f103c8 BSP 说明
## 简介
| 硬件 | 描述 |
| --------- | ------------- |
| 芯片型号 | ch32f103c8 |
| CPU | ARM Cortex M3 |
| 主频 | 72M |
| 片内SRAM | 20K |
| 片内FLASH | 64K |
## 编译说明
板级包支持MDK5开发环境，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| ---------- | ---------------------------- |
| MDK5 | MDK534 |
## 外设支持
本 BSP 目前对外设驱动的支持情况如下：
| 驱动 | 支持情况 | 备注 |
| --------- | -------- | :------------------------:|
| UART | 支持 | USART1/2/3 |
| GPIO | 支持 | PA0...PD2 |
| IIC | 支持 | 硬件I2C(7位) |
| SPI | 支持 | SPI1/2 |
| WDT | 支持 | IWDG |
| RTC | 支持 | 外部或内部低速晶振 |
### IO在板级支持包中的映射情况
| IO号 | 板级包中的定义 |
| ---- | -------------- |
| PA9 | USART1_TX |
| PA10 | USART1_RX |
| PA2 | USART2_TX |
| PA3 | USART2_RX |
| PC10 | USART3_TX |
| PC11 | USART3_RX |
| PA4 | SPI1_CS |
| PA5 | SPI1_SCK |
| PA6 | SPI1_MISO |
| PA7 | SPI1_MOSI |
| PB12 | SPI2_CS |
| PB13 | SPI2_SCK |
| PB14 | SPI2_MISO |
| PB15 | SPI2_MOSI |
| PB8 | I2C1_SCL |
| PB9 | I2C1_SDA |
| PB10 | I2C2_SCL |
| PB11 | I2C2_SDA |
## 使用说明
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
### 快速上手
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 SWD 下载程序，在通过 wch-link或公版daplink 连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，在串口上可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Aug 30 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
## 联系人信息
维护人:
- [charlown](https://github.com/charlown)

15
bsp/wch/arm/ch32f103c8-core/SConscript Normal file
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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

60
bsp/wch/arm/ch32f103c8-core/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/Libraries'):
libraries_path_prefix = SDK_ROOT + '/Libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
ch32_library = 'CH32F10x_StdPeriph_Driver'
rtconfig.BSP_LIBRARY_TYPE = ch32_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, ch32_library, 'SConscript')))
# common include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ch32_drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

17
bsp/wch/arm/ch32f103c8-core/applications/SConscript Normal file
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# RT-Thread building script for component
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
main.c
""")
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

18
bsp/wch/arm/ch32f103c8-core/applications/main.c Normal file
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@@ -0,0 +1,18 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
int main(void)
{
return RT_EOK;
}

95
bsp/wch/arm/ch32f103c8-core/board/Kconfig Normal file
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menu "Hardware Drivers Config"
config SOC_ARM_SERIES_CH32F103
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "On-chip Peripheral Drivers"
config BSP_USING_UART
bool "using onchip usart"
select RT_USING_SERIAL
default n
if BSP_USING_UART
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default n
config BSP_USING_UART3
bool "using uart3"
default n
endif
config BSP_USING_SPI
bool "using onchip spi"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "using spi1"
default n
config BSP_USING_SPI2
bool "using spi2"
default n
endif
config BSP_USING_HWI2C
bool "using onchip i2c"
select RT_USING_I2C
default n
if BSP_USING_HWI2C
config BSP_USING_HWI2C1
bool "using i2c1"
default n
config BSP_USING_HWI2C2
bool "using i2c2"
default n
endif
config BSP_USING_IWDT
bool "using onchip iwdt"
select RT_USING_WDT
select LSI_VALUE
default n
config BSP_USING_RTC
bool "using onchip rtc"
select RT_USING_RTC
default n
if BSP_USING_RTC
config BSP_USING_RTC_LSI
bool "using LSI clock for rtc, if not, LSE default"
select LSI_VALUE
default n
endif
config LSI_VALUE
int
default 40000
endmenu
menu "Onboard Peripheral Drivers"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

25
bsp/wch/arm/ch32f103c8-core/board/SConscript Normal file
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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
system_ch32f10x.c
board.c
''')
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/CH32F10x_StdPeriph_Driver/CMSIS/WCH/CH32F10x/Source/ARM/startup_ch32f10x.s']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

203
bsp/wch/arm/ch32f103c8-core/board/board.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "board.h"
#include "ch32f10x_rcc.h"
rt_uint32_t ch32_get_sysclock_frequency(void)
{
RCC_ClocksTypeDef RCC_Clocks;
RCC_GetClocksFreq(&RCC_Clocks);
return RCC_Clocks.SYSCLK_Frequency;
}
void ch32f1_usart_clock_and_io_init(USART_TypeDef *usartx)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (usartx == USART1)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
/* USART1 TX-->A.9 RX-->A.10 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
}
if (usartx == USART2)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
/* USART2 TX-->A.2 RX-->A.3 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOA, &GPIO_InitStructure);
}
if (usartx == USART3)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
/* USART3 TX-->C.10 RX-->C.11 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
}
}
void ch32f1_spi_clock_and_io_init(SPI_TypeDef *spix)
{
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
if (spix == SPI1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_7;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_Init(GPIOB, &GPIO_InitStructure);
}
if (spix == SPI2)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
GPIO_Init(GPIOB, &GPIO_InitStructure);
}
}
rt_uint32_t ch32f1_spi_clock_get(SPI_TypeDef *spix)
{
RCC_ClocksTypeDef RCC_Clocks;
RCC_GetClocksFreq(&RCC_Clocks);
if (spix == SPI1)
{
return RCC_Clocks.PCLK2_Frequency;
}
if (spix == SPI2)
{
return RCC_Clocks.PCLK1_Frequency;
}
return RCC_Clocks.PCLK2_Frequency;
}
void ch32f1_i2c_clock_and_io_init(I2C_TypeDef *i2cx)
{
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
if (i2cx == I2C1)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_PinRemapConfig(GPIO_Remap_I2C1, ENABLE);
}
if (i2cx == I2C2)
{
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11;
GPIO_Init(GPIOB, &GPIO_InitStructure);
}
}
void ch32f1_i2c_config(I2C_TypeDef *i2cx)
{
I2C_InitTypeDef I2C_InitTSturcture;
if (i2cx == I2C1)
{
I2C_InitTSturcture.I2C_ClockSpeed = 100000;
I2C_InitTSturcture.I2C_Mode = I2C_Mode_I2C;
I2C_InitTSturcture.I2C_DutyCycle = I2C_DutyCycle_16_9;
I2C_InitTSturcture.I2C_OwnAddress1 = 0;
I2C_InitTSturcture.I2C_Ack = I2C_Ack_Enable;
I2C_InitTSturcture.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_Init(I2C1, &I2C_InitTSturcture);
I2C_Cmd(I2C1, ENABLE);
I2C_AcknowledgeConfig(I2C1, ENABLE);
}
if (i2cx == I2C2)
{
I2C_InitTSturcture.I2C_ClockSpeed = 100000;
I2C_InitTSturcture.I2C_Mode = I2C_Mode_I2C;
I2C_InitTSturcture.I2C_DutyCycle = I2C_DutyCycle_16_9;
I2C_InitTSturcture.I2C_OwnAddress1 = 0;
I2C_InitTSturcture.I2C_Ack = I2C_Ack_Enable;
I2C_InitTSturcture.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_Init(I2C2, &I2C_InitTSturcture);
I2C_Cmd(I2C2, ENABLE);
I2C_AcknowledgeConfig(I2C2, ENABLE);
}
}

57
bsp/wch/arm/ch32f103c8-core/board/board.h Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-10 charlown first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "ch32f10x.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CH32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define FLASH_PAGE_SIZE (64)
#define CH32_FLASH_SIZE (1024 * 1024)
#define CH32_FLASH_END_ADDRESS ((uint32_t)(CH32_FLASH_START_ADRESS + CH32_FLASH_SIZE))
#define CH32_SRAM_SIZE 20
#define CH32_SRAM_END (0x20000000 + CH32_SRAM_SIZE * 1024)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END CH32_SRAM_END
#ifdef __cplusplus
}
#endif
rt_uint32_t ch32_get_sysclock_frequency(void);
void ch32f1_usart_clock_and_io_init(USART_TypeDef* usartx);
void ch32f1_spi_clock_and_io_init(SPI_TypeDef* spix);
rt_uint32_t ch32f1_spi_clock_get(SPI_TypeDef* spix);
void ch32f1_i2c_clock_and_io_init(I2C_TypeDef* i2cx);
void ch32f1_i2c_config(I2C_TypeDef* i2cx);
#endif /* __BOARD_H__ */

33
bsp/wch/arm/ch32f103c8-core/board/ch32f10x_conf.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32f10x_conf.h
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : Library configuration file.
*******************************************************************************/
#ifndef __CH32F10x_CONF_H
#define __CH32F10x_CONF_H
#include "ch32f10x_adc.h"
#include "ch32f10x_bkp.h"
#include "ch32f10x_can.h"
#include "ch32f10x_crc.h"
#include "ch32f10x_dac.h"
#include "ch32f10x_dbgmcu.h"
#include "ch32f10x_dma.h"
#include "ch32f10x_exti.h"
#include "ch32f10x_flash.h"
#include "ch32f10x_gpio.h"
#include "ch32f10x_i2c.h"
#include "ch32f10x_iwdg.h"
#include "ch32f10x_pwr.h"
#include "ch32f10x_rcc.h"
#include "ch32f10x_rtc.h"
#include "ch32f10x_spi.h"
#include "ch32f10x_tim.h"
#include "ch32f10x_usart.h"
#include "ch32f10x_wwdg.h"
#include "ch32f10x_misc.h"
#endif /* __CH32F10x_CONF_H */

16
bsp/wch/arm/ch32f103c8-core/board/linker_scripts/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00010000 { ; load region size_region
ER_IROM1 0x08000000 0x00010000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00005000 { ; RW data
.ANY (+RW +ZI)
}
}

554
bsp/wch/arm/ch32f103c8-core/board/system_ch32f10x.c Normal file
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/*********************COPYRIGHT(C) 2019 WCH. A11 rights reserved***********************
* File Name : ch32f10x_system.c
* Author : WCH
* Version : V1.0.0
* Date : 2019/10/15
* Description : CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
****************************************************************************************/
#include "ch32f10x.h"
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
// #define SYSCLK_FREQ_HSE HSE_VALUE
/* #define SYSCLK_FREQ_24MHz 24000000 */
// #define SYSCLK_FREQ_48MHz 48000000
/* #define SYSCLK_FREQ_56MHz 56000000 */
#define SYSCLK_FREQ_72MHz 72000000
/* Uncomment the following line if you need to relocate your vector Table in Internal SRAM */
/* #define VECT_TAB_SRAM */
/* Vector Table base offset field This value must be a multiple of 0x200 */
#define VECT_TAB_OFFSET 0x0
/* Clock Definitions */
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */
uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* ch32f10x_system_private_functionprototypes */
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE(void);
#elif defined SYSCLK_FREQ_24MHz
static void SetSysClockTo24(void);
#elif defined SYSCLK_FREQ_48MHz
static void SetSysClockTo48(void);
#elif defined SYSCLK_FREQ_56MHz
static void SetSysClockTo56(void);
#elif defined SYSCLK_FREQ_72MHz
static void SetSysClockTo72(void);
#endif
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/******************************************************************************************
* Function Name : SystemInit
* Description : Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
* Input : None
* Return : None
*******************************************************************************************/
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/******************************************************************************************
* Function Name : SystemCoreClockUpdate
* Description : Update SystemCoreClock variable according to Clock Register Values.
* Input : None
* Return : None
*******************************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
{
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
}
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
SystemCoreClock >>= tmp;
}
/******************************************************************************************
* Function Name : SetSysClock
* Description : Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClock(void)
{
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_24MHz
SetSysClockTo24();
#elif defined SYSCLK_FREQ_48MHz
SetSysClockTo48();
#elif defined SYSCLK_FREQ_56MHz
SetSysClockTo56();
#elif defined SYSCLK_FREQ_72MHz
SetSysClockTo72();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
* source (default after reset)
*/
}
#ifdef DATA_IN_ExtSRAM
/******************************************************************************************
* Function Name : SystemInit_ExtMemCtl
* Description : Setup the external memory controller.
* Input : None
* Return : None
*******************************************************************************************/
void SystemInit_ExtMemCtl(void)
{
RCC->AHBENR = 0x00000114;
RCC->APB2ENR = 0x000001E0;
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#ifdef SYSCLK_FREQ_HSE
/******************************************************************************************
* Function Name : SetSysClockToHSE
* Description : elects HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
/* Select HSE as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_24MHz
/******************************************************************************************
* Function Name : SetSysClockTo24
* Description : Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo24(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz
/******************************************************************************************
* Function Name : SetSysClockTo48
* Description : Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo48(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 1 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_56MHz
/******************************************************************************************
* Function Name : SetSysClockTo56
* Description : Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo56(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_72MHz
/******************************************************************************************
* Function Name : SetSysClockTo72
* Description : Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
* Input : None
* Return : None
*******************************************************************************************/
static void SetSysClockTo72(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
/* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#endif

851
bsp/wch/arm/ch32f103c8-core/project.uvprojx Normal file
View File

@@ -0,0 +1,851 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread-ch32f103x</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>CH32F103C8</Device>
<Vendor>WCH</Vendor>
<PackID>Keil.WCH32F1xx_DFP.1.0.1</PackID>
<PackURL>http://www.wch.cn/</PackURL>
<Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0CH32F1xx -FS08000000 -FL010000 -FP0($$Device:CH32F103C8$Flash\CH32F1xx.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:CH32F103C8$Device\Include\ch32f10x.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:CH32F103C8$SVD\CH32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rt-thread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x10000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>3</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>__RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine></Undefine>
<IncludePath>applications;.;..\Libraries\CH32F10x_StdPeriph_Driver\CMSIS;..\Libraries\CH32F10x_StdPeriph_Driver\CMSIS\WCH\CH32F10x\Include;..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\inc;..\..\..\..\libcpu\arm\common;..\..\..\..\libcpu\arm\cortex-m3;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\spi;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;board;..\Libraries\ch32_drivers;..\Libraries\ch32_drivers\config;.;..\..\..\..\include;..\..\..\..\components\libc\compilers\common;..\..\..\..\components\libc\compilers\common\none-gcc;..\..\..\..\components\finsh;..\..\..\..\examples\utest\testcases\kernel</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Applications</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>applications\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>ch32f10x_lib</GroupName>
<Files>
<File>
<FileName>ch32f10x_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_wwdg.c</FilePath>
</File>
<File>
<FileName>ch32f10x_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_pwr.c</FilePath>
</File>
<File>
<FileName>ch32f10x_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_i2c.c</FilePath>
</File>
<File>
<FileName>ch32f10x_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_usart.c</FilePath>
</File>
<File>
<FileName>ch32f10x_iwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_iwdg.c</FilePath>
</File>
<File>
<FileName>ch32f10x_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_tim.c</FilePath>
</File>
<File>
<FileName>ch32f10x_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_dma.c</FilePath>
</File>
<File>
<FileName>ch32f10x_dbgmcu.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_dbgmcu.c</FilePath>
</File>
<File>
<FileName>ch32f10x_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_spi.c</FilePath>
</File>
<File>
<FileName>ch32f10x_bkp.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_bkp.c</FilePath>
</File>
<File>
<FileName>ch32f10x_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_rtc.c</FilePath>
</File>
<File>
<FileName>ch32f10x_can.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_can.c</FilePath>
</File>
<File>
<FileName>ch32f10x_misc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_misc.c</FilePath>
</File>
<File>
<FileName>ch32f10x_dac.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_dac.c</FilePath>
</File>
<File>
<FileName>ch32f10x_exti.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_exti.c</FilePath>
</File>
<File>
<FileName>ch32f10x_crc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_crc.c</FilePath>
</File>
<File>
<FileName>ch32f10x_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_adc.c</FilePath>
</File>
<File>
<FileName>ch32f10x_flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_flash.c</FilePath>
</File>
<File>
<FileName>ch32f10x_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_gpio.c</FilePath>
</File>
<File>
<FileName>ch32f10x_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\StdPeriph_Driver\src\ch32f10x_rcc.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\libcpu\arm\cortex-m3\context_rvds.S</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\libcpu\arm\cortex-m3\cpuport.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>0</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define> </Define>
<Undefine> </Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<ClangAsOpt>0</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>i2c_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\i2c\i2c_core.c</FilePath>
</File>
<File>
<FileName>i2c_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\i2c\i2c_dev.c</FilePath>
</File>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\rtc\rtc.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\serial\serial.c</FilePath>
</File>
<File>
<FileName>spi_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\spi\spi_core.c</FilePath>
</File>
<File>
<FileName>spi_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\spi\spi_dev.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\ringbuffer.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\workqueue.c</FilePath>
</File>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\completion.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\waitqueue.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\pipe.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
<File>
<FileName>watchdog.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\drivers\watchdog\watchdog.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>startup_ch32f10x.s</FileName>
<FileType>2</FileType>
<FilePath>..\Libraries\CH32F10x_StdPeriph_Driver\CMSIS\WCH\CH32F10x\Source\ARM\startup_ch32f10x.s</FilePath>
</File>
<File>
<FileName>system_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>board\system_ch32f10x.c</FilePath>
</File>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>drv_rtc_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_rtc_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_hwi2c_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_hwi2c_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_gpio_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_gpio_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_spi_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_spi_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_uart_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_uart_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_iwdt_ch32f10x.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_iwdt_ch32f10x.c</FilePath>
</File>
<File>
<FileName>drv_common.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\ch32_drivers\drv_common.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\idle.c</FilePath>
</File>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\ipc.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\components.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\timer.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\mem.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\clock.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\object.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\device.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\src\thread.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<Files>
<File>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\libc\compilers\common\time.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>msh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>project</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

202
bsp/wch/arm/ch32f103c8-core/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2"
#define RT_VER_NUM 0x40004
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_I2C
#define RT_I2C_DEBUG
#define RT_USING_PIN
#define RT_USING_RTC
#define RT_USING_SPI
#define RT_USING_WDT
/* Using USB */
/* POSIX layer and C standard library */
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define SOC_ARM_FAMILY_CH32
#define SOC_ARM_SERIES_CH32F103
/* Hardware Drivers Config */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_UART2
#define BSP_USING_UART3
#define BSP_USING_SPI
#define BSP_USING_SPI1
#define BSP_USING_SPI2
#define BSP_USING_HWI2C
#define BSP_USING_HWI2C1
#define BSP_USING_HWI2C2
#define BSP_USING_IWDT
#define BSP_USING_RTC
#define BSP_USING_RTC_LSI
#define LSI_VALUE 40000
/* Onboard Peripheral Drivers */
/* Board extended module Drivers */
#endif

150
bsp/wch/arm/ch32f103c8-core/rtconfig.py Normal file
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import os
# toolchains options
ARCH='arm'
CPU='cortex-m3'
CROSS_TOOL='keil'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m0plus -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M3 '
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map'
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M0'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M0'
AFLAGS += ' --fpu None'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

390
bsp/wch/arm/ch32f103c8-core/template.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread-ch32f103x</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>CH32F103C8</Device>
<Vendor>WCH</Vendor>
<PackID>Keil.WCH32F1xx_DFP.1.0.1</PackID>
<PackURL>http://www.wch.cn/</PackURL>
<Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0CH32F1xx -FS08000000 -FL010000 -FP0($$Device:CH32F103C8$Flash\CH32F1xx.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:CH32F103C8$Device\Include\ch32f10x.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:CH32F103C8$SVD\CH32F103xx.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
<OutputName>rt-thread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>0</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x10000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>

36
bsp/wch/arm/tools/sdk_dist.py Normal file
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import os
import sys
import shutil
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
# BSP dist function
def dist_do_building(BSP_ROOT, dist_dir):
from mkdist import bsp_copy_files
import rtconfig
print("=> copy ch32 bsp library")
library_dir = os.path.join(dist_dir, 'Libraries')
library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries')
bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE),
os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
print("=> copy bsp drivers")
bsp_copy_files(os.path.join(library_path, 'ch32_drivers'), os.path.join(library_dir, 'ch32_drivers'))
shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
# change RTT_ROOT in Kconfig
if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')):
return
with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f:
data = f.readlines()
with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f:
found = 0
for line in data:
if line.find('RTT_ROOT') != -1:
found = 1
if line.find('../Libraries') != -1 and found:
position = line.find('../Libraries')
line = line[0:position] + 'Libraries/Kconfig"\n'
found = 0
f.write(line)