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Boolify the 'fetch' parameter of the get_thread_regcache function. All of the current uses pass true for this parameter. Therefore, define its default value as true and remove the argument from the uses. We still keep the parameter, though, to give downstream targets the option to obtain a regcache without having to fetch the whole contents. Our (Intel) downstream target is an example. Approved-By: Simon Marchi <simon.marchi@efficios.com>
303 lines
8.0 KiB
C++
303 lines
8.0 KiB
C++
/* Copyright (C) 1995-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "arch/arm.h"
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#include "arch/arm-linux.h"
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#include "linux-low.h"
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#include "linux-aarch32-low.h"
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#include <sys/ptrace.h>
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/* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h.
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On Bionic elf.h and linux/elf.h have conflicting definitions. */
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#ifndef ELFMAG0
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#include <elf.h>
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#endif
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/* Correct in either endianness. */
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#define arm_abi_breakpoint 0xef9f0001UL
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/* For new EABI binaries. We recognize it regardless of which ABI
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is used for gdbserver, so single threaded debugging should work
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OK, but for multi-threaded debugging we only insert the current
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ABI's breakpoint instruction. For now at least. */
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#define arm_eabi_breakpoint 0xe7f001f0UL
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#if (defined __ARM_EABI__ || defined __aarch64__)
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static const unsigned long arm_breakpoint = arm_eabi_breakpoint;
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#else
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static const unsigned long arm_breakpoint = arm_abi_breakpoint;
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#endif
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#define arm_breakpoint_len 4
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static const unsigned short thumb_breakpoint = 0xde01;
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#define thumb_breakpoint_len 2
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static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 };
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#define thumb2_breakpoint_len 4
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/* Some older versions of GNU/Linux and Android do not define
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the following macros. */
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#ifndef NT_ARM_VFP
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#define NT_ARM_VFP 0x400
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#endif
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/* Collect GP registers from REGCACHE to buffer BUF. */
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void
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arm_fill_gregset (struct regcache *regcache, void *buf)
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{
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int i;
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uint32_t *regs = (uint32_t *) buf;
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uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
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for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
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collect_register (regcache, i, ®s[i]);
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collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]);
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/* Keep reserved bits bit 20 to bit 23. */
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regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
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| (cpsr & 0x00f00000));
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}
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/* Supply GP registers contents, stored in BUF, to REGCACHE. */
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void
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arm_store_gregset (struct regcache *regcache, const void *buf)
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{
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int i;
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char zerobuf[8];
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const uint32_t *regs = (const uint32_t *) buf;
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uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
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memset (zerobuf, 0, 8);
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for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
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supply_register (regcache, i, ®s[i]);
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for (; i < ARM_PS_REGNUM; i++)
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supply_register (regcache, i, zerobuf);
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/* Clear reserved bits bit 20 to bit 23. */
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cpsr &= 0xff0fffff;
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supply_register (regcache, ARM_PS_REGNUM, &cpsr);
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}
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/* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */
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void
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arm_fill_vfpregset_num (struct regcache *regcache, void *buf, int num)
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{
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int i, base;
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gdb_assert (num == 16 || num == 32);
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base = find_regno (regcache->tdesc, "d0");
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for (i = 0; i < num; i++)
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collect_register (regcache, base + i, (char *) buf + i * 8);
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collect_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
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}
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/* Supply NUM number of VFP registers contents, stored in BUF, to
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REGCACHE. */
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void
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arm_store_vfpregset_num (struct regcache *regcache, const void *buf, int num)
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{
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int i, base;
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gdb_assert (num == 16 || num == 32);
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base = find_regno (regcache->tdesc, "d0");
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for (i = 0; i < num; i++)
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supply_register (regcache, base + i, (char *) buf + i * 8);
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supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
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}
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static void
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arm_fill_vfpregset (struct regcache *regcache, void *buf)
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{
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arm_fill_vfpregset_num (regcache, buf, 32);
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}
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static void
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arm_store_vfpregset (struct regcache *regcache, const void *buf)
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{
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arm_store_vfpregset_num (regcache, buf, 32);
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}
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/* Register sets with using PTRACE_GETREGSET. */
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static struct regset_info aarch32_regsets[] = {
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
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ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
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arm_fill_gregset, arm_store_gregset },
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{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, ARM_VFP3_REGS_SIZE,
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EXTENDED_REGS,
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arm_fill_vfpregset, arm_store_vfpregset },
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NULL_REGSET
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};
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static struct regsets_info aarch32_regsets_info =
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{
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aarch32_regsets, /* regsets */
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0, /* num_regsets */
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NULL, /* disabled_regsets */
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};
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struct regs_info regs_info_aarch32 =
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{
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NULL, /* regset_bitmap */
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NULL, /* usrregs */
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&aarch32_regsets_info
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};
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/* Returns 1 if the current instruction set is thumb, 0 otherwise. */
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int
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arm_is_thumb_mode (void)
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{
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regcache *regcache = get_thread_regcache (current_thread);
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unsigned long cpsr;
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collect_register_by_name (regcache, "cpsr", &cpsr);
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if (cpsr & 0x20)
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return 1;
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else
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return 0;
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}
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/* Returns 1 if there is a software breakpoint at location. */
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int
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arm_breakpoint_at (CORE_ADDR where)
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{
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if (arm_is_thumb_mode ())
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{
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/* Thumb mode. */
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unsigned short insn;
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the_target->read_memory (where, (unsigned char *) &insn, 2);
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if (insn == thumb_breakpoint)
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return 1;
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if (insn == thumb2_breakpoint[0])
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{
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the_target->read_memory (where + 2, (unsigned char *) &insn, 2);
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if (insn == thumb2_breakpoint[1])
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return 1;
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}
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}
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else
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{
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/* ARM mode. */
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unsigned long insn;
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the_target->read_memory (where, (unsigned char *) &insn, 4);
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if (insn == arm_abi_breakpoint)
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return 1;
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if (insn == arm_eabi_breakpoint)
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return 1;
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}
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return 0;
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}
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/* Implementation of linux_target_ops method "breakpoint_kind_from_pc".
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Determine the type and size of breakpoint to insert at PCPTR. Uses the
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program counter value to determine whether a 16-bit or 32-bit breakpoint
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should be used. It returns the breakpoint's kind, and adjusts the program
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counter (if necessary) to point to the actual memory location where the
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breakpoint should be inserted. */
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int
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arm_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
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{
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if (IS_THUMB_ADDR (*pcptr))
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{
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gdb_byte buf[2];
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*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
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/* Check whether we are replacing a thumb2 32-bit instruction. */
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if (target_read_memory (*pcptr, buf, 2) == 0)
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{
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unsigned short inst1 = 0;
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target_read_memory (*pcptr, (gdb_byte *) &inst1, 2);
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if (thumb_insn_size (inst1) == 4)
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return ARM_BP_KIND_THUMB2;
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}
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return ARM_BP_KIND_THUMB;
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}
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else
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return ARM_BP_KIND_ARM;
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}
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/* Implementation of the linux_target_ops method "sw_breakpoint_from_kind". */
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const gdb_byte *
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arm_sw_breakpoint_from_kind (int kind , int *size)
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{
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*size = arm_breakpoint_len;
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/* Define an ARM-mode breakpoint; we only set breakpoints in the C
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library, which is most likely to be ARM. If the kernel supports
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clone events, we will never insert a breakpoint, so even a Thumb
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C library will work; so will mixing EABI/non-EABI gdbserver and
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application. */
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switch (kind)
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{
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case ARM_BP_KIND_THUMB:
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*size = thumb_breakpoint_len;
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return (gdb_byte *) &thumb_breakpoint;
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case ARM_BP_KIND_THUMB2:
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*size = thumb2_breakpoint_len;
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return (gdb_byte *) &thumb2_breakpoint;
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case ARM_BP_KIND_ARM:
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*size = arm_breakpoint_len;
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return (const gdb_byte *) &arm_breakpoint;
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default:
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return NULL;
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}
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return NULL;
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}
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/* Implementation of the linux_target_ops method
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"breakpoint_kind_from_current_state". */
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int
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arm_breakpoint_kind_from_current_state (CORE_ADDR *pcptr)
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{
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if (arm_is_thumb_mode ())
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{
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*pcptr = MAKE_THUMB_ADDR (*pcptr);
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return arm_breakpoint_kind_from_pc (pcptr);
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}
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else
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{
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return arm_breakpoint_kind_from_pc (pcptr);
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}
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}
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void
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initialize_low_arch_aarch32 (void)
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{
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initialize_regsets_info (&aarch32_regsets_info);
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}
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