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33 Commits
gdb-8.3-br
...
users/ARM/
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File diff suppressed because it is too large
Load Diff
@@ -154,6 +154,8 @@ automatically cause those extensions to be disabled.
|
||||
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
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||||
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
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||||
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
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||||
@item @code{sve} @tab ARMv8-A @tab ARMv8-A or later
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||||
@tab Enable the Scalable Vector Extensions.
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||||
@end multitable
|
||||
|
||||
@node AArch64 Syntax
|
||||
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||||
@@ -29,19 +29,19 @@ Disassembly of section \.text:
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||||
54: 9ba28c20 umsubl x0, w1, w2, x3
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||||
58: 9ba2fc20 umnegl x0, w1, w2
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||||
5c: 9ba2fc20 umnegl x0, w1, w2
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||||
60: 1a9f0420 csinc w0, w1, wzr, eq
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||||
64: 1a810420 cinc w0, w1, ne
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||||
68: 1a810420 cinc w0, w1, ne
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||||
6c: 1a9f37e0 cset w0, cs
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||||
70: 1a9f37e0 cset w0, cs
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||||
74: da9f2020 csinv x0, x1, xzr, cs
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||||
78: da812020 cinv x0, x1, cc
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||||
7c: da812020 cinv x0, x1, cc
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||||
80: da9f43e0 csetm x0, pl
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||||
84: da9f43e0 csetm x0, pl
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||||
88: da9eb7e0 csneg x0, xzr, x30, lt
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||||
8c: da9eb7c0 cneg x0, x30, ge
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||||
90: da9eb7c0 cneg x0, x30, ge
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60: 1a9f0420 csinc w0, w1, wzr, eq // eq = none
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64: 1a810420 cinc w0, w1, ne // ne = any
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||||
68: 1a810420 cinc w0, w1, ne // ne = any
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6c: 1a9f37e0 cset w0, cs // cs = hs, nlast
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70: 1a9f37e0 cset w0, cs // cs = hs, nlast
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74: da9f2020 csinv x0, x1, xzr, cs // cs = hs, nlast
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78: da812020 cinv x0, x1, cc // cc = lo, ul, last
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7c: da812020 cinv x0, x1, cc // cc = lo, ul, last
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80: da9f43e0 csetm x0, pl // pl = nfrst
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84: da9f43e0 csetm x0, pl // pl = nfrst
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||||
88: da9eb7e0 csneg x0, xzr, x30, lt // lt = tstop
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8c: da9eb7c0 cneg x0, x30, ge // ge = tcont
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90: da9eb7c0 cneg x0, x30, ge // ge = tcont
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94: ea020020 ands x0, x1, x2
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||||
98: ea02003f tst x1, x2
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||||
9c: ea02003f tst x1, x2
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||||
|
||||
58
gas/testsuite/gas/aarch64/b_c_1.d
Normal file
58
gas/testsuite/gas/aarch64/b_c_1.d
Normal file
@@ -0,0 +1,58 @@
|
||||
# objdump: -d
|
||||
|
||||
.*: .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+0 <\.text>:
|
||||
.*: 54.....0 b\.eq 0 <\.text> // b\.none
|
||||
.*: 54.....0 b\.eq 0 <\.text> // b\.none
|
||||
.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
|
||||
.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
|
||||
.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
|
||||
.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
|
||||
.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
|
||||
.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
|
||||
.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
|
||||
.*: 54.....4 b\.mi 0 <\.text> // b\.first
|
||||
.*: 54.....4 b\.mi 0 <\.text> // b\.first
|
||||
.*: 54.....5 b\.pl 0 <\.text> // b\.nfrst
|
||||
.*: 54.....5 b\.pl 0 <\.text> // b\.nfrst
|
||||
.*: 54.....6 b\.vs 0 <\.text>
|
||||
.*: 54.....7 b\.vc 0 <\.text>
|
||||
.*: 54.....8 b\.hi 0 <\.text> // b\.pmore
|
||||
.*: 54.....8 b\.hi 0 <\.text> // b\.pmore
|
||||
.*: 54.....9 b\.ls 0 <\.text> // b\.plast
|
||||
.*: 54.....9 b\.ls 0 <\.text> // b\.plast
|
||||
.*: 54.....a b\.ge 0 <\.text> // b\.tcont
|
||||
.*: 54.....a b\.ge 0 <\.text> // b\.tcont
|
||||
.*: 54.....b b\.lt 0 <\.text> // b\.tstop
|
||||
.*: 54.....b b\.lt 0 <\.text> // b\.tstop
|
||||
.*: 54.....c b\.gt 0 <\.text>
|
||||
.*: 54.....d b\.le 0 <\.text>
|
||||
.*: 9a830041 csel x1, x2, x3, eq // eq = none
|
||||
.*: 9a830041 csel x1, x2, x3, eq // eq = none
|
||||
.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
|
||||
.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
|
||||
.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
|
||||
.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
|
||||
.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
|
||||
.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
|
||||
.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
|
||||
.*: 9a834041 csel x1, x2, x3, mi // mi = first
|
||||
.*: 9a834041 csel x1, x2, x3, mi // mi = first
|
||||
.*: 9a835041 csel x1, x2, x3, pl // pl = nfrst
|
||||
.*: 9a835041 csel x1, x2, x3, pl // pl = nfrst
|
||||
.*: 9a836041 csel x1, x2, x3, vs
|
||||
.*: 9a837041 csel x1, x2, x3, vc
|
||||
.*: 9a838041 csel x1, x2, x3, hi // hi = pmore
|
||||
.*: 9a838041 csel x1, x2, x3, hi // hi = pmore
|
||||
.*: 9a839041 csel x1, x2, x3, ls // ls = plast
|
||||
.*: 9a839041 csel x1, x2, x3, ls // ls = plast
|
||||
.*: 9a83a041 csel x1, x2, x3, ge // ge = tcont
|
||||
.*: 9a83a041 csel x1, x2, x3, ge // ge = tcont
|
||||
.*: 9a83b041 csel x1, x2, x3, lt // lt = tstop
|
||||
.*: 9a83b041 csel x1, x2, x3, lt // lt = tstop
|
||||
.*: 9a83c041 csel x1, x2, x3, gt
|
||||
.*: 9a83d041 csel x1, x2, x3, le
|
||||
76
gas/testsuite/gas/aarch64/b_c_1.s
Normal file
76
gas/testsuite/gas/aarch64/b_c_1.s
Normal file
@@ -0,0 +1,76 @@
|
||||
1:
|
||||
b.eq 1b
|
||||
b.none 1b
|
||||
|
||||
b.cs 1b
|
||||
b.hs 1b
|
||||
b.nlast 1b
|
||||
|
||||
b.cc 1b
|
||||
b.lo 1b
|
||||
b.ul 1b
|
||||
b.last 1b
|
||||
|
||||
b.mi 1b
|
||||
b.first 1b
|
||||
|
||||
b.pl 1b
|
||||
b.nfrst 1b
|
||||
|
||||
b.vs 1b
|
||||
|
||||
b.vc 1b
|
||||
|
||||
b.hi 1b
|
||||
b.pmore 1b
|
||||
|
||||
b.ls 1b
|
||||
b.plast 1b
|
||||
|
||||
b.ge 1b
|
||||
b.tcont 1b
|
||||
|
||||
b.lt 1b
|
||||
b.tstop 1b
|
||||
|
||||
b.gt 1b
|
||||
|
||||
b.le 1b
|
||||
|
||||
csel x1, x2, x3, eq
|
||||
csel x1, x2, x3, none
|
||||
|
||||
csel x1, x2, x3, cs
|
||||
csel x1, x2, x3, hs
|
||||
csel x1, x2, x3, nlast
|
||||
|
||||
csel x1, x2, x3, cc
|
||||
csel x1, x2, x3, lo
|
||||
csel x1, x2, x3, ul
|
||||
csel x1, x2, x3, last
|
||||
|
||||
csel x1, x2, x3, mi
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||||
csel x1, x2, x3, first
|
||||
|
||||
csel x1, x2, x3, pl
|
||||
csel x1, x2, x3, nfrst
|
||||
|
||||
csel x1, x2, x3, vs
|
||||
|
||||
csel x1, x2, x3, vc
|
||||
|
||||
csel x1, x2, x3, hi
|
||||
csel x1, x2, x3, pmore
|
||||
|
||||
csel x1, x2, x3, ls
|
||||
csel x1, x2, x3, plast
|
||||
|
||||
csel x1, x2, x3, ge
|
||||
csel x1, x2, x3, tcont
|
||||
|
||||
csel x1, x2, x3, lt
|
||||
csel x1, x2, x3, tstop
|
||||
|
||||
csel x1, x2, x3, gt
|
||||
|
||||
csel x1, x2, x3, le
|
||||
@@ -5,5 +5,5 @@
|
||||
Disassembly of section \.text:
|
||||
|
||||
0000000000000000 <.*>:
|
||||
0: 54000000 b.eq 0 <bar>
|
||||
0: 54000000 b\.eq 0 <bar> // b\.none
|
||||
0: R_AARCH64_CONDBR19 bar\+0x100000
|
||||
|
||||
@@ -144,3 +144,21 @@
|
||||
[^:]*:255: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[-1\],\[x0\]'
|
||||
[^:]*:258: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[16\],\[x0\]'
|
||||
[^:]*:259: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[67\],\[x0\]'
|
||||
[^:]*:261: Error: invalid floating-point constant at operand 2 -- `fmov d0,#2'
|
||||
[^:]*:262: Error: invalid floating-point constant at operand 2 -- `fmov d0,#-2'
|
||||
[^:]*:263: Error: invalid floating-point constant at operand 2 -- `fmov s0,2'
|
||||
[^:]*:264: Error: invalid floating-point constant at operand 2 -- `fmov s0,-2'
|
||||
[^:]*:266: Error: '\]' expected at operand 2 -- `ldr x0,\[x1,#1,mul vl\]'
|
||||
[^:]*:267: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul vl\]'
|
||||
[^:]*:268: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul#1\]'
|
||||
[^:]*:269: Error: invalid use of 'MUL' at operand 2 -- `ldr x0,\[x1,x2,mul#4\]'
|
||||
[^:]*:271: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,x0,mul\]'
|
||||
[^:]*:272: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,x0,mul#1\]'
|
||||
[^:]*:273: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,w0,mul\]'
|
||||
[^:]*:274: Error: invalid use of 'MUL' at operand 2 -- `strb w7,\[x30,w0,mul#2\]'
|
||||
[^:]*:276: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,1,mul#1'
|
||||
[^:]*:277: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,2,mul#255'
|
||||
[^:]*:278: Error: invalid use of 'MUL' at operand 3 -- `adds x1,sp,3,mul#256'
|
||||
[^:]*:279: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xff,mul#1'
|
||||
[^:]*:280: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfe,mul#255'
|
||||
[^:]*:281: Error: invalid use of 'MUL' at operand 4 -- `orr x0,x0,#0xfc,mul#256'
|
||||
|
||||
@@ -257,3 +257,25 @@
|
||||
ld2 {v0.b, v1.b}[15], [x0]
|
||||
ld2 {v0.b, v1.b}[16], [x0]
|
||||
ld2 {v0.b, v1.b}[67], [x0]
|
||||
|
||||
fmov d0, #2
|
||||
fmov d0, #-2
|
||||
fmov s0, 2
|
||||
fmov s0, -2
|
||||
|
||||
ldr x0, [x1, #1, mul vl]
|
||||
ldr x0, [x1, x2, mul vl]
|
||||
ldr x0, [x1, x2, mul #1]
|
||||
ldr x0, [x1, x2, mul #4]
|
||||
|
||||
strb w7, [x30, x0, mul]
|
||||
strb w7, [x30, x0, mul #1]
|
||||
strb w7, [x30, w0, mul]
|
||||
strb w7, [x30, w0, mul #2]
|
||||
|
||||
adds x1, sp, 1, mul #1
|
||||
adds x1, sp, 2, mul #255
|
||||
adds x1, sp, 3, mul #256
|
||||
orr x0, x0, #0xff, mul #1
|
||||
orr x0, x0, #0xfe, mul #255
|
||||
orr x0, x0, #0xfc, mul #256
|
||||
|
||||
@@ -6,12 +6,12 @@
|
||||
Disassembly of section \.text:
|
||||
|
||||
0000000000000000 <.*>:
|
||||
[0-9a-f]+: 1e200400 fccmp s0, s0, #0x0, eq
|
||||
[0-9a-f]+: 1ee00400 fccmp h0, h0, #0x0, eq
|
||||
[0-9a-f]+: 1e200400 fccmp s0, s0, #0x0, eq // eq = none
|
||||
[0-9a-f]+: 1ee00400 fccmp h0, h0, #0x0, eq // eq = none
|
||||
[0-9a-f]+: 1e22d420 fccmp s1, s2, #0x0, le
|
||||
[0-9a-f]+: 1ee2d420 fccmp h1, h2, #0x0, le
|
||||
[0-9a-f]+: 1e200410 fccmpe s0, s0, #0x0, eq
|
||||
[0-9a-f]+: 1ee00410 fccmpe h0, h0, #0x0, eq
|
||||
[0-9a-f]+: 1e200410 fccmpe s0, s0, #0x0, eq // eq = none
|
||||
[0-9a-f]+: 1ee00410 fccmpe h0, h0, #0x0, eq // eq = none
|
||||
[0-9a-f]+: 1e22d430 fccmpe s1, s2, #0x0, le
|
||||
[0-9a-f]+: 1ee2d430 fccmpe h1, h2, #0x0, le
|
||||
[0-9a-f]+: 1e202000 fcmp s0, s0
|
||||
@@ -26,8 +26,8 @@ Disassembly of section \.text:
|
||||
[0-9a-f]+: 1ee02008 fcmp h0, #0\.0
|
||||
[0-9a-f]+: 1e202018 fcmpe s0, #0\.0
|
||||
[0-9a-f]+: 1ee02018 fcmpe h0, #0\.0
|
||||
[0-9a-f]+: 1e210c00 fcsel s0, s0, s1, eq
|
||||
[0-9a-f]+: 1ee10c00 fcsel h0, h0, h1, eq
|
||||
[0-9a-f]+: 1e210c00 fcsel s0, s0, s1, eq // eq = none
|
||||
[0-9a-f]+: 1ee10c00 fcsel h0, h0, h1, eq // eq = none
|
||||
[0-9a-f]+: 9ee60000 fmov x0, h0
|
||||
[0-9a-f]+: 1ee60000 fmov w0, h0
|
||||
[0-9a-f]+: 9ee70001 fmov h1, x0
|
||||
|
||||
@@ -13,8 +13,8 @@ Disassembly of section .text:
|
||||
10: 93c3fc41 extr x1, x2, x3, #63
|
||||
14: 93c30041 extr x1, x2, x3, #0
|
||||
18: 13837c41 extr w1, w2, w3, #31
|
||||
1c: 9a9f17e1 cset x1, eq
|
||||
20: da9f13e1 csetm x1, eq
|
||||
1c: 9a9f17e1 cset x1, eq // eq = none
|
||||
20: da9f13e1 csetm x1, eq // eq = none
|
||||
24: 71000021 subs w1, w1, #0x0
|
||||
28: 7100003f cmp w1, #0x0
|
||||
2c: 4b0203e1 neg w1, w2
|
||||
@@ -64,17 +64,17 @@ Disassembly of section .text:
|
||||
d4: 92400c85 and x5, x4, #0xf
|
||||
d8: 0a230041 bic w1, w2, w3
|
||||
dc: 8a230041 bic x1, x2, x3
|
||||
e0: 54000001 b.ne e0 <sp\+0x90>
|
||||
e0: 54000001 b\.ne e0 <sp\+0x90> // b\.any
|
||||
e4: 17ffffff b e0 <sp\+0x90>
|
||||
e8: 14000001 b ec <sp\+0x9c>
|
||||
ec: 54ffffa0 b.eq e0 <sp\+0x90>
|
||||
f0: 54000001 b.ne f0 <sp\+0xa0>
|
||||
ec: 54ffffa0 b\.eq e0 <sp\+0x90> // b\.none
|
||||
f0: 54000001 b\.ne f0 <sp\+0xa0> // b\.any
|
||||
f4: 17ffffff b f0 <sp\+0xa0>
|
||||
f8: 14000001 b fc <sp\+0xac>
|
||||
fc: 54ffffa0 b.eq f0 <sp\+0xa0>
|
||||
fc: 54ffffa0 b\.eq f0 <sp\+0xa0> // b\.none
|
||||
100: d61f0040 br x2
|
||||
104: 54ffffc2 b.cs fc <sp\+0xac>
|
||||
108: 54ffffa3 b.cc fc <sp\+0xac>
|
||||
104: 54ffffc2 b\.cs fc <sp\+0xac> // b\.hs, b\.nlast
|
||||
108: 54ffffa3 b\.cc fc <sp\+0xac> // b\.lo, b\.ul, b\.last
|
||||
...
|
||||
10c: R_AARCH64_ABS32 .text\+0x50
|
||||
110: R_AARCH64_ABS64 .text\+0x50
|
||||
|
||||
@@ -30,19 +30,19 @@ Disassembly of section \.text:
|
||||
54: 9ba28c20 umsubl x0, w1, w2, x3
|
||||
58: 9ba2fc20 umsubl x0, w1, w2, xzr
|
||||
5c: 9ba2fc20 umsubl x0, w1, w2, xzr
|
||||
60: 1a9f0420 csinc w0, w1, wzr, eq
|
||||
64: 1a810420 csinc w0, w1, w1, eq
|
||||
68: 1a810420 csinc w0, w1, w1, eq
|
||||
6c: 1a9f37e0 csinc w0, wzr, wzr, cc
|
||||
70: 1a9f37e0 csinc w0, wzr, wzr, cc
|
||||
74: da9f2020 csinv x0, x1, xzr, cs
|
||||
78: da812020 csinv x0, x1, x1, cs
|
||||
7c: da812020 csinv x0, x1, x1, cs
|
||||
80: da9f43e0 csinv x0, xzr, xzr, mi
|
||||
84: da9f43e0 csinv x0, xzr, xzr, mi
|
||||
88: da9eb7e0 csneg x0, xzr, x30, lt
|
||||
8c: da9eb7c0 csneg x0, x30, x30, lt
|
||||
90: da9eb7c0 csneg x0, x30, x30, lt
|
||||
60: 1a9f0420 csinc w0, w1, wzr, eq // eq = none
|
||||
64: 1a810420 csinc w0, w1, w1, eq // eq = none
|
||||
68: 1a810420 csinc w0, w1, w1, eq // eq = none
|
||||
6c: 1a9f37e0 csinc w0, wzr, wzr, cc // cc = lo, ul, last
|
||||
70: 1a9f37e0 csinc w0, wzr, wzr, cc // cc = lo, ul, last
|
||||
74: da9f2020 csinv x0, x1, xzr, cs // cs = hs, nlast
|
||||
78: da812020 csinv x0, x1, x1, cs // cs = hs, nlast
|
||||
7c: da812020 csinv x0, x1, x1, cs // cs = hs, nlast
|
||||
80: da9f43e0 csinv x0, xzr, xzr, mi // mi = first
|
||||
84: da9f43e0 csinv x0, xzr, xzr, mi // mi = first
|
||||
88: da9eb7e0 csneg x0, xzr, x30, lt // lt = tstop
|
||||
8c: da9eb7c0 csneg x0, x30, x30, lt // lt = tstop
|
||||
90: da9eb7c0 csneg x0, x30, x30, lt // lt = tstop
|
||||
94: ea020020 ands x0, x1, x2
|
||||
98: ea02003f ands xzr, x1, x2
|
||||
9c: ea02003f ands xzr, x1, x2
|
||||
|
||||
@@ -9,7 +9,7 @@ Disassembly of section \.text:
|
||||
4: 98000241 ldrsw x1, 4c <\.text\+0x4c>
|
||||
8: 98000007 ldrsw x7, 0 <\.text>
|
||||
8: R_AARCH64_LD_PREL_LO19 \.data\+0x4
|
||||
c: fa42a02a ccmp x1, x2, #0xa, ge
|
||||
c: fa42a02a ccmp x1, x2, #0xa, ge // ge = tcont
|
||||
10: 53001eaf uxtb w15, w21
|
||||
14: 53003f67 uxth w7, w27
|
||||
18: 2a1f03e8 mov w8, wzr
|
||||
|
||||
@@ -109,8 +109,8 @@ Disassembly of section \.text:
|
||||
fc: 37400522 tbnz w2, #8, 1a0 <lab>
|
||||
100: b7780002 tbnz x2, #47, 0 <xlab>
|
||||
100: R_AARCH64_TSTBR14 xlab
|
||||
104: 540004e0 b\.eq 1a0 <lab>
|
||||
108: 54000000 b\.eq 0 <xlab>
|
||||
104: 540004e0 b\.eq 1a0 <lab> // b\.none
|
||||
108: 54000000 b\.eq 0 <xlab> // b\.none
|
||||
108: R_AARCH64_CONDBR19 xlab
|
||||
10c: b40004a0 cbz x0, 1a0 <lab>
|
||||
110: b500001e cbnz x30, 0 <xlab>
|
||||
|
||||
151
gas/testsuite/gas/aarch64/sve-add.d
Normal file
151
gas/testsuite/gas/aarch64/sve-add.d
Normal file
@@ -0,0 +1,151 @@
|
||||
#as: -march=armv8-a+sve
|
||||
#objdump: -dr
|
||||
|
||||
.*: file format .*
|
||||
|
||||
|
||||
Disassembly of section .*:
|
||||
|
||||
0+ <.*>:
|
||||
.*: 2520c020 add z0\.b, z0\.b, #1
|
||||
.*: 2520cfe0 add z0\.b, z0\.b, #127
|
||||
.*: 2520d000 add z0\.b, z0\.b, #128
|
||||
.*: 2520d020 add z0\.b, z0\.b, #129
|
||||
.*: 2520dfe0 add z0\.b, z0\.b, #255
|
||||
.*: 2520c000 add z0\.b, z0\.b, #0
|
||||
.*: 2520c020 add z0\.b, z0\.b, #1
|
||||
.*: 2520cfe0 add z0\.b, z0\.b, #127
|
||||
.*: 2520d000 add z0\.b, z0\.b, #128
|
||||
.*: 2520dfe0 add z0\.b, z0\.b, #255
|
||||
.*: 2560e000 add z0\.h, z0\.h, #0, lsl #8
|
||||
.*: 2560c020 add z0\.h, z0\.h, #1
|
||||
.*: 2560cfe0 add z0\.h, z0\.h, #127
|
||||
.*: 2560d000 add z0\.h, z0\.h, #128
|
||||
.*: 2560d020 add z0\.h, z0\.h, #129
|
||||
.*: 2560dfe0 add z0\.h, z0\.h, #255
|
||||
.*: 2560e020 add z0\.h, z0\.h, #256
|
||||
.*: 2560efe0 add z0\.h, z0\.h, #32512
|
||||
.*: 2560f000 add z0\.h, z0\.h, #32768
|
||||
.*: 2560f020 add z0\.h, z0\.h, #33024
|
||||
.*: 2560c000 add z0\.h, z0\.h, #0
|
||||
.*: 2560c020 add z0\.h, z0\.h, #1
|
||||
.*: 2560cfe0 add z0\.h, z0\.h, #127
|
||||
.*: 2560d000 add z0\.h, z0\.h, #128
|
||||
.*: 2560d020 add z0\.h, z0\.h, #129
|
||||
.*: 2560dfe0 add z0\.h, z0\.h, #255
|
||||
.*: 2560e020 add z0\.h, z0\.h, #256
|
||||
.*: 2560efe0 add z0\.h, z0\.h, #32512
|
||||
.*: 2560f000 add z0\.h, z0\.h, #32768
|
||||
.*: 2560f020 add z0\.h, z0\.h, #33024
|
||||
.*: 2560ffe0 add z0\.h, z0\.h, #65280
|
||||
.*: 2560e020 add z0\.h, z0\.h, #256
|
||||
.*: 2560efe0 add z0\.h, z0\.h, #32512
|
||||
.*: 2560f000 add z0\.h, z0\.h, #32768
|
||||
.*: 2560f020 add z0\.h, z0\.h, #33024
|
||||
.*: 2560ffe0 add z0\.h, z0\.h, #65280
|
||||
.*: 2560e000 add z0\.h, z0\.h, #0, lsl #8
|
||||
.*: 2560e020 add z0\.h, z0\.h, #256
|
||||
.*: 2560efe0 add z0\.h, z0\.h, #32512
|
||||
.*: 2560f000 add z0\.h, z0\.h, #32768
|
||||
.*: 2560ffe0 add z0\.h, z0\.h, #65280
|
||||
.*: 25a0c000 add z0\.s, z0\.s, #0
|
||||
.*: 25a0c020 add z0\.s, z0\.s, #1
|
||||
.*: 25a0cfe0 add z0\.s, z0\.s, #127
|
||||
.*: 25a0d000 add z0\.s, z0\.s, #128
|
||||
.*: 25a0d020 add z0\.s, z0\.s, #129
|
||||
.*: 25a0dfe0 add z0\.s, z0\.s, #255
|
||||
.*: 25a0e020 add z0\.s, z0\.s, #256
|
||||
.*: 25a0efe0 add z0\.s, z0\.s, #32512
|
||||
.*: 25a0f000 add z0\.s, z0\.s, #32768
|
||||
.*: 25a0ffe0 add z0\.s, z0\.s, #65280
|
||||
.*: 25a0e000 add z0\.s, z0\.s, #0, lsl #8
|
||||
.*: 25a0e020 add z0\.s, z0\.s, #256
|
||||
.*: 25a0efe0 add z0\.s, z0\.s, #32512
|
||||
.*: 25a0f000 add z0\.s, z0\.s, #32768
|
||||
.*: 25a0ffe0 add z0\.s, z0\.s, #65280
|
||||
.*: 25e0c000 add z0\.d, z0\.d, #0
|
||||
.*: 25e0c020 add z0\.d, z0\.d, #1
|
||||
.*: 25e0cfe0 add z0\.d, z0\.d, #127
|
||||
.*: 25e0d000 add z0\.d, z0\.d, #128
|
||||
.*: 25e0d020 add z0\.d, z0\.d, #129
|
||||
.*: 25e0dfe0 add z0\.d, z0\.d, #255
|
||||
.*: 25e0e020 add z0\.d, z0\.d, #256
|
||||
.*: 25e0efe0 add z0\.d, z0\.d, #32512
|
||||
.*: 25e0f000 add z0\.d, z0\.d, #32768
|
||||
.*: 25e0ffe0 add z0\.d, z0\.d, #65280
|
||||
.*: 25e0e000 add z0\.d, z0\.d, #0, lsl #8
|
||||
.*: 25e0e020 add z0\.d, z0\.d, #256
|
||||
.*: 25e0efe0 add z0\.d, z0\.d, #32512
|
||||
.*: 25e0f000 add z0\.d, z0\.d, #32768
|
||||
.*: 25e0ffe0 add z0\.d, z0\.d, #65280
|
||||
.*: 2521c020 sub z0\.b, z0\.b, #1
|
||||
.*: 2521cfe0 sub z0\.b, z0\.b, #127
|
||||
.*: 2521d000 sub z0\.b, z0\.b, #128
|
||||
.*: 2521d020 sub z0\.b, z0\.b, #129
|
||||
.*: 2521dfe0 sub z0\.b, z0\.b, #255
|
||||
.*: 2521c000 sub z0\.b, z0\.b, #0
|
||||
.*: 2521c020 sub z0\.b, z0\.b, #1
|
||||
.*: 2521cfe0 sub z0\.b, z0\.b, #127
|
||||
.*: 2521d000 sub z0\.b, z0\.b, #128
|
||||
.*: 2521dfe0 sub z0\.b, z0\.b, #255
|
||||
.*: 2561e000 sub z0\.h, z0\.h, #0, lsl #8
|
||||
.*: 2561c020 sub z0\.h, z0\.h, #1
|
||||
.*: 2561cfe0 sub z0\.h, z0\.h, #127
|
||||
.*: 2561d000 sub z0\.h, z0\.h, #128
|
||||
.*: 2561d020 sub z0\.h, z0\.h, #129
|
||||
.*: 2561dfe0 sub z0\.h, z0\.h, #255
|
||||
.*: 2561e020 sub z0\.h, z0\.h, #256
|
||||
.*: 2561efe0 sub z0\.h, z0\.h, #32512
|
||||
.*: 2561f000 sub z0\.h, z0\.h, #32768
|
||||
.*: 2561f020 sub z0\.h, z0\.h, #33024
|
||||
.*: 2561c000 sub z0\.h, z0\.h, #0
|
||||
.*: 2561c020 sub z0\.h, z0\.h, #1
|
||||
.*: 2561cfe0 sub z0\.h, z0\.h, #127
|
||||
.*: 2561d000 sub z0\.h, z0\.h, #128
|
||||
.*: 2561d020 sub z0\.h, z0\.h, #129
|
||||
.*: 2561dfe0 sub z0\.h, z0\.h, #255
|
||||
.*: 2561e020 sub z0\.h, z0\.h, #256
|
||||
.*: 2561efe0 sub z0\.h, z0\.h, #32512
|
||||
.*: 2561f000 sub z0\.h, z0\.h, #32768
|
||||
.*: 2561f020 sub z0\.h, z0\.h, #33024
|
||||
.*: 2561ffe0 sub z0\.h, z0\.h, #65280
|
||||
.*: 2561e020 sub z0\.h, z0\.h, #256
|
||||
.*: 2561efe0 sub z0\.h, z0\.h, #32512
|
||||
.*: 2561f000 sub z0\.h, z0\.h, #32768
|
||||
.*: 2561f020 sub z0\.h, z0\.h, #33024
|
||||
.*: 2561ffe0 sub z0\.h, z0\.h, #65280
|
||||
.*: 2561e000 sub z0\.h, z0\.h, #0, lsl #8
|
||||
.*: 2561e020 sub z0\.h, z0\.h, #256
|
||||
.*: 2561efe0 sub z0\.h, z0\.h, #32512
|
||||
.*: 2561f000 sub z0\.h, z0\.h, #32768
|
||||
.*: 2561ffe0 sub z0\.h, z0\.h, #65280
|
||||
.*: 25a1c000 sub z0\.s, z0\.s, #0
|
||||
.*: 25a1c020 sub z0\.s, z0\.s, #1
|
||||
.*: 25a1cfe0 sub z0\.s, z0\.s, #127
|
||||
.*: 25a1d000 sub z0\.s, z0\.s, #128
|
||||
.*: 25a1d020 sub z0\.s, z0\.s, #129
|
||||
.*: 25a1dfe0 sub z0\.s, z0\.s, #255
|
||||
.*: 25a1e020 sub z0\.s, z0\.s, #256
|
||||
.*: 25a1efe0 sub z0\.s, z0\.s, #32512
|
||||
.*: 25a1f000 sub z0\.s, z0\.s, #32768
|
||||
.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
|
||||
.*: 25a1e000 sub z0\.s, z0\.s, #0, lsl #8
|
||||
.*: 25a1e020 sub z0\.s, z0\.s, #256
|
||||
.*: 25a1efe0 sub z0\.s, z0\.s, #32512
|
||||
.*: 25a1f000 sub z0\.s, z0\.s, #32768
|
||||
.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
|
||||
.*: 25e1c000 sub z0\.d, z0\.d, #0
|
||||
.*: 25e1c020 sub z0\.d, z0\.d, #1
|
||||
.*: 25e1cfe0 sub z0\.d, z0\.d, #127
|
||||
.*: 25e1d000 sub z0\.d, z0\.d, #128
|
||||
.*: 25e1d020 sub z0\.d, z0\.d, #129
|
||||
.*: 25e1dfe0 sub z0\.d, z0\.d, #255
|
||||
.*: 25e1e020 sub z0\.d, z0\.d, #256
|
||||
.*: 25e1efe0 sub z0\.d, z0\.d, #32512
|
||||
.*: 25e1f000 sub z0\.d, z0\.d, #32768
|
||||
.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
|
||||
.*: 25e1e000 sub z0\.d, z0\.d, #0, lsl #8
|
||||
.*: 25e1e020 sub z0\.d, z0\.d, #256
|
||||
.*: 25e1efe0 sub z0\.d, z0\.d, #32512
|
||||
.*: 25e1f000 sub z0\.d, z0\.d, #32768
|
||||
.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
|
||||
149
gas/testsuite/gas/aarch64/sve-add.s
Normal file
149
gas/testsuite/gas/aarch64/sve-add.s
Normal file
@@ -0,0 +1,149 @@
|
||||
add z0.b, z0.b, #-255
|
||||
add z0.b, z0.b, #-129
|
||||
add z0.b, z0.b, #-128
|
||||
add z0.b, z0.b, #-127
|
||||
add z0.b, z0.b, #-1
|
||||
add z0.b, z0.b, #0
|
||||
add z0.b, z0.b, #1
|
||||
add z0.b, z0.b, #127
|
||||
add z0.b, z0.b, #128
|
||||
add z0.b, z0.b, #255
|
||||
|
||||
add z0.h, z0.h, #-65536
|
||||
add z0.h, z0.h, #-65535
|
||||
add z0.h, z0.h, #-65536 + 127
|
||||
add z0.h, z0.h, #-65536 + 128
|
||||
add z0.h, z0.h, #-65536 + 129
|
||||
add z0.h, z0.h, #-65536 + 255
|
||||
add z0.h, z0.h, #-65536 + 256
|
||||
add z0.h, z0.h, #-32768 - 256
|
||||
add z0.h, z0.h, #-32768
|
||||
add z0.h, z0.h, #-32768 + 256
|
||||
add z0.h, z0.h, #0
|
||||
add z0.h, z0.h, #1
|
||||
add z0.h, z0.h, #127
|
||||
add z0.h, z0.h, #128
|
||||
add z0.h, z0.h, #129
|
||||
add z0.h, z0.h, #255
|
||||
add z0.h, z0.h, #256
|
||||
add z0.h, z0.h, #32768 - 256
|
||||
add z0.h, z0.h, #32768
|
||||
add z0.h, z0.h, #32768 + 256
|
||||
add z0.h, z0.h, #65536 - 256
|
||||
add z0.h, z0.h, #-255, lsl #8
|
||||
add z0.h, z0.h, #-129, lsl #8
|
||||
add z0.h, z0.h, #-128, lsl #8
|
||||
add z0.h, z0.h, #-127, lsl #8
|
||||
add z0.h, z0.h, #-1, lsl #8
|
||||
add z0.h, z0.h, #0, lsl #8
|
||||
add z0.h, z0.h, #1, lsl #8
|
||||
add z0.h, z0.h, #127, lsl #8
|
||||
add z0.h, z0.h, #128, lsl #8
|
||||
add z0.h, z0.h, #255, lsl #8
|
||||
|
||||
add z0.s, z0.s, #0
|
||||
add z0.s, z0.s, #1
|
||||
add z0.s, z0.s, #127
|
||||
add z0.s, z0.s, #128
|
||||
add z0.s, z0.s, #129
|
||||
add z0.s, z0.s, #255
|
||||
add z0.s, z0.s, #256
|
||||
add z0.s, z0.s, #0x7f00
|
||||
add z0.s, z0.s, #0x8000
|
||||
add z0.s, z0.s, #0xff00
|
||||
add z0.s, z0.s, #0, lsl #8
|
||||
add z0.s, z0.s, #1, lsl #8
|
||||
add z0.s, z0.s, #127, lsl #8
|
||||
add z0.s, z0.s, #128, lsl #8
|
||||
add z0.s, z0.s, #255, lsl #8
|
||||
|
||||
add z0.d, z0.d, #0
|
||||
add z0.d, z0.d, #1
|
||||
add z0.d, z0.d, #127
|
||||
add z0.d, z0.d, #128
|
||||
add z0.d, z0.d, #129
|
||||
add z0.d, z0.d, #255
|
||||
add z0.d, z0.d, #256
|
||||
add z0.d, z0.d, #0x7f00
|
||||
add z0.d, z0.d, #0x8000
|
||||
add z0.d, z0.d, #0xff00
|
||||
add z0.d, z0.d, #0, lsl #8
|
||||
add z0.d, z0.d, #1, lsl #8
|
||||
add z0.d, z0.d, #127, lsl #8
|
||||
add z0.d, z0.d, #128, lsl #8
|
||||
add z0.d, z0.d, #255, lsl #8
|
||||
|
||||
sub z0.b, z0.b, #-255
|
||||
sub z0.b, z0.b, #-129
|
||||
sub z0.b, z0.b, #-128
|
||||
sub z0.b, z0.b, #-127
|
||||
sub z0.b, z0.b, #-1
|
||||
sub z0.b, z0.b, #0
|
||||
sub z0.b, z0.b, #1
|
||||
sub z0.b, z0.b, #127
|
||||
sub z0.b, z0.b, #128
|
||||
sub z0.b, z0.b, #255
|
||||
|
||||
sub z0.h, z0.h, #-65536
|
||||
sub z0.h, z0.h, #-65535
|
||||
sub z0.h, z0.h, #-65536 + 127
|
||||
sub z0.h, z0.h, #-65536 + 128
|
||||
sub z0.h, z0.h, #-65536 + 129
|
||||
sub z0.h, z0.h, #-65536 + 255
|
||||
sub z0.h, z0.h, #-65536 + 256
|
||||
sub z0.h, z0.h, #-32768 - 256
|
||||
sub z0.h, z0.h, #-32768
|
||||
sub z0.h, z0.h, #-32768 + 256
|
||||
sub z0.h, z0.h, #0
|
||||
sub z0.h, z0.h, #1
|
||||
sub z0.h, z0.h, #127
|
||||
sub z0.h, z0.h, #128
|
||||
sub z0.h, z0.h, #129
|
||||
sub z0.h, z0.h, #255
|
||||
sub z0.h, z0.h, #256
|
||||
sub z0.h, z0.h, #32768 - 256
|
||||
sub z0.h, z0.h, #32768
|
||||
sub z0.h, z0.h, #32768 + 256
|
||||
sub z0.h, z0.h, #65536 - 256
|
||||
sub z0.h, z0.h, #-255, lsl #8
|
||||
sub z0.h, z0.h, #-129, lsl #8
|
||||
sub z0.h, z0.h, #-128, lsl #8
|
||||
sub z0.h, z0.h, #-127, lsl #8
|
||||
sub z0.h, z0.h, #-1, lsl #8
|
||||
sub z0.h, z0.h, #0, lsl #8
|
||||
sub z0.h, z0.h, #1, lsl #8
|
||||
sub z0.h, z0.h, #127, lsl #8
|
||||
sub z0.h, z0.h, #128, lsl #8
|
||||
sub z0.h, z0.h, #255, lsl #8
|
||||
|
||||
sub z0.s, z0.s, #0
|
||||
sub z0.s, z0.s, #1
|
||||
sub z0.s, z0.s, #127
|
||||
sub z0.s, z0.s, #128
|
||||
sub z0.s, z0.s, #129
|
||||
sub z0.s, z0.s, #255
|
||||
sub z0.s, z0.s, #256
|
||||
sub z0.s, z0.s, #0x7f00
|
||||
sub z0.s, z0.s, #0x8000
|
||||
sub z0.s, z0.s, #0xff00
|
||||
sub z0.s, z0.s, #0, lsl #8
|
||||
sub z0.s, z0.s, #1, lsl #8
|
||||
sub z0.s, z0.s, #127, lsl #8
|
||||
sub z0.s, z0.s, #128, lsl #8
|
||||
sub z0.s, z0.s, #255, lsl #8
|
||||
|
||||
sub z0.d, z0.d, #0
|
||||
sub z0.d, z0.d, #1
|
||||
sub z0.d, z0.d, #127
|
||||
sub z0.d, z0.d, #128
|
||||
sub z0.d, z0.d, #129
|
||||
sub z0.d, z0.d, #255
|
||||
sub z0.d, z0.d, #256
|
||||
sub z0.d, z0.d, #0x7f00
|
||||
sub z0.d, z0.d, #0x8000
|
||||
sub z0.d, z0.d, #0xff00
|
||||
sub z0.d, z0.d, #0, lsl #8
|
||||
sub z0.d, z0.d, #1, lsl #8
|
||||
sub z0.d, z0.d, #127, lsl #8
|
||||
sub z0.d, z0.d, #128, lsl #8
|
||||
sub z0.d, z0.d, #255, lsl #8
|
||||
161
gas/testsuite/gas/aarch64/sve-dup.d
Normal file
161
gas/testsuite/gas/aarch64/sve-dup.d
Normal file
@@ -0,0 +1,161 @@
|
||||
#as: -march=armv8-a+sve
|
||||
#objdump: -dr
|
||||
|
||||
.*: file format .*
|
||||
|
||||
|
||||
Disassembly of section .*:
|
||||
|
||||
0+ <.*>:
|
||||
.*: 2538c020 mov z0\.b, #1
|
||||
.*: 2538cfe0 mov z0\.b, #127
|
||||
.*: 2538d000 mov z0\.b, #-128
|
||||
.*: 2538d020 mov z0\.b, #-127
|
||||
.*: 2538dfe0 mov z0\.b, #-1
|
||||
.*: 2538c000 mov z0\.b, #0
|
||||
.*: 2538c020 mov z0\.b, #1
|
||||
.*: 2538cfe0 mov z0\.b, #127
|
||||
.*: 2538d000 mov z0\.b, #-128
|
||||
.*: 2538dfe0 mov z0\.b, #-1
|
||||
.*: 2578c020 mov z0\.h, #1
|
||||
.*: 2578cfe0 mov z0\.h, #127
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578f020 mov z0\.h, #-32512
|
||||
.*: 2578d000 mov z0\.h, #-128
|
||||
.*: 2578d020 mov z0\.h, #-127
|
||||
.*: 2578dfe0 mov z0\.h, #-1
|
||||
.*: 2578c000 mov z0\.h, #0
|
||||
.*: 2578c020 mov z0\.h, #1
|
||||
.*: 2578cfe0 mov z0\.h, #127
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 2578d000 mov z0\.h, #-128
|
||||
.*: 2578d020 mov z0\.h, #-127
|
||||
.*: 2578dfe0 mov z0\.h, #-1
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578f020 mov z0\.h, #-32512
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 2578e000 mov z0\.h, #0, lsl #8
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 25b8f000 mov z0\.s, #-32768
|
||||
.*: 25b8f020 mov z0\.s, #-32512
|
||||
.*: 25b8d000 mov z0\.s, #-128
|
||||
.*: 25b8d020 mov z0\.s, #-127
|
||||
.*: 25b8dfe0 mov z0\.s, #-1
|
||||
.*: 25b8c000 mov z0\.s, #0
|
||||
.*: 25b8c020 mov z0\.s, #1
|
||||
.*: 25b8cfe0 mov z0\.s, #127
|
||||
.*: 25b8e020 mov z0\.s, #256
|
||||
.*: 25b8efe0 mov z0\.s, #32512
|
||||
.*: 25b8d000 mov z0\.s, #-128
|
||||
.*: 25b8d020 mov z0\.s, #-127
|
||||
.*: 25b8dfe0 mov z0\.s, #-1
|
||||
.*: 25b8f000 mov z0\.s, #-32768
|
||||
.*: 25b8f020 mov z0\.s, #-32512
|
||||
.*: 25b8ffe0 mov z0\.s, #-256
|
||||
.*: 25b8e000 mov z0\.s, #0, lsl #8
|
||||
.*: 25b8e020 mov z0\.s, #256
|
||||
.*: 25b8efe0 mov z0\.s, #32512
|
||||
.*: 25f8f000 mov z0\.d, #-32768
|
||||
.*: 25f8f020 mov z0\.d, #-32512
|
||||
.*: 25f8d000 mov z0\.d, #-128
|
||||
.*: 25f8d020 mov z0\.d, #-127
|
||||
.*: 25f8dfe0 mov z0\.d, #-1
|
||||
.*: 25f8c000 mov z0\.d, #0
|
||||
.*: 25f8c020 mov z0\.d, #1
|
||||
.*: 25f8cfe0 mov z0\.d, #127
|
||||
.*: 25f8e020 mov z0\.d, #256
|
||||
.*: 25f8efe0 mov z0\.d, #32512
|
||||
.*: 25f8d000 mov z0\.d, #-128
|
||||
.*: 25f8d020 mov z0\.d, #-127
|
||||
.*: 25f8dfe0 mov z0\.d, #-1
|
||||
.*: 25f8f000 mov z0\.d, #-32768
|
||||
.*: 25f8f020 mov z0\.d, #-32512
|
||||
.*: 25f8ffe0 mov z0\.d, #-256
|
||||
.*: 25f8e000 mov z0\.d, #0, lsl #8
|
||||
.*: 25f8e020 mov z0\.d, #256
|
||||
.*: 25f8efe0 mov z0\.d, #32512
|
||||
.*: 2538c020 mov z0\.b, #1
|
||||
.*: 2538cfe0 mov z0\.b, #127
|
||||
.*: 2538d000 mov z0\.b, #-128
|
||||
.*: 2538d020 mov z0\.b, #-127
|
||||
.*: 2538dfe0 mov z0\.b, #-1
|
||||
.*: 2538c000 mov z0\.b, #0
|
||||
.*: 2538c020 mov z0\.b, #1
|
||||
.*: 2538cfe0 mov z0\.b, #127
|
||||
.*: 2538d000 mov z0\.b, #-128
|
||||
.*: 2538dfe0 mov z0\.b, #-1
|
||||
.*: 2578c020 mov z0\.h, #1
|
||||
.*: 2578cfe0 mov z0\.h, #127
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578f020 mov z0\.h, #-32512
|
||||
.*: 2578d000 mov z0\.h, #-128
|
||||
.*: 2578d020 mov z0\.h, #-127
|
||||
.*: 2578dfe0 mov z0\.h, #-1
|
||||
.*: 2578c000 mov z0\.h, #0
|
||||
.*: 2578c020 mov z0\.h, #1
|
||||
.*: 2578cfe0 mov z0\.h, #127
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 2578d000 mov z0\.h, #-128
|
||||
.*: 2578d020 mov z0\.h, #-127
|
||||
.*: 2578dfe0 mov z0\.h, #-1
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578f020 mov z0\.h, #-32512
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 2578e000 mov z0\.h, #0, lsl #8
|
||||
.*: 2578e020 mov z0\.h, #256
|
||||
.*: 2578efe0 mov z0\.h, #32512
|
||||
.*: 2578f000 mov z0\.h, #-32768
|
||||
.*: 2578ffe0 mov z0\.h, #-256
|
||||
.*: 25b8f000 mov z0\.s, #-32768
|
||||
.*: 25b8f020 mov z0\.s, #-32512
|
||||
.*: 25b8d000 mov z0\.s, #-128
|
||||
.*: 25b8d020 mov z0\.s, #-127
|
||||
.*: 25b8dfe0 mov z0\.s, #-1
|
||||
.*: 25b8c000 mov z0\.s, #0
|
||||
.*: 25b8c020 mov z0\.s, #1
|
||||
.*: 25b8cfe0 mov z0\.s, #127
|
||||
.*: 25b8e020 mov z0\.s, #256
|
||||
.*: 25b8efe0 mov z0\.s, #32512
|
||||
.*: 25b8d000 mov z0\.s, #-128
|
||||
.*: 25b8d020 mov z0\.s, #-127
|
||||
.*: 25b8dfe0 mov z0\.s, #-1
|
||||
.*: 25b8f000 mov z0\.s, #-32768
|
||||
.*: 25b8f020 mov z0\.s, #-32512
|
||||
.*: 25b8ffe0 mov z0\.s, #-256
|
||||
.*: 25b8e000 mov z0\.s, #0, lsl #8
|
||||
.*: 25b8e020 mov z0\.s, #256
|
||||
.*: 25b8efe0 mov z0\.s, #32512
|
||||
.*: 25f8f000 mov z0\.d, #-32768
|
||||
.*: 25f8f020 mov z0\.d, #-32512
|
||||
.*: 25f8d000 mov z0\.d, #-128
|
||||
.*: 25f8d020 mov z0\.d, #-127
|
||||
.*: 25f8dfe0 mov z0\.d, #-1
|
||||
.*: 25f8c000 mov z0\.d, #0
|
||||
.*: 25f8c020 mov z0\.d, #1
|
||||
.*: 25f8cfe0 mov z0\.d, #127
|
||||
.*: 25f8e020 mov z0\.d, #256
|
||||
.*: 25f8efe0 mov z0\.d, #32512
|
||||
.*: 25f8d000 mov z0\.d, #-128
|
||||
.*: 25f8d020 mov z0\.d, #-127
|
||||
.*: 25f8dfe0 mov z0\.d, #-1
|
||||
.*: 25f8f000 mov z0\.d, #-32768
|
||||
.*: 25f8f020 mov z0\.d, #-32512
|
||||
.*: 25f8ffe0 mov z0\.d, #-256
|
||||
.*: 25f8e000 mov z0\.d, #0, lsl #8
|
||||
.*: 25f8e020 mov z0\.d, #256
|
||||
.*: 25f8efe0 mov z0\.d, #32512
|
||||
159
gas/testsuite/gas/aarch64/sve-dup.s
Normal file
159
gas/testsuite/gas/aarch64/sve-dup.s
Normal file
@@ -0,0 +1,159 @@
|
||||
dup z0.b, #-255
|
||||
dup z0.b, #-129
|
||||
dup z0.b, #-128
|
||||
dup z0.b, #-127
|
||||
dup z0.b, #-1
|
||||
dup z0.b, #0
|
||||
dup z0.b, #1
|
||||
dup z0.b, #127
|
||||
dup z0.b, #128
|
||||
dup z0.b, #255
|
||||
|
||||
dup z0.h, #-65535
|
||||
dup z0.h, #-65536 + 127
|
||||
dup z0.h, #-65536 + 256
|
||||
dup z0.h, #-32768
|
||||
dup z0.h, #-32768 + 256
|
||||
dup z0.h, #-128
|
||||
dup z0.h, #-127
|
||||
dup z0.h, #-1
|
||||
dup z0.h, #0
|
||||
dup z0.h, #1
|
||||
dup z0.h, #127
|
||||
dup z0.h, #256
|
||||
dup z0.h, #32768 - 256
|
||||
dup z0.h, #32768
|
||||
dup z0.h, #65536 - 256
|
||||
dup z0.h, #65536 - 128
|
||||
dup z0.h, #65536 - 127
|
||||
dup z0.h, #65535
|
||||
dup z0.h, #-255, lsl #8
|
||||
dup z0.h, #-129, lsl #8
|
||||
dup z0.h, #-128, lsl #8
|
||||
dup z0.h, #-127, lsl #8
|
||||
dup z0.h, #-1, lsl #8
|
||||
dup z0.h, #0, lsl #8
|
||||
dup z0.h, #1, lsl #8
|
||||
dup z0.h, #127, lsl #8
|
||||
dup z0.h, #128, lsl #8
|
||||
dup z0.h, #255, lsl #8
|
||||
|
||||
dup z0.s, #-32768
|
||||
dup z0.s, #-32768 + 256
|
||||
dup z0.s, #-128
|
||||
dup z0.s, #-127
|
||||
dup z0.s, #-1
|
||||
dup z0.s, #0
|
||||
dup z0.s, #1
|
||||
dup z0.s, #127
|
||||
dup z0.s, #256
|
||||
dup z0.s, #32768 - 256
|
||||
dup z0.s, #0xffffff80
|
||||
dup z0.s, #0xffffff81
|
||||
dup z0.s, #0xffffffff
|
||||
dup z0.s, #-128, lsl #8
|
||||
dup z0.s, #-127, lsl #8
|
||||
dup z0.s, #-1, lsl #8
|
||||
dup z0.s, #0, lsl #8
|
||||
dup z0.s, #1, lsl #8
|
||||
dup z0.s, #127, lsl #8
|
||||
|
||||
dup z0.d, #-32768
|
||||
dup z0.d, #-32768 + 256
|
||||
dup z0.d, #-128
|
||||
dup z0.d, #-127
|
||||
dup z0.d, #-1
|
||||
dup z0.d, #0
|
||||
dup z0.d, #1
|
||||
dup z0.d, #127
|
||||
dup z0.d, #256
|
||||
dup z0.d, #32768 - 256
|
||||
dup z0.d, #0xffffffffffffff80
|
||||
dup z0.d, #0xffffffffffffff81
|
||||
dup z0.d, #0xffffffffffffffff
|
||||
dup z0.d, #-128, lsl #8
|
||||
dup z0.d, #-127, lsl #8
|
||||
dup z0.d, #-1, lsl #8
|
||||
dup z0.d, #0, lsl #8
|
||||
dup z0.d, #1, lsl #8
|
||||
dup z0.d, #127, lsl #8
|
||||
|
||||
mov z0.b, #-255
|
||||
mov z0.b, #-129
|
||||
mov z0.b, #-128
|
||||
mov z0.b, #-127
|
||||
mov z0.b, #-1
|
||||
mov z0.b, #0
|
||||
mov z0.b, #1
|
||||
mov z0.b, #127
|
||||
mov z0.b, #128
|
||||
mov z0.b, #255
|
||||
|
||||
mov z0.h, #-65535
|
||||
mov z0.h, #-65536 + 127
|
||||
mov z0.h, #-65536 + 256
|
||||
mov z0.h, #-32768
|
||||
mov z0.h, #-32768 + 256
|
||||
mov z0.h, #-128
|
||||
mov z0.h, #-127
|
||||
mov z0.h, #-1
|
||||
mov z0.h, #0
|
||||
mov z0.h, #1
|
||||
mov z0.h, #127
|
||||
mov z0.h, #256
|
||||
mov z0.h, #32768 - 256
|
||||
mov z0.h, #32768
|
||||
mov z0.h, #65536 - 256
|
||||
mov z0.h, #65536 - 128
|
||||
mov z0.h, #65536 - 127
|
||||
mov z0.h, #65535
|
||||
mov z0.h, #-255, lsl #8
|
||||
mov z0.h, #-129, lsl #8
|
||||
mov z0.h, #-128, lsl #8
|
||||
mov z0.h, #-127, lsl #8
|
||||
mov z0.h, #-1, lsl #8
|
||||
mov z0.h, #0, lsl #8
|
||||
mov z0.h, #1, lsl #8
|
||||
mov z0.h, #127, lsl #8
|
||||
mov z0.h, #128, lsl #8
|
||||
mov z0.h, #255, lsl #8
|
||||
|
||||
mov z0.s, #-32768
|
||||
mov z0.s, #-32768 + 256
|
||||
mov z0.s, #-128
|
||||
mov z0.s, #-127
|
||||
mov z0.s, #-1
|
||||
mov z0.s, #0
|
||||
mov z0.s, #1
|
||||
mov z0.s, #127
|
||||
mov z0.s, #256
|
||||
mov z0.s, #32768 - 256
|
||||
mov z0.s, #0xffffff80
|
||||
mov z0.s, #0xffffff81
|
||||
mov z0.s, #0xffffffff
|
||||
mov z0.s, #-128, lsl #8
|
||||
mov z0.s, #-127, lsl #8
|
||||
mov z0.s, #-1, lsl #8
|
||||
mov z0.s, #0, lsl #8
|
||||
mov z0.s, #1, lsl #8
|
||||
mov z0.s, #127, lsl #8
|
||||
|
||||
mov z0.d, #-32768
|
||||
mov z0.d, #-32768 + 256
|
||||
mov z0.d, #-128
|
||||
mov z0.d, #-127
|
||||
mov z0.d, #-1
|
||||
mov z0.d, #0
|
||||
mov z0.d, #1
|
||||
mov z0.d, #127
|
||||
mov z0.d, #256
|
||||
mov z0.d, #32768 - 256
|
||||
mov z0.d, #0xffffffffffffff80
|
||||
mov z0.d, #0xffffffffffffff81
|
||||
mov z0.d, #0xffffffffffffffff
|
||||
mov z0.d, #-128, lsl #8
|
||||
mov z0.d, #-127, lsl #8
|
||||
mov z0.d, #-1, lsl #8
|
||||
mov z0.d, #0, lsl #8
|
||||
mov z0.d, #1, lsl #8
|
||||
mov z0.d, #127, lsl #8
|
||||
4
gas/testsuite/gas/aarch64/sve-invalid.d
Normal file
4
gas/testsuite/gas/aarch64/sve-invalid.d
Normal file
@@ -0,0 +1,4 @@
|
||||
#name: Invalid SVE instructions
|
||||
#as: -march=armv8-a+sve
|
||||
#source: sve-invalid.s
|
||||
#error-output: sve-invalid.l
|
||||
944
gas/testsuite/gas/aarch64/sve-invalid.l
Normal file
944
gas/testsuite/gas/aarch64/sve-invalid.l
Normal file
@@ -0,0 +1,944 @@
|
||||
[^:]*: Assembler messages:
|
||||
.*: Error: operand 2 should be an SVE predicate register -- `fmov z1,z2'
|
||||
.*: Error: operand mismatch -- `fmov z1,#1\.0'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmov z1\.s,#1\.000000000000000000e\+00
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: fmov z1\.d,#1\.000000000000000000e\+00
|
||||
.*: Error: operand mismatch -- `fmov z1,#0\.0'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: fmov z1\.s,#0\.0
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: fmov z1\.d,#0\.0
|
||||
.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/'
|
||||
.*: Error: missing predication type at operand 2 -- `not z0\.s,p1/,z2\.s'
|
||||
.*: Error: unexpected character `c' in predication type at operand 2 -- `not z0\.s,p1/c,z2\.s'
|
||||
.*: Error: operand mismatch -- `movprfx z0\.h,z1\.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0,z1
|
||||
.*: Error: operand mismatch -- `movprfx z0,z1\.h'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0,z1
|
||||
.*: Error: operand mismatch -- `movprfx z0\.h,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0,z1
|
||||
.*: Error: operand mismatch -- `movprfx z0\.h,z1\.s'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0,z1
|
||||
.*: Error: operand mismatch -- `movprfx z0,p1/m,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0,p1/z,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0\.b,p1/m,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0\.b,p1/z,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0,p1/m,z1\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0,p1/z,z1\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0\.h,p1/m,z1\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0\.h,p1/z,z1\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand mismatch -- `movprfx z0\.b,p1,z1\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: movprfx z0\.b,p1/z,z1\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: movprfx z0\.b,p1/m,z1\.b
|
||||
.*: Info: movprfx z0\.h,p1/z,z1\.h
|
||||
.*: Info: movprfx z0\.h,p1/m,z1\.h
|
||||
.*: Info: movprfx z0\.s,p1/z,z1\.s
|
||||
.*: Info: movprfx z0\.s,p1/m,z1\.s
|
||||
.*: Info: movprfx z0\.d,p1/z,z1\.d
|
||||
.*: Info: movprfx z0\.d,p1/m,z1\.d
|
||||
.*: Error: operand 1 should be an SVE vector register -- `movprfx p0,p1'
|
||||
.*: Error: operand mismatch -- `ldr p0\.b,\[x1\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ldr p0,\[x1\]
|
||||
.*: Error: operand mismatch -- `ldr z0\.b,\[x1\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ldr z0,\[x1\]
|
||||
.*: Error: operand mismatch -- `str p0\.b,\[x1\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: str p0,\[x1\]
|
||||
.*: Error: operand mismatch -- `str z0\.b,\[x1\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: str z0,\[x1\]
|
||||
.*: Error: operand mismatch -- `mov z0,b0'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: mov z0\.b,b0
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: mov z0\.h,h0
|
||||
.*: Info: mov z0\.s,s0
|
||||
.*: Info: mov z0\.d,d0
|
||||
.*: Error: operand mismatch -- `mov z0,z1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: mov z0\.d,z1\.d
|
||||
.*: Error: operand mismatch -- `mov p0,p1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: mov p0\.b,p1\.b
|
||||
.*: Error: operand mismatch -- `add z0,z0,z2'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.b,z0\.b,z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.h,z0\.h,z2\.h
|
||||
.*: Info: add z0\.s,z0\.s,z2\.s
|
||||
.*: Info: add z0\.d,z0\.d,z2\.d
|
||||
.*: Error: operand mismatch -- `add z0,z0,#2'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.b,z0\.b,#2
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.h,z0\.h,#2
|
||||
.*: Info: add z0\.s,z0\.s,#2
|
||||
.*: Info: add z0\.d,z0\.d,#2
|
||||
.*: Error: operand mismatch -- `add z0,z1,z2'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.b,z1\.b,z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.h,z1\.h,z2\.h
|
||||
.*: Info: add z0\.s,z1\.s,z2\.s
|
||||
.*: Info: add z0\.d,z1\.d,z2\.d
|
||||
.*: Error: operand 2 must be the same register as operand 1 -- `add z0,z1,#1'
|
||||
.*: Error: operand 2 must be the same register as operand 1 -- `add z0\.b,z1\.b,#1'
|
||||
.*: Error: operand mismatch -- `add z0\.b,z0\.h,#1'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.b,z0\.b,#1
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.h,z0\.h,#1
|
||||
.*: Info: add z0\.s,z0\.s,#1
|
||||
.*: Info: add z0\.d,z0\.d,#1
|
||||
.*: Error: constant expression required at operand 2 -- `mov z0\.b,z32\.b'
|
||||
.*: Error: operand 2 should be an SVE predicate register -- `mov p0\.b,p16\.b'
|
||||
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p8/z,z1\.b,z2\.b'
|
||||
.*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p15/z,z1\.b,z2\.b'
|
||||
.*: Error: operand mismatch -- `ld1w z0\.s,p0,\[x0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1w \{z0\.s\},p0/z,\[x0\]
|
||||
.*: Error: operand mismatch -- `ld1w z0\.s,p0/m,\[x0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: ld1w \{z0\.s\},p0/z,\[x0\]
|
||||
.*: Error: operand mismatch -- `cmpeq p0\.b,p0,z1\.b,z2\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: cmpeq p0\.b,p0/z,z1\.b,z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: cmpeq p0\.h,p0/z,z1\.h,z2\.h
|
||||
.*: Info: cmpeq p0\.s,p0/z,z1\.s,z2\.s
|
||||
.*: Info: cmpeq p0\.d,p0/z,z1\.d,z2\.d
|
||||
.*: Error: operand mismatch -- `cmpeq p0\.b,p0/m,z1\.b,z2\.b'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: cmpeq p0\.b,p0/z,z1\.b,z2\.b
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: cmpeq p0\.h,p0/z,z1\.h,z2\.h
|
||||
.*: Info: cmpeq p0\.s,p0/z,z1\.s,z2\.s
|
||||
.*: Info: cmpeq p0\.d,p0/z,z1\.d,z2\.d
|
||||
.*: Error: operand mismatch -- `add z0\.s,p0,z0\.s,z1\.s'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.s,p0/m,z0\.s,z1\.s
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.b,p0/m,z0\.b,z1\.b
|
||||
.*: Info: add z0\.h,p0/m,z0\.h,z1\.h
|
||||
.*: Info: add z0\.d,p0/m,z0\.d,z1\.d
|
||||
.*: Error: operand mismatch -- `add z0\.s,p0/z,z0\.s,z1\.s'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: add z0\.s,p0/m,z0\.s,z1\.s
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: add z0\.b,p0/m,z0\.b,z1\.b
|
||||
.*: Info: add z0\.h,p0/m,z0\.h,z1\.h
|
||||
.*: Info: add z0\.d,p0/m,z0\.d,z1\.d
|
||||
.*: Error: operand mismatch -- `st1w z0\.s,p0/z,\[x0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: st1w \{z0\.s\},p0,\[x0\]
|
||||
.*: Error: operand mismatch -- `st1w z0\.s,p0/m,\[x0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: st1w \{z0\.s\},p0,\[x0\]
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1b z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1h z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1w z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1d z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1b z0,p1/z,\[x1,xzr\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1h z0,p1/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1w z0,p1/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1d z0,p1/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1b z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1h z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1w z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1d z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1b z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1h z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1w z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1d z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1b z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1h z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1w z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1d z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1b z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1h z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1w z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1d z0,p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1b {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ld1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1b {z0},p1/z,\[x1,xzr\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1h {z0},p1/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1w {z0},p1/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldff1d {z0},p1/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1b {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnf1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1b {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `ldnt1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1b {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `st1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1b {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1h {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1w {z0},p1/z,\[x1\]'
|
||||
.*: Error: missing type suffix at operand 1 -- `stnt1d {z0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {x0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {b0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {h0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {s0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {d0},p1/z,\[x1\]'
|
||||
.*: Error: operand 1 should be a list of SVE vector registers -- `ld1b {v0\.2s},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.h},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.s},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.d},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.h,z1},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.h,z1\.s},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.h,z1\.d},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.s,z1},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.s,z1\.d},p1/z,\[x1\]'
|
||||
.*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.d,z1},p1/z,\[x1\]'
|
||||
.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#-9,mul vl\]'
|
||||
.*: Error: only 'MUL VL' is permitted at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#0,mul#1\]'
|
||||
.*: Error: '\]' expected at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#0,mul vl#1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#foo,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#7,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -8 to 7 at operand 3 -- `ld1b z0\.b,p1/z,\[x1,#8,mul vl\]'
|
||||
.*: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#-18,mul vl\]'
|
||||
.*: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#-17,mul vl\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#foo,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 2 at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#1,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#14,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld2b \{z0\.b,z1\.b\},p1/z,\[x1,#16,mul vl\]'
|
||||
.*: Error: immediate offset out of range -24 to 21 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#-27,mul vl\]'
|
||||
.*: Error: immediate offset out of range -24 to 21 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#-26,mul vl\]'
|
||||
.*: Error: immediate offset out of range -24 to 21 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#-25,mul vl\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#foo,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 3 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#1,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 3 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#2,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#21,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -24 to 21 at operand 3 -- `ld3b \{z0\.b-z2\.b\},p1/z,\[x1,#24,mul vl\]'
|
||||
.*: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#-36,mul vl\]'
|
||||
.*: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#-35,mul vl\]'
|
||||
.*: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#-34,mul vl\]'
|
||||
.*: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#-33,mul vl\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#foo,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#1,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#2,mul vl\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#3,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#28,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld4b \{z0\.b-z3\.b\},p1/z,\[x1,#32,mul vl\]'
|
||||
.*: Error: immediate offset out of range -32 to 31 at operand 3 -- `prfb pldl1keep,p1,\[x1,#-33,mul vl\]'
|
||||
.*: Error: constant offset required at operand 3 -- `prfb pldl1keep,p1,\[x1,#foo,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `prfb pldl1keep,p1,\[x1,#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `prfb pldl1keep,p1,\[x1,#31,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -32 to 31 at operand 3 -- `prfb pldl1keep,p1,\[x1,#32,mul vl\]'
|
||||
.*: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr z0,\[x1,#-257,mul vl\]'
|
||||
.*: Error: constant offset required at operand 2 -- `ldr z0,\[x1,#foo,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `ldr z0,\[x1,#1\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `ldr z0,\[x1,#255,mul vl\]!'
|
||||
.*: Error: immediate offset out of range -256 to 255 at operand 2 -- `ldr z0,\[x1,#256,mul vl\]'
|
||||
.*: Error: immediate offset out of range 0 to 63 at operand 3 -- `ld1rb z0\.b,p1/z,\[x1,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1rb z0\.b,p1/z,\[x1,#foo\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rb z0\.b,p1/z,\[x1,#1,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rb z0\.b,p1/z,\[x1,#63\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rb z0\.b,p1/z,\[x1\],#63'
|
||||
.*: Error: immediate offset out of range 0 to 63 at operand 3 -- `ld1rb z0\.b,p1/z,\[x1,#64\]'
|
||||
.*: Error: immediate offset out of range 0 to 126 at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#-2\]'
|
||||
.*: Error: immediate offset out of range 0 to 126 at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 2 at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#2,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#126\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rh z0\.h,p1/z,\[x1\],#126'
|
||||
.*: Error: immediate offset out of range 0 to 126 at operand 3 -- `ld1rh z0\.h,p1/z,\[x1,#128\]'
|
||||
.*: Error: immediate offset out of range 0 to 252 at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#-4\]'
|
||||
.*: Error: immediate offset out of range 0 to 252 at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#1\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#4,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#252\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rw z0\.s,p1/z,\[x1\],#252'
|
||||
.*: Error: immediate offset out of range 0 to 252 at operand 3 -- `ld1rw z0\.s,p1/z,\[x1,#256\]'
|
||||
.*: Error: immediate offset out of range 0 to 504 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#-8\]'
|
||||
.*: Error: immediate offset out of range 0 to 504 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#1\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#2\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#4\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#8,mul vl\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#504\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1rd z0\.d,p1/z,\[x1\],#504'
|
||||
.*: Error: immediate offset out of range 0 to 504 at operand 3 -- `ld1rd z0\.d,p1/z,\[x1,#512\]'
|
||||
.*: Error: register offset not allowed in pre-indexed addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,x2\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1\],x2'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,x2,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,x2,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,x2,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.b,p1/z,\[x1,x2,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,w2,sxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.b,p1/z,\[x1,w2,uxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,x2\]'
|
||||
.*: Error: register offset not allowed in pre-indexed addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,x2,lsl#1\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,x2,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,x2,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.h,p1/z,\[x1,x2,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,w2,sxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.h,p1/z,\[x1,w2,uxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,x2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,x2,lsl#1\]'
|
||||
.*: Error: register offset not allowed in pre-indexed addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,x2,lsl#2\]!'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,x2,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.s,p1/z,\[x1,x2,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,w2,sxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,w2,uxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,x2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,x2,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,x2,lsl#2\]'
|
||||
.*: Error: register offset not allowed in pre-indexed addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,x2,lsl#3\]!'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1d z0\.d,p1/z,\[x1,x2,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,w2,sxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,w2,uxtw\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,lsl#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,lsl#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,lsl#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,lsl#2\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,sxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,sxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,sxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,sxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,uxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,uxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.s,p1/z,\[x1,z2\.s,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,uxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.s,p1/z,\[x1,z2\.s,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,uxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.s,p1/z,\[x1,z2\.s,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,sxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,sxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,sxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,sxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,sxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,sxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,sxtw#2\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,uxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,uxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1b z0\.d,p1/z,\[x1,z2\.d,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,uxtw#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1h z0\.d,p1/z,\[x1,z2\.d,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,uxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,uxtw#3\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1w z0\.d,p1/z,\[x1,z2\.d,uxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,uxtw#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,uxtw#2\]'
|
||||
.*: Error: constant shift amount required at operand 3 -- `ld1d z0\.d,p1/z,\[x1,z2\.d,uxtw x3\]'
|
||||
.*: Error: immediate offset out of range 0 to 31 at operand 3 -- `ld1b z0\.d,p1/z,\[z2\.d,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1b z0\.d,p1/z,\[z2\.d,#foo\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1b z0\.d,p1/z,\[z2\.d,#1,mul vl\]'
|
||||
.*: Error: immediate offset out of range 0 to 31 at operand 3 -- `ld1b z0\.d,p1/z,\[z2\.d,#32\]'
|
||||
.*: Error: immediate offset out of range 0 to 62 at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#-2\]'
|
||||
.*: Error: immediate offset out of range 0 to 62 at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 2 at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#1\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#2,mul vl\]'
|
||||
.*: Error: immediate offset out of range 0 to 62 at operand 3 -- `ld1h z0\.d,p1/z,\[z2\.d,#64\]'
|
||||
.*: Error: immediate offset out of range 0 to 124 at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#-4\]'
|
||||
.*: Error: immediate offset out of range 0 to 124 at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#1\]'
|
||||
.*: Error: immediate value should be a multiple of 4 at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#2\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#4,mul vl\]'
|
||||
.*: Error: immediate offset out of range 0 to 124 at operand 3 -- `ld1w z0\.d,p1/z,\[z2\.d,#128\]'
|
||||
.*: Error: immediate offset out of range 0 to 248 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#-8\]'
|
||||
.*: Error: immediate offset out of range 0 to 248 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#-1\]'
|
||||
.*: Error: constant offset required at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#foo\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#1\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#2\]'
|
||||
.*: Error: immediate value should be a multiple of 8 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#4\]'
|
||||
.*: Error: invalid addressing mode at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#8,mul vl\]'
|
||||
.*: Error: immediate offset out of range 0 to 248 at operand 3 -- `ld1d z0\.d,p1/z,\[z2\.d,#256\]'
|
||||
.*: Error: shift amount out of range 0 to 63 at operand 2 -- `adr z0\.s,\[z1\.s,z2\.s,lsl#-1\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[z1\.s,z2\.s,lsl#4\]'
|
||||
.*: Error: constant shift amount required at operand 2 -- `adr z0\.s,\[z1\.s,z2\.s,lsl x3\]'
|
||||
.*: Error: offset has different size from base at operand 2 -- `adr z0\.s,\[z1\.s,z2\.d\]'
|
||||
.*: Error: offset has different size from base at operand 2 -- `adr z0\.s,\[z1\.s,x2\]'
|
||||
.*: Error: offset has different size from base at operand 2 -- `adr z0\.s,\[z1\.d,z2\.s\]'
|
||||
.*: Error: invalid use of 32-bit register offset at operand 2 -- `adr z0\.s,\[z1\.d,w2\]'
|
||||
.*: Error: offset has different size from base at operand 2 -- `adr z0\.s,\[x1,z2\.s\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[x1,z2\.d\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[z1\.d,x2\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[x1,x2\]'
|
||||
.*: Error: shift amount out of range 0 to 63 at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,lsl#-1\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,lsl#4\]'
|
||||
.*: Error: constant shift amount required at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,lsl x3\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[z1\.s,z2\.s,sxtw\]'
|
||||
.*: Error: shift amount out of range 0 to 63 at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,sxtw#-1\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,sxtw#4\]'
|
||||
.*: Error: constant shift amount required at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,sxtw x3\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.s,\[z1\.s,z2\.s,uxtw\]'
|
||||
.*: Error: shift amount out of range 0 to 63 at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,uxtw#-1\]'
|
||||
.*: Error: invalid addressing mode at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,uxtw#4\]'
|
||||
.*: Error: constant shift amount required at operand 2 -- `adr z0\.d,\[z1\.d,z2\.d,uxtw x3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1b z0\.b,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1b z0\.h,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1b z0\.s,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1b z0\.d,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sb z0\.h,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sb z0\.s,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sb z0\.d,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1h z0\.h,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1h z0\.s,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1h z0\.d,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sh z0\.s,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sh z0\.d,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1w z0\.s,p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1w z0\.d,p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1sw z0\.d,p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld1d z0\.d,p0/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld2b {z0\.b-z1\.b},p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld2h {z0\.h-z1\.h},p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld2w {z0\.s-z1\.s},p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld2d {z0\.d-z1\.d},p0/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld3b {z0\.b-z2\.b},p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld3h {z0\.h-z2\.h},p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld3w {z0\.s-z2\.s},p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld3d {z0\.d-z2\.d},p0/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld4b {z0\.b-z3\.b},p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld4h {z0\.h-z3\.h},p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld4w {z0\.s-z3\.s},p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ld4d {z0\.d-z3\.d},p0/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ldnt1b z0\.b,p0/z,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ldnt1h z0\.h,p0/z,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ldnt1w z0\.s,p0/z,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `ldnt1d z0\.d,p0/z,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1b z0\.b,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1b z0\.h,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1b z0\.s,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1b z0\.d,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1h z0\.h,p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1h z0\.s,p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1h z0\.d,p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1w z0\.s,p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1w z0\.d,p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st1d z0\.d,p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st2b {z0\.b-z1\.b},p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st2h {z0\.h-z1\.h},p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st2w {z0\.s-z1\.s},p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st2d {z0\.d-z1\.d},p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st3b {z0\.b-z2\.b},p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st3h {z0\.h-z2\.h},p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st3w {z0\.s-z2\.s},p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st3d {z0\.d-z2\.d},p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st4b {z0\.b-z3\.b},p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st4h {z0\.h-z3\.h},p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st4w {z0\.s-z3\.s},p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `st4d {z0\.d-z3\.d},p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `stnt1b z0\.b,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `stnt1h z0\.h,p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `stnt1w z0\.s,p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `stnt1d z0\.d,p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `prfb pldl1keep,p0,\[x1,xzr\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `prfh pldl1keep,p0,\[x1,xzr,lsl#1\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `prfw pldl1keep,p0,\[x1,xzr,lsl#2\]'
|
||||
.*: Error: index register xzr is not allowed at operand 3 -- `prfd pldl1keep,p0,\[x1,xzr,lsl#3\]'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.b,z0\.b,#-257'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.b,z0\.b,#256'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 3 -- `add z0\.b,z0\.b,#1,lsl#1'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 3 -- `add z0\.b,z0\.b,#0,lsl#8'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 3 -- `add z0\.b,z0\.b,#1,lsl#8'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.h,z0\.h,#-65537'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-65536\+257'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-32768\+255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-257'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-128'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-127'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#-1'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#65536-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#65536-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#65536-128'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.h,z0\.h,#65535'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.h,z0\.h,#65536'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 3 -- `add z0\.h,z0\.h,#1,lsl#1'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.h,z0\.h,#-257,lsl#8'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.h,z0\.h,#256,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-256'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-128'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-1'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#65536'
|
||||
.*: Error: immediate too big for element size at operand 3 -- `add z0\.s,z0\.s,#0x100000000'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 3 -- `add z0\.s,z0\.s,#1,lsl#1'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#-1,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.s,z0\.s,#256,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-256'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-128'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-1'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#65536'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#0x100000000'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 3 -- `add z0\.d,z0\.d,#1,lsl#1'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#-1,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 3 -- `add z0\.d,z0\.d,#256,lsl#8'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.b,#-257'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.b,#256'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 2 -- `dup z0\.b,#1,lsl#1'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 2 -- `dup z0\.b,#0,lsl#8'
|
||||
.*: Error: no shift amount allowed for 8-bit constants at operand 2 -- `dup z0\.b,#1,lsl#8'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.h,#-65537'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#-32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#-32768\+255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#-257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#128'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#65536-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.h,#65536-129'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.h,#65536'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 2 -- `dup z0\.h,#1,lsl#1'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.h,#-257,lsl#8'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.h,#256,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-65536'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-32769'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-32768\+255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#128'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#32768'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#65536'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#0xffffff7f'
|
||||
.*: Error: immediate too big for element size at operand 2 -- `dup z0\.s,#0x100000000'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 2 -- `dup z0\.s,#1,lsl#1'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#-129,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.s,#128,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-65536'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-32769'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-32768\+255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-129'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#128'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#257'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#32768-255'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#32767'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#32768'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#65536'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#0xffffff7f'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#0x100000000'
|
||||
.*: Error: shift amount should be 0 or 8 at operand 2 -- `dup z0\.d,#1,lsl#1'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#-129,lsl#8'
|
||||
.*: Error: invalid arithmetic immediate at operand 2 -- `dup z0\.d,#128,lsl#8'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x0101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x01010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x80808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x00010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x80008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x80000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.b,z0\.b,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x01010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x80808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x00010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x80008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x80000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.h,z0\.h,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.s,z0\.s,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `and z0\.d,z0\.d,#0xd'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x0101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x01010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x80808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x00010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x80008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x80000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.b,z0\.b,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x01010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x80808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x00010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x80008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x80000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.h,z0\.h,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x0101010101010101'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x7f7f7f7f7f7f7f7f'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x8080808080808080'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0xfefefefefefefefe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x0001000100010001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x7fff7fff7fff7fff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x8000800080008000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0xfffefffefffefffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x0000000100000001'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x7fffffff7fffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x8000000080000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0xfffffffefffffffe'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x7fffffffffffffff'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.s,z0\.s,#0x8000000000000000'
|
||||
.*: Error: immediate out of range at operand 3 -- `bic z0\.d,z0\.d,#0xd'
|
||||
.*: Error: immediate zero expected at operand 4 -- `fcmeq p0\.s,p1/z,z2\.s,#1'
|
||||
.*: Error: immediate zero expected at operand 4 -- `fcmeq p0\.s,p1/z,z2\.s,#1\.0'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#0'
|
||||
.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#0\.0'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#1'
|
||||
.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#1\.5'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#2'
|
||||
.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#2\.0'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#0'
|
||||
.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#0\.0'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1'
|
||||
.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1\.0'
|
||||
.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1\.5'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#2'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#0'
|
||||
.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#0\.5'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#1'
|
||||
.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#1\.5'
|
||||
.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#2'
|
||||
.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#2\.0'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `ptrue p1\.b,vl0'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `ptrue p1\.b,vl255'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `ptrue p1\.b,#-1'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `ptrue p1\.b,#32'
|
||||
.*: Error: immediate operand required at operand 2 -- `ptrue p1\.b,x0'
|
||||
.*: Error: immediate operand required at operand 2 -- `ptrue p1\.b,z0\.s'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `cntb x0,vl0'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `cntb x0,vl255'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `cntb x0,#-1'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `cntb x0,#32'
|
||||
.*: Error: immediate operand required at operand 2 -- `cntb x0,x0'
|
||||
.*: Error: immediate operand required at operand 2 -- `cntb x0,z0\.s'
|
||||
.*: Error: operand 2 should be an enumeration value such as POW2 -- `cntb x0,mul#1'
|
||||
.*: Error: multiplier out of range 1 to 16 at operand 2 -- `cntb x0,pow2,mul#0'
|
||||
.*: Error: multiplier out of range 1 to 16 at operand 2 -- `cntb x0,pow2,mul#17'
|
||||
.*: Error: shift expression expected at operand 2 -- `cntb x0,pow2,#1'
|
||||
.*: Error: operand 1 should be an enumeration value such as PLDL1KEEP -- `prfb pldl0keep,p1,\[x0\]'
|
||||
.*: Error: operand 1 should be an enumeration value such as PLDL1KEEP -- `prfb pldl4keep,p1,\[x0\]'
|
||||
.*: Error: operand 1 should be an enumeration value such as PLDL1KEEP -- `prfb #-1,p1,\[x0\]'
|
||||
.*: Error: operand 1 should be an enumeration value such as PLDL1KEEP -- `prfb #16,p1,\[x0\]'
|
||||
.*: Error: immediate operand required at operand 1 -- `prfb x0,p1,\[x0\]'
|
||||
.*: Error: immediate operand required at operand 1 -- `prfb z0\.s,p1,\[x0\]'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#8'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#9'
|
||||
.*: Error: operand 3 should be an SVE vector register -- `lsl z0\.b,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#16'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#17'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#-1'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#32'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#33'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#-1'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#64'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#65'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#8'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#9'
|
||||
.*: Error: operand 4 should be an SVE vector register -- `lsl z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#16'
|
||||
.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#17'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#-1'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#32'
|
||||
.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#33'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#-1'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#64'
|
||||
.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#65'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#0'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#9'
|
||||
.*: Error: operand 3 should be an SVE vector register -- `lsr z0\.b,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#17'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#-1'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#0'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#33'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#-1'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#0'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#65'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#-1'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#0'
|
||||
.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#9'
|
||||
.*: Error: operand 4 should be an SVE vector register -- `lsr z0\.b,p1/m,z0\.b,x0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#-1'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#0'
|
||||
.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#17'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#-1'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#0'
|
||||
.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#33'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#-1'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#0'
|
||||
.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#65'
|
||||
.*: Error: immediate value out of range -16 to 15 at operand 2 -- `index z0\.s,#-17,#1'
|
||||
.*: Error: immediate value out of range -16 to 15 at operand 2 -- `index z0\.s,#16,#1'
|
||||
.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#-17'
|
||||
.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#16'
|
||||
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl x0,sp,#-33'
|
||||
.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl sp,x0,#32'
|
||||
.*: Error: operand 2 should be an integer register or SP -- `addpl x0,xzr,#1'
|
||||
.*: Error: operand 1 should be an integer or stack pointer register -- `addpl xzr,x0,#1'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#-129'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#128'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#-129'
|
||||
.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#128'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,#-1'
|
||||
.*: Error: immediate value out of range 0 to 7 at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,#8'
|
||||
.*: Error: immediate operand required at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,z2\.s'
|
||||
.*: Error: immediate value out of range 0 to 127 at operand 4 -- `cmphi p0\.s,p1/z,z2\.s,#-1'
|
||||
.*: Error: immediate value out of range 0 to 127 at operand 4 -- `cmphi p0\.s,p1/z,z2\.s,#128'
|
||||
.*: Error: immediate value out of range 0 to 255 at operand 3 -- `umax z0\.s,z0\.s,#-1'
|
||||
.*: Error: immediate value out of range 0 to 255 at operand 3 -- `umax z0\.s,z0\.s,#256'
|
||||
.*: Error: immediate value out of range 0 to 255 at operand 4 -- `ext z0\.b,z0\.b,z1\.b,#-1'
|
||||
.*: Error: immediate value out of range 0 to 255 at operand 4 -- `ext z0\.b,z0\.b,z1\.b,#256'
|
||||
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]'
|
||||
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]'
|
||||
.*: Error: register element index out of range 0 to 15 at operand 2 -- `dup z0\.s,z1\.s\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 15 at operand 2 -- `dup z0\.s,z1\.s\[16\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.s,z1\.s\[x0\]'
|
||||
.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[8\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.d,z1\.d\[x0\]'
|
||||
1163
gas/testsuite/gas/aarch64/sve-invalid.s
Normal file
1163
gas/testsuite/gas/aarch64/sve-invalid.s
Normal file
File diff suppressed because it is too large
Load Diff
3
gas/testsuite/gas/aarch64/sve-reg-diagnostic.d
Normal file
3
gas/testsuite/gas/aarch64/sve-reg-diagnostic.d
Normal file
@@ -0,0 +1,3 @@
|
||||
#name: Diagnostics Quality (SVE registers)
|
||||
#source: sve-reg-diagnostic.s
|
||||
#error-output: sve-reg-diagnostic.l
|
||||
24
gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
Normal file
24
gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
Normal file
@@ -0,0 +1,24 @@
|
||||
.*: Assembler messages:
|
||||
.*: Error: operand 3 should be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,x0'
|
||||
.*: Error: operand 3 should be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
|
||||
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
|
||||
.*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
|
||||
.*: Error: base register expected at operand 2 -- `ldr x1,\[s0\]'
|
||||
.*: Error: base register expected at operand 2 -- `ldr x1,\[z0\]'
|
||||
.*: Error: base register expected at operand 2 -- `ldr x1,\[z0\.s\]'
|
||||
.*: Error: base register expected at operand 2 -- `ldr x1,\[p0\]'
|
||||
.*: Error: base register expected at operand 2 -- `ldr x1,\[p0\.b\]'
|
||||
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl p0\.b\]'
|
||||
.*: Error: invalid shift amount at operand 2 -- `ldr x0,\[x1,x2,lsl#p0\.b\]'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#x0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,s0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#s0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,z0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#z0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,z0\.s'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#z0\.s'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,p0'
|
||||
.*: Error: immediate out of range at operand 3 -- `and x0,x0,#p0'
|
||||
.*: Error: operand 3 should be an integer register -- `lsl x0,x0,s0'
|
||||
.*: Error: immediate operand required at operand 1 -- `svc x0'
|
||||
.*: Error: immediate operand required at operand 1 -- `svc s0'
|
||||
143
gas/testsuite/gas/aarch64/sve-reg-diagnostic.s
Normal file
143
gas/testsuite/gas/aarch64/sve-reg-diagnostic.s
Normal file
@@ -0,0 +1,143 @@
|
||||
.equ x0, 0
|
||||
.equ s0, 0
|
||||
.equ z0, 0
|
||||
.equ z0.s, 0
|
||||
.equ p0, 0
|
||||
.equ p0.b, 1
|
||||
|
||||
cmeq v0.4s, v1.4s, x0 // Error (wrong register type)
|
||||
cmeq v0.4s, v1.4s, #x0 // OK
|
||||
cmeq v0.4s, v1.4s, s0 // Error (wrong register type)
|
||||
cmeq v0.4s, v1.4s, #s0 // OK
|
||||
cmeq v0.4s, v1.4s, z0 // OK (for compatibility)
|
||||
cmeq v0.4s, v1.4s, #z0 // OK
|
||||
cmeq v0.4s, v1.4s, z0.s // OK (for compatibility)
|
||||
cmeq v0.4s, v1.4s, #z0.s // OK
|
||||
cmeq v0.4s, v1.4s, p0 // OK (for compatibility)
|
||||
cmeq v0.4s, v1.4s, #p0 // OK
|
||||
cmeq v0.4s, v1.4s, p0.b // Error (not 0)
|
||||
cmeq v0.4s, v1.4s, #p0.b // Error (not 0)
|
||||
|
||||
ldr x1, [x0, x0] // OK
|
||||
ldr x1, [x0, #x0] // OK
|
||||
ldr x1, [x2, s0] // OK (not considered a register here)
|
||||
ldr x1, [x2, #s0] // OK
|
||||
ldr x1, [x2, z0] // OK (for compatibility)
|
||||
ldr x1, [x2, #z0] // OK
|
||||
ldr x2, [x2, z0.s] // OK (for compatibility)
|
||||
ldr x1, [x2, #z0.s] // OK
|
||||
ldr x2, [x2, p0] // OK (not considered a register here)
|
||||
ldr x1, [x2, #p0] // OK
|
||||
ldr x2, [x2, p0.b] // OK (not considered a register here)
|
||||
ldr x1, [x2, #p0.b] // OK
|
||||
|
||||
ldr x1, [x0] // OK
|
||||
ldr x1, [s0] // Error (not a base register)
|
||||
ldr x1, [z0] // Error
|
||||
ldr x1, [z0.s] // Error
|
||||
ldr x1, [p0] // Error (not a base register)
|
||||
ldr x1, [p0.b] // Error (not a base register)
|
||||
|
||||
ldr x0, [x1, x2, lsl x0] // OK (not considered a register here)
|
||||
ldr x0, [x1, x2, lsl #x0] // OK
|
||||
ldr x0, [x1, x2, lsl s0] // OK (not considered a register here)
|
||||
ldr x0, [x1, x2, lsl #s0] // OK
|
||||
ldr x0, [x1, x2, lsl z0] // OK (not considered a register here)
|
||||
ldr x0, [x1, x2, lsl #z0] // OK
|
||||
ldr x0, [x1, x2, lsl z0.s] // OK (not considered a register here)
|
||||
ldr x0, [x1, x2, lsl #z0.s] // OK
|
||||
ldr x0, [x1, x2, lsl p0] // OK (not considered a register here)
|
||||
ldr x0, [x1, x2, lsl #p0] // OK
|
||||
ldr x0, [x1, x2, lsl p0.b] // Error (invalid shift amount)
|
||||
ldr x0, [x1, x2, lsl #p0.b] // Error (invalid shift amount)
|
||||
|
||||
mov x0, x0 // OK
|
||||
mov x0, #x0 // OK
|
||||
mov x0, s0 // OK (not considered a register here)
|
||||
mov x0, #s0 // OK
|
||||
mov x0, z0 // OK (not considered a register here)
|
||||
mov x0, #z0 // OK
|
||||
mov x0, z0.s // OK (not considered a register here)
|
||||
mov x0, #z0.s // OK
|
||||
mov x0, p0 // OK (not considered a register here)
|
||||
mov x0, #p0 // OK
|
||||
mov x0, p0.b // OK (not considered a register here)
|
||||
mov x0, #p0.b // OK
|
||||
|
||||
movk x0, x0 // OK (not considered a register here)
|
||||
movk x0, #x0 // OK
|
||||
movk x0, s0 // OK (not considered a register here)
|
||||
movk x0, #s0 // OK
|
||||
movk x0, z0 // OK (not considered a register here)
|
||||
movk x0, #z0 // OK
|
||||
movk x0, z0.s // OK (not considered a register here)
|
||||
movk x0, #z0.s // OK
|
||||
movk x0, p0 // OK (not considered a register here)
|
||||
movk x0, #p0 // OK
|
||||
movk x0, p0.b // OK (not considered a register here)
|
||||
movk x0, #p0.b // OK
|
||||
|
||||
add x0, x0, x0 // OK
|
||||
add x0, x0, #x0 // OK
|
||||
add x0, x0, s0 // OK (not considered a register here)
|
||||
add x0, x0, #s0 // OK
|
||||
add x0, x0, z0 // OK (not considered a register here)
|
||||
add x0, x0, #z0 // OK
|
||||
add x0, x0, z0.s // OK (not considered a register here)
|
||||
add x0, x0, #z0.s // OK
|
||||
add x0, x0, p0 // OK (not considered a register here)
|
||||
add x0, x0, #p0 // OK
|
||||
add x0, x0, p0.b // OK (not considered a register here)
|
||||
add x0, x0, #p0.b // OK
|
||||
|
||||
and x0, x0, x0 // OK
|
||||
and x0, x0, #x0 // Error (immediate out of range)
|
||||
and x0, x0, s0 // Error (immediate out of range)
|
||||
and x0, x0, #s0 // Error (immediate out of range)
|
||||
and x0, x0, z0 // Error (immediate out of range)
|
||||
and x0, x0, #z0 // Error (immediate out of range)
|
||||
and x0, x0, z0.s // Error (immediate out of range)
|
||||
and x0, x0, #z0.s // Error (immediate out of range)
|
||||
and x0, x0, p0 // Error (immediate out of range)
|
||||
and x0, x0, #p0 // Error (immediate out of range)
|
||||
and x0, x0, p0.b // OK (not considered a register here)
|
||||
and x0, x0, #p0.b // OK
|
||||
|
||||
lsl x0, x0, x0 // OK
|
||||
lsl x0, x0, #x0 // OK
|
||||
lsl x0, x0, s0 // Error (wrong register type)
|
||||
lsl x0, x0, #s0 // OK
|
||||
lsl x0, x0, z0 // OK (for compatibility)
|
||||
lsl x0, x0, #z0 // OK
|
||||
lsl x0, x0, z0.s // OK (for compatibility)
|
||||
lsl x0, x0, #z0.s // OK
|
||||
lsl x0, x0, p0 // OK (for compatibility)
|
||||
lsl x0, x0, #p0 // OK
|
||||
lsl x0, x0, p0.b // OK (for compatibility)
|
||||
lsl x0, x0, #p0.b // OK
|
||||
|
||||
adr x0, x0 // OK (not considered a register here)
|
||||
adr x0, #x0 // OK
|
||||
adr x0, s0 // OK (not considered a register here)
|
||||
adr x0, #s0 // OK
|
||||
adr x0, z0 // OK (not considered a register here)
|
||||
adr x0, #z0 // OK
|
||||
adr x0, z0.s // OK (not considered a register here)
|
||||
adr x0, #z0.s // OK
|
||||
adr x0, p0 // OK (not considered a register here)
|
||||
adr x0, #p0 // OK
|
||||
adr x0, p0.b // OK (not considered a register here)
|
||||
adr x0, #p0.b // OK
|
||||
|
||||
svc x0 // Error (immediate operand required)
|
||||
svc #x0 // OK
|
||||
svc s0 // Error (immediate operand required)
|
||||
svc #s0 // OK
|
||||
svc z0 // OK (for compatibility)
|
||||
svc #z0 // OK
|
||||
svc z0.s // OK (for compatibility)
|
||||
svc #z0.s // OK
|
||||
svc p0 // OK (for compatibility)
|
||||
svc #p0 // OK
|
||||
svc p0.b // OK (for compatibility)
|
||||
svc #p0.b // OK
|
||||
38238
gas/testsuite/gas/aarch64/sve.d
Normal file
38238
gas/testsuite/gas/aarch64/sve.d
Normal file
File diff suppressed because it is too large
Load Diff
38247
gas/testsuite/gas/aarch64/sve.s
Normal file
38247
gas/testsuite/gas/aarch64/sve.s
Normal file
File diff suppressed because it is too large
Load Diff
@@ -51,6 +51,7 @@ typedef uint32_t aarch64_insn;
|
||||
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
|
||||
#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
|
||||
#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
|
||||
#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
|
||||
|
||||
/* Architectures are the sum of the base and extensions. */
|
||||
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
|
||||
@@ -120,6 +121,8 @@ enum aarch64_operand_class
|
||||
AARCH64_OPND_CLASS_SISD_REG,
|
||||
AARCH64_OPND_CLASS_SIMD_REGLIST,
|
||||
AARCH64_OPND_CLASS_CP_REG,
|
||||
AARCH64_OPND_CLASS_SVE_REG,
|
||||
AARCH64_OPND_CLASS_PRED_REG,
|
||||
AARCH64_OPND_CLASS_ADDRESS,
|
||||
AARCH64_OPND_CLASS_IMMEDIATE,
|
||||
AARCH64_OPND_CLASS_SYSTEM,
|
||||
@@ -198,6 +201,7 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_BIT_NUM, /* Immediate. */
|
||||
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
|
||||
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
|
||||
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
|
||||
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
|
||||
each condition flag. */
|
||||
|
||||
@@ -241,6 +245,100 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
|
||||
AARCH64_OPND_PRFOP, /* Prefetch operation. */
|
||||
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
|
||||
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
|
||||
AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
|
||||
AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
|
||||
AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
|
||||
AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
|
||||
AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
|
||||
AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
|
||||
AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
|
||||
AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
|
||||
AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
|
||||
Bit 14 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
|
||||
Bit 22 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
|
||||
Bit 14 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
|
||||
Bit 22 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
|
||||
Bit 14 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
|
||||
Bit 22 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
|
||||
Bit 14 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
|
||||
Bit 22 controls S/U choice. */
|
||||
AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
|
||||
AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
|
||||
AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
|
||||
AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
|
||||
AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
|
||||
AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
|
||||
AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
|
||||
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
|
||||
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
|
||||
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
|
||||
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
|
||||
AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
|
||||
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
|
||||
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
|
||||
AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
|
||||
AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
|
||||
AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
|
||||
AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
|
||||
AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
|
||||
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
|
||||
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
|
||||
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
|
||||
AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
|
||||
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
|
||||
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
|
||||
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
|
||||
AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
|
||||
AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
|
||||
AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
|
||||
AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
|
||||
AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
|
||||
AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
|
||||
AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
|
||||
AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
|
||||
AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
|
||||
AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
|
||||
AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
|
||||
AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
|
||||
AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
|
||||
AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
|
||||
AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
|
||||
AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
|
||||
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
|
||||
AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
|
||||
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
|
||||
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
|
||||
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
|
||||
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
|
||||
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
|
||||
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
|
||||
};
|
||||
|
||||
/* Qualifier constrains an operand. It either specifies a variant of an
|
||||
@@ -294,6 +392,9 @@ enum aarch64_opnd_qualifier
|
||||
AARCH64_OPND_QLF_V_2D,
|
||||
AARCH64_OPND_QLF_V_1Q,
|
||||
|
||||
AARCH64_OPND_QLF_P_Z,
|
||||
AARCH64_OPND_QLF_P_M,
|
||||
|
||||
/* Constraint on value. */
|
||||
AARCH64_OPND_QLF_imm_0_7,
|
||||
AARCH64_OPND_QLF_imm_0_15,
|
||||
@@ -385,6 +486,18 @@ enum aarch64_insn_class
|
||||
movewide,
|
||||
pcreladdr,
|
||||
ic_system,
|
||||
sve_cpy,
|
||||
sve_index,
|
||||
sve_limm,
|
||||
sve_misc,
|
||||
sve_movprfx,
|
||||
sve_pred_zm,
|
||||
sve_shift_pred,
|
||||
sve_shift_unpred,
|
||||
sve_size_bhs,
|
||||
sve_size_bhsd,
|
||||
sve_size_hsd,
|
||||
sve_size_sd,
|
||||
testbranch,
|
||||
};
|
||||
|
||||
@@ -475,6 +588,18 @@ enum aarch64_op
|
||||
OP_UXTL,
|
||||
OP_UXTL2,
|
||||
|
||||
OP_MOV_P_P,
|
||||
OP_MOV_Z_P_Z,
|
||||
OP_MOV_Z_V,
|
||||
OP_MOV_Z_Z,
|
||||
OP_MOV_Z_Zi,
|
||||
OP_MOVM_P_P_P,
|
||||
OP_MOVS_P_P,
|
||||
OP_MOVZS_P_P_P,
|
||||
OP_MOVZ_P_P_P,
|
||||
OP_NOTS_P_P_P_Z,
|
||||
OP_NOT_P_P_P_Z,
|
||||
|
||||
OP_TOTAL_NUM, /* Pseudo. */
|
||||
};
|
||||
|
||||
@@ -539,6 +664,10 @@ struct aarch64_opcode
|
||||
/* Flags providing information about this instruction */
|
||||
uint32_t flags;
|
||||
|
||||
/* If nonzero, this operand and operand 0 are both registers and
|
||||
are required to have the same register number. */
|
||||
unsigned char tied_operand;
|
||||
|
||||
/* If non-NULL, a function to verify that a given instruction is valid. */
|
||||
bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
|
||||
};
|
||||
@@ -598,7 +727,9 @@ extern aarch64_opcode aarch64_opcode_table[];
|
||||
#define F_OD(X) (((X) & 0x7) << 24)
|
||||
/* Instruction has the field of 'sz'. */
|
||||
#define F_LSE_SZ (1 << 27)
|
||||
/* Next bit is 28. */
|
||||
/* Require an exact qualifier match, even for NIL qualifiers. */
|
||||
#define F_STRICT (1ULL << 28)
|
||||
/* Next bit is 29. */
|
||||
|
||||
static inline bfd_boolean
|
||||
alias_opcode_p (const aarch64_opcode *opcode)
|
||||
@@ -713,6 +844,8 @@ enum aarch64_modifier_kind
|
||||
AARCH64_MOD_SXTH,
|
||||
AARCH64_MOD_SXTW,
|
||||
AARCH64_MOD_SXTX,
|
||||
AARCH64_MOD_MUL,
|
||||
AARCH64_MOD_MUL_VL,
|
||||
};
|
||||
|
||||
bfd_boolean
|
||||
@@ -726,7 +859,7 @@ typedef struct
|
||||
{
|
||||
/* A list of names with the first one as the disassembly preference;
|
||||
terminated by NULL if fewer than 3. */
|
||||
const char *names[3];
|
||||
const char *names[4];
|
||||
aarch64_insn value;
|
||||
} aarch64_cond;
|
||||
|
||||
@@ -804,10 +937,10 @@ struct aarch64_opnd_info
|
||||
struct
|
||||
{
|
||||
enum aarch64_modifier_kind kind;
|
||||
int amount;
|
||||
unsigned operator_present: 1; /* Only valid during encoding. */
|
||||
/* Value of the 'S' field in ld/st reg offset; used only in decoding. */
|
||||
unsigned amount_present: 1;
|
||||
int64_t amount;
|
||||
} shifter;
|
||||
|
||||
unsigned skip:1; /* Operand is not completed if there is a fixup needed
|
||||
@@ -870,6 +1003,10 @@ typedef struct aarch64_inst aarch64_inst;
|
||||
No syntax error, but the operands are not a valid combination, e.g.
|
||||
FMOV D0,S0
|
||||
|
||||
AARCH64_OPDE_UNTIED_OPERAND
|
||||
The asm failed to use the same register for a destination operand
|
||||
and a tied source operand.
|
||||
|
||||
AARCH64_OPDE_OUT_OF_RANGE
|
||||
Error about some immediate value out of a valid range.
|
||||
|
||||
@@ -906,6 +1043,7 @@ enum aarch64_operand_error_kind
|
||||
AARCH64_OPDE_SYNTAX_ERROR,
|
||||
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
|
||||
AARCH64_OPDE_INVALID_VARIANT,
|
||||
AARCH64_OPDE_UNTIED_OPERAND,
|
||||
AARCH64_OPDE_OUT_OF_RANGE,
|
||||
AARCH64_OPDE_UNALIGNED,
|
||||
AARCH64_OPDE_REG_LIST,
|
||||
@@ -980,6 +1118,9 @@ aarch64_get_operand_name (enum aarch64_opnd);
|
||||
extern const char *
|
||||
aarch64_get_operand_desc (enum aarch64_opnd);
|
||||
|
||||
extern bfd_boolean
|
||||
aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
|
||||
|
||||
#ifdef DEBUG_AARCH64
|
||||
extern int debug_dump;
|
||||
|
||||
@@ -1002,6 +1143,9 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
|
||||
#define DEBUG_TRACE_IF(C, M, ...) ;
|
||||
#endif /* DEBUG_AARCH64 */
|
||||
|
||||
extern const char *const aarch64_sve_pattern_array[32];
|
||||
extern const char *const aarch64_sve_prfop_array[16];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -440,6 +440,125 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
|
||||
case 1131: /* sys */
|
||||
value = 1131; /* --> sys. */
|
||||
break;
|
||||
case 1881: /* bic */
|
||||
case 1186: /* and */
|
||||
value = 1186; /* --> and. */
|
||||
break;
|
||||
case 1169: /* mov */
|
||||
case 1188: /* and */
|
||||
value = 1188; /* --> and. */
|
||||
break;
|
||||
case 1173: /* movs */
|
||||
case 1189: /* ands */
|
||||
value = 1189; /* --> ands. */
|
||||
break;
|
||||
case 1882: /* cmple */
|
||||
case 1224: /* cmpge */
|
||||
value = 1224; /* --> cmpge. */
|
||||
break;
|
||||
case 1885: /* cmplt */
|
||||
case 1227: /* cmpgt */
|
||||
value = 1227; /* --> cmpgt. */
|
||||
break;
|
||||
case 1883: /* cmplo */
|
||||
case 1229: /* cmphi */
|
||||
value = 1229; /* --> cmphi. */
|
||||
break;
|
||||
case 1884: /* cmpls */
|
||||
case 1232: /* cmphs */
|
||||
value = 1232; /* --> cmphs. */
|
||||
break;
|
||||
case 1166: /* mov */
|
||||
case 1254: /* cpy */
|
||||
value = 1254; /* --> cpy. */
|
||||
break;
|
||||
case 1168: /* mov */
|
||||
case 1255: /* cpy */
|
||||
value = 1255; /* --> cpy. */
|
||||
break;
|
||||
case 1892: /* fmov */
|
||||
case 1171: /* mov */
|
||||
case 1256: /* cpy */
|
||||
value = 1256; /* --> cpy. */
|
||||
break;
|
||||
case 1161: /* mov */
|
||||
case 1268: /* dup */
|
||||
value = 1268; /* --> dup. */
|
||||
break;
|
||||
case 1163: /* mov */
|
||||
case 1160: /* mov */
|
||||
case 1269: /* dup */
|
||||
value = 1269; /* --> dup. */
|
||||
break;
|
||||
case 1891: /* fmov */
|
||||
case 1165: /* mov */
|
||||
case 1270: /* dup */
|
||||
value = 1270; /* --> dup. */
|
||||
break;
|
||||
case 1164: /* mov */
|
||||
case 1271: /* dupm */
|
||||
value = 1271; /* --> dupm. */
|
||||
break;
|
||||
case 1886: /* eon */
|
||||
case 1273: /* eor */
|
||||
value = 1273; /* --> eor. */
|
||||
break;
|
||||
case 1174: /* not */
|
||||
case 1275: /* eor */
|
||||
value = 1275; /* --> eor. */
|
||||
break;
|
||||
case 1175: /* nots */
|
||||
case 1276: /* eors */
|
||||
value = 1276; /* --> eors. */
|
||||
break;
|
||||
case 1887: /* facle */
|
||||
case 1281: /* facge */
|
||||
value = 1281; /* --> facge. */
|
||||
break;
|
||||
case 1888: /* faclt */
|
||||
case 1282: /* facgt */
|
||||
value = 1282; /* --> facgt. */
|
||||
break;
|
||||
case 1889: /* fcmle */
|
||||
case 1291: /* fcmge */
|
||||
value = 1291; /* --> fcmge. */
|
||||
break;
|
||||
case 1890: /* fcmlt */
|
||||
case 1293: /* fcmgt */
|
||||
value = 1293; /* --> fcmgt. */
|
||||
break;
|
||||
case 1158: /* fmov */
|
||||
case 1299: /* fcpy */
|
||||
value = 1299; /* --> fcpy. */
|
||||
break;
|
||||
case 1157: /* fmov */
|
||||
case 1316: /* fdup */
|
||||
value = 1316; /* --> fdup. */
|
||||
break;
|
||||
case 1159: /* mov */
|
||||
case 1614: /* orr */
|
||||
value = 1614; /* --> orr. */
|
||||
break;
|
||||
case 1893: /* orn */
|
||||
case 1615: /* orr */
|
||||
value = 1615; /* --> orr. */
|
||||
break;
|
||||
case 1162: /* mov */
|
||||
case 1617: /* orr */
|
||||
value = 1617; /* --> orr. */
|
||||
break;
|
||||
case 1172: /* movs */
|
||||
case 1618: /* orrs */
|
||||
value = 1618; /* --> orrs. */
|
||||
break;
|
||||
case 1167: /* mov */
|
||||
case 1674: /* sel */
|
||||
value = 1674; /* --> sel. */
|
||||
break;
|
||||
case 1170: /* mov */
|
||||
case 1675: /* sel */
|
||||
value = 1675; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
||||
@@ -480,6 +599,27 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 27:
|
||||
case 35:
|
||||
case 36:
|
||||
case 139:
|
||||
case 140:
|
||||
case 141:
|
||||
case 142:
|
||||
case 143:
|
||||
case 144:
|
||||
case 145:
|
||||
case 146:
|
||||
case 147:
|
||||
case 148:
|
||||
case 161:
|
||||
case 162:
|
||||
case 163:
|
||||
case 164:
|
||||
case 165:
|
||||
case 166:
|
||||
case 167:
|
||||
case 168:
|
||||
case 169:
|
||||
case 170:
|
||||
case 173:
|
||||
return aarch64_ins_regno (self, info, code, inst);
|
||||
case 12:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst);
|
||||
@@ -500,7 +640,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 34:
|
||||
return aarch64_ins_ldst_elemlist (self, info, code, inst);
|
||||
case 37:
|
||||
case 46:
|
||||
case 47:
|
||||
case 48:
|
||||
case 49:
|
||||
@@ -513,10 +652,21 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 56:
|
||||
case 57:
|
||||
case 58:
|
||||
case 67:
|
||||
case 59:
|
||||
case 68:
|
||||
case 69:
|
||||
case 70:
|
||||
case 71:
|
||||
case 136:
|
||||
case 138:
|
||||
case 153:
|
||||
case 154:
|
||||
case 155:
|
||||
case 156:
|
||||
case 157:
|
||||
case 158:
|
||||
case 159:
|
||||
case 160:
|
||||
return aarch64_ins_imm (self, info, code, inst);
|
||||
case 38:
|
||||
case 39:
|
||||
@@ -525,46 +675,124 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 41:
|
||||
case 42:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
|
||||
case 59:
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
case 46:
|
||||
case 129:
|
||||
return aarch64_ins_fpimm (self, info, code, inst);
|
||||
case 60:
|
||||
return aarch64_ins_aimm (self, info, code, inst);
|
||||
case 134:
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
case 61:
|
||||
return aarch64_ins_imm_half (self, info, code, inst);
|
||||
return aarch64_ins_aimm (self, info, code, inst);
|
||||
case 62:
|
||||
return aarch64_ins_imm_half (self, info, code, inst);
|
||||
case 63:
|
||||
return aarch64_ins_fbits (self, info, code, inst);
|
||||
case 64:
|
||||
case 65:
|
||||
case 66:
|
||||
return aarch64_ins_cond (self, info, code, inst);
|
||||
case 71:
|
||||
case 77:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst);
|
||||
case 72:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst);
|
||||
case 78:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst);
|
||||
case 73:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst);
|
||||
case 74:
|
||||
case 75:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst);
|
||||
case 76:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst);
|
||||
case 77:
|
||||
return aarch64_ins_addr_uimm12 (self, info, code, inst);
|
||||
case 78:
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst);
|
||||
case 79:
|
||||
return aarch64_ins_sysreg (self, info, code, inst);
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst);
|
||||
case 80:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst);
|
||||
return aarch64_ins_sysreg (self, info, code, inst);
|
||||
case 81:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst);
|
||||
case 82:
|
||||
case 83:
|
||||
case 84:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst);
|
||||
case 85:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst);
|
||||
case 86:
|
||||
return aarch64_ins_barrier (self, info, code, inst);
|
||||
case 87:
|
||||
return aarch64_ins_prfop (self, info, code, inst);
|
||||
return aarch64_ins_barrier (self, info, code, inst);
|
||||
case 88:
|
||||
return aarch64_ins_prfop (self, info, code, inst);
|
||||
case 89:
|
||||
return aarch64_ins_hint (self, info, code, inst);
|
||||
case 90:
|
||||
case 91:
|
||||
case 92:
|
||||
case 93:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
|
||||
case 94:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
|
||||
case 95:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
|
||||
case 96:
|
||||
case 97:
|
||||
case 98:
|
||||
case 99:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
||||
case 100:
|
||||
case 101:
|
||||
case 102:
|
||||
case 103:
|
||||
case 104:
|
||||
case 105:
|
||||
case 106:
|
||||
case 107:
|
||||
case 108:
|
||||
case 109:
|
||||
case 110:
|
||||
case 111:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
||||
case 112:
|
||||
case 113:
|
||||
case 114:
|
||||
case 115:
|
||||
case 116:
|
||||
case 117:
|
||||
case 118:
|
||||
case 119:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
||||
case 120:
|
||||
case 121:
|
||||
case 122:
|
||||
case 123:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
||||
case 124:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
||||
case 125:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
||||
case 126:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
||||
case 127:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
case 128:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst);
|
||||
case 130:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst);
|
||||
case 131:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst);
|
||||
case 132:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
|
||||
case 133:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst);
|
||||
case 135:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst);
|
||||
case 137:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst);
|
||||
case 149:
|
||||
case 150:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst);
|
||||
case 151:
|
||||
case 152:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst);
|
||||
case 171:
|
||||
return aarch64_ins_sve_index (self, info, code, inst);
|
||||
case 172:
|
||||
case 174:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
}
|
||||
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
#include "sysdep.h"
|
||||
#include <stdarg.h>
|
||||
#include "libiberty.h"
|
||||
#include "aarch64-asm.h"
|
||||
|
||||
/* Utilities. */
|
||||
@@ -55,6 +56,25 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
|
||||
va_end (va);
|
||||
}
|
||||
|
||||
/* Insert a raw field value VALUE into all fields in SELF->fields.
|
||||
The least significant bit goes in the final field. */
|
||||
|
||||
static void
|
||||
insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
|
||||
aarch64_insn value)
|
||||
{
|
||||
unsigned int i;
|
||||
enum aarch64_field_kind kind;
|
||||
|
||||
for (i = ARRAY_SIZE (self->fields); i-- > 0; )
|
||||
if (self->fields[i] != FLD_NIL)
|
||||
{
|
||||
kind = self->fields[i];
|
||||
insert_field (kind, code, value, 0);
|
||||
value >>= fields[kind].width;
|
||||
}
|
||||
}
|
||||
|
||||
/* Operand inserters. */
|
||||
|
||||
/* Insert register number. */
|
||||
@@ -318,17 +338,11 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int64_t imm;
|
||||
/* Maximum of two fields to insert. */
|
||||
assert (self->fields[2] == FLD_NIL);
|
||||
|
||||
imm = info->imm.value;
|
||||
if (operand_need_shift_by_two (self))
|
||||
imm >>= 2;
|
||||
if (self->fields[1] == FLD_NIL)
|
||||
insert_field (self->fields[0], code, imm, 0);
|
||||
else
|
||||
/* e.g. TBZ b5:b40. */
|
||||
insert_fields (code, imm, 0, 2, self->fields[1], self->fields[0]);
|
||||
insert_all_fields (self, code, imm);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -403,6 +417,16 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert fields for an 8-bit floating-point immediate. */
|
||||
const char *
|
||||
aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_all_fields (self, code, info->imm.value);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert #<fbits> for the immediate operand in fp fix-point instructions,
|
||||
e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
|
||||
const char *
|
||||
@@ -428,19 +452,20 @@ aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert logical/bitmask immediate for e.g. the last operand in
|
||||
ORR <Wd|WSP>, <Wn>, #<imm>. */
|
||||
const char *
|
||||
aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
/* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether
|
||||
the operand should be inverted before encoding. */
|
||||
static const char *
|
||||
aarch64_ins_limm_1 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst, bfd_boolean invert_p)
|
||||
{
|
||||
aarch64_insn value;
|
||||
uint64_t imm = info->imm.value;
|
||||
int is32 = aarch64_get_qualifier_esize (inst->operands[0].qualifier) == 4;
|
||||
int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
|
||||
|
||||
if (inst->opcode->op == OP_BIC)
|
||||
if (invert_p)
|
||||
imm = ~imm;
|
||||
if (aarch64_logical_immediate_p (imm, is32, &value) == FALSE)
|
||||
if (aarch64_logical_immediate_p (imm, esize, &value) == FALSE)
|
||||
/* The constraint check should have guaranteed this wouldn't happen. */
|
||||
assert (0);
|
||||
|
||||
@@ -449,6 +474,25 @@ aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Insert logical/bitmask immediate for e.g. the last operand in
|
||||
ORR <Wd|WSP>, <Wn>, #<imm>. */
|
||||
const char *
|
||||
aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
aarch64_insn *code, const aarch64_inst *inst)
|
||||
{
|
||||
return aarch64_ins_limm_1 (self, info, code, inst,
|
||||
inst->opcode->op == OP_BIC);
|
||||
}
|
||||
|
||||
/* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */
|
||||
const char *
|
||||
aarch64_ins_inv_limm (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
return aarch64_ins_limm_1 (self, info, code, inst, TRUE);
|
||||
}
|
||||
|
||||
/* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
|
||||
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
|
||||
const char *
|
||||
@@ -721,6 +765,314 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
|
||||
where <simm4> is a 4-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm4> is encoded in the SVE_imm4 field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 + get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
|
||||
where <simm6> is a 6-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm6> is encoded in the SVE_imm6 field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 + get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
|
||||
where <simm9> is a 9-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
|
||||
and imm3 fields, with imm3 being the less-significant part. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 + get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_fields (code, info->addr.offset.imm / factor, 0,
|
||||
2, FLD_imm3, FLD_SVE_imm6);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
|
||||
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 << get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
|
||||
is SELF's operand-dependent value. fields[0] specifies the base
|
||||
register field and fields[1] specifies the offset register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (self->fields[1], code, info->addr.offset.regno, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
|
||||
<shift> is SELF's operand-dependent value. fields[0] specifies the
|
||||
base register field, fields[1] specifies the offset register field and
|
||||
fields[2] is a single-bit field that selects SXTW over UXTW. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (self->fields[1], code, info->addr.offset.regno, 0);
|
||||
if (info->shifter.kind == AARCH64_MOD_UXTW)
|
||||
insert_field (self->fields[2], code, 0, 0);
|
||||
else
|
||||
insert_field (self->fields[2], code, 1, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
|
||||
5-bit unsigned number and where <shift> is SELF's operand-dependent value.
|
||||
fields[0] specifies the base register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int factor = 1 << get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
|
||||
where <modifier> is fixed by the instruction and where <msz> is a
|
||||
2-bit unsigned number. fields[0] specifies the base register field
|
||||
and fields[1] specifies the offset register field. */
|
||||
static const char *
|
||||
aarch64_ext_sve_addr_zz (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code)
|
||||
{
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
insert_field (self->fields[1], code, info->addr.offset.regno, 0);
|
||||
insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code);
|
||||
}
|
||||
|
||||
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code);
|
||||
}
|
||||
|
||||
/* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
const char *
|
||||
aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code);
|
||||
}
|
||||
|
||||
/* Encode an SVE ADD/SUB immediate. */
|
||||
const char *
|
||||
aarch64_ins_sve_aimm (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (info->shifter.amount == 8)
|
||||
insert_all_fields (self, code, (info->imm.value & 0xff) | 256);
|
||||
else if (info->imm.value != 0 && (info->imm.value & 0xff) == 0)
|
||||
insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256);
|
||||
else
|
||||
insert_all_fields (self, code, info->imm.value & 0xff);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE CPY/DUP immediate. */
|
||||
const char *
|
||||
aarch64_ins_sve_asimm (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
}
|
||||
|
||||
/* Encode Zn[MM], where MM has a 7-bit triangular encoding. The fields
|
||||
array specifies which field to use for Zn. MM is encoded in the
|
||||
concatenation of imm5 and SVE_tszh, with imm5 being the less
|
||||
significant part. */
|
||||
const char *
|
||||
aarch64_ins_sve_index (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
|
||||
insert_field (self->fields[0], code, info->reglane.regno, 0);
|
||||
insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
|
||||
2, FLD_imm5, FLD_SVE_tszh);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */
|
||||
const char *
|
||||
aarch64_ins_sve_limm_mov (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
}
|
||||
|
||||
/* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
|
||||
to use for Zn. */
|
||||
const char *
|
||||
aarch64_ins_sve_reglist (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_field (self->fields[0], code, info->reglist.first_regno, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
|
||||
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
|
||||
field. */
|
||||
const char *
|
||||
aarch64_ins_sve_scale (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_all_fields (self, code, info->imm.value);
|
||||
insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE shift left immediate. */
|
||||
const char *
|
||||
aarch64_ins_sve_shlimm (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
const aarch64_opnd_info *prev_operand;
|
||||
unsigned int esize;
|
||||
|
||||
assert (info->idx > 0);
|
||||
prev_operand = &inst->operands[info->idx - 1];
|
||||
esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
|
||||
insert_all_fields (self, code, 8 * esize + info->imm.value);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode an SVE shift right immediate. */
|
||||
const char *
|
||||
aarch64_ins_sve_shrimm (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info, aarch64_insn *code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
const aarch64_opnd_info *prev_operand;
|
||||
unsigned int esize;
|
||||
|
||||
assert (info->idx > 0);
|
||||
prev_operand = &inst->operands[info->idx - 1];
|
||||
esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
|
||||
insert_all_fields (self, code, 16 * esize - info->imm.value);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode a single-bit immediate that selects between #0.5 and #1.0.
|
||||
The fields array specifies which field to use. */
|
||||
const char *
|
||||
aarch64_ins_sve_float_half_one (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (info->imm.value == 0x3f000000)
|
||||
insert_field (self->fields[0], code, 0, 0);
|
||||
else
|
||||
insert_field (self->fields[0], code, 1, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode a single-bit immediate that selects between #0.5 and #2.0.
|
||||
The fields array specifies which field to use. */
|
||||
const char *
|
||||
aarch64_ins_sve_float_half_two (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (info->imm.value == 0x3f000000)
|
||||
insert_field (self->fields[0], code, 0, 0);
|
||||
else
|
||||
insert_field (self->fields[0], code, 1, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode a single-bit immediate that selects between #0.0 and #1.0.
|
||||
The fields array specifies which field to use. */
|
||||
const char *
|
||||
aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (info->imm.value == 0)
|
||||
insert_field (self->fields[0], code, 0, 0);
|
||||
else
|
||||
insert_field (self->fields[0], code, 1, 0);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Miscellaneous encoding functions. */
|
||||
|
||||
/* Encode size[0], i.e. bit 22, for
|
||||
@@ -788,12 +1140,35 @@ encode_fcvt (aarch64_inst *inst)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Return the index in qualifiers_list that INST is using. Should only
|
||||
be called once the qualifiers are known to be valid. */
|
||||
|
||||
static int
|
||||
aarch64_get_variant (struct aarch64_inst *inst)
|
||||
{
|
||||
int i, nops, variant;
|
||||
|
||||
nops = aarch64_num_of_operands (inst->opcode);
|
||||
for (variant = 0; variant < AARCH64_MAX_QLF_SEQ_NUM; ++variant)
|
||||
{
|
||||
for (i = 0; i < nops; ++i)
|
||||
if (inst->opcode->qualifiers_list[variant][i]
|
||||
!= inst->operands[i].qualifier)
|
||||
break;
|
||||
if (i == nops)
|
||||
return variant;
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Do miscellaneous encodings that are not common enough to be driven by
|
||||
flags. */
|
||||
|
||||
static void
|
||||
do_misc_encoding (aarch64_inst *inst)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
switch (inst->opcode->op)
|
||||
{
|
||||
case OP_FCVT:
|
||||
@@ -808,6 +1183,47 @@ do_misc_encoding (aarch64_inst *inst)
|
||||
case OP_FCVTXN_S:
|
||||
encode_asisd_fcvtxn (inst);
|
||||
break;
|
||||
case OP_MOV_P_P:
|
||||
case OP_MOVS_P_P:
|
||||
/* Copy Pn to Pm and Pg. */
|
||||
value = extract_field (FLD_SVE_Pn, inst->value, 0);
|
||||
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
|
||||
insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0);
|
||||
break;
|
||||
case OP_MOV_Z_P_Z:
|
||||
/* Copy Zd to Zm. */
|
||||
value = extract_field (FLD_SVE_Zd, inst->value, 0);
|
||||
insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
|
||||
break;
|
||||
case OP_MOV_Z_V:
|
||||
/* Fill in the zero immediate. */
|
||||
insert_field (FLD_SVE_tsz, &inst->value,
|
||||
1 << aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
case OP_MOV_Z_Z:
|
||||
/* Copy Zn to Zm. */
|
||||
value = extract_field (FLD_SVE_Zn, inst->value, 0);
|
||||
insert_field (FLD_SVE_Zm_16, &inst->value, value, 0);
|
||||
break;
|
||||
case OP_MOV_Z_Zi:
|
||||
break;
|
||||
case OP_MOVM_P_P_P:
|
||||
/* Copy Pd to Pm. */
|
||||
value = extract_field (FLD_SVE_Pd, inst->value, 0);
|
||||
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
|
||||
break;
|
||||
case OP_MOVZS_P_P_P:
|
||||
case OP_MOVZ_P_P_P:
|
||||
/* Copy Pn to Pm. */
|
||||
value = extract_field (FLD_SVE_Pn, inst->value, 0);
|
||||
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
|
||||
break;
|
||||
case OP_NOTS_P_P_P_Z:
|
||||
case OP_NOT_P_P_P_Z:
|
||||
/* Copy Pg to Pm. */
|
||||
value = extract_field (FLD_SVE_Pg4_10, inst->value, 0);
|
||||
insert_field (FLD_SVE_Pm, &inst->value, value, 0);
|
||||
break;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
@@ -966,6 +1382,65 @@ do_special_encoding (struct aarch64_inst *inst)
|
||||
DEBUG_TRACE ("exit with coding 0x%x", (uint32_t) inst->value);
|
||||
}
|
||||
|
||||
/* Some instructions (including all SVE ones) use the instruction class
|
||||
to describe how a qualifiers_list index is represented in the instruction
|
||||
encoding. If INST is such an instruction, encode the chosen qualifier
|
||||
variant. */
|
||||
|
||||
static void
|
||||
aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
|
||||
{
|
||||
switch (inst->opcode->iclass)
|
||||
{
|
||||
case sve_cpy:
|
||||
insert_fields (&inst->value, aarch64_get_variant (inst),
|
||||
0, 2, FLD_SVE_M_14, FLD_size);
|
||||
break;
|
||||
|
||||
case sve_index:
|
||||
case sve_shift_pred:
|
||||
case sve_shift_unpred:
|
||||
/* For indices and shift amounts, the variant is encoded as
|
||||
part of the immediate. */
|
||||
break;
|
||||
|
||||
case sve_limm:
|
||||
/* For sve_limm, the .B, .H, and .S forms are just a convenience
|
||||
and depend on the immediate. They don't have a separate
|
||||
encoding. */
|
||||
break;
|
||||
|
||||
case sve_misc:
|
||||
/* sve_misc instructions have only a single variant. */
|
||||
break;
|
||||
|
||||
case sve_movprfx:
|
||||
insert_fields (&inst->value, aarch64_get_variant (inst),
|
||||
0, 2, FLD_SVE_M_16, FLD_size);
|
||||
break;
|
||||
|
||||
case sve_pred_zm:
|
||||
insert_field (FLD_SVE_M_4, &inst->value, aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
case sve_size_bhs:
|
||||
case sve_size_bhsd:
|
||||
insert_field (FLD_size, &inst->value, aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
case sve_size_hsd:
|
||||
insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
|
||||
break;
|
||||
|
||||
case sve_size_sd:
|
||||
insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Converters converting an alias opcode instruction to its real form. */
|
||||
|
||||
/* ROR <Wd>, <Ws>, #<shift>
|
||||
@@ -1334,6 +1809,10 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
|
||||
if (opcode_has_special_coder (opcode))
|
||||
do_special_encoding (inst);
|
||||
|
||||
/* Possibly use the instruction class to encode the chosen qualifier
|
||||
variant. */
|
||||
aarch64_encode_variant_using_iclass (inst);
|
||||
|
||||
encoding_exit:
|
||||
DEBUG_TRACE ("exit with %s", opcode->name);
|
||||
|
||||
|
||||
@@ -50,9 +50,11 @@ AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_half);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_fpimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_fbits);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_aimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_limm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_ft);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
|
||||
@@ -68,6 +70,27 @@ AARCH64_DECL_OPD_INSERTER (ins_hint);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_prfop);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
|
||||
|
||||
#undef AARCH64_DECL_OPD_INSERTER
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -123,7 +123,7 @@ parse_aarch64_dis_options (const char *options)
|
||||
is encoded in H:L:M in some cases, the fields H:L:M should be passed in
|
||||
the order of H, L, M. */
|
||||
|
||||
static inline aarch64_insn
|
||||
aarch64_insn
|
||||
extract_fields (aarch64_insn code, aarch64_insn mask, ...)
|
||||
{
|
||||
uint32_t num;
|
||||
@@ -145,6 +145,26 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...)
|
||||
return value;
|
||||
}
|
||||
|
||||
/* Extract the value of all fields in SELF->fields from instruction CODE.
|
||||
The least significant bit comes from the final field. */
|
||||
|
||||
static aarch64_insn
|
||||
extract_all_fields (const aarch64_operand *self, aarch64_insn code)
|
||||
{
|
||||
aarch64_insn value;
|
||||
unsigned int i;
|
||||
enum aarch64_field_kind kind;
|
||||
|
||||
value = 0;
|
||||
for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
|
||||
{
|
||||
kind = self->fields[i];
|
||||
value <<= fields[kind].width;
|
||||
value |= extract_field (kind, code, 0);
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
/* Sign-extend bit I of VALUE. */
|
||||
static inline int32_t
|
||||
sign_extend (aarch64_insn value, unsigned i)
|
||||
@@ -575,17 +595,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int64_t imm;
|
||||
/* Maximum of two fields to extract. */
|
||||
assert (self->fields[2] == FLD_NIL);
|
||||
|
||||
if (self->fields[1] == FLD_NIL)
|
||||
imm = extract_field (self->fields[0], code, 0);
|
||||
else
|
||||
/* e.g. TBZ b5:b40. */
|
||||
imm = extract_fields (code, 0, 2, self->fields[0], self->fields[1]);
|
||||
|
||||
if (info->type == AARCH64_OPND_FPIMM)
|
||||
info->imm.is_fp = 1;
|
||||
imm = extract_all_fields (self, code);
|
||||
|
||||
if (operand_need_sign_extension (self))
|
||||
imm = sign_extend (imm, get_operand_fields_width (self) - 1);
|
||||
@@ -681,6 +692,17 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an 8-bit floating-point immediate. */
|
||||
int
|
||||
aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
info->imm.value = extract_all_fields (self, code);
|
||||
info->imm.is_fp = 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
|
||||
int
|
||||
aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
@@ -712,32 +734,21 @@ aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
|
||||
|
||||
int
|
||||
aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
/* Return true if VALUE is a valid logical immediate encoding, storing the
|
||||
decoded value in *RESULT if so. ESIZE is the number of bytes in the
|
||||
decoded immediate. */
|
||||
static int
|
||||
decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
|
||||
{
|
||||
uint64_t imm, mask;
|
||||
uint32_t sf;
|
||||
uint32_t N, R, S;
|
||||
unsigned simd_size;
|
||||
aarch64_insn value;
|
||||
|
||||
value = extract_fields (code, 0, 3, FLD_N, FLD_immr, FLD_imms);
|
||||
assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_W
|
||||
|| inst->operands[0].qualifier == AARCH64_OPND_QLF_X);
|
||||
sf = aarch64_get_qualifier_esize (inst->operands[0].qualifier) != 4;
|
||||
|
||||
/* value is N:immr:imms. */
|
||||
S = value & 0x3f;
|
||||
R = (value >> 6) & 0x3f;
|
||||
N = (value >> 12) & 0x1;
|
||||
|
||||
if (sf == 0 && N == 1)
|
||||
return 0;
|
||||
|
||||
/* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
|
||||
(in other words, right rotated by R), then replicated. */
|
||||
if (N != 0)
|
||||
@@ -760,6 +771,10 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
/* Top bits are IGNORED. */
|
||||
R &= simd_size - 1;
|
||||
}
|
||||
|
||||
if (simd_size > esize * 8)
|
||||
return 0;
|
||||
|
||||
/* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
|
||||
if (S == simd_size - 1)
|
||||
return 0;
|
||||
@@ -781,11 +796,38 @@ aarch64_ext_limm (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
default: assert (0); return 0;
|
||||
}
|
||||
|
||||
info->imm.value = sf ? imm : imm & 0xffffffff;
|
||||
*result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
|
||||
int
|
||||
aarch64_ext_limm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
uint32_t esize;
|
||||
aarch64_insn value;
|
||||
|
||||
value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
|
||||
self->fields[2]);
|
||||
esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
|
||||
return decode_limm (esize, value, &info->imm.value);
|
||||
}
|
||||
|
||||
/* Decode a logical immediate for the BIC alias of AND (etc.). */
|
||||
int
|
||||
aarch64_ext_inv_limm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
if (!aarch64_ext_limm (self, info, code, inst))
|
||||
return 0;
|
||||
info->imm.value = ~info->imm.value;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
|
||||
or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
|
||||
int
|
||||
@@ -1163,6 +1205,413 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
|
||||
where <offset> is given by the OFFSET parameter and where <factor> is
|
||||
1 plus SELF's operand-dependent value. fields[0] specifies the field
|
||||
that holds <base>. */
|
||||
static int
|
||||
aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
int64_t offset)
|
||||
{
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
|
||||
info->addr.offset.is_reg = FALSE;
|
||||
info->addr.writeback = FALSE;
|
||||
info->addr.preind = TRUE;
|
||||
if (offset != 0)
|
||||
info->shifter.kind = AARCH64_MOD_MUL_VL;
|
||||
info->shifter.amount = 1;
|
||||
info->shifter.operator_present = (info->addr.offset.imm != 0);
|
||||
info->shifter.amount_present = FALSE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
|
||||
where <simm4> is a 4-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm4> is encoded in the SVE_imm4 field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = extract_field (FLD_SVE_imm4, code, 0);
|
||||
offset = ((offset + 8) & 15) - 8;
|
||||
return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
|
||||
where <simm6> is a 6-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm6> is encoded in the SVE_imm6 field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = extract_field (FLD_SVE_imm6, code, 0);
|
||||
offset = (((offset + 32) & 63) - 32);
|
||||
return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
|
||||
where <simm9> is a 9-bit signed value and where <factor> is 1 plus
|
||||
SELF's operand-dependent value. fields[0] specifies the field that
|
||||
holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
|
||||
and imm3 fields, with imm3 being the less-significant part. */
|
||||
int
|
||||
aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info,
|
||||
aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset;
|
||||
|
||||
offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
|
||||
offset = (((offset + 256) & 511) - 256);
|
||||
return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
|
||||
is given by the OFFSET parameter and where <shift> is SELF's operand-
|
||||
dependent value. fields[0] specifies the base register field <base>. */
|
||||
static int
|
||||
aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
int64_t offset)
|
||||
{
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
|
||||
info->addr.offset.is_reg = FALSE;
|
||||
info->addr.writeback = FALSE;
|
||||
info->addr.preind = TRUE;
|
||||
info->shifter.operator_present = FALSE;
|
||||
info->shifter.amount_present = FALSE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
|
||||
is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
|
||||
value. fields[0] specifies the base register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset = extract_field (FLD_SVE_imm6, code, 0);
|
||||
return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
|
||||
is SELF's operand-dependent value. fields[0] specifies the base
|
||||
register field and fields[1] specifies the offset register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int index;
|
||||
|
||||
index = extract_field (self->fields[1], code, 0);
|
||||
if (index == 31 && (self->flags & OPD_F_NO_ZR) != 0)
|
||||
return 0;
|
||||
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.regno = index;
|
||||
info->addr.offset.is_reg = TRUE;
|
||||
info->addr.writeback = FALSE;
|
||||
info->addr.preind = TRUE;
|
||||
info->shifter.kind = AARCH64_MOD_LSL;
|
||||
info->shifter.amount = get_operand_specific_data (self);
|
||||
info->shifter.operator_present = (info->shifter.amount != 0);
|
||||
info->shifter.amount_present = (info->shifter.amount != 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
|
||||
<shift> is SELF's operand-dependent value. fields[0] specifies the
|
||||
base register field, fields[1] specifies the offset register field and
|
||||
fields[2] is a single-bit field that selects SXTW over UXTW. */
|
||||
int
|
||||
aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.regno = extract_field (self->fields[1], code, 0);
|
||||
info->addr.offset.is_reg = TRUE;
|
||||
info->addr.writeback = FALSE;
|
||||
info->addr.preind = TRUE;
|
||||
if (extract_field (self->fields[2], code, 0))
|
||||
info->shifter.kind = AARCH64_MOD_SXTW;
|
||||
else
|
||||
info->shifter.kind = AARCH64_MOD_UXTW;
|
||||
info->shifter.amount = get_operand_specific_data (self);
|
||||
info->shifter.operator_present = TRUE;
|
||||
info->shifter.amount_present = (info->shifter.amount != 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
|
||||
5-bit unsigned number and where <shift> is SELF's operand-dependent value.
|
||||
fields[0] specifies the base register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int offset = extract_field (FLD_imm5, code, 0);
|
||||
return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
|
||||
where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
|
||||
number. fields[0] specifies the base register field and fields[1]
|
||||
specifies the offset register field. */
|
||||
static int
|
||||
aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
aarch64_insn code, enum aarch64_modifier_kind kind)
|
||||
{
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
info->addr.offset.regno = extract_field (self->fields[1], code, 0);
|
||||
info->addr.offset.is_reg = TRUE;
|
||||
info->addr.writeback = FALSE;
|
||||
info->addr.preind = TRUE;
|
||||
info->shifter.kind = kind;
|
||||
info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
|
||||
info->shifter.operator_present = (kind != AARCH64_MOD_LSL
|
||||
|| info->shifter.amount != 0);
|
||||
info->shifter.amount_present = (info->shifter.amount != 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
|
||||
}
|
||||
|
||||
/* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
|
||||
<msz> is a 2-bit unsigned number. fields[0] specifies the base register
|
||||
field and fields[1] specifies the offset register field. */
|
||||
int
|
||||
aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
|
||||
}
|
||||
|
||||
/* Finish decoding an SVE arithmetic immediate, given that INFO already
|
||||
has the raw field value and that the low 8 bits decode to VALUE. */
|
||||
static int
|
||||
decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
|
||||
{
|
||||
info->shifter.kind = AARCH64_MOD_LSL;
|
||||
info->shifter.amount = 0;
|
||||
if (info->imm.value & 0x100)
|
||||
{
|
||||
if (value == 0)
|
||||
/* Decode 0x100 as #0, LSL #8. */
|
||||
info->shifter.amount = 8;
|
||||
else
|
||||
value *= 256;
|
||||
}
|
||||
info->shifter.operator_present = (info->shifter.amount != 0);
|
||||
info->shifter.amount_present = (info->shifter.amount != 0);
|
||||
info->imm.value = value;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE ADD/SUB immediate. */
|
||||
int
|
||||
aarch64_ext_sve_aimm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
return (aarch64_ext_imm (self, info, code, inst)
|
||||
&& decode_sve_aimm (info, (uint8_t) info->imm.value));
|
||||
}
|
||||
|
||||
/* Decode an SVE CPY/DUP immediate. */
|
||||
int
|
||||
aarch64_ext_sve_asimm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
return (aarch64_ext_imm (self, info, code, inst)
|
||||
&& decode_sve_aimm (info, (int8_t) info->imm.value));
|
||||
}
|
||||
|
||||
/* Decode a single-bit immediate that selects between #0.5 and #1.0.
|
||||
The fields array specifies which field to use. */
|
||||
int
|
||||
aarch64_ext_sve_float_half_one (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (extract_field (self->fields[0], code, 0))
|
||||
info->imm.value = 0x3f800000;
|
||||
else
|
||||
info->imm.value = 0x3f000000;
|
||||
info->imm.is_fp = TRUE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode a single-bit immediate that selects between #0.5 and #2.0.
|
||||
The fields array specifies which field to use. */
|
||||
int
|
||||
aarch64_ext_sve_float_half_two (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (extract_field (self->fields[0], code, 0))
|
||||
info->imm.value = 0x40000000;
|
||||
else
|
||||
info->imm.value = 0x3f000000;
|
||||
info->imm.is_fp = TRUE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode a single-bit immediate that selects between #0.0 and #1.0.
|
||||
The fields array specifies which field to use. */
|
||||
int
|
||||
aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (extract_field (self->fields[0], code, 0))
|
||||
info->imm.value = 0x3f800000;
|
||||
else
|
||||
info->imm.value = 0x0;
|
||||
info->imm.is_fp = TRUE;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
|
||||
array specifies which field to use for Zn. MM is encoded in the
|
||||
concatenation of imm5 and SVE_tszh, with imm5 being the less
|
||||
significant part. */
|
||||
int
|
||||
aarch64_ext_sve_index (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int val;
|
||||
|
||||
info->reglane.regno = extract_field (self->fields[0], code, 0);
|
||||
val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
if ((val & 15) == 0)
|
||||
return 0;
|
||||
while ((val & 1) == 0)
|
||||
val /= 2;
|
||||
info->reglane.index = val / 2;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode a logical immediate for the MOV alias of SVE DUPM. */
|
||||
int
|
||||
aarch64_ext_sve_limm_mov (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
|
||||
return (aarch64_ext_limm (self, info, code, inst)
|
||||
&& aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
|
||||
}
|
||||
|
||||
/* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
|
||||
to use for Zn. The opcode-dependent value specifies the number
|
||||
of registers in the list. */
|
||||
int
|
||||
aarch64_ext_sve_reglist (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
info->reglist.first_regno = extract_field (self->fields[0], code, 0);
|
||||
info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
|
||||
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
|
||||
field. */
|
||||
int
|
||||
aarch64_ext_sve_scale (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (!aarch64_ext_imm (self, info, code, inst))
|
||||
return 0;
|
||||
val = extract_field (FLD_SVE_imm4, code, 0);
|
||||
info->shifter.kind = AARCH64_MOD_MUL;
|
||||
info->shifter.amount = val + 1;
|
||||
info->shifter.operator_present = (val != 0);
|
||||
info->shifter.amount_present = (val != 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Return the top set bit in VALUE, which is expected to be relatively
|
||||
small. */
|
||||
static uint64_t
|
||||
get_top_bit (uint64_t value)
|
||||
{
|
||||
while ((value & -value) != value)
|
||||
value -= value & -value;
|
||||
return value;
|
||||
}
|
||||
|
||||
/* Decode an SVE shift-left immediate. */
|
||||
int
|
||||
aarch64_ext_sve_shlimm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
if (!aarch64_ext_imm (self, info, code, inst)
|
||||
|| info->imm.value == 0)
|
||||
return 0;
|
||||
|
||||
info->imm.value -= get_top_bit (info->imm.value);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode an SVE shift-right immediate. */
|
||||
int
|
||||
aarch64_ext_sve_shrimm (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, const aarch64_insn code,
|
||||
const aarch64_inst *inst)
|
||||
{
|
||||
if (!aarch64_ext_imm (self, info, code, inst)
|
||||
|| info->imm.value == 0)
|
||||
return 0;
|
||||
|
||||
info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Bitfields that are commonly used to encode certain operands' information
|
||||
may be partially used as part of the base opcode in some instructions.
|
||||
@@ -1362,17 +1811,59 @@ decode_fcvt (aarch64_inst *inst)
|
||||
static int
|
||||
do_misc_decoding (aarch64_inst *inst)
|
||||
{
|
||||
unsigned int value;
|
||||
switch (inst->opcode->op)
|
||||
{
|
||||
case OP_FCVT:
|
||||
return decode_fcvt (inst);
|
||||
|
||||
case OP_FCVTN:
|
||||
case OP_FCVTN2:
|
||||
case OP_FCVTL:
|
||||
case OP_FCVTL2:
|
||||
return decode_asimd_fcvt (inst);
|
||||
|
||||
case OP_FCVTXN_S:
|
||||
return decode_asisd_fcvtxn (inst);
|
||||
|
||||
case OP_MOV_P_P:
|
||||
case OP_MOVS_P_P:
|
||||
value = extract_field (FLD_SVE_Pn, inst->value, 0);
|
||||
return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
|
||||
&& value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
|
||||
|
||||
case OP_MOV_Z_P_Z:
|
||||
return (extract_field (FLD_SVE_Zd, inst->value, 0)
|
||||
== extract_field (FLD_SVE_Zm_16, inst->value, 0));
|
||||
|
||||
case OP_MOV_Z_V:
|
||||
/* Index must be zero. */
|
||||
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
return value == 1 || value == 2 || value == 4 || value == 8;
|
||||
|
||||
case OP_MOV_Z_Z:
|
||||
return (extract_field (FLD_SVE_Zn, inst->value, 0)
|
||||
== extract_field (FLD_SVE_Zm_16, inst->value, 0));
|
||||
|
||||
case OP_MOV_Z_Zi:
|
||||
/* Index must be nonzero. */
|
||||
value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
|
||||
return value != 1 && value != 2 && value != 4 && value != 8;
|
||||
|
||||
case OP_MOVM_P_P_P:
|
||||
return (extract_field (FLD_SVE_Pd, inst->value, 0)
|
||||
== extract_field (FLD_SVE_Pm, inst->value, 0));
|
||||
|
||||
case OP_MOVZS_P_P_P:
|
||||
case OP_MOVZ_P_P_P:
|
||||
return (extract_field (FLD_SVE_Pn, inst->value, 0)
|
||||
== extract_field (FLD_SVE_Pm, inst->value, 0));
|
||||
|
||||
case OP_NOTS_P_P_P_Z:
|
||||
case OP_NOT_P_P_P_Z:
|
||||
return (extract_field (FLD_SVE_Pm, inst->value, 0)
|
||||
== extract_field (FLD_SVE_Pg4_10, inst->value, 0));
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
@@ -1995,6 +2486,105 @@ determine_disassembling_preference (struct aarch64_inst *inst)
|
||||
}
|
||||
}
|
||||
|
||||
/* Some instructions (including all SVE ones) use the instruction class
|
||||
to describe how a qualifiers_list index is represented in the instruction
|
||||
encoding. If INST is such an instruction, decode the appropriate fields
|
||||
and fill in the operand qualifiers accordingly. Return true if no
|
||||
problems are found. */
|
||||
|
||||
static bfd_boolean
|
||||
aarch64_decode_variant_using_iclass (aarch64_inst *inst)
|
||||
{
|
||||
int i, variant;
|
||||
|
||||
variant = 0;
|
||||
switch (inst->opcode->iclass)
|
||||
{
|
||||
case sve_cpy:
|
||||
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
|
||||
break;
|
||||
|
||||
case sve_index:
|
||||
i = extract_field (FLD_SVE_tsz, inst->value, 0);
|
||||
if (i == 0)
|
||||
return FALSE;
|
||||
while ((i & 1) == 0)
|
||||
{
|
||||
i >>= 1;
|
||||
variant += 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case sve_limm:
|
||||
/* Pick the smallest applicable element size. */
|
||||
if ((inst->value & 0x20600) == 0x600)
|
||||
variant = 0;
|
||||
else if ((inst->value & 0x20400) == 0x400)
|
||||
variant = 1;
|
||||
else if ((inst->value & 0x20000) == 0)
|
||||
variant = 2;
|
||||
else
|
||||
variant = 3;
|
||||
break;
|
||||
|
||||
case sve_misc:
|
||||
/* sve_misc instructions have only a single variant. */
|
||||
break;
|
||||
|
||||
case sve_movprfx:
|
||||
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16);
|
||||
break;
|
||||
|
||||
case sve_pred_zm:
|
||||
variant = extract_field (FLD_SVE_M_4, inst->value, 0);
|
||||
break;
|
||||
|
||||
case sve_shift_pred:
|
||||
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
|
||||
sve_shift:
|
||||
if (i == 0)
|
||||
return FALSE;
|
||||
while (i != 1)
|
||||
{
|
||||
i >>= 1;
|
||||
variant += 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case sve_shift_unpred:
|
||||
i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
|
||||
goto sve_shift;
|
||||
|
||||
case sve_size_bhs:
|
||||
variant = extract_field (FLD_size, inst->value, 0);
|
||||
if (variant >= 3)
|
||||
return FALSE;
|
||||
break;
|
||||
|
||||
case sve_size_bhsd:
|
||||
variant = extract_field (FLD_size, inst->value, 0);
|
||||
break;
|
||||
|
||||
case sve_size_hsd:
|
||||
i = extract_field (FLD_size, inst->value, 0);
|
||||
if (i < 1)
|
||||
return FALSE;
|
||||
variant = i - 1;
|
||||
break;
|
||||
|
||||
case sve_size_sd:
|
||||
variant = extract_field (FLD_SVE_sz, inst->value, 0);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* No mapping between instruction class and qualifiers. */
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
|
||||
inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
|
||||
return TRUE;
|
||||
}
|
||||
/* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
|
||||
fails, which meanes that CODE is not an instruction of OPCODE; otherwise
|
||||
return 1.
|
||||
@@ -2042,6 +2632,14 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
|
||||
goto decode_fail;
|
||||
}
|
||||
|
||||
/* Possibly use the instruction class to determine the correct
|
||||
qualifier. */
|
||||
if (!aarch64_decode_variant_using_iclass (inst))
|
||||
{
|
||||
DEBUG_TRACE ("iclass-based decoder FAIL");
|
||||
goto decode_fail;
|
||||
}
|
||||
|
||||
/* Call operand decoders. */
|
||||
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
|
||||
{
|
||||
@@ -2189,6 +2787,22 @@ print_operands (bfd_vma pc, const aarch64_opcode *opcode,
|
||||
}
|
||||
}
|
||||
|
||||
/* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
|
||||
|
||||
static void
|
||||
remove_dot_suffix (char *name, const aarch64_inst *inst)
|
||||
{
|
||||
char *ptr;
|
||||
size_t len;
|
||||
|
||||
ptr = strchr (inst->opcode->name, '.');
|
||||
assert (ptr && inst->cond);
|
||||
len = ptr - inst->opcode->name;
|
||||
assert (len < 8);
|
||||
strncpy (name, inst->opcode->name, len);
|
||||
name[len] = '\0';
|
||||
}
|
||||
|
||||
/* Print the instruction mnemonic name. */
|
||||
|
||||
static void
|
||||
@@ -2199,21 +2813,35 @@ print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
|
||||
/* For instructions that are truly conditionally executed, e.g. b.cond,
|
||||
prepare the full mnemonic name with the corresponding condition
|
||||
suffix. */
|
||||
char name[8], *ptr;
|
||||
size_t len;
|
||||
char name[8];
|
||||
|
||||
ptr = strchr (inst->opcode->name, '.');
|
||||
assert (ptr && inst->cond);
|
||||
len = ptr - inst->opcode->name;
|
||||
assert (len < 8);
|
||||
strncpy (name, inst->opcode->name, len);
|
||||
name [len] = '\0';
|
||||
remove_dot_suffix (name, inst);
|
||||
(*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
|
||||
}
|
||||
|
||||
/* Decide whether we need to print a comment after the operands of
|
||||
instruction INST. */
|
||||
|
||||
static void
|
||||
print_comment (const aarch64_inst *inst, struct disassemble_info *info)
|
||||
{
|
||||
if (inst->opcode->flags & F_COND)
|
||||
{
|
||||
char name[8];
|
||||
unsigned int i, num_conds;
|
||||
|
||||
remove_dot_suffix (name, inst);
|
||||
num_conds = ARRAY_SIZE (inst->cond->names);
|
||||
for (i = 1; i < num_conds && inst->cond->names[i]; ++i)
|
||||
(*info->fprintf_func) (info->stream, "%s %s.%s",
|
||||
i == 1 ? " //" : ",",
|
||||
name, inst->cond->names[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Print the instruction according to *INST. */
|
||||
|
||||
static void
|
||||
@@ -2222,6 +2850,7 @@ print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
|
||||
{
|
||||
print_mnemonic_name (inst, info);
|
||||
print_operands (pc, inst->opcode, inst->operands, info);
|
||||
print_comment (inst, info);
|
||||
}
|
||||
|
||||
/* Entry-point of the instruction disassembler and printer. */
|
||||
|
||||
@@ -72,9 +72,11 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_fpimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
|
||||
@@ -90,6 +92,27 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_u6);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rr_lsl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rz_xtw);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zi_u5);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
|
||||
|
||||
#undef AARCH64_DECL_OPD_EXTRACTOR
|
||||
|
||||
|
||||
@@ -378,13 +378,9 @@ initialize_decoder_tree (void)
|
||||
static void __attribute__ ((format (printf, 2, 3)))
|
||||
indented_print (unsigned int indent, const char *format, ...)
|
||||
{
|
||||
/* 80 number of spaces pluc a NULL terminator. */
|
||||
static const char spaces[81] =
|
||||
" ";
|
||||
va_list ap;
|
||||
va_start (ap, format);
|
||||
assert (indent <= 80);
|
||||
printf ("%s", &spaces[80 - indent]);
|
||||
printf ("%*s", indent, "");
|
||||
vprintf (format, ap);
|
||||
va_end (ap);
|
||||
}
|
||||
|
||||
@@ -82,6 +82,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"},
|
||||
@@ -113,6 +114,91 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
|
||||
};
|
||||
|
||||
@@ -190,6 +276,17 @@ static const unsigned op_enum_table [] =
|
||||
382,
|
||||
404,
|
||||
406,
|
||||
1162,
|
||||
1167,
|
||||
1160,
|
||||
1159,
|
||||
1163,
|
||||
1170,
|
||||
1172,
|
||||
1173,
|
||||
1169,
|
||||
1175,
|
||||
1174,
|
||||
};
|
||||
|
||||
/* Given the opcode enumerator OP, return the pointer to the corresponding
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -91,6 +91,51 @@ enum aarch64_field_kind
|
||||
FLD_b5,
|
||||
FLD_b40,
|
||||
FLD_scale,
|
||||
FLD_SVE_M_4,
|
||||
FLD_SVE_M_14,
|
||||
FLD_SVE_M_16,
|
||||
FLD_SVE_N,
|
||||
FLD_SVE_Pd,
|
||||
FLD_SVE_Pg3,
|
||||
FLD_SVE_Pg4_5,
|
||||
FLD_SVE_Pg4_10,
|
||||
FLD_SVE_Pg4_16,
|
||||
FLD_SVE_Pm,
|
||||
FLD_SVE_Pn,
|
||||
FLD_SVE_Pt,
|
||||
FLD_SVE_Rm,
|
||||
FLD_SVE_Rn,
|
||||
FLD_SVE_Vd,
|
||||
FLD_SVE_Vm,
|
||||
FLD_SVE_Vn,
|
||||
FLD_SVE_Za_5,
|
||||
FLD_SVE_Za_16,
|
||||
FLD_SVE_Zd,
|
||||
FLD_SVE_Zm_5,
|
||||
FLD_SVE_Zm_16,
|
||||
FLD_SVE_Zn,
|
||||
FLD_SVE_Zt,
|
||||
FLD_SVE_i1,
|
||||
FLD_SVE_imm3,
|
||||
FLD_SVE_imm4,
|
||||
FLD_SVE_imm5,
|
||||
FLD_SVE_imm5b,
|
||||
FLD_SVE_imm6,
|
||||
FLD_SVE_imm7,
|
||||
FLD_SVE_imm8,
|
||||
FLD_SVE_imm9,
|
||||
FLD_SVE_immr,
|
||||
FLD_SVE_imms,
|
||||
FLD_SVE_msz,
|
||||
FLD_SVE_pattern,
|
||||
FLD_SVE_prfop,
|
||||
FLD_SVE_sz,
|
||||
FLD_SVE_tsz,
|
||||
FLD_SVE_tszh,
|
||||
FLD_SVE_tszl_8,
|
||||
FLD_SVE_tszl_19,
|
||||
FLD_SVE_xs_14,
|
||||
FLD_SVE_xs_22,
|
||||
};
|
||||
|
||||
/* Field description. */
|
||||
@@ -137,6 +182,9 @@ extern const aarch64_operand aarch64_operands[];
|
||||
value by 2 to get the value
|
||||
of an immediate operand. */
|
||||
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
|
||||
#define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_LSB 5
|
||||
#define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */
|
||||
|
||||
static inline bfd_boolean
|
||||
operand_has_inserter (const aarch64_operand *operand)
|
||||
@@ -168,6 +216,13 @@ operand_maybe_stack_pointer (const aarch64_operand *operand)
|
||||
return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
/* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
|
||||
static inline unsigned int
|
||||
get_operand_specific_data (const aarch64_operand *operand)
|
||||
{
|
||||
return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
|
||||
}
|
||||
|
||||
/* Return the total width of the operand *OPERAND. */
|
||||
static inline unsigned
|
||||
get_operand_fields_width (const aarch64_operand *operand)
|
||||
@@ -278,6 +333,9 @@ extract_field (enum aarch64_field_kind kind, aarch64_insn code,
|
||||
{
|
||||
return extract_field_2 (&fields[kind], code, mask);
|
||||
}
|
||||
|
||||
extern aarch64_insn
|
||||
extract_fields (aarch64_insn code, aarch64_insn mask, ...);
|
||||
|
||||
/* Inline functions selecting operand to do the encoding/decoding for a
|
||||
certain instruction bit-field. */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user