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binutils-a
| Author | SHA1 | Date | |
|---|---|---|---|
|
0ee8d3c039 |
24
ChangeLog
24
ChangeLog
@@ -1,3 +1,27 @@
|
||||
2008-08-31 Aaron W. LaFramboise <aaronavay62@aaronwl.com>
|
||||
|
||||
* configure.ac (RPATH_ENVVAR): Use PATH on Windows.
|
||||
(GCC_SHLIB_SUBDIR): New.
|
||||
* Makefile.tpl (HOST_LIB_PATH_gcc): Use GCC_SHLIB_SUBDIR.
|
||||
* configure: Regenerate.
|
||||
* Makefile.in: Regenerate.
|
||||
|
||||
2008-08-28 Tristan Gingold <gingold@adacore.com>
|
||||
|
||||
* configure.ac (powerpc-*-darwin*, i?86-*-darwin*,x86_64-*-darwin9):
|
||||
Enable bfd, binutils and opcodes.
|
||||
* configure: Regenerate.
|
||||
|
||||
2008-08-16 Nicolas Roche <roche@adacore.com>
|
||||
|
||||
* Makefile.tpl: Add BOOT_ADAFLAGS.
|
||||
* Makefile.in: Regenerate.
|
||||
|
||||
2008-08-16 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* configure.ac (mips*-*-*linux*, mips*-*-gnu*): Use mt-mips-gnu.
|
||||
* configure: Regenerate.
|
||||
|
||||
2008-07-30 Paolo Bonzini <bonzini@gnu.org>
|
||||
|
||||
Sync with gcc:
|
||||
|
||||
@@ -105,6 +105,11 @@ GDB_NLM_DEPS =
|
||||
# the libraries.
|
||||
RPATH_ENVVAR = @RPATH_ENVVAR@
|
||||
|
||||
# On targets where RPATH_ENVVAR is PATH, a subdirectory of the GCC build path
|
||||
# is used instead of the directory itself to avoid including built
|
||||
# executables in PATH.
|
||||
GCC_SHLIB_SUBDIR = @GCC_SHLIB_SUBDIR@
|
||||
|
||||
# Build programs are put under this directory.
|
||||
BUILD_SUBDIR = @build_subdir@
|
||||
# This is set by the configure script to the arguments to use when configuring
|
||||
@@ -291,6 +296,7 @@ BUILD_PREFIX_1 = @BUILD_PREFIX_1@
|
||||
# here so that they can be overridden by Makefile fragments.
|
||||
BOOT_CFLAGS= -g -O2
|
||||
BOOT_LDFLAGS=
|
||||
BOOT_ADAFLAGS=-gnatpg -gnata
|
||||
|
||||
BISON = @BISON@
|
||||
YACC = @YACC@
|
||||
@@ -444,7 +450,7 @@ HOST_LIB_PATH = $(HOST_LIB_PATH_bfd)$(HOST_LIB_PATH_opcodes)$(HOST_LIB_PATH_gmp)
|
||||
|
||||
# Define HOST_LIB_PATH_gcc here, for the sake of TARGET_LIB_PATH, ouch
|
||||
@if gcc
|
||||
HOST_LIB_PATH_gcc = $$r/$(HOST_SUBDIR)/gcc:$$r/$(HOST_SUBDIR)/prev-gcc:
|
||||
HOST_LIB_PATH_gcc = $$r/$(HOST_SUBDIR)/gcc$(GCC_SHLIB_SUBDIR):$$r/$(HOST_SUBDIR)/prev-gcc$(GCC_SHLIB_SUBDIR):
|
||||
@endif gcc
|
||||
|
||||
|
||||
|
||||
@@ -108,6 +108,11 @@ GDB_NLM_DEPS =
|
||||
# the libraries.
|
||||
RPATH_ENVVAR = @RPATH_ENVVAR@
|
||||
|
||||
# On targets where RPATH_ENVVAR is PATH, a subdirectory of the GCC build path
|
||||
# is used instead of the directory itself to avoid including built
|
||||
# executables in PATH.
|
||||
GCC_SHLIB_SUBDIR = @GCC_SHLIB_SUBDIR@
|
||||
|
||||
# Build programs are put under this directory.
|
||||
BUILD_SUBDIR = @build_subdir@
|
||||
# This is set by the configure script to the arguments to use when configuring
|
||||
@@ -294,6 +299,7 @@ BUILD_PREFIX_1 = @BUILD_PREFIX_1@
|
||||
# here so that they can be overridden by Makefile fragments.
|
||||
BOOT_CFLAGS= -g -O2
|
||||
BOOT_LDFLAGS=
|
||||
BOOT_ADAFLAGS=-gnatpg -gnata
|
||||
|
||||
BISON = @BISON@
|
||||
YACC = @YACC@
|
||||
@@ -439,7 +445,7 @@ HOST_LIB_PATH = [+ FOR host_modules +][+
|
||||
|
||||
# Define HOST_LIB_PATH_gcc here, for the sake of TARGET_LIB_PATH, ouch
|
||||
@if gcc
|
||||
HOST_LIB_PATH_gcc = $$r/$(HOST_SUBDIR)/gcc:$$r/$(HOST_SUBDIR)/prev-gcc:
|
||||
HOST_LIB_PATH_gcc = $$r/$(HOST_SUBDIR)/gcc$(GCC_SHLIB_SUBDIR):$$r/$(HOST_SUBDIR)/prev-gcc$(GCC_SHLIB_SUBDIR):
|
||||
@endif gcc
|
||||
|
||||
[+ FOR host_modules +][+ IF lib_path +]
|
||||
|
||||
@@ -1,3 +1,19 @@
|
||||
2008-08-09 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* mt-mips16-compat: New file, taken from mt-mips-elfoabi.
|
||||
* mt-mips-elfoabi: Include mt-mips16-compat.
|
||||
* mt-mips-gnu: New file.
|
||||
|
||||
2008-08-03 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* mt-spu (all-ld): Update for ld Makefile changes.
|
||||
|
||||
2008-08-02 Keith Seitz <keiths@redhat.com>
|
||||
|
||||
* tcl.m4 (SC_PATH_TCLCONFIG): Add some simple logic to deal
|
||||
with cygwin.
|
||||
(SC_PATH_TKCONFIG): Likewise.
|
||||
|
||||
2008-07-30 Paolo Bonzini <bonzini@gnu.org>
|
||||
|
||||
* mh-pa: New, from gcc/config/pa/x-ada.
|
||||
|
||||
@@ -1,6 +1 @@
|
||||
# The *-elfoabi configurations are intended to be usable for both
|
||||
# MIPS16 and non-MIPS16 code, but the libraries are all non-MIPS16.
|
||||
# Add -minterlink-mips16 so that the libraries can be used with both
|
||||
# ISA modes.
|
||||
CFLAGS_FOR_TARGET += -minterlink-mips16
|
||||
CXXFLAGS_FOR_TARGET += -minterlink-mips16
|
||||
include $(srcdir)/config/mt-mips16-compat
|
||||
|
||||
2
config/mt-mips-gnu
Normal file
2
config/mt-mips-gnu
Normal file
@@ -0,0 +1,2 @@
|
||||
include $(srcdir)/config/mt-gnu
|
||||
include $(srcdir)/config/mt-mips16-compat
|
||||
5
config/mt-mips16-compat
Normal file
5
config/mt-mips16-compat
Normal file
@@ -0,0 +1,5 @@
|
||||
# Configurations use this fragment if they support MIPS16 and non-MIPS16 code,
|
||||
# but if the libraries are all non-MIPS16. Add -minterlink-mips16 so
|
||||
# that the libraries can be used with both ISA modes.
|
||||
CFLAGS_FOR_TARGET += -minterlink-mips16
|
||||
CXXFLAGS_FOR_TARGET += -minterlink-mips16
|
||||
@@ -1,4 +1,2 @@
|
||||
# spu ld makefile invokes as-new in maintainer mode.
|
||||
all-ld: $(MAINT) all-gas
|
||||
# spu ld makefile invokes bin2c
|
||||
all-ld: all-binutils
|
||||
# spu ld makefile invokes as-new and bin2c in maintainer mode.
|
||||
all-ld: $(MAINT) all-gas all-binutils
|
||||
|
||||
@@ -32,6 +32,10 @@ AC_DEFUN([SC_PATH_TCLCONFIG], [
|
||||
AC_CACHE_VAL(ac_cv_c_tclconfig,[
|
||||
|
||||
# First check to see if --with-tcl was specified.
|
||||
case "${host}" in
|
||||
*-*-cygwin*) platDir="win" ;;
|
||||
*) platDir="unix" ;;
|
||||
esac
|
||||
if test x"${with_tclconfig}" != x ; then
|
||||
if test -f "${with_tclconfig}/tclConfig.sh" ; then
|
||||
ac_cv_c_tclconfig=`(cd ${with_tclconfig}; pwd)`
|
||||
@@ -55,8 +59,8 @@ AC_DEFUN([SC_PATH_TCLCONFIG], [
|
||||
`ls -dr ../../../tcl[[8-9]].[[0-9]].[[0-9]]* 2>/dev/null` \
|
||||
`ls -dr ../../../tcl[[8-9]].[[0-9]] 2>/dev/null` \
|
||||
`ls -dr ../../../tcl[[8-9]].[[0-9]]* 2>/dev/null` ; do
|
||||
if test -f "$i/unix/tclConfig.sh" ; then
|
||||
ac_cv_c_tclconfig=`(cd $i/unix; pwd)`
|
||||
if test -f "$i/$platDir/tclConfig.sh" ; then
|
||||
ac_cv_c_tclconfig=`(cd $i/$platDir; pwd)`
|
||||
break
|
||||
fi
|
||||
done
|
||||
@@ -99,8 +103,8 @@ AC_DEFUN([SC_PATH_TCLCONFIG], [
|
||||
`ls -dr ${srcdir}/../tcl[[8-9]].[[0-9]].[[0-9]]* 2>/dev/null` \
|
||||
`ls -dr ${srcdir}/../tcl[[8-9]].[[0-9]] 2>/dev/null` \
|
||||
`ls -dr ${srcdir}/../tcl[[8-9]].[[0-9]]* 2>/dev/null` ; do
|
||||
if test -f "$i/unix/tclConfig.sh" ; then
|
||||
ac_cv_c_tclconfig=`(cd $i/unix; pwd)`
|
||||
if test -f "$i/$platDir/tclConfig.sh" ; then
|
||||
ac_cv_c_tclconfig=`(cd $i/$platDir; pwd)`
|
||||
break
|
||||
fi
|
||||
done
|
||||
@@ -161,6 +165,10 @@ AC_DEFUN([SC_PATH_TKCONFIG], [
|
||||
fi
|
||||
|
||||
# then check for a private Tk library
|
||||
case "${host}" in
|
||||
*-*-cygwin*) platDir="win" ;;
|
||||
*) platDir="unix" ;;
|
||||
esac
|
||||
if test x"${ac_cv_c_tkconfig}" = x ; then
|
||||
for i in \
|
||||
../tk \
|
||||
@@ -175,8 +183,8 @@ AC_DEFUN([SC_PATH_TKCONFIG], [
|
||||
`ls -dr ../../../tk[[8-9]].[[0-9]].[[0-9]]* 2>/dev/null` \
|
||||
`ls -dr ../../../tk[[8-9]].[[0-9]] 2>/dev/null` \
|
||||
`ls -dr ../../../tk[[8-9]].[[0-9]]* 2>/dev/null` ; do
|
||||
if test -f "$i/unix/tkConfig.sh" ; then
|
||||
ac_cv_c_tkconfig=`(cd $i/unix; pwd)`
|
||||
if test -f "$i/$platDir/tkConfig.sh" ; then
|
||||
ac_cv_c_tkconfig=`(cd $i/$platDir; pwd)`
|
||||
break
|
||||
fi
|
||||
done
|
||||
@@ -218,8 +226,8 @@ AC_DEFUN([SC_PATH_TKCONFIG], [
|
||||
`ls -dr ${srcdir}/../tk[[8-9]].[[0-9]].[[0-9]]* 2>/dev/null` \
|
||||
`ls -dr ${srcdir}/../tk[[8-9]].[[0-9]] 2>/dev/null` \
|
||||
`ls -dr ${srcdir}/../tk[[8-9]].[[0-9]]* 2>/dev/null` ; do
|
||||
if test -f "$i/unix/tkConfig.sh" ; then
|
||||
ac_cv_c_tkconfig=`(cd $i/unix; pwd)`
|
||||
if test -f "$i/$platDir/tkConfig.sh" ; then
|
||||
ac_cv_c_tkconfig=`(cd $i/$platDir; pwd)`
|
||||
break
|
||||
fi
|
||||
done
|
||||
|
||||
18
configure
vendored
18
configure
vendored
@@ -272,7 +272,7 @@ PACKAGE_STRING=
|
||||
PACKAGE_BUGREPORT=
|
||||
|
||||
ac_unique_file="move-if-change"
|
||||
ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS TOPLEVEL_CONFIGURE_ARGUMENTS build build_cpu build_vendor build_os build_noncanonical host_noncanonical target_noncanonical host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA LN LN_S build_libsubdir build_subdir host_subdir target_subdir CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CXX CXXFLAGS ac_ct_CXX GNATBIND ac_ct_GNATBIND GNATMAKE ac_ct_GNATMAKE do_compare gmplibs gmpinc stage1_languages SYSROOT_CFLAGS_FOR_TARGET DEBUG_PREFIX_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET CXXFLAGS_FOR_TARGET RPATH_ENVVAR tooldir build_tooldir CONFIGURE_GDB_TK GDB_TK INSTALL_GDB_TK build_configargs build_configdirs host_configargs configdirs target_configargs AR_FOR_BUILD AS_FOR_BUILD CC_FOR_BUILD CFLAGS_FOR_BUILD CXXFLAGS_FOR_BUILD CXX_FOR_BUILD DLLTOOL_FOR_BUILD GCJ_FOR_BUILD GFORTRAN_FOR_BUILD LDFLAGS_FOR_BUILD LD_FOR_BUILD NM_FOR_BUILD RANLIB_FOR_BUILD WINDMC_FOR_BUILD WINDRES_FOR_BUILD config_shell YACC BISON M4 LEX FLEX MAKEINFO EXPECT RUNTEST AR AS DLLTOOL LD LIPO NM RANLIB STRIP WINDRES WINDMC OBJCOPY OBJDUMP CC_FOR_TARGET CXX_FOR_TARGET GCC_FOR_TARGET GCJ_FOR_TARGET GFORTRAN_FOR_TARGET AR_FOR_TARGET AS_FOR_TARGET DLLTOOL_FOR_TARGET LD_FOR_TARGET LIPO_FOR_TARGET NM_FOR_TARGET OBJDUMP_FOR_TARGET RANLIB_FOR_TARGET STRIP_FOR_TARGET WINDRES_FOR_TARGET WINDMC_FOR_TARGET RAW_CXX_FOR_TARGET FLAGS_FOR_TARGET COMPILER_AS_FOR_TARGET COMPILER_LD_FOR_TARGET COMPILER_NM_FOR_TARGET MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT stage1_cflags stage1_checking stage2_werror_flag datarootdir docdir pdfdir htmldir LIBOBJS LTLIBOBJS'
|
||||
ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS TOPLEVEL_CONFIGURE_ARGUMENTS build build_cpu build_vendor build_os build_noncanonical host_noncanonical target_noncanonical host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA LN LN_S build_libsubdir build_subdir host_subdir target_subdir CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT CXX CXXFLAGS ac_ct_CXX GNATBIND ac_ct_GNATBIND GNATMAKE ac_ct_GNATMAKE do_compare gmplibs gmpinc stage1_languages SYSROOT_CFLAGS_FOR_TARGET DEBUG_PREFIX_CFLAGS_FOR_TARGET CFLAGS_FOR_TARGET CXXFLAGS_FOR_TARGET RPATH_ENVVAR GCC_SHLIB_SUBDIR tooldir build_tooldir CONFIGURE_GDB_TK GDB_TK INSTALL_GDB_TK build_configargs build_configdirs host_configargs configdirs target_configargs AR_FOR_BUILD AS_FOR_BUILD CC_FOR_BUILD CFLAGS_FOR_BUILD CXXFLAGS_FOR_BUILD CXX_FOR_BUILD DLLTOOL_FOR_BUILD GCJ_FOR_BUILD GFORTRAN_FOR_BUILD LDFLAGS_FOR_BUILD LD_FOR_BUILD NM_FOR_BUILD RANLIB_FOR_BUILD WINDMC_FOR_BUILD WINDRES_FOR_BUILD config_shell YACC BISON M4 LEX FLEX MAKEINFO EXPECT RUNTEST AR AS DLLTOOL LD LIPO NM RANLIB STRIP WINDRES WINDMC OBJCOPY OBJDUMP CC_FOR_TARGET CXX_FOR_TARGET GCC_FOR_TARGET GCJ_FOR_TARGET GFORTRAN_FOR_TARGET AR_FOR_TARGET AS_FOR_TARGET DLLTOOL_FOR_TARGET LD_FOR_TARGET LIPO_FOR_TARGET NM_FOR_TARGET OBJDUMP_FOR_TARGET RANLIB_FOR_TARGET STRIP_FOR_TARGET WINDRES_FOR_TARGET WINDMC_FOR_TARGET RAW_CXX_FOR_TARGET FLAGS_FOR_TARGET COMPILER_AS_FOR_TARGET COMPILER_LD_FOR_TARGET COMPILER_NM_FOR_TARGET MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT stage1_cflags stage1_checking stage2_werror_flag datarootdir docdir pdfdir htmldir LIBOBJS LTLIBOBJS'
|
||||
ac_subst_files='serialization_dependencies host_makefile_frag target_makefile_frag alphaieee_frag ospace_frag'
|
||||
ac_pwd=`pwd`
|
||||
|
||||
@@ -2198,7 +2198,7 @@ case "${target}" in
|
||||
noconfigdirs="$noconfigdirs target-newlib target-libgloss ${libgcj}"
|
||||
;;
|
||||
powerpc-*-darwin* | i[3456789]86-*-darwin* | x86_64-*-darwin9*)
|
||||
noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof"
|
||||
noconfigdirs="$noconfigdirs ld gas gdb gprof"
|
||||
noconfigdirs="$noconfigdirs sim target-rda"
|
||||
;;
|
||||
*-*-darwin*)
|
||||
@@ -5448,6 +5448,9 @@ case "${target}" in
|
||||
mipsisa*-*-elfoabi*)
|
||||
target_makefile_frag="config/mt-mips-elfoabi"
|
||||
;;
|
||||
mips*-*-*linux* | mips*-*-gnu*)
|
||||
target_makefile_frag="config/mt-mips-gnu"
|
||||
;;
|
||||
*-*-netware*)
|
||||
target_makefile_frag="config/mt-netware"
|
||||
;;
|
||||
@@ -5591,12 +5594,21 @@ case "${host}" in
|
||||
;;
|
||||
esac
|
||||
|
||||
# Decide which environment variable is used to find dynamic libraries.
|
||||
case "${host}" in
|
||||
*-*-hpux*) RPATH_ENVVAR=SHLIB_PATH ;;
|
||||
*-*-darwin* | *-*-rhapsody* ) RPATH_ENVVAR=DYLD_LIBRARY_PATH ;;
|
||||
*-*-mingw* | *-*-cygwin ) RPATH_ENVVAR=PATH ;;
|
||||
*) RPATH_ENVVAR=LD_LIBRARY_PATH ;;
|
||||
esac
|
||||
|
||||
# On systems where the dynamic library environment variable is PATH,
|
||||
if test "$RPATH_ENVVAR" = PATH; then
|
||||
GCC_SHLIB_SUBDIR=/shlib
|
||||
else
|
||||
GCC_SHLIB_SUBDIR=
|
||||
fi
|
||||
|
||||
# Record target_configdirs and the configure arguments for target and
|
||||
# build configuration in Makefile.
|
||||
target_configdirs=`echo "${target_configdirs}" | sed -e 's/target-//g'`
|
||||
@@ -6069,6 +6081,7 @@ done
|
||||
|
||||
|
||||
|
||||
|
||||
# Build module lists & subconfigure args.
|
||||
|
||||
|
||||
@@ -12968,6 +12981,7 @@ s,@DEBUG_PREFIX_CFLAGS_FOR_TARGET@,$DEBUG_PREFIX_CFLAGS_FOR_TARGET,;t t
|
||||
s,@CFLAGS_FOR_TARGET@,$CFLAGS_FOR_TARGET,;t t
|
||||
s,@CXXFLAGS_FOR_TARGET@,$CXXFLAGS_FOR_TARGET,;t t
|
||||
s,@RPATH_ENVVAR@,$RPATH_ENVVAR,;t t
|
||||
s,@GCC_SHLIB_SUBDIR@,$GCC_SHLIB_SUBDIR,;t t
|
||||
s,@tooldir@,$tooldir,;t t
|
||||
s,@build_tooldir@,$build_tooldir,;t t
|
||||
s,@CONFIGURE_GDB_TK@,$CONFIGURE_GDB_TK,;t t
|
||||
|
||||
15
configure.ac
15
configure.ac
@@ -447,7 +447,7 @@ case "${target}" in
|
||||
noconfigdirs="$noconfigdirs target-newlib target-libgloss ${libgcj}"
|
||||
;;
|
||||
powerpc-*-darwin* | i[[3456789]]86-*-darwin* | x86_64-*-darwin9*)
|
||||
noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof"
|
||||
noconfigdirs="$noconfigdirs ld gas gdb gprof"
|
||||
noconfigdirs="$noconfigdirs sim target-rda"
|
||||
;;
|
||||
*-*-darwin*)
|
||||
@@ -1904,6 +1904,9 @@ case "${target}" in
|
||||
mipsisa*-*-elfoabi*)
|
||||
target_makefile_frag="config/mt-mips-elfoabi"
|
||||
;;
|
||||
mips*-*-*linux* | mips*-*-gnu*)
|
||||
target_makefile_frag="config/mt-mips-gnu"
|
||||
;;
|
||||
*-*-netware*)
|
||||
target_makefile_frag="config/mt-netware"
|
||||
;;
|
||||
@@ -2047,12 +2050,21 @@ case "${host}" in
|
||||
;;
|
||||
esac
|
||||
|
||||
# Decide which environment variable is used to find dynamic libraries.
|
||||
case "${host}" in
|
||||
*-*-hpux*) RPATH_ENVVAR=SHLIB_PATH ;;
|
||||
*-*-darwin* | *-*-rhapsody* ) RPATH_ENVVAR=DYLD_LIBRARY_PATH ;;
|
||||
*-*-mingw* | *-*-cygwin ) RPATH_ENVVAR=PATH ;;
|
||||
*) RPATH_ENVVAR=LD_LIBRARY_PATH ;;
|
||||
esac
|
||||
|
||||
# On systems where the dynamic library environment variable is PATH,
|
||||
if test "$RPATH_ENVVAR" = PATH; then
|
||||
GCC_SHLIB_SUBDIR=/shlib
|
||||
else
|
||||
GCC_SHLIB_SUBDIR=
|
||||
fi
|
||||
|
||||
# Record target_configdirs and the configure arguments for target and
|
||||
# build configuration in Makefile.
|
||||
target_configdirs=`echo "${target_configdirs}" | sed -e 's/target-//g'`
|
||||
@@ -2510,6 +2522,7 @@ AC_SUBST_FILE(ospace_frag)
|
||||
|
||||
# Miscellanea: directories, flags, etc.
|
||||
AC_SUBST(RPATH_ENVVAR)
|
||||
AC_SUBST(GCC_SHLIB_SUBDIR)
|
||||
AC_SUBST(tooldir)
|
||||
AC_SUBST(build_tooldir)
|
||||
AC_SUBST(CONFIGURE_GDB_TK)
|
||||
|
||||
656
cpu/ChangeLog
656
cpu/ChangeLog
@@ -1,656 +0,0 @@
|
||||
2008-01-29 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
|
||||
to source.
|
||||
|
||||
2007-10-22 Hans-Peter Nilsson <hp@axis.com>
|
||||
|
||||
* cris.cpu (movs, movu): Use result of extension operation when
|
||||
updating flags.
|
||||
|
||||
2007-07-04 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* cris.cpu: Update copyright notice to refer to GPLv3.
|
||||
* frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
|
||||
m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
|
||||
sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
|
||||
xc16x.opc: Likewise.
|
||||
* iq2000.cpu: Fix copyright notice to refer to FSF.
|
||||
|
||||
2007-04-30 Mark Salter <msalter@sadr.localdomain>
|
||||
|
||||
* frv.cpu (spr-names): Support new coprocessor SPR registers.
|
||||
|
||||
2007-04-20 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* xc16x.cpu: Restore after accidentally overwriting this file with
|
||||
xc16x.opc.
|
||||
|
||||
2007-03-29 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (Imm-8-s4n): Fix print hook.
|
||||
(Lab-24-8, Lab-32-8, Lab-40-8): Fix.
|
||||
(arith-jnz-imm4-dst-defn): Make relaxable.
|
||||
(arith-jnz16-imm4-dst-defn): Fix encodings.
|
||||
|
||||
2007-03-20 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
|
||||
mem20): New.
|
||||
(src16-16-20-An-relative-*): New.
|
||||
(dst16-*-20-An-relative-*): New.
|
||||
(dst16-16-16sa-*): New
|
||||
(dst16-16-16ar-*): New
|
||||
(dst32-16-16sa-Unprefixed-*): New
|
||||
(jsri): Fix operands.
|
||||
(setzx): Fix encoding.
|
||||
|
||||
2007-03-08 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* m32r.opc: Formatting.
|
||||
|
||||
2006-05-22 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
|
||||
|
||||
2006-04-10 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.opc (parse_unsigned_bitbase): Take a new parameter which
|
||||
decides if this function accepts symbolic constants or not.
|
||||
(parse_signed_bitbase): Likewise.
|
||||
(parse_unsigned_bitbase8): Pass the new parameter.
|
||||
(parse_unsigned_bitbase11): Likewise.
|
||||
(parse_unsigned_bitbase16): Likewise.
|
||||
(parse_unsigned_bitbase19): Likewise.
|
||||
(parse_unsigned_bitbase27): Likewise.
|
||||
(parse_signed_bitbase8): Likewise.
|
||||
(parse_signed_bitbase11): Likewise.
|
||||
(parse_signed_bitbase19): Likewise.
|
||||
|
||||
2006-03-13 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (Bit3-S): New.
|
||||
(btst:s): New.
|
||||
* m32c.opc (parse_bit3_S): New.
|
||||
|
||||
* m32c.cpu (decimal-subtraction16-insn): Add second operand.
|
||||
(btst): Add optional :G suffix for MACH32.
|
||||
(or.b:S): New.
|
||||
(pop.w:G): Add optional :G suffix for MACH16.
|
||||
(push.b.imm): Fix syntax.
|
||||
|
||||
2006-03-10 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (mul.l): New.
|
||||
(mulu.l): New.
|
||||
|
||||
2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
|
||||
|
||||
* xc16x.opc (parse_hash): Return NULL if the input was parsed or
|
||||
an error message otherwise.
|
||||
(parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
|
||||
Fix up comments to correctly describe the functions.
|
||||
|
||||
2006-02-24 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (RL_TYPE): New attribute, with macros.
|
||||
(Lab-8-24): Add RELAX.
|
||||
(unary-insn-defn-g, binary-arith-imm-dst-defn,
|
||||
binary-arith-imm4-dst-defn): Add 1ADDR attribute.
|
||||
(binary-arith-src-dst-defn): Add 2ADDR attribute.
|
||||
(jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
|
||||
jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
|
||||
attribute.
|
||||
(jsri16, jsri32): Add 1ADDR attribute.
|
||||
(jsr32.w, jsr32.a): Add JUMP attribute.
|
||||
|
||||
2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
|
||||
Anil Paranjape <anilp1@kpitcummins.com>
|
||||
Shilin Shakti <shilins@kpitcummins.com>
|
||||
|
||||
* xc16x.cpu: New file containing complete CGEN specific XC16X CPU
|
||||
description.
|
||||
* xc16x.opc: New file containing supporting XC16C routines.
|
||||
|
||||
2006-02-10 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
|
||||
|
||||
2006-01-06 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (mov.w:q): Fix mode.
|
||||
(push32.b.imm): Likewise, for the comment.
|
||||
|
||||
2005-12-16 Nathan Sidwell <nathan@codesourcery.com>
|
||||
|
||||
Second part of ms1 to mt renaming.
|
||||
* mt.cpu (define-arch, define-isa): Set name to mt.
|
||||
(define-mach): Adjust.
|
||||
* mt.opc (CGEN_ASM_HASH): Update.
|
||||
(mt_asm_hash, mt_cgen_insn_supported): Renamed.
|
||||
(parse_loopsize, parse_imm16): Adjust.
|
||||
|
||||
2005-12-13 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (jsri): Fix order so register names aren't treated as
|
||||
symbols.
|
||||
(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
|
||||
indexwd, indexws): Fix encodings.
|
||||
|
||||
2005-12-12 Nathan Sidwell <nathan@codesourcery.com>
|
||||
|
||||
* mt.cpu: Rename from ms1.cpu.
|
||||
* mt.opc: Rename from ms1.opc.
|
||||
|
||||
2005-12-06 Hans-Peter Nilsson <hp@axis.com>
|
||||
|
||||
* cris.cpu (simplecris-common-writable-specregs)
|
||||
(simplecris-common-readable-specregs): Split from
|
||||
simplecris-common-specregs. All users changed.
|
||||
(cris-implemented-writable-specregs-v0)
|
||||
(cris-implemented-readable-specregs-v0): Similar from
|
||||
cris-implemented-specregs-v0.
|
||||
(cris-implemented-writable-specregs-v3)
|
||||
(cris-implemented-readable-specregs-v3)
|
||||
(cris-implemented-writable-specregs-v8)
|
||||
(cris-implemented-readable-specregs-v8)
|
||||
(cris-implemented-writable-specregs-v10)
|
||||
(cris-implemented-readable-specregs-v10)
|
||||
(cris-implemented-writable-specregs-v32)
|
||||
(cris-implemented-readable-specregs-v32): Similar.
|
||||
(bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
|
||||
insns and specializations.
|
||||
|
||||
2005-11-08 Nathan Sidwell <nathan@codesourcery.com>
|
||||
|
||||
Add ms2
|
||||
* ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
|
||||
model.
|
||||
(f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
|
||||
f-cb2incr, f-rc3): New fields.
|
||||
(LOOP): New instruction.
|
||||
(JAL-HAZARD): New hazard.
|
||||
(imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
|
||||
New operands.
|
||||
(mul, muli, dbnz, iflush): Enable for ms2
|
||||
(jal, reti): Has JAL-HAZARD.
|
||||
(ldctxt, ldfb, stfb): Only ms1.
|
||||
(fbcb): Only ms1,ms1-003.
|
||||
(wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
|
||||
fbcbincrs, mfbcbincrs): Enable for ms2.
|
||||
(loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
|
||||
* ms1.opc (parse_loopsize): New.
|
||||
(parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
|
||||
(print_pcrel): New.
|
||||
|
||||
2005-10-28 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
Contribute the following change:
|
||||
2003-09-24 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
|
||||
CGEN_ATTR_VALUE_TYPE.
|
||||
* m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
|
||||
Use cgen_bitset_intersect_p.
|
||||
|
||||
2005-10-27 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
|
||||
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
|
||||
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
|
||||
imm operand is needed.
|
||||
(adjnz, sbjnz): Pass the right operands.
|
||||
(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
|
||||
unary-insn): Add -g variants for opcodes that need to support :G.
|
||||
(not.BW:G, push.BW:G): Call it.
|
||||
(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
|
||||
stzx16-imm8-imm8-abs16): Fix operand typos.
|
||||
* m32c.opc (m32c_asm_hash): Support bnCND.
|
||||
(parse_signed4n, print_signed4n): New.
|
||||
|
||||
2005-10-26 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
|
||||
(mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
|
||||
mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
|
||||
dsp8[sp] is signed.
|
||||
(mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
|
||||
(mov.BW:S r0,r1): Fix typo r1l->r1.
|
||||
(tst): Allow :G suffix.
|
||||
* m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
|
||||
|
||||
2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
|
||||
|
||||
2005-10-25 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
|
||||
making one a macro of the other.
|
||||
|
||||
2005-10-21 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
|
||||
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
|
||||
indexld, indexls): .w variants have `1' bit.
|
||||
(rot32.b): QI, not SI.
|
||||
(rot32.w): HI, not SI.
|
||||
(xchg16): HI for .w variant.
|
||||
|
||||
2005-10-19 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* m32r.opc (parse_slo16): Fix bad application of previous patch.
|
||||
|
||||
2005-10-18 Andreas Schwab <schwab@suse.de>
|
||||
|
||||
* m32r.opc (parse_slo16): Better version of previous patch.
|
||||
|
||||
2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
|
||||
size.
|
||||
|
||||
2005-07-25 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c.opc (parse_unsigned8): Add %dsp8().
|
||||
(parse_signed8): Add %hi8().
|
||||
(parse_unsigned16): Add %dsp16().
|
||||
(parse_signed16): Add %lo16() and %hi16().
|
||||
(parse_lab_5_3): Make valuep a bfd_vma *.
|
||||
|
||||
2005-07-18 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
|
||||
components.
|
||||
(f-lab32-jmp-s): Fix insertion sequence.
|
||||
(Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
|
||||
(Dsp-40-s8): Make parameter be signed.
|
||||
(Dsp-40-s16): Likewise.
|
||||
(Dsp-48-s8): Likewise.
|
||||
(Dsp-48-s16): Likewise.
|
||||
(Imm-13-u3): Likewise. (Despite its name!)
|
||||
(BitBase16-16-s8): Make the parameter be unsigned.
|
||||
(BitBase16-8-u11-S): Likewise.
|
||||
(Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
|
||||
jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
|
||||
relaxation.
|
||||
|
||||
* m32c.opc: Fix formatting.
|
||||
Use safe-ctype.h instead of ctype.h
|
||||
Move duplicated code sequences into a macro.
|
||||
Fix compile time warnings about signedness mismatches.
|
||||
Remove dead code.
|
||||
(parse_lab_5_3): New parser function.
|
||||
|
||||
2005-07-16 Jim Blandy <jimb@redhat.com>
|
||||
|
||||
* m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
|
||||
to represent isa sets.
|
||||
|
||||
2005-07-15 Jim Blandy <jimb@redhat.com>
|
||||
|
||||
* m32c.cpu, m32c.opc: Fix copyright.
|
||||
|
||||
2005-07-14 Jim Blandy <jimb@redhat.com>
|
||||
|
||||
* m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
|
||||
|
||||
2005-07-14 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* ms1.opc (print_dollarhex): Correct format string.
|
||||
|
||||
2005-07-06 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* iq2000.cpu: Include from binutils cpu dir.
|
||||
|
||||
2005-07-05 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
|
||||
unsigned in order to avoid compile time warnings about sign
|
||||
conflicts.
|
||||
|
||||
* ms1.opc (parse_*): Likewise.
|
||||
(parse_imm16): Use a "void *" as it is passed both signed and
|
||||
unsigned arguments.
|
||||
|
||||
2005-07-01 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* frv.opc: Update to ISO C90 function declaration style.
|
||||
* iq2000.opc: Likewise.
|
||||
* m32r.opc: Likewise.
|
||||
* sh.opc: Likewise.
|
||||
|
||||
2005-06-15 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
Contributed by Red Hat.
|
||||
* ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
|
||||
* ms1.opc: New file. Written by Stan Cox.
|
||||
|
||||
2005-05-10 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* Update the address and phone number of the FSF organization in
|
||||
the GPL notices in the following files:
|
||||
cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
|
||||
m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
|
||||
sh64-media.cpu, simplify.inc
|
||||
|
||||
2005-02-24 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* frv.opc (parse_A): Warning fix.
|
||||
|
||||
2005-02-23 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* frv.opc: Fixed compile time warnings about differing signed'ness
|
||||
of pointers passed to functions.
|
||||
* m32r.opc: Likewise.
|
||||
|
||||
2005-02-11 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000.opc (parse_jtargq10): Change type of valuep argument to
|
||||
'bfd_vma *' in order avoid compile time warning message.
|
||||
|
||||
2005-01-28 Hans-Peter Nilsson <hp@axis.com>
|
||||
|
||||
* cris.cpu (mstep): Add missing insn.
|
||||
|
||||
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
|
||||
|
||||
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
|
||||
* frv.cpu: Add support for TLS annotations in loads and calll.
|
||||
* frv.opc (parse_symbolic_address): New.
|
||||
(parse_ldd_annotation): New.
|
||||
(parse_call_annotation): New.
|
||||
(parse_ld_annotation): New.
|
||||
(parse_ulo16, parse_uslo16): Use parse_symbolic_address.
|
||||
Introduce TLS relocations.
|
||||
(parse_d12, parse_s12, parse_u12): Likewise.
|
||||
(parse_uhi16): Likewise. Fix constant checking on 64-bit host.
|
||||
(parse_call_label, print_at): New.
|
||||
|
||||
2004-12-21 Mikael Starvik <starvik@axis.com>
|
||||
|
||||
* cris.cpu (cris-set-mem): Correct integral write semantics.
|
||||
|
||||
2004-11-29 Hans-Peter Nilsson <hp@axis.com>
|
||||
|
||||
* cris.cpu: New file.
|
||||
|
||||
2004-11-15 Michael K. Lechner <mike.lechner@gmail.com>
|
||||
|
||||
* iq2000.cpu: Added quotes around macro arguments so that they
|
||||
will work with newer versions of guile.
|
||||
|
||||
2004-10-27 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
|
||||
wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
|
||||
operand.
|
||||
* iq2000.cpu (dnop index): Rename to _index to avoid complications
|
||||
with guile.
|
||||
|
||||
2004-08-27 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* frv.cpu (cfmovs): Change UNIT attribute to FMALL.
|
||||
|
||||
2004-05-15 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
|
||||
|
||||
2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
|
||||
|
||||
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* frv.cpu (define-arch frv): Add fr450 mach.
|
||||
(define-mach fr450): New.
|
||||
(define-model fr450): New. Add profile units to every fr450 insn.
|
||||
(define-attr UNIT): Add MDCUTSSI.
|
||||
(define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
|
||||
(define-attr AUDIO): New boolean.
|
||||
(f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
|
||||
(f-LRA-null, f-TLBPR-null): New fields.
|
||||
(scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
|
||||
(tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
|
||||
(LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
|
||||
(LRA-null, TLBPR-null): New macros.
|
||||
(iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
|
||||
(load-real-address): New macro.
|
||||
(lrai, lrad, tlbpr): New instructions.
|
||||
(media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
|
||||
(mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
|
||||
(mdcutssi): Change UNIT attribute to MDCUTSSI.
|
||||
(media-low-clear-semantics, media-scope-limit-semantics)
|
||||
(media-quad-limit, media-quad-shift): New macros.
|
||||
(mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
|
||||
* frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
|
||||
(frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
|
||||
(frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
|
||||
(fr450_unit_mapping): New array.
|
||||
(fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
|
||||
for new MDCUTSSI unit.
|
||||
(fr450_check_insn_major_constraints): New function.
|
||||
(check_insn_major_constraints): Use it.
|
||||
|
||||
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
|
||||
(scutss): Change unit to I0.
|
||||
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
|
||||
(mqsaths): Fix FR400-MAJOR categorization.
|
||||
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
|
||||
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
|
||||
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
|
||||
combinations.
|
||||
|
||||
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
|
||||
(rstb, rsth, rst, rstd, rstq): Delete.
|
||||
(rstbf, rsthf, rstf, rstdf, rstqf): Delete.
|
||||
|
||||
2004-02-23 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* Apply these patches from Renesas:
|
||||
|
||||
2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* cpu/m32r.opc (my_print_insn): Fixed incorrect output when
|
||||
disassembling codes for 0x*2 addresses.
|
||||
|
||||
2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
|
||||
|
||||
2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
|
||||
|
||||
* cpu/m32r.cpu : Add new model m32r2.
|
||||
Add new instructions.
|
||||
Replace occurrances of 'Mitsubishi' with 'Renesas'.
|
||||
Changed PIPE attr of push from O to OS.
|
||||
Care for Little-endian of M32R.
|
||||
* cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
|
||||
Care for Little-endian of M32R.
|
||||
(parse_slo16): signed extension for value.
|
||||
|
||||
2004-02-20 Andrew Cagney <cagney@redhat.com>
|
||||
|
||||
* m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
|
||||
Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
|
||||
|
||||
* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
|
||||
written by Ben Elliston.
|
||||
|
||||
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
|
||||
|
||||
* frv.cpu (UNIT): Add IACC.
|
||||
(iacc-multiply-r-r): Use it.
|
||||
* frv.opc (fr400_unit_mapping): Add entry for IACC.
|
||||
(fr500_unit_mapping, fr550_unit_mapping): Likewise.
|
||||
|
||||
2004-01-06 Alexandre Oliva <aoliva@redhat.com>
|
||||
|
||||
2003-12-19 Alexandre Oliva <aoliva@redhat.com>
|
||||
* frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
|
||||
cut&paste errors in shifting/truncating numerical operands.
|
||||
2003-08-08 Alexandre Oliva <aoliva@redhat.com>
|
||||
* frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
|
||||
(parse_uslo16): Likewise.
|
||||
(parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
|
||||
(parse_d12): Parse gotoff12 and gotofffuncdesc12.
|
||||
(parse_s12): Likewise.
|
||||
2003-08-04 Alexandre Oliva <aoliva@redhat.com>
|
||||
* frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
|
||||
(parse_uslo16): Likewise.
|
||||
(parse_uhi16): Parse gothi and gotfuncdeschi.
|
||||
(parse_d12): Parse got12 and gotfuncdesc12.
|
||||
(parse_s12): Likewise.
|
||||
|
||||
2003-10-10 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu (dnpmop): New p-macro.
|
||||
(GRdoublek): Use dnpmop.
|
||||
(CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
|
||||
(store-double-r-r): Use (.sym regtype doublek).
|
||||
(r-store-double): Ditto.
|
||||
(store-double-r-r-u): Ditto.
|
||||
(conditional-store-double): Ditto.
|
||||
(conditional-store-double-u): Ditto.
|
||||
(store-double-r-simm): Ditto.
|
||||
(fmovs): Assign to UNIT FMALL.
|
||||
|
||||
2003-10-06 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu, frv.opc: Add support for fr550.
|
||||
|
||||
2003-09-24 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu (u-commit): New modelling unit for fr500.
|
||||
(mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
|
||||
(commit-r): Use u-commit model for fr500.
|
||||
(commit): Ditto.
|
||||
(conditional-float-binary-op): Take profiling data as an argument.
|
||||
Update callers.
|
||||
(ne-float-binary-op): Ditto.
|
||||
|
||||
2003-09-19 Michael Snyder <msnyder@redhat.com>
|
||||
|
||||
* frv.cpu (nldqi): Delete unimplemented instruction.
|
||||
|
||||
2003-09-12 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
|
||||
(clear-ne-flag-r): Pass insn profiling in as an argument. Call
|
||||
frv_ref_SI to get input register referenced for profiling.
|
||||
(clear-ne-flag-all): Pass insn profiling in as an argument.
|
||||
(clrgr,clrfr,clrga,clrfa): Add profiling information.
|
||||
|
||||
2003-09-11 Michael Snyder <msnyder@redhat.com>
|
||||
|
||||
* frv.cpu: Typographical corrections.
|
||||
|
||||
2003-09-09 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu (media-dual-complex): Change UNIT to FMALL.
|
||||
(conditional-media-dual-complex, media-quad-complex): Likewise.
|
||||
|
||||
2003-09-04 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.cpu (register-transfer): Pass in all attributes in on argument.
|
||||
Update all callers.
|
||||
(conditional-register-transfer): Ditto.
|
||||
(cache-preload): Ditto.
|
||||
(floating-point-conversion): Ditto.
|
||||
(floating-point-neg): Ditto.
|
||||
(float-abs): Ditto.
|
||||
(float-binary-op-s): Ditto.
|
||||
(conditional-float-binary-op): Ditto.
|
||||
(ne-float-binary-op): Ditto.
|
||||
(float-dual-arith): Ditto.
|
||||
(ne-float-dual-arith): Ditto.
|
||||
|
||||
2003-09-03 Dave Brolley <brolley@redhat.com>
|
||||
|
||||
* frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
|
||||
* frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
|
||||
MCLRACC-1.
|
||||
(A): Removed operand.
|
||||
(A0,A1): New operands replace operand A.
|
||||
(mnop): Now a real insn
|
||||
(mclracc): Removed insn.
|
||||
(mclracc-0, mclracc-1): New insns replace mclracc.
|
||||
(all insns): Use new UNIT attributes.
|
||||
|
||||
2003-08-21 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
|
||||
and u-media-dual-btoh with output parameter.
|
||||
(cmbtoh): Add profiling hack.
|
||||
|
||||
2003-08-19 Michael Snyder <msnyder@redhat.com>
|
||||
|
||||
* frv.cpu: Fix typo, Frintkeven -> FRintkeven
|
||||
|
||||
2003-06-10 Doug Evans <dje@sebabeach.org>
|
||||
|
||||
* frv.cpu: Add IDOC attribute.
|
||||
|
||||
2003-06-06 Andrew Cagney <cagney@redhat.com>
|
||||
|
||||
Contributed by Red Hat.
|
||||
* iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
|
||||
Stan Cox, and Frank Ch. Eigler.
|
||||
* iq2000.opc: New file. Written by Ben Elliston, Frank
|
||||
Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
|
||||
* iq2000m.cpu: New file. Written by Jeff Johnston.
|
||||
* iq10.cpu: New file. Written by Jeff Johnston.
|
||||
|
||||
2003-06-05 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* frv.cpu (FRintieven): New operand. An even-numbered only
|
||||
version of the FRinti operand.
|
||||
(FRintjeven): Likewise for FRintj.
|
||||
(FRintkeven): Likewise for FRintk.
|
||||
(mdcutssi, media-dual-word-rotate-r-r, mqsaths,
|
||||
media-quad-arith-sat-semantics, media-quad-arith-sat,
|
||||
conditional-media-quad-arith-sat, mdunpackh,
|
||||
media-quad-multiply-semantics, media-quad-multiply,
|
||||
conditional-media-quad-multiply, media-quad-complex-i,
|
||||
media-quad-multiply-acc-semantics, media-quad-multiply-acc,
|
||||
conditional-media-quad-multiply-acc, munpackh,
|
||||
media-quad-multiply-cross-acc-semantics, mdpackh,
|
||||
media-quad-multiply-cross-acc, mbtoh-semantics,
|
||||
media-quad-cross-multiply-cross-acc-semantics,
|
||||
media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
|
||||
media-quad-cross-multiply-acc-semantics, cmbtoh,
|
||||
media-quad-cross-multiply-acc, media-quad-complex, mhtob,
|
||||
media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
|
||||
cmhtob): Use new operands.
|
||||
* frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
|
||||
(parse_even_register): New function.
|
||||
|
||||
2003-06-03 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
|
||||
immediate value not unsigned.
|
||||
|
||||
2003-06-03 Andrew Cagney <cagney@redhat.com>
|
||||
|
||||
Contributed by Red Hat.
|
||||
* frv.cpu: New file. Written by Dave Brolley, Catherine Moore,
|
||||
and Eric Christopher.
|
||||
* frv.opc: New file. Written by Catherine Moore, and Dave
|
||||
Brolley.
|
||||
* simplify.inc: New file. Written by Doug Evans.
|
||||
|
||||
2003-05-02 Andrew Cagney <cagney@redhat.com>
|
||||
|
||||
* New file.
|
||||
|
||||
|
||||
Local Variables:
|
||||
mode: change-log
|
||||
left-margin: 8
|
||||
fill-column: 74
|
||||
version-control: never
|
||||
End:
|
||||
4553
cpu/cris.cpu
4553
cpu/cris.cpu
File diff suppressed because it is too large
Load Diff
9789
cpu/frv.cpu
9789
cpu/frv.cpu
File diff suppressed because it is too large
Load Diff
1917
cpu/frv.opc
1917
cpu/frv.opc
File diff suppressed because it is too large
Load Diff
1112
cpu/iq10.cpu
1112
cpu/iq10.cpu
File diff suppressed because it is too large
Load Diff
1196
cpu/iq2000.cpu
1196
cpu/iq2000.cpu
File diff suppressed because it is too large
Load Diff
320
cpu/iq2000.opc
320
cpu/iq2000.opc
@@ -1,320 +0,0 @@
|
||||
/* IQ2000 opcode support. -*- C -*-
|
||||
|
||||
Copyright 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Red Hat Inc; developed under contract from Fujitsu.
|
||||
|
||||
This file is part of the GNU Binutils.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't
|
||||
appropriate in .cpu files, so it resides here. This especially applies
|
||||
to assembly/disassembly where parsing/printing can be quite involved.
|
||||
Such things aren't really part of the specification of the cpu, per se,
|
||||
so .cpu files provide the general framework and .opc files handle the
|
||||
nitty-gritty details as necessary.
|
||||
|
||||
Each section is delimited with start and end markers.
|
||||
|
||||
<arch>-opc.h additions use: "-- opc.h"
|
||||
<arch>-opc.c additions use: "-- opc.c"
|
||||
<arch>-asm.c additions use: "-- asm.c"
|
||||
<arch>-dis.c additions use: "-- dis.c"
|
||||
<arch>-ibd.h additions use: "-- ibd.h". */
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
/* Allows reason codes to be output when assembler errors occur. */
|
||||
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||
|
||||
/* Override disassembly hashing - there are variable bits in the top
|
||||
byte of these instructions. */
|
||||
#define CGEN_DIS_HASH_SIZE 8
|
||||
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
|
||||
|
||||
/* following activates check beyond hashing since some iq2000 and iq10
|
||||
instructions have same mnemonics but different functionality. */
|
||||
#define CGEN_VALIDATE_INSN_SUPPORTED
|
||||
|
||||
extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
|
||||
|
||||
/* -- asm.c */
|
||||
|
||||
#include "safe-ctype.h"
|
||||
|
||||
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
|
||||
|
||||
/* Special check to ensure that instruction exists for given machine. */
|
||||
|
||||
int
|
||||
iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
|
||||
{
|
||||
int machs = cd->machs;
|
||||
|
||||
return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0;
|
||||
}
|
||||
|
||||
static int
|
||||
iq2000_cgen_isa_register (const char **strp)
|
||||
{
|
||||
int len;
|
||||
int ch1, ch2;
|
||||
|
||||
if (**strp == 'r' || **strp == 'R')
|
||||
{
|
||||
len = strlen (*strp);
|
||||
if (len == 2)
|
||||
{
|
||||
ch1 = (*strp)[1];
|
||||
if ('0' <= ch1 && ch1 <= '9')
|
||||
return 1;
|
||||
}
|
||||
else if (len == 3)
|
||||
{
|
||||
ch1 = (*strp)[1];
|
||||
ch2 = (*strp)[2];
|
||||
if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9'))
|
||||
return 1;
|
||||
if ('3' == ch1 && (ch2 == '0' || ch2 == '1'))
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
if (**strp == '%'
|
||||
&& TOLOWER ((*strp)[1]) != 'l'
|
||||
&& TOLOWER ((*strp)[1]) != 'h')
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Handle negated literal. */
|
||||
|
||||
static const char *
|
||||
parse_mimm (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
|
||||
/* Verify this isn't a register. */
|
||||
if (iq2000_cgen_isa_register (strp))
|
||||
errmsg = _("immediate value cannot be register");
|
||||
else
|
||||
{
|
||||
long value;
|
||||
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
|
||||
if (errmsg == NULL)
|
||||
{
|
||||
long x = (-value) & 0xFFFF0000;
|
||||
|
||||
if (x != 0 && x != (long) 0xFFFF0000)
|
||||
errmsg = _("immediate value out of range");
|
||||
else
|
||||
*valuep = (-value & 0xFFFF);
|
||||
}
|
||||
}
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* Handle signed/unsigned literal. */
|
||||
|
||||
static const char *
|
||||
parse_imm (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
|
||||
if (iq2000_cgen_isa_register (strp))
|
||||
errmsg = _("immediate value cannot be register");
|
||||
else
|
||||
{
|
||||
long value;
|
||||
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value);
|
||||
if (errmsg == NULL)
|
||||
{
|
||||
long x = value & 0xFFFF0000;
|
||||
|
||||
if (x != 0 && x != (long) 0xFFFF0000)
|
||||
errmsg = _("immediate value out of range");
|
||||
else
|
||||
*valuep = (value & 0xFFFF);
|
||||
}
|
||||
}
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* Handle iq10 21-bit jmp offset. */
|
||||
|
||||
static const char *
|
||||
parse_jtargq10 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
int reloc ATTRIBUTE_UNUSED,
|
||||
enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED,
|
||||
bfd_vma *valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
bfd_vma value;
|
||||
enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER;
|
||||
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21,
|
||||
& result_type, & value);
|
||||
if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
{
|
||||
/* Check value is within 23-bits
|
||||
(remembering that 2-bit shift right will occur). */
|
||||
if (value > 0x7fffff)
|
||||
return _("21-bit offset out of range");
|
||||
}
|
||||
*valuep = (value & 0x7FFFFF);
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* Handle high(). */
|
||||
|
||||
static const char *
|
||||
parse_hi16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
if (strncasecmp (*strp, "%hi(", 4) == 0)
|
||||
{
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
const char *errmsg;
|
||||
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
{
|
||||
/* If value has top-bit of %lo on, then it will
|
||||
sign-propagate and so we compensate by adding
|
||||
1 to the resultant %hi value. */
|
||||
if (value & 0x8000)
|
||||
value += 0x10000;
|
||||
value >>= 16;
|
||||
value &= 0xffff;
|
||||
}
|
||||
*valuep = value;
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* We add %uhi in case a user just wants the high 16-bits or is using
|
||||
an insn like ori for %lo which does not sign-propagate. */
|
||||
if (strncasecmp (*strp, "%uhi(", 5) == 0)
|
||||
{
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
const char *errmsg;
|
||||
|
||||
*strp += 5;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
value >>= 16;
|
||||
|
||||
value &= 0xffff;
|
||||
*valuep = value;
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return parse_imm (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* Handle %lo in a signed context.
|
||||
The signedness of the value doesn't matter to %lo(), but this also
|
||||
handles the case where %lo() isn't present. */
|
||||
|
||||
static const char *
|
||||
parse_lo16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
if (strncasecmp (*strp, "%lo(", 4) == 0)
|
||||
{
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
value &= 0xffff;
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return parse_imm (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* Handle %lo in a negated signed context.
|
||||
The signedness of the value doesn't matter to %lo(), but this also
|
||||
handles the case where %lo() isn't present. */
|
||||
|
||||
static const char *
|
||||
parse_mlo16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
if (strncasecmp (*strp, "%lo(", 4) == 0)
|
||||
{
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
value = (-value) & 0xffff;
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return parse_mimm (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* -- */
|
||||
631
cpu/iq2000m.cpu
631
cpu/iq2000m.cpu
@@ -1,631 +0,0 @@
|
||||
; IQ2000-only CPU description. -*- Scheme -*-
|
||||
;
|
||||
; Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc.
|
||||
;
|
||||
; Contributed by Red Hat Inc; developed under contract from Vitesse.
|
||||
;
|
||||
; This file is part of the GNU Binutils.
|
||||
;
|
||||
; This program is free software; you can redistribute it and/or modify
|
||||
; it under the terms of the GNU General Public License as published by
|
||||
; the Free Software Foundation; either version 3 of the License, or
|
||||
; (at your option) any later version.
|
||||
;
|
||||
; This program is distributed in the hope that it will be useful,
|
||||
; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; GNU General Public License for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with this program; if not, write to the Free Software
|
||||
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
; MA 02110-1301, USA.
|
||||
|
||||
(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT)
|
||||
"andoui $rt,$rs,$hi16"
|
||||
(+ OP_ANDOUI rs rt hi16)
|
||||
(set rt (and rs (or (sll hi16 16) #xFFFF)))
|
||||
())
|
||||
|
||||
(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
|
||||
"andoui ${rt-rs},$hi16"
|
||||
(+ OP_ANDOUI rt-rs hi16)
|
||||
(set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF)))
|
||||
())
|
||||
|
||||
(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT)
|
||||
"orui ${rt-rs},$hi16"
|
||||
(+ OP_ORUI rt-rs hi16)
|
||||
(set rt-rs (or rt-rs (sll hi16 16)))
|
||||
())
|
||||
|
||||
(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT)
|
||||
"orui $rt,$rs,$hi16"
|
||||
(+ OP_ORUI rs rt hi16)
|
||||
(set rt (or rs (sll hi16 16)))
|
||||
())
|
||||
|
||||
(dni bgtz "branch if greater than zero" (MACH2000 USES-RS)
|
||||
"bgtz $rs,$offset"
|
||||
(+ OP_BGTZ rs (f-rt 0) offset)
|
||||
(if (gt rs 0)
|
||||
(delay 1 (set pc offset)))
|
||||
())
|
||||
|
||||
|
||||
(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS)
|
||||
"bgtzl $rs,$offset"
|
||||
(+ OP_BGTZL rs (f-rt 0) offset)
|
||||
(if (gt rs 0)
|
||||
(delay 1 (set pc offset))
|
||||
(skip 1))
|
||||
())
|
||||
|
||||
(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS)
|
||||
"blez $rs,$offset"
|
||||
(+ OP_BLEZ rs (f-rt 0) offset)
|
||||
(if (le rs 0)
|
||||
(delay 1 (set pc offset)))
|
||||
())
|
||||
|
||||
(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS)
|
||||
"blezl $rs,$offset"
|
||||
(+ OP_BLEZL rs (f-rt 0) offset)
|
||||
(if (le rs 0)
|
||||
(delay 1 (set pc offset))
|
||||
(skip 1))
|
||||
())
|
||||
|
||||
|
||||
(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT)
|
||||
"mrgb $rd,$rs,$rt,$mask"
|
||||
(+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB)
|
||||
(sequence ((SI temp))
|
||||
(if (bitclear? mask 0)
|
||||
(set temp (and rs #xFF))
|
||||
(set temp (and rt #xFF)))
|
||||
(if (bitclear? mask 1)
|
||||
(set temp (or temp (and rs #xFF00)))
|
||||
(set temp (or temp (and rt #xFF00))))
|
||||
(if (bitclear? mask 2)
|
||||
(set temp (or temp (and rs #xFF0000)))
|
||||
(set temp (or temp (and rt #xFF0000))))
|
||||
(if (bitclear? mask 3)
|
||||
(set temp (or temp (and rs #xFF000000)))
|
||||
(set temp (or temp (and rt #xFF000000))))
|
||||
(set rd temp))
|
||||
())
|
||||
|
||||
(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT)
|
||||
"mrgb ${rd-rs},$rt,$mask"
|
||||
(+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB)
|
||||
(sequence ((SI temp))
|
||||
(if (bitclear? mask 0)
|
||||
(set temp (and rd-rs #xFF))
|
||||
(set temp (and rt #xFF)))
|
||||
(if (bitclear? mask 1)
|
||||
(set temp (or temp (and rd-rs #xFF00)))
|
||||
(set temp (or temp (and rt #xFF00))))
|
||||
(if (bitclear? mask 2)
|
||||
(set temp (or temp (and rd-rs #xFF0000)))
|
||||
(set temp (or temp (and rt #xFF0000))))
|
||||
(if (bitclear? mask 3)
|
||||
(set temp (or temp (and rd-rs #xFF000000)))
|
||||
(set temp (or temp (and rt #xFF000000))))
|
||||
(set rd-rs temp))
|
||||
())
|
||||
|
||||
; NOTE: None of these instructions' semantics are specified, so they
|
||||
; will not work in a simulator.
|
||||
;
|
||||
; Architectural and coprocessor instructions.
|
||||
; BREAK and SYSCALL are implemented with escape hatches to the C
|
||||
; code. These are used by the test suite to indicate pass/failures.
|
||||
|
||||
(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS)
|
||||
"bctxt $rs,$offset"
|
||||
(+ OP_REGIMM rs (f-rt 6) offset)
|
||||
(unimp bctxt)
|
||||
())
|
||||
|
||||
(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI)
|
||||
"bc0f $offset"
|
||||
(+ OP_COP0 (f-rs 8) (f-rt 0) offset)
|
||||
(unimp bc0f)
|
||||
())
|
||||
|
||||
(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
|
||||
"bc0fl $offset"
|
||||
(+ OP_COP0 (f-rs 8) (f-rt 2) offset)
|
||||
(unimp bc0fl)
|
||||
())
|
||||
|
||||
(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI)
|
||||
"bc3f $offset"
|
||||
(+ OP_COP3 (f-rs 8) (f-rt 0) offset)
|
||||
(unimp bc3f)
|
||||
())
|
||||
|
||||
(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
|
||||
"bc3fl $offset"
|
||||
(+ OP_COP3 (f-rs 8) (f-rt 2) offset)
|
||||
(unimp bc3fl)
|
||||
())
|
||||
|
||||
(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI)
|
||||
"bc0t $offset"
|
||||
(+ OP_COP0 (f-rs 8) (f-rt 1) offset)
|
||||
(unimp bc0t)
|
||||
())
|
||||
|
||||
(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
|
||||
"bc0tl $offset"
|
||||
(+ OP_COP0 (f-rs 8) (f-rt 3) offset)
|
||||
(unimp bc0tl)
|
||||
())
|
||||
|
||||
(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI)
|
||||
"bc3t $offset"
|
||||
(+ OP_COP3 (f-rs 8) (f-rt 1) offset)
|
||||
(unimp bc3t)
|
||||
())
|
||||
|
||||
(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI)
|
||||
"bc3tl $offset"
|
||||
(+ OP_COP3 (f-rs 8) (f-rt 3) offset)
|
||||
(unimp bc3tl)
|
||||
())
|
||||
|
||||
; Note that we don't set the USES-RD or USES-RT attributes for many of the following
|
||||
; instructions, as it's the COP register that's being specified.
|
||||
|
||||
(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
|
||||
"cfc0 $rt,$rd"
|
||||
(+ OP_COP0 (f-rs 2) rt rd (f-10-11 0))
|
||||
(unimp cfc0)
|
||||
())
|
||||
|
||||
(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
|
||||
"cfc1 $rt,$rd"
|
||||
(+ OP_COP1 (f-rs 2) rt rd (f-10-11 0))
|
||||
(unimp cfc1)
|
||||
())
|
||||
|
||||
(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
|
||||
"cfc2 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 2) rt rd (f-10-11 0))
|
||||
(unimp cfc2)
|
||||
())
|
||||
|
||||
(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
|
||||
"cfc3 $rt,$rd"
|
||||
(+ OP_COP3 (f-rs 2) rt rd (f-10-11 0))
|
||||
(unimp cfc3)
|
||||
())
|
||||
|
||||
; COPz instructions are an instruction form, not real instructions
|
||||
; with associated assembly mnemonics. Therefore, they are omitted
|
||||
; from the ISA description.
|
||||
|
||||
(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN)
|
||||
"chkhdr $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0))
|
||||
(unimp chkhdr)
|
||||
())
|
||||
|
||||
(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT)
|
||||
"ctc0 $rt,$rd"
|
||||
(+ OP_COP0 (f-rs 6) rt rd (f-10-11 0))
|
||||
(unimp ctc0)
|
||||
())
|
||||
|
||||
(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT)
|
||||
"ctc1 $rt,$rd"
|
||||
(+ OP_COP1 (f-rs 6) rt rd (f-10-11 0))
|
||||
(unimp ctc1)
|
||||
())
|
||||
|
||||
(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT)
|
||||
"ctc2 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 6) rt rd (f-10-11 0))
|
||||
(unimp ctc2)
|
||||
())
|
||||
|
||||
(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT)
|
||||
"ctc3 $rt,$rd"
|
||||
(+ OP_COP3 (f-rs 6) rt rd (f-10-11 0))
|
||||
(unimp ctc3)
|
||||
())
|
||||
|
||||
(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS)
|
||||
"jcr $rs"
|
||||
(+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR)
|
||||
(unimp jcr)
|
||||
())
|
||||
|
||||
(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"luc32 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
|
||||
(unimp luc32)
|
||||
())
|
||||
|
||||
(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"luc32l $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
|
||||
(unimp luc32l)
|
||||
())
|
||||
|
||||
(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"luc64 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11))
|
||||
(unimp luc64)
|
||||
())
|
||||
|
||||
(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"luc64l $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15))
|
||||
(unimp luc64l)
|
||||
())
|
||||
|
||||
(dni luk "lookup key" (MACH2000 USES-RD USES-RT)
|
||||
"luk $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8))
|
||||
(unimp luk)
|
||||
())
|
||||
|
||||
(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"lulck $rt"
|
||||
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4))
|
||||
(unimp lulck)
|
||||
())
|
||||
|
||||
(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lum32 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
|
||||
(unimp lum32)
|
||||
())
|
||||
|
||||
(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lum32l $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
|
||||
(unimp lum32l)
|
||||
())
|
||||
|
||||
(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lum64 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10))
|
||||
(unimp lum64)
|
||||
())
|
||||
|
||||
(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lum64l $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14))
|
||||
(unimp lum64l)
|
||||
())
|
||||
|
||||
(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lur $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
|
||||
(unimp lur)
|
||||
())
|
||||
|
||||
(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"lurl $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5))
|
||||
(unimp lurl)
|
||||
())
|
||||
|
||||
(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"luulck $rt"
|
||||
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0))
|
||||
(unimp luulck)
|
||||
())
|
||||
|
||||
(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT)
|
||||
"mfc0 $rt,$rd"
|
||||
(+ OP_COP0 (f-rs 0) rt rd (f-10-11 0))
|
||||
(unimp mfc0)
|
||||
())
|
||||
|
||||
(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT)
|
||||
"mfc1 $rt,$rd"
|
||||
(+ OP_COP1 (f-rs 0) rt rd (f-10-11 0))
|
||||
(unimp mfc1)
|
||||
())
|
||||
|
||||
(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
|
||||
"mfc2 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 0) rt rd (f-10-11 0))
|
||||
(unimp mfc2)
|
||||
())
|
||||
|
||||
(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN)
|
||||
"mfc3 $rt,$rd"
|
||||
(+ OP_COP3 (f-rs 0) rt rd (f-10-11 0))
|
||||
(unimp mfc3)
|
||||
())
|
||||
|
||||
(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT)
|
||||
"mtc0 $rt,$rd"
|
||||
(+ OP_COP0 (f-rs 4) rt rd (f-10-11 0))
|
||||
(unimp mtc0)
|
||||
())
|
||||
|
||||
(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT)
|
||||
"mtc1 $rt,$rd"
|
||||
(+ OP_COP1 (f-rs 4) rt rd (f-10-11 0))
|
||||
(unimp mtc1)
|
||||
())
|
||||
|
||||
(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT)
|
||||
"mtc2 $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 4) rt rd (f-10-11 0))
|
||||
(unimp mtc2)
|
||||
())
|
||||
|
||||
(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT)
|
||||
"mtc3 $rt,$rd"
|
||||
(+ OP_COP3 (f-rs 4) rt rd (f-10-11 0))
|
||||
(unimp mtc3)
|
||||
())
|
||||
|
||||
(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"pkrl $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7))
|
||||
(unimp pkrl)
|
||||
())
|
||||
|
||||
(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN)
|
||||
"pkrlr1 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 29) rt count _index)
|
||||
(unimp pkrlr1)
|
||||
())
|
||||
|
||||
(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN)
|
||||
"pkrlr30 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 31) rt count _index)
|
||||
(unimp pkrlr30)
|
||||
())
|
||||
|
||||
(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"rb $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4))
|
||||
(unimp rb)
|
||||
())
|
||||
|
||||
(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN)
|
||||
"rbr1 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 24) rt count _index)
|
||||
(unimp rbr1)
|
||||
())
|
||||
|
||||
(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN)
|
||||
"rbr30 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 26) rt count _index)
|
||||
(unimp rbr30)
|
||||
())
|
||||
|
||||
(dni rfe "restore from exception" (MACH2000)
|
||||
"rfe"
|
||||
(+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16))
|
||||
(unimp rfe)
|
||||
())
|
||||
|
||||
(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"rx $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6))
|
||||
(unimp rx)
|
||||
())
|
||||
|
||||
(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN)
|
||||
"rxr1 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 28) rt count _index)
|
||||
(unimp rxr1)
|
||||
())
|
||||
|
||||
(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN)
|
||||
"rxr30 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 30) rt count _index)
|
||||
(unimp rxr30)
|
||||
())
|
||||
|
||||
(dni sleep "sleep" (MACH2000 YIELD-INSN)
|
||||
"sleep"
|
||||
(+ OP_SPECIAL execode FUNC_SLEEP)
|
||||
(unimp sleep)
|
||||
())
|
||||
|
||||
(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN)
|
||||
"srrd $rt"
|
||||
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16))
|
||||
(unimp srrd)
|
||||
())
|
||||
|
||||
(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"srrdl $rt"
|
||||
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20))
|
||||
(unimp srrdl)
|
||||
())
|
||||
|
||||
(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"srulck $rt"
|
||||
(+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22))
|
||||
(unimp srulck)
|
||||
())
|
||||
|
||||
(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"srwr $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17))
|
||||
(unimp srwr)
|
||||
())
|
||||
|
||||
(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"srwru $rt,$rd"
|
||||
(+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21))
|
||||
(unimp srwru)
|
||||
())
|
||||
|
||||
(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN)
|
||||
"trapqfl"
|
||||
(+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8))
|
||||
(unimp trapqfl)
|
||||
())
|
||||
|
||||
(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN)
|
||||
"trapqne"
|
||||
(+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9))
|
||||
(unimp trapqne)
|
||||
())
|
||||
|
||||
(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN)
|
||||
"traprel $rt"
|
||||
(+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10))
|
||||
(unimp traprel)
|
||||
())
|
||||
|
||||
(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"wb $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0))
|
||||
(unimp wb)
|
||||
())
|
||||
|
||||
(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"wbu $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1))
|
||||
(unimp wbu)
|
||||
())
|
||||
|
||||
(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wbr1 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 16) rt count _index)
|
||||
(unimp wbr1)
|
||||
())
|
||||
|
||||
(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wbr1u $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 17) rt count _index)
|
||||
(unimp wbr1u)
|
||||
())
|
||||
|
||||
(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wbr30 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 18) rt count _index)
|
||||
(unimp wbr30)
|
||||
())
|
||||
|
||||
(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wbr30u $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 19) rt count _index)
|
||||
(unimp wbr30u)
|
||||
())
|
||||
|
||||
(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"wx $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2))
|
||||
(unimp wx)
|
||||
())
|
||||
|
||||
(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN)
|
||||
"wxu $rd,$rt"
|
||||
(+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3))
|
||||
(unimp wxu)
|
||||
())
|
||||
|
||||
(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wxr1 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 20) rt count _index)
|
||||
(unimp wxr1)
|
||||
())
|
||||
|
||||
(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wxr1u $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 21) rt count _index)
|
||||
(unimp wxr1u)
|
||||
())
|
||||
|
||||
(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wxr30 $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 22) rt count _index)
|
||||
(unimp wxr30)
|
||||
())
|
||||
|
||||
(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN)
|
||||
"wxr30u $rt,$_index,$count"
|
||||
(+ OP_COP3 (f-rs 23) rt count _index)
|
||||
(unimp wxr30u)
|
||||
())
|
||||
|
||||
|
||||
; Load/Store instructions.
|
||||
|
||||
(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT)
|
||||
"ldw $rt,$lo16($base)"
|
||||
(+ OP_LDW base rt lo16)
|
||||
(sequence ((SI addr))
|
||||
(set addr (and (add base lo16) (inv 3)))
|
||||
(set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr))
|
||||
(set rt (mem SI (add addr 4))))
|
||||
())
|
||||
|
||||
(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT)
|
||||
"sdw $rt,$lo16($base)"
|
||||
(+ OP_SDW base rt lo16)
|
||||
(sequence ((SI addr))
|
||||
(set addr (and (add base lo16) (inv 3)))
|
||||
(set (mem SI (add addr 4)) rt)
|
||||
(set (mem SI addr) (reg h-gr (add (ifield f-rt) 1))))
|
||||
())
|
||||
|
||||
|
||||
; Jump instructions
|
||||
|
||||
(dni j "jump" (MACH2000)
|
||||
"j $jmptarg"
|
||||
(+ OP_J (f-rsrvd 0) jmptarg)
|
||||
(delay 1 (set pc jmptarg))
|
||||
())
|
||||
|
||||
(dni jal "jump and link" (MACH2000 USES-R31)
|
||||
"jal $jmptarg"
|
||||
(+ OP_JAL (f-rsrvd 0) jmptarg)
|
||||
(delay 1
|
||||
(sequence ()
|
||||
(set (reg h-gr 31) (add pc 8))
|
||||
(set pc jmptarg)))
|
||||
())
|
||||
|
||||
(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT)
|
||||
"bmb $rs,$rt,$offset"
|
||||
(+ OP_BMB rs rt offset)
|
||||
(sequence ((BI branch?))
|
||||
(set branch? 0)
|
||||
(if (eq (and rs #xFF) (and rt #xFF))
|
||||
(set branch? 1))
|
||||
(if (eq (and rs #xFF00) (and rt #xFF00))
|
||||
(set branch? 1))
|
||||
(if (eq (and rs #xFF0000) (and rt #xFF0000))
|
||||
(set branch? 1))
|
||||
(if (eq (and rs #xFF000000) (and rt #xFF000000))
|
||||
(set branch? 1))
|
||||
(if branch?
|
||||
(delay 1 (set pc offset))))
|
||||
())
|
||||
|
||||
|
||||
; Macros
|
||||
|
||||
(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS)
|
||||
"ldw $rt,$lo16"
|
||||
(emit ldw rt lo16 (base 0))
|
||||
)
|
||||
|
||||
(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS)
|
||||
"sdw $rt,$lo16"
|
||||
(emit sdw rt lo16 (base 0))
|
||||
)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
10520
cpu/m32c.cpu
10520
cpu/m32c.cpu
File diff suppressed because it is too large
Load Diff
1187
cpu/m32c.opc
1187
cpu/m32c.opc
File diff suppressed because it is too large
Load Diff
2427
cpu/m32r.cpu
2427
cpu/m32r.cpu
File diff suppressed because it is too large
Load Diff
324
cpu/m32r.opc
324
cpu/m32r.opc
@@ -1,324 +0,0 @@
|
||||
/* M32R opcode support. -*- C -*-
|
||||
|
||||
Copyright 1998, 1999, 2000, 2001, 2004, 2005, 2007
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Red Hat Inc; developed under contract from
|
||||
Mitsubishi Electric Corporation.
|
||||
|
||||
This file is part of the GNU Binutils.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
|
||||
/* This file is an addendum to m32r.cpu. Heavy use of C code isn't
|
||||
appropriate in .cpu files, so it resides here. This especially applies
|
||||
to assembly/disassembly where parsing/printing can be quite involved.
|
||||
Such things aren't really part of the specification of the cpu, per se,
|
||||
so .cpu files provide the general framework and .opc files handle the
|
||||
nitty-gritty details as necessary.
|
||||
|
||||
Each section is delimited with start and end markers.
|
||||
|
||||
<arch>-opc.h additions use: "-- opc.h"
|
||||
<arch>-opc.c additions use: "-- opc.c"
|
||||
<arch>-asm.c additions use: "-- asm.c"
|
||||
<arch>-dis.c additions use: "-- dis.c"
|
||||
<arch>-ibd.h additions use: "-- ibd.h" */
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
#undef CGEN_DIS_HASH_SIZE
|
||||
#define CGEN_DIS_HASH_SIZE 256
|
||||
#undef CGEN_DIS_HASH
|
||||
#if 0
|
||||
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
|
||||
#define CGEN_DIS_HASH(buffer, value) \
|
||||
(X (buffer) | \
|
||||
(X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \
|
||||
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
|
||||
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
|
||||
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
|
||||
#else
|
||||
#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value)
|
||||
extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT);
|
||||
#endif
|
||||
|
||||
/* -- */
|
||||
|
||||
/* -- opc.c */
|
||||
unsigned int
|
||||
m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value)
|
||||
{
|
||||
unsigned int x;
|
||||
|
||||
if (value & 0xffff0000) /* 32bit instructions. */
|
||||
value = (value >> 16) & 0xffff;
|
||||
|
||||
x = (value >> 8) & 0xf0;
|
||||
if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
|
||||
return x;
|
||||
|
||||
if (x == 0x70 || x == 0xf0)
|
||||
return x | ((value >> 8) & 0x0f);
|
||||
|
||||
if (x == 0x30)
|
||||
return x | ((value & 0x70) >> 4);
|
||||
else
|
||||
return x | ((value & 0xf0) >> 4);
|
||||
}
|
||||
|
||||
/* -- */
|
||||
|
||||
/* -- asm.c */
|
||||
static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
|
||||
|
||||
/* Handle '#' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (**strp == '#')
|
||||
++*strp;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Handle shigh(), high(). */
|
||||
|
||||
static const char *
|
||||
parse_hi16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
if (**strp == '#')
|
||||
++*strp;
|
||||
|
||||
if (strncasecmp (*strp, "high(", 5) == 0)
|
||||
{
|
||||
*strp += 5;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
{
|
||||
value >>= 16;
|
||||
value &= 0xffff;
|
||||
}
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
else if (strncasecmp (*strp, "shigh(", 6) == 0)
|
||||
{
|
||||
*strp += 6;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
{
|
||||
value += 0x8000;
|
||||
value >>= 16;
|
||||
value &= 0xffff;
|
||||
}
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* Handle low() in a signed context. Also handle sda().
|
||||
The signedness of the value doesn't matter to low(), but this also
|
||||
handles the case where low() isn't present. */
|
||||
|
||||
static const char *
|
||||
parse_slo16 (CGEN_CPU_DESC cd,
|
||||
const char ** strp,
|
||||
int opindex,
|
||||
long * valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
if (**strp == '#')
|
||||
++*strp;
|
||||
|
||||
if (strncasecmp (*strp, "low(", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
value = ((value & 0xffff) ^ 0x8000) - 0x8000;
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
if (strncasecmp (*strp, "sda(", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
|
||||
NULL, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return cgen_parse_signed_integer (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* Handle low() in an unsigned context.
|
||||
The signedness of the value doesn't matter to low(), but this also
|
||||
handles the case where low() isn't present. */
|
||||
|
||||
static const char *
|
||||
parse_ulo16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
if (**strp == '#')
|
||||
++*strp;
|
||||
|
||||
if (strncasecmp (*strp, "low(", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
|
||||
& result_type, & value);
|
||||
if (**strp != ')')
|
||||
return MISSING_CLOSING_PARENTHESIS;
|
||||
++*strp;
|
||||
if (errmsg == NULL
|
||||
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
|
||||
value &= 0xffff;
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
}
|
||||
|
||||
/* -- */
|
||||
|
||||
/* -- dis.c */
|
||||
/* Immediate values are prefixed with '#'. */
|
||||
|
||||
#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
|
||||
do \
|
||||
{ \
|
||||
if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \
|
||||
(*info->fprintf_func) (info->stream, "#"); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Handle '#' prefixes as operands. */
|
||||
|
||||
static void
|
||||
print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
(*info->fprintf_func) (info->stream, "#");
|
||||
}
|
||||
|
||||
#undef CGEN_PRINT_INSN
|
||||
#define CGEN_PRINT_INSN my_print_insn
|
||||
|
||||
static int
|
||||
my_print_insn (CGEN_CPU_DESC cd,
|
||||
bfd_vma pc,
|
||||
disassemble_info *info)
|
||||
{
|
||||
bfd_byte buffer[CGEN_MAX_INSN_SIZE];
|
||||
bfd_byte *buf = buffer;
|
||||
int status;
|
||||
int buflen = (pc & 3) == 0 ? 4 : 2;
|
||||
int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
|
||||
bfd_byte *x;
|
||||
|
||||
/* Read the base part of the insn. */
|
||||
|
||||
status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
|
||||
buf, buflen, info);
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* 32 bit insn? */
|
||||
x = (big_p ? &buf[0] : &buf[3]);
|
||||
if ((pc & 3) == 0 && (*x & 0x80) != 0)
|
||||
return print_insn (cd, pc, info, buf, buflen);
|
||||
|
||||
/* Print the first insn. */
|
||||
if ((pc & 3) == 0)
|
||||
{
|
||||
buf += (big_p ? 0 : 2);
|
||||
if (print_insn (cd, pc, info, buf, 2) == 0)
|
||||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||||
buf += (big_p ? 2 : -2);
|
||||
}
|
||||
|
||||
x = (big_p ? &buf[0] : &buf[1]);
|
||||
if (*x & 0x80)
|
||||
{
|
||||
/* Parallel. */
|
||||
(*info->fprintf_func) (info->stream, " || ");
|
||||
*x &= 0x7f;
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, " -> ");
|
||||
|
||||
/* The "& 3" is to pass a consistent address.
|
||||
Parallel insns arguably both begin on the word boundary.
|
||||
Also, branch insns are calculated relative to the word boundary. */
|
||||
if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
|
||||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||||
|
||||
return (pc & 3) ? 2 : 4;
|
||||
}
|
||||
|
||||
/* -- */
|
||||
1352
cpu/mt.cpu
1352
cpu/mt.cpu
File diff suppressed because it is too large
Load Diff
472
cpu/mt.opc
472
cpu/mt.opc
@@ -1,472 +0,0 @@
|
||||
/* Morpho Technologies mRISC opcode support, for GNU Binutils. -*- C -*-
|
||||
Copyright 2001, 2007, 2008 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Red Hat Inc; developed under contract from
|
||||
Morpho Technologies.
|
||||
|
||||
This file is part of the GNU Binutils.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
|
||||
/* Each section is delimited with start and end markers.
|
||||
|
||||
<arch>-opc.h additions use: "-- opc.h"
|
||||
<arch>-opc.c additions use: "-- opc.c"
|
||||
<arch>-asm.c additions use: "-- asm.c"
|
||||
<arch>-dis.c additions use: "-- dis.c"
|
||||
<arch>-ibd.h additions use: "-- ibd.h" */
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
/* Check applicability of instructions against machines. */
|
||||
#define CGEN_VALIDATE_INSN_SUPPORTED
|
||||
|
||||
/* Allows reason codes to be output when assembler errors occur. */
|
||||
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||
|
||||
/* Override disassembly hashing - there are variable bits in the top
|
||||
byte of these instructions. */
|
||||
#define CGEN_DIS_HASH_SIZE 8
|
||||
#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE)
|
||||
|
||||
#define CGEN_ASM_HASH_SIZE 127
|
||||
#define CGEN_ASM_HASH(insn) mt_asm_hash (insn)
|
||||
|
||||
extern unsigned int mt_asm_hash (const char *);
|
||||
|
||||
extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *);
|
||||
|
||||
|
||||
/* -- opc.c */
|
||||
#include "safe-ctype.h"
|
||||
|
||||
/* Special check to ensure that instruction exists for given machine. */
|
||||
|
||||
int
|
||||
mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn)
|
||||
{
|
||||
int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
|
||||
|
||||
/* No mach attribute? Assume it's supported for all machs. */
|
||||
if (machs == 0)
|
||||
return 1;
|
||||
|
||||
return ((machs & cd->machs) != 0);
|
||||
}
|
||||
|
||||
/* A better hash function for instruction mnemonics. */
|
||||
|
||||
unsigned int
|
||||
mt_asm_hash (const char* insn)
|
||||
{
|
||||
unsigned int hash;
|
||||
const char* m = insn;
|
||||
|
||||
for (hash = 0; *m && ! ISSPACE (*m); m++)
|
||||
hash = (hash * 23) ^ (0x1F & TOLOWER (*m));
|
||||
|
||||
/* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */
|
||||
|
||||
return hash % CGEN_ASM_HASH_SIZE;
|
||||
}
|
||||
|
||||
|
||||
/* -- asm.c */
|
||||
/* Range checking for signed numbers. Returns 0 if acceptable
|
||||
and 1 if the value is out of bounds for a signed quantity. */
|
||||
|
||||
static int
|
||||
signed_out_of_bounds (long val)
|
||||
{
|
||||
if ((val < -32768) || (val > 32767))
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_loopsize (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
void *arg)
|
||||
{
|
||||
signed long * valuep = (signed long *) arg;
|
||||
const char *errmsg;
|
||||
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_vma value;
|
||||
|
||||
/* Is it a control transfer instructions? */
|
||||
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE)
|
||||
{
|
||||
code = BFD_RELOC_MT_PCINSN8;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, code,
|
||||
& result_type, & value);
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
abort ();
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_imm16 (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
void *arg)
|
||||
{
|
||||
signed long * valuep = (signed long *) arg;
|
||||
const char *errmsg;
|
||||
enum cgen_parse_operand_result result_type;
|
||||
bfd_reloc_code_real_type code = BFD_RELOC_NONE;
|
||||
bfd_vma value;
|
||||
|
||||
/* Is it a control transfer instructions? */
|
||||
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O)
|
||||
{
|
||||
code = BFD_RELOC_16_PCREL;
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, code,
|
||||
& result_type, & value);
|
||||
if (errmsg == NULL)
|
||||
{
|
||||
if (signed_out_of_bounds (value))
|
||||
errmsg = _("Operand out of range. Must be between -32768 and 32767.");
|
||||
}
|
||||
*valuep = value;
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* If it's not a control transfer instruction, then
|
||||
we have to check for %OP relocating operators. */
|
||||
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L)
|
||||
;
|
||||
else if (strncmp (*strp, "%hi16", 5) == 0)
|
||||
{
|
||||
*strp += 5;
|
||||
code = BFD_RELOC_HI16;
|
||||
}
|
||||
else if (strncmp (*strp, "%lo16", 5) == 0)
|
||||
{
|
||||
*strp += 5;
|
||||
code = BFD_RELOC_LO16;
|
||||
}
|
||||
|
||||
/* If we found a %OP relocating operator, then parse it as an address.
|
||||
If not, we need to parse it as an integer, either signed or unsigned
|
||||
depending on which operand type we have. */
|
||||
if (code != BFD_RELOC_NONE)
|
||||
{
|
||||
/* %OP relocating operator found. */
|
||||
errmsg = cgen_parse_address (cd, strp, opindex, code,
|
||||
& result_type, & value);
|
||||
if (errmsg == NULL)
|
||||
{
|
||||
switch (result_type)
|
||||
{
|
||||
case (CGEN_PARSE_OPERAND_RESULT_NUMBER):
|
||||
if (code == BFD_RELOC_HI16)
|
||||
value = (value >> 16) & 0xFFFF;
|
||||
else if (code == BFD_RELOC_LO16)
|
||||
value = value & 0xFFFF;
|
||||
else
|
||||
errmsg = _("Biiiig Trouble in parse_imm16!");
|
||||
break;
|
||||
|
||||
case (CGEN_PARSE_OPERAND_RESULT_QUEUED):
|
||||
/* No special processing for this case. */
|
||||
break;
|
||||
|
||||
default:
|
||||
errmsg = _("The percent-operator's operand is not a symbol");
|
||||
break;
|
||||
}
|
||||
}
|
||||
*valuep = value;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Parse hex values like 0xffff as unsigned, and sign extend
|
||||
them manually. */
|
||||
int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16);
|
||||
|
||||
if ((*strp)[0] == '0'
|
||||
&& ((*strp)[1] == 'x' || (*strp)[1] == 'X'))
|
||||
parse_signed = 0;
|
||||
|
||||
/* No relocating operator. Parse as an number. */
|
||||
if (parse_signed)
|
||||
{
|
||||
/* Parse as as signed integer. */
|
||||
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
|
||||
|
||||
if (errmsg == NULL)
|
||||
{
|
||||
#if 0
|
||||
/* Manual range checking is needed for the signed case. */
|
||||
if (*valuep & 0x8000)
|
||||
value = 0xffff0000 | *valuep;
|
||||
else
|
||||
value = *valuep;
|
||||
|
||||
if (signed_out_of_bounds (value))
|
||||
errmsg = _("Operand out of range. Must be between -32768 and 32767.");
|
||||
/* Truncate to 16 bits. This is necessary
|
||||
because cgen will have sign extended *valuep. */
|
||||
*valuep &= 0xFFFF;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep);
|
||||
|
||||
if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16
|
||||
&& *valuep >= 0x8000
|
||||
&& *valuep <= 0xffff)
|
||||
*valuep -= 0x10000;
|
||||
}
|
||||
}
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
|
||||
static const char *
|
||||
parse_dup (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 0;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
|
||||
static const char *
|
||||
parse_ball (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 0;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_xmode (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 0;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_rc (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0)
|
||||
{
|
||||
*strp += 1;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0)
|
||||
{
|
||||
*strp += 1;
|
||||
*valuep = 0;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_cbrb (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 0;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_rbbc (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 0;
|
||||
}
|
||||
else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 2;
|
||||
}
|
||||
else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 3;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_type (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
int opindex,
|
||||
unsigned long *valuep)
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0)
|
||||
{
|
||||
*strp += 3;
|
||||
*valuep = 0;
|
||||
}
|
||||
else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
*valuep = 1;
|
||||
}
|
||||
else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0)
|
||||
{
|
||||
*strp += 2;
|
||||
*valuep = 2;
|
||||
}
|
||||
else
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
|
||||
|
||||
if ((errmsg == NULL) && (*valuep == 3))
|
||||
errmsg = _("invalid operand. type may have values 0,1,2 only.");
|
||||
|
||||
return errmsg;
|
||||
}
|
||||
|
||||
/* -- dis.c */
|
||||
static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
|
||||
static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int);
|
||||
|
||||
static void
|
||||
print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
info->fprintf_func (info->stream, "$%lx", value);
|
||||
|
||||
if (0)
|
||||
print_normal (cd, dis_info, value, attrs, pc, length);
|
||||
}
|
||||
|
||||
static void
|
||||
print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
print_address (cd, dis_info, value + pc, attrs, pc, length);
|
||||
}
|
||||
|
||||
/* -- */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
369
cpu/sh.cpu
369
cpu/sh.cpu
@@ -1,369 +0,0 @@
|
||||
; Hitachi SH architecture description. -*- Scheme -*-
|
||||
;
|
||||
; Copyright 2000, 2001, 2007 Free Software Foundation, Inc.
|
||||
;
|
||||
; Contributed by Red Hat Inc; developed under contract from Hitachi
|
||||
; Semiconductor (America) Inc.
|
||||
;
|
||||
; This file is part of the GNU Binutils.
|
||||
;
|
||||
; This program is free software; you can redistribute it and/or modify
|
||||
; it under the terms of the GNU General Public License as published by
|
||||
; the Free Software Foundation; either version 3 of the License, or
|
||||
; (at your option) any later version.
|
||||
;
|
||||
; This program is distributed in the hope that it will be useful,
|
||||
; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; GNU General Public License for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with this program; if not, write to the Free Software
|
||||
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
; MA 02110-1301, USA.
|
||||
|
||||
|
||||
(include "simplify.inc")
|
||||
|
||||
(define-arch
|
||||
(name sh)
|
||||
(comment "Hitachi SuperH (SH)")
|
||||
(insn-lsb0? #t)
|
||||
(machs sh2 sh3 sh3e sh4 sh5)
|
||||
(isas compact media)
|
||||
)
|
||||
|
||||
|
||||
; Instruction sets.
|
||||
|
||||
(define-isa
|
||||
(name media)
|
||||
(comment "SHmedia 32-bit instruction set")
|
||||
(base-insn-bitsize 32)
|
||||
)
|
||||
|
||||
(define-isa
|
||||
(name compact)
|
||||
(comment "SHcompact 16-bit instruction set")
|
||||
(base-insn-bitsize 16)
|
||||
)
|
||||
|
||||
|
||||
; CPU family.
|
||||
|
||||
(define-cpu
|
||||
(name sh64)
|
||||
(comment "SH 64-bit family")
|
||||
(endian either)
|
||||
(word-bitsize 32)
|
||||
)
|
||||
|
||||
|
||||
(define-mach
|
||||
(name sh2)
|
||||
(comment "SH-2 CPU core")
|
||||
(cpu sh64)
|
||||
(isas compact)
|
||||
)
|
||||
|
||||
(define-mach
|
||||
(name sh3)
|
||||
(comment "SH-3 CPU core")
|
||||
(cpu sh64)
|
||||
(isas compact)
|
||||
)
|
||||
|
||||
(define-mach
|
||||
(name sh3e)
|
||||
(comment "SH-3e CPU core")
|
||||
(cpu sh64)
|
||||
(isas compact)
|
||||
)
|
||||
|
||||
(define-mach
|
||||
(name sh4)
|
||||
(comment "SH-4 CPU core")
|
||||
(cpu sh64)
|
||||
(isas compact)
|
||||
)
|
||||
|
||||
(define-mach
|
||||
(name sh5)
|
||||
(comment "SH-5 CPU core")
|
||||
(cpu sh64)
|
||||
(isas compact media)
|
||||
)
|
||||
|
||||
(define-model
|
||||
(name sh5)
|
||||
(comment "SH-5 reference implementation")
|
||||
(mach sh5)
|
||||
(unit u-exec "Execution unit" ()
|
||||
1 1 ; issue done
|
||||
() () () ())
|
||||
)
|
||||
|
||||
; Hardware elements.
|
||||
|
||||
(define-hardware
|
||||
(name h-pc)
|
||||
(comment "Program counter")
|
||||
(attrs PC (ISA compact,media))
|
||||
(type pc UDI)
|
||||
(get () (raw-reg h-pc))
|
||||
(set (newval) (sequence ()
|
||||
(set (raw-reg h-ism) (and newval 1))
|
||||
(set (raw-reg h-pc) (and newval (inv UDI 1)))))
|
||||
)
|
||||
|
||||
(define-pmacro (-build-greg-name n) ((.sym r n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-gr)
|
||||
(comment "General purpose integer registers")
|
||||
(attrs (ISA media,compact))
|
||||
(type register DI (64))
|
||||
(indices keyword "" (.map -build-greg-name (.iota 64)))
|
||||
(get (index)
|
||||
(if DI (eq index 63)
|
||||
(const 0)
|
||||
(raw-reg h-gr index)))
|
||||
(set (index newval)
|
||||
(if (ne index 63)
|
||||
(set (raw-reg h-gr index) newval)
|
||||
(nop)))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-grc)
|
||||
(comment "General purpose integer registers (SHcompact view)")
|
||||
(attrs VIRTUAL (ISA compact))
|
||||
(type register SI (16))
|
||||
(indices keyword "" (.map -build-greg-name (.iota 16)))
|
||||
(get (index)
|
||||
(and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
|
||||
(set (index newval)
|
||||
(set (raw-reg h-gr index) (ext DI newval)))
|
||||
)
|
||||
|
||||
(define-pmacro (-build-creg-name n) ((.sym cr n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-cr)
|
||||
(comment "Control registers")
|
||||
(attrs (ISA media))
|
||||
(type register DI (64))
|
||||
(indices keyword "" (.map -build-creg-name (.iota 64)))
|
||||
(get (index)
|
||||
(if DI (eq index 0)
|
||||
(zext DI (reg h-sr))
|
||||
(raw-reg h-cr index)))
|
||||
(set (index newval)
|
||||
(if (eq index 0)
|
||||
(set (reg h-sr) newval)
|
||||
(set (raw-reg h-cr index) newval)))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-sr)
|
||||
(comment "Status register")
|
||||
(attrs (ISA compact,media))
|
||||
(type register SI)
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-fpscr)
|
||||
(comment "Floating point status and control register")
|
||||
(attrs (ISA compact,media))
|
||||
(type register SI)
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-frbit)
|
||||
(comment "Floating point register file bit")
|
||||
(attrs (ISA media,compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 14) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-szbit)
|
||||
(comment "Floating point transfer size bit")
|
||||
(attrs (ISA media,compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 13) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-prbit)
|
||||
(comment "Floating point precision bit")
|
||||
(attrs (ISA media,compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 12) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-sbit)
|
||||
(comment "Multiply-accumulate saturation flag")
|
||||
(attrs (ISA compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 1) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-mbit)
|
||||
(comment "Divide-step M flag")
|
||||
(attrs (ISA compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 9) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-qbit)
|
||||
(comment "Divide-step Q flag")
|
||||
(attrs (ISA compact) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (and (srl (reg h-sr) 8) 1))
|
||||
(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
|
||||
)
|
||||
|
||||
(define-pmacro (-build-freg-name n) ((.sym fr n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-fr)
|
||||
(comment "Single precision floating point registers")
|
||||
(attrs (ISA media,compact))
|
||||
(type register SF (64))
|
||||
(indices keyword "" (.map -build-freg-name (.iota 64)))
|
||||
)
|
||||
|
||||
|
||||
(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-fp)
|
||||
(comment "Single precision floating point register pairs")
|
||||
(attrs (ISA media,compact))
|
||||
(type register DF (32))
|
||||
(indices keyword "" (.map -build-fpair-name (.iota 32)))
|
||||
)
|
||||
|
||||
(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-fv)
|
||||
(comment "Single precision floating point vectors")
|
||||
(attrs VIRTUAL (ISA media,compact))
|
||||
(type register SF (16))
|
||||
(indices keyword "" (.map -build-fvec-name (.iota 16)))
|
||||
; Mask with $F to ensure 0 <= index < 15.
|
||||
(get (index) (reg h-fr (mul (and UQI index 15) 4)))
|
||||
(set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-fmtx)
|
||||
(comment "Single precision floating point matrices")
|
||||
(attrs VIRTUAL (ISA media))
|
||||
(type register SF (4))
|
||||
(indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
|
||||
; Mask with $3 to ensure 0 <= index < 4.
|
||||
(get (index) (reg h-fr (mul (and UQI index 3) 16)))
|
||||
(set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
|
||||
)
|
||||
|
||||
(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
|
||||
|
||||
(define-hardware
|
||||
(name h-dr)
|
||||
(comment "Double precision floating point registers")
|
||||
(attrs (ISA media,compact) VIRTUAL)
|
||||
(type register DF (32))
|
||||
(indices keyword "" (.map -build-dreg-name (.iota 64)))
|
||||
(get (index)
|
||||
(subword DF
|
||||
(or
|
||||
(sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
|
||||
(zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
|
||||
(set (index newval)
|
||||
(sequence ()
|
||||
(set (reg h-fr index)
|
||||
(subword SF (subword SI newval 0) 0))
|
||||
(set (reg h-fr (add index 1))
|
||||
(subword SF (subword SI newval 1) 0))))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-tr)
|
||||
(comment "Branch target registers")
|
||||
(attrs (ISA media))
|
||||
(type register DI (8))
|
||||
(indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-endian)
|
||||
(comment "Current endian mode")
|
||||
(attrs (ISA compact,media) VIRTUAL)
|
||||
(type register BI)
|
||||
(get () (c-call BI "sh64_endian"))
|
||||
(set (newval) (error "cannot alter target byte order mid-program"))
|
||||
)
|
||||
|
||||
(define-hardware
|
||||
(name h-ism)
|
||||
(comment "Current instruction set mode")
|
||||
(attrs (ISA compact,media))
|
||||
(type register BI)
|
||||
(get () (raw-reg h-ism))
|
||||
(set (newval) (error "cannot set ism directly"))
|
||||
)
|
||||
|
||||
|
||||
; Operands.
|
||||
|
||||
(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
|
||||
(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
|
||||
|
||||
; Universally useful macros.
|
||||
|
||||
; A pmacro for use in semantic bodies of unimplemented insns.
|
||||
(define-pmacro (unimp mnemonic) (nop))
|
||||
|
||||
; Join 2 ints together in natural bit order.
|
||||
(define-pmacro (-join-si s1 s0)
|
||||
(or (sll (zext DI s1) 32)
|
||||
(zext DI s0)))
|
||||
|
||||
; Join 4 half-ints together in natural bit order.
|
||||
(define-pmacro (-join-hi h3 h2 h1 h0)
|
||||
(or (sll (zext DI h3) 48)
|
||||
(or (sll (zext DI h2) 32)
|
||||
(or (sll (zext DI h1) 16)
|
||||
(zext DI h0)))))
|
||||
|
||||
; Join 8 quarter-ints together in natural bit order.
|
||||
(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
|
||||
(or (sll (zext DI b7) 56)
|
||||
(or (sll (zext DI b6) 48)
|
||||
(or (sll (zext DI b5) 40)
|
||||
(or (sll (zext DI b4) 32)
|
||||
(or (sll (zext DI b3) 24)
|
||||
(or (sll (zext DI b2) 16)
|
||||
(or (sll (zext DI b1) 8)
|
||||
(zext DI b0)))))))))
|
||||
|
||||
|
||||
; Include the two instruction set descriptions from their respective
|
||||
; source files.
|
||||
|
||||
(if (keep-isa? (compact))
|
||||
(include "sh64-compact.cpu"))
|
||||
|
||||
(if (keep-isa? (media))
|
||||
(include "sh64-media.cpu"))
|
||||
77
cpu/sh.opc
77
cpu/sh.opc
@@ -1,77 +0,0 @@
|
||||
/* SHmedia opcode support. -*- C -*-
|
||||
|
||||
Copyright 2000, 2005, 2007 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Red Hat Inc; developed under contract from Hitachi
|
||||
Semiconductor (America) Inc.
|
||||
|
||||
This file is part of the GNU Binutils.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
|
||||
/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't
|
||||
appropriate in .cpu files, so it resides here. This especially applies
|
||||
to assembly/disassembly where parsing/printing can be quite involved.
|
||||
Such things aren't really part of the specification of the cpu, per se,
|
||||
so .cpu files provide the general framework and .opc files handle the
|
||||
nitty-gritty details as necessary.
|
||||
|
||||
Each section is delimited with start and end markers.
|
||||
|
||||
<arch>-opc.h additions use: "-- opc.h"
|
||||
<arch>-opc.c additions use: "-- opc.c"
|
||||
<arch>-asm.c additions use: "-- asm.c"
|
||||
<arch>-dis.c additions use: "-- dis.c"
|
||||
<arch>-ibd.h additions use: "-- ibd.h" */
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
/* Allows reason codes to be output when assembler errors occur. */
|
||||
#define CGEN_VERBOSE_ASSEMBLER_ERRORS
|
||||
|
||||
/* Override disassembly hashing - there are variable bits in the top
|
||||
byte of these instructions. */
|
||||
#define CGEN_DIS_HASH_SIZE 8
|
||||
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
|
||||
|
||||
/* -- asm.c */
|
||||
|
||||
static const char *
|
||||
parse_fsd (CGEN_CPU_DESC cd,
|
||||
const char ** strp,
|
||||
int opindex,
|
||||
long * valuep)
|
||||
{
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* -- dis.c */
|
||||
|
||||
static void
|
||||
print_likely (CGEN_CPU_DESC cd,
|
||||
void * dis_info,
|
||||
long value,
|
||||
unsigned int attrs,
|
||||
bfd_vma pc,
|
||||
int length)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
(*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
|
||||
}
|
||||
|
||||
/* -- */
|
||||
1748
cpu/sh64-compact.cpu
1748
cpu/sh64-compact.cpu
File diff suppressed because it is too large
Load Diff
1733
cpu/sh64-media.cpu
1733
cpu/sh64-media.cpu
File diff suppressed because it is too large
Load Diff
216
cpu/simplify.inc
216
cpu/simplify.inc
@@ -1,216 +0,0 @@
|
||||
; Collection of macros, for GNU Binutils .cpu files. -*- Scheme -*-
|
||||
;
|
||||
; Copyright 2000, 2007 Free Software Foundation, Inc.
|
||||
;
|
||||
; Contributed by Red Hat Inc.
|
||||
;
|
||||
; This file is part of the GNU Binutils.
|
||||
;
|
||||
; This program is free software; you can redistribute it and/or modify
|
||||
; it under the terms of the GNU General Public License as published by
|
||||
; the Free Software Foundation; either version 3 of the License, or
|
||||
; (at your option) any later version.
|
||||
;
|
||||
; This program is distributed in the hope that it will be useful,
|
||||
; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; GNU General Public License for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with this program; if not, write to the Free Software
|
||||
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
|
||||
; MA 02110-1301, USA.
|
||||
|
||||
; Enums.
|
||||
|
||||
; Define a normal enum without using name/value pairs.
|
||||
; This is currently the same as define-full-enum but it needn't remain
|
||||
; that way (it's define-full-enum that would change).
|
||||
|
||||
(define-pmacro (define-normal-enum name comment attrs prefix vals)
|
||||
"\
|
||||
Define a normal enum, fixed number of arguments.
|
||||
"
|
||||
(define-full-enum name comment attrs prefix vals)
|
||||
)
|
||||
|
||||
; Define a normal insn enum.
|
||||
|
||||
(define-pmacro (define-normal-insn-enum name comment attrs prefix fld vals)
|
||||
"\
|
||||
Define a normal instruction opcode enum.
|
||||
"
|
||||
(define-full-insn-enum name comment attrs prefix fld vals)
|
||||
)
|
||||
|
||||
; Instruction fields.
|
||||
|
||||
; Normally, fields are unsigned have no encode/decode needs.
|
||||
|
||||
(define-pmacro (define-normal-ifield name comment attrs start length)
|
||||
"Define a normal instruction field.\n"
|
||||
(define-full-ifield name comment attrs start length UINT #f #f)
|
||||
)
|
||||
|
||||
; For those who don't like typing.
|
||||
|
||||
(define-pmacro df
|
||||
"Shorthand form of define-full-ifield.\n"
|
||||
define-full-ifield
|
||||
)
|
||||
(define-pmacro dnf
|
||||
"Shorthand form of define-normal-ifield.\n"
|
||||
define-normal-ifield
|
||||
)
|
||||
|
||||
; Define a normal multi-ifield.
|
||||
; FIXME: The define-normal version for ifields doesn't include the mode.
|
||||
|
||||
(define-pmacro (define-normal-multi-ifield name comment attrs
|
||||
mode subflds insert extract)
|
||||
"Define a normal multi-part instruction field.\n"
|
||||
(define-full-multi-ifield name comment attrs mode subflds insert extract)
|
||||
)
|
||||
|
||||
; For those who don't like typing.
|
||||
|
||||
(define-pmacro dnmf
|
||||
"Shorthand form of define-normal-multi-ifield.\n"
|
||||
define-normal-multi-ifield
|
||||
)
|
||||
|
||||
; Simple multi-ifields: mode is UINT, default insert/extract support.
|
||||
|
||||
(define-pmacro (dsmf name comment attrs subflds)
|
||||
"Define a simple multi-part instruction field.\n"
|
||||
(define-full-multi-ifield name comment attrs UINT subflds #f #f)
|
||||
)
|
||||
|
||||
; Hardware.
|
||||
|
||||
; Simpler version for most hardware elements.
|
||||
; Allow special assembler support specification but no semantic-name or
|
||||
; get/set specs.
|
||||
|
||||
(define-pmacro (define-normal-hardware name comment attrs type
|
||||
indices values handlers)
|
||||
"\
|
||||
Define a normal hardware element.
|
||||
"
|
||||
(define-full-hardware name comment attrs name type
|
||||
indices values handlers () () ())
|
||||
)
|
||||
|
||||
; For those who don't like typing.
|
||||
|
||||
(define-pmacro dnh
|
||||
"Shorthand form of define-normal-hardware.\n"
|
||||
define-normal-hardware
|
||||
)
|
||||
|
||||
; Simpler version of dnh that leaves out the indices, values, handlers,
|
||||
; get, set, and layout specs.
|
||||
; This is useful for 1 bit registers.
|
||||
; ??? While dsh and dnh aren't that distinguishable when perusing a .cpu file,
|
||||
; they both take a fixed number of positional arguments, and dsh is a proper
|
||||
; subset of dnh with all arguments in the same positions, so methinks things
|
||||
; are ok.
|
||||
|
||||
(define-pmacro (define-simple-hardware name comment attrs type)
|
||||
"\
|
||||
Define a simple hardware element (usually a scalar register).
|
||||
"
|
||||
(define-full-hardware name comment attrs name type () () () () () ())
|
||||
)
|
||||
|
||||
(define-pmacro dsh
|
||||
"Shorthand form of define-simple-hardware.\n"
|
||||
define-simple-hardware
|
||||
)
|
||||
|
||||
; Operands.
|
||||
|
||||
(define-pmacro (define-normal-operand name comment attrs type index)
|
||||
"Define a normal operand.\n"
|
||||
(define-full-operand name comment attrs type DFLT index () () ())
|
||||
)
|
||||
|
||||
; For those who don't like typing.
|
||||
; FIXME: dno?
|
||||
|
||||
(define-pmacro dnop
|
||||
"Shorthand form of define-normal-operand.\n"
|
||||
define-normal-operand
|
||||
)
|
||||
|
||||
(define-pmacro (dndo x-name x-mode x-args
|
||||
x-syntax x-base-ifield x-encoding x-ifield-assertion
|
||||
x-getter x-setter)
|
||||
"Define a normal derived operand."
|
||||
(define-derived-operand
|
||||
(name x-name)
|
||||
(mode x-mode)
|
||||
(args x-args)
|
||||
(syntax x-syntax)
|
||||
(base-ifield x-base-ifield)
|
||||
(encoding x-encoding)
|
||||
(ifield-assertion x-ifield-assertion)
|
||||
(getter x-getter)
|
||||
(setter x-setter)
|
||||
)
|
||||
)
|
||||
|
||||
; Instructions.
|
||||
|
||||
; Define an instruction object, normal version.
|
||||
; At present all fields must be specified.
|
||||
; Fields ifield-assertion is absent.
|
||||
|
||||
(define-pmacro (define-normal-insn name comment attrs syntax fmt semantics timing)
|
||||
"Define a normal instruction.\n"
|
||||
(define-full-insn name comment attrs syntax fmt () semantics timing)
|
||||
)
|
||||
|
||||
; To reduce the amount of typing.
|
||||
; Note that this is the same name as the D'ni in MYST. Oooohhhh.....
|
||||
; this must be the right way to go. :-)
|
||||
|
||||
(define-pmacro dni
|
||||
"Shorthand form of define-normal-insn.\n"
|
||||
define-normal-insn
|
||||
)
|
||||
|
||||
; Macro instructions.
|
||||
|
||||
; Define a macro-insn object, normal version.
|
||||
; This only supports expanding to one real insn.
|
||||
|
||||
(define-pmacro (define-normal-macro-insn name comment attrs syntax expansion)
|
||||
"Define a normal macro instruction.\n"
|
||||
(define-full-minsn name comment attrs syntax expansion)
|
||||
)
|
||||
|
||||
; To reduce the amount of typing.
|
||||
|
||||
(define-pmacro dnmi
|
||||
"Shorthand form of define-normal-macro-insn.\n"
|
||||
define-normal-macro-insn
|
||||
)
|
||||
|
||||
; Modes.
|
||||
; ??? Not currently available for use.
|
||||
;
|
||||
; Define Normal Mode
|
||||
;
|
||||
;(define-pmacro (define-normal-mode name comment attrs bits bytes
|
||||
; non-mode-c-type printf-type sem-mode ptr-to host?)
|
||||
; "Define a normal mode.\n"
|
||||
; (define-full-mode name comment attrs bits bytes
|
||||
; non-mode-c-type printf-type sem-mode ptr-to host?)
|
||||
;)
|
||||
;
|
||||
; For those who don't like typing.
|
||||
;(define-pmacro dnm
|
||||
; "Shorthand form of define-normal-mode.\n"
|
||||
; define-normal-mode
|
||||
;)
|
||||
3129
cpu/xc16x.cpu
3129
cpu/xc16x.cpu
File diff suppressed because it is too large
Load Diff
245
cpu/xc16x.opc
245
cpu/xc16x.opc
@@ -1,245 +0,0 @@
|
||||
/* XC16X opcode support. -*- C -*-
|
||||
|
||||
Copyright 2006, 2007 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by KPIT Cummins Infosystems Ltd.; developed under contract
|
||||
from Infineon Systems, GMBH , Germany.
|
||||
|
||||
This file is part of the GNU Binutils.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
||||
02110-1301, USA. */
|
||||
|
||||
|
||||
/* This file is an addendum to xc16x.cpu. Heavy use of C code isn't
|
||||
appropriate in .cpu files, so it resides here. This especially applies
|
||||
to assembly/disassembly where parsing/printing can be quite involved.
|
||||
Such things aren't really part of the specification of the cpu, per se,
|
||||
so .cpu files provide the general framework and .opc files handle the
|
||||
nitty-gritty details as necessary.
|
||||
|
||||
Each section is delimited with start and end markers.
|
||||
|
||||
<arch>-opc.h additions use: "-- opc.h"
|
||||
<arch>-opc.c additions use: "-- opc.c"
|
||||
<arch>-asm.c additions use: "-- asm.c"
|
||||
<arch>-dis.c additions use: "-- dis.c"
|
||||
<arch>-ibd.h additions use: "-- ibd.h" */
|
||||
|
||||
/* -- opc.h */
|
||||
|
||||
#define CGEN_DIS_HASH_SIZE 8
|
||||
#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
|
||||
|
||||
/* -- */
|
||||
|
||||
/* -- opc.c */
|
||||
|
||||
/* -- */
|
||||
|
||||
/* -- asm.c */
|
||||
/* Handle '#' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (**strp == '#')
|
||||
{
|
||||
++*strp;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing '#' prefix");
|
||||
}
|
||||
|
||||
/* Handle '.' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (**strp == '.')
|
||||
{
|
||||
++*strp;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing '.' prefix");
|
||||
}
|
||||
|
||||
/* Handle 'pof:' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (strncasecmp (*strp, "pof:", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing 'pof:' prefix");
|
||||
}
|
||||
|
||||
/* Handle 'pag:' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (strncasecmp (*strp, "pag:", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing 'pag:' prefix");
|
||||
}
|
||||
|
||||
/* Handle 'sof' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (strncasecmp (*strp, "sof:", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing 'sof:' prefix");
|
||||
}
|
||||
|
||||
/* Handle 'seg' prefixes (i.e. skip over them). */
|
||||
|
||||
static const char *
|
||||
parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
const char **strp,
|
||||
int opindex ATTRIBUTE_UNUSED,
|
||||
long *valuep ATTRIBUTE_UNUSED)
|
||||
{
|
||||
if (strncasecmp (*strp, "seg:", 4) == 0)
|
||||
{
|
||||
*strp += 4;
|
||||
return NULL;
|
||||
}
|
||||
return _("Missing 'seg:' prefix");
|
||||
}
|
||||
/* -- */
|
||||
|
||||
/* -- dis.c */
|
||||
|
||||
#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \
|
||||
do \
|
||||
{ \
|
||||
if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_DOT_PREFIX)) \
|
||||
info->fprintf_func (info->stream, "."); \
|
||||
if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_POF_PREFIX)) \
|
||||
info->fprintf_func (info->stream, "#pof:"); \
|
||||
if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_PAG_PREFIX)) \
|
||||
info->fprintf_func (info->stream, "#pag:"); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Print a 'pof:' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info ATTRIBUTE_UNUSED,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
}
|
||||
|
||||
/* Print a 'pag:' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info ATTRIBUTE_UNUSED,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
}
|
||||
|
||||
/* Print a 'sof:' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
info->fprintf_func (info->stream, "sof:");
|
||||
}
|
||||
|
||||
/* Print a 'seg:' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
info->fprintf_func (info->stream, "seg:");
|
||||
}
|
||||
|
||||
/* Print a '#' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = (disassemble_info *) dis_info;
|
||||
|
||||
info->fprintf_func (info->stream, "#");
|
||||
}
|
||||
|
||||
/* Print a '.' prefix to an operand. */
|
||||
|
||||
static void
|
||||
print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info ATTRIBUTE_UNUSED,
|
||||
long value ATTRIBUTE_UNUSED,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
}
|
||||
|
||||
/* -- */
|
||||
6931
texinfo/texinfo.tex
Normal file
6931
texinfo/texinfo.tex
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user