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sim: riscv: Fix PC at gdb breakpoints

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The uncompressed EBREAK instruction does not work
correctly this way, and the comment saying that
GDB expects us to step over EBREAK is just wrong.
The PC was always 4 bytes too high, which skips one
instruction at break and step over commands, and
causes complete chaos.  The compressed EBREAK was
already implemented correctly.

Tested by using gdb's "target sim" and single-stepping.

Approved-By: Andrew Burgess <aburgess@redhat.com>
This commit is contained in:
Bernd Edlinger
2024-04-12 08:55:11 +02:00
parent 5966e2eb3f
commit ae14cde6fd
1 changed files with 1 additions and 3 deletions
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4
sim/riscv/sim-main.c
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@@ -623,9 +623,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
break;
case MATCH_EBREAK:
TRACE_INSN (cpu, "ebreak;");
/* GDB expects us to step over EBREAK. */
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc + 4, sim_stopped,
SIM_SIGTRAP);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_stopped, SIM_SIGTRAP);
break;
case MATCH_ECALL:
TRACE_INSN (cpu, "ecall;");