mirror of
https://github.com/bminor/binutils-gdb.git
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ix86: Disable AVX512F when disabling AVX2
Since AVX2 is required for AVX512F, we should disable AVX512F when AVX2 is disabled. gas/ PR gas/24359 * testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7, x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test. Remove optimize-6c and x86-64-optimize-7c tests. * testsuite/gas/i386/noavx-3.l: Updated. * testsuite/gas/i386/noavx-4.d: Likewise. * testsuite/gas/i386/noavx-5.d: Likewise. * testsuite/gas/i386/noavx-3.s: Add AVX512F tests. * testsuite/gas/i386/noavx-4.s: Remove AVX512F tests. * testsuite/gas/i386/nosse-5.s: Likewise. * testsuite/gas/i386/optimize-6a.d: Removed. * testsuite/gas/i386/optimize-6c.d: Likewise. * testsuite/gas/i386/optimize-7.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.d: Likewise. * testsuite/gas/i386/x86-64-optimize-7c.d: Likewise. * testsuite/gas/i386/x86-64-optimize-8.d: Likewise. * testsuite/gas/i386/optimize-6a.l: New file. * testsuite/gas/i386/optimize-6a.s: Likewise. * testsuite/gas/i386/optimize-7.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.l: Likewise. * testsuite/gas/i386/x86-64-optimize-7a.s: Likewise. * testsuite/gas/i386/x86-64-optimize-8.l: Likewise. opcodes/ PR gas/24359 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to CPU_ANY_AVX2_FLAGS. * i386-init.h: Regenerated.
This commit is contained in:
H.J. Lu
@@ -1,3 +1,28 @@
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2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/24359
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* testsuite/gas/i386/i386.exp: Change optimize-6a, optimize-7,
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x86-64-optimize-7a and x86-64-optimize-8 tests to run_list_test.
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Remove optimize-6c and x86-64-optimize-7c tests.
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* testsuite/gas/i386/noavx-3.l: Updated.
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* testsuite/gas/i386/noavx-4.d: Likewise.
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* testsuite/gas/i386/noavx-5.d: Likewise.
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* testsuite/gas/i386/noavx-3.s: Add AVX512F tests.
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* testsuite/gas/i386/noavx-4.s: Remove AVX512F tests.
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* testsuite/gas/i386/nosse-5.s: Likewise.
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* testsuite/gas/i386/optimize-6a.d: Removed.
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* testsuite/gas/i386/optimize-6c.d: Likewise.
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* testsuite/gas/i386/optimize-7.d: Likewise.
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* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
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* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
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* testsuite/gas/i386/x86-64-optimize-8.d: Likewise.
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* testsuite/gas/i386/optimize-6a.l: New file.
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* testsuite/gas/i386/optimize-6a.s: Likewise.
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* testsuite/gas/i386/optimize-7.l: Likewise.
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* testsuite/gas/i386/x86-64-optimize-7a.l: Likewise.
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* testsuite/gas/i386/x86-64-optimize-7a.s: Likewise.
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* testsuite/gas/i386/x86-64-optimize-8.l: Likewise.
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2019-03-18 Alan Modra <amodra@gmail.com>
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* config/m68k-parse.y (yylex): Use temp_ilp and restore_ilp.
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@@ -473,10 +473,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "optimize-3"
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run_dump_test "optimize-4"
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run_dump_test "optimize-5"
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run_dump_test "optimize-6a"
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run_list_test "optimize-6a" "-I${srcdir}/$subdir -march=+noavx -al"
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run_dump_test "optimize-6b"
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run_dump_test "optimize-6c"
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run_dump_test "optimize-7"
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run_list_test "optimize-7" "-I${srcdir}/$subdir -march=+noavx2 -al"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@@ -988,10 +987,9 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-optimize-4"
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run_dump_test "x86-64-optimize-5"
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run_dump_test "x86-64-optimize-6"
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run_dump_test "x86-64-optimize-7a"
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run_list_test "x86-64-optimize-7a" "-I${srcdir}/$subdir -march=+noavx -al"
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run_dump_test "x86-64-optimize-7b"
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run_dump_test "x86-64-optimize-7c"
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run_dump_test "x86-64-optimize-8"
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run_list_test "x86-64-optimize-8" "-I${srcdir}/$subdir -march=+noavx2 -al"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@@ -11,6 +11,10 @@
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.*:37: Error: .*noavx.*
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.*:38: Error: .*noavx.*
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.*:39: Error: .*noavx.*
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.*:42: Error: .*noavx.*
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.*:43: Error: .*noavx.*
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.*:44: Error: .*noavx.*
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.*:45: Error: .*noavx.*
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GAS LISTING .*
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#...
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[ ]*1[ ]+\# Test \.arch \[\.avxX|\.noavxX\]
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@@ -63,8 +67,8 @@ GAS LISTING .*
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[ ]*39[ ]+vfrczpd %xmm7,%xmm7
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[ ]*40[ ]+\?\?\?\? 0F77 emms
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[ ]*41[ ]+\?\?\?\? 0FAEE8 lfence
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[ ]*42[ ]+\?\?\?\? 8DB42600 \.p2align 4
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[ ]*42[ ]+0000008D
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[ ]*42[ ]+B6000000
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[ ]*42[ ]+00
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[ ]*42[ ]+vaddps %xmm6, %xmm5, %xmm4
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[ ]*43[ ]+vaddps %ymm6, %ymm5, %ymm4
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[ ]*44[ ]+vaddps %zmm6, %zmm5, %zmm4
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[ ]*45[ ]+vaddss %xmm6, %xmm5, %xmm4
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#pass
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@@ -39,4 +39,8 @@
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vfrczpd %xmm7,%xmm7
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emms
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lfence
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vaddps %xmm6, %xmm5, %xmm4
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vaddps %ymm6, %ymm5, %ymm4
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vaddps %zmm6, %zmm5, %zmm4
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vaddss %xmm6, %xmm5, %xmm4
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.p2align 4
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@@ -12,14 +12,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 62 f1 54 2f 58 e6 vaddps %ymm6,%ymm5,%ymm4\{%k7\}
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[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
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[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: 62 f1 54 0f 58 e6 vaddps %xmm6,%xmm5,%xmm4\{%k7\}
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[ ]*[a-f0-9]+: 62 f1 54 2f 58 e6 vaddps %ymm6,%ymm5,%ymm4\{%k7\}
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[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
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[ ]*[a-f0-9]+: c5 d0 58 e6 vaddps %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: c5 d4 58 e6 vaddps %ymm6,%ymm5,%ymm4
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[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: 62 f1 54 08 58 e6 vaddps %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: 62 f1 54 28 58 e6 vaddps %ymm6,%ymm5,%ymm4
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[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
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[ ]*[a-f0-9]+: 62 f1 56 08 58 e6 vaddss %xmm6,%xmm5,%xmm4
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#pass
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@@ -9,14 +9,6 @@
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vaddps %zmm6, %zmm5, %zmm4
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vaddss %xmm6, %xmm5, %xmm4
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.arch .noavx2
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vaddps %xmm6, %xmm5, %xmm4{%k7}
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vaddps %ymm6, %ymm5, %ymm4{%k7}
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vaddps %zmm6, %zmm5, %zmm4
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vaddps %xmm6, %xmm5, %xmm4
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vaddps %ymm6, %ymm5, %ymm4
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vaddss %xmm6, %xmm5, %xmm4
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.arch .noavx
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vaddps %xmm6, %xmm5, %xmm4
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vaddps %ymm6, %ymm5, %ymm4
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vaddps %zmm6, %zmm5, %zmm4
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vaddss %xmm6, %xmm5, %xmm4
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@@ -21,8 +21,4 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: c5 d0 58 e6 vaddps %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: c5 d4 58 e6 vaddps %ymm6,%ymm5,%ymm4
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[ ]*[a-f0-9]+: c5 d2 58 e6 vaddss %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: 62 f1 54 08 58 e6 vaddps %xmm6,%xmm5,%xmm4
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[ ]*[a-f0-9]+: 62 f1 54 28 58 e6 vaddps %ymm6,%ymm5,%ymm4
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[ ]*[a-f0-9]+: 62 f1 54 48 58 e6 vaddps %zmm6,%zmm5,%zmm4
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[ ]*[a-f0-9]+: 62 f1 56 08 58 e6 vaddss %xmm6,%xmm5,%xmm4
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#pass
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@@ -20,8 +20,3 @@
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vaddps %xmm6, %xmm5, %xmm4
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vaddps %ymm6, %ymm5, %ymm4
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vaddss %xmm6, %xmm5, %xmm4
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.arch .noavx
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vaddps %xmm6, %xmm5, %xmm4
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vaddps %ymm6, %ymm5, %ymm4
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vaddps %zmm6, %zmm5, %zmm4
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vaddss %xmm6, %xmm5, %xmm4
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@@ -1,40 +0,0 @@
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#source: optimize-6.s
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#as: -O2 -march=+noavx
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#objdump: -drw
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#name: optimized encoding 6a with -O2
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: 62 f1 f5 4f 55 e9 vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 74 4f 55 e9 vandnps %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 74 08 55 e9 vandnps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f df e9 vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 08 df e9 vpandnd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f df e9 vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 08 df e9 vpandnq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f 57 e9 vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 08 57 e9 vxorpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 74 4f 57 e9 vxorps %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 74 08 57 e9 vxorps %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f ef e9 vpxord %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 08 ef e9 vpxord %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f ef e9 vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 08 ef e9 vpxorq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 08 f8 e9 vpsubb %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 08 f9 e9 vpsubw %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 75 08 fa e9 vpsubd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
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+[a-f0-9]+: 62 f1 f5 08 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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#pass
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82
gas/testsuite/gas/i386/optimize-6a.l
Normal file
82
gas/testsuite/gas/i386/optimize-6a.l
Normal file
@@ -0,0 +1,82 @@
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.*: Assembler messages:
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.*:6: Error: .*
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.*:7: Error: .*
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.*:9: Error: .*
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.*:10: Error: .*
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.*:12: Error: .*
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.*:13: Error: .*
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.*:15: Error: .*
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.*:16: Error: .*
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.*:18: Error: .*
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.*:19: Error: .*
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.*:21: Error: .*
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.*:22: Error: .*
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.*:24: Error: .*
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.*:25: Error: .*
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.*:27: Error: .*
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.*:28: Error: .*
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.*:30: Error: .*
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.*:31: Error: .*
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.*:33: Error: .*
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.*:34: Error: .*
|
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.*:36: Error: .*
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.*:37: Error: .*
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.*:39: Error: .*
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.*:40: Error: .*
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.*:42: Error: .*
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.*:43: Error: .*
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.*:45: Error: .*
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.*:46: Error: .*
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GAS LISTING .*
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[ ]*1[ ]+\# Check instructions with optimized encoding
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[ ]*2[ ]+
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[ ]*3[ ]+\.include "optimize-6\.s"
|
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[ ]*1[ ]+\# Check instructions with optimized encoding
|
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[ ]*2[ ]+
|
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[ ]*3[ ]+\.allow_index_reg
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[ ]*4[ ]+\.text
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[ ]*5[ ]+_start:
|
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[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm5
|
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[ ]*8[ ]+
|
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[ ]*9[ ]+vandnps %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*10[ ]+vandnps %zmm1, %zmm1, %zmm5
|
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[ ]*11[ ]+
|
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[ ]*12[ ]+vpandnd %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*13[ ]+vpandnd %zmm1, %zmm1, %zmm5
|
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[ ]*14[ ]+
|
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[ ]*15[ ]+vpandnq %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*16[ ]+vpandnq %zmm1, %zmm1, %zmm5
|
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[ ]*17[ ]+
|
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[ ]*18[ ]+vxorpd %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*19[ ]+vxorpd %zmm1, %zmm1, %zmm5
|
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[ ]*20[ ]+
|
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[ ]*21[ ]+vxorps %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*22[ ]+vxorps %zmm1, %zmm1, %zmm5
|
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[ ]*23[ ]+
|
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[ ]*24[ ]+vpxord %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*25[ ]+vpxord %zmm1, %zmm1, %zmm5
|
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[ ]*26[ ]+
|
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[ ]*27[ ]+vpxorq %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*28[ ]+vpxorq %zmm1, %zmm1, %zmm5
|
||||
[ ]*29[ ]+
|
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[ ]*30[ ]+vpsubb %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*31[ ]+vpsubb %zmm1, %zmm1, %zmm5
|
||||
[ ]*32[ ]+
|
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[ ]*33[ ]+vpsubw %zmm1, %zmm1, %zmm5\{%k7\}
|
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[ ]*34[ ]+vpsubw %zmm1, %zmm1, %zmm5
|
||||
[ ]*35[ ]+
|
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[ ]*36[ ]+vpsubd %zmm1, %zmm1, %zmm5\{%k7\}
|
||||
[ ]*37[ ]+vpsubd %zmm1, %zmm1, %zmm5
|
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[ ]*38[ ]+
|
||||
[ ]*39[ ]+vpsubq %zmm1, %zmm1, %zmm5\{%k7\}
|
||||
[ ]*40[ ]+vpsubq %zmm1, %zmm1, %zmm5
|
||||
[ ]*41[ ]+
|
||||
[ ]*42[ ]+kxord %k1, %k1, %k5
|
||||
[ ]*43[ ]+kxorq %k1, %k1, %k5
|
||||
[ ]*44[ ]+
|
||||
[ ]*45[ ]+kandnd %k1, %k1, %k5
|
||||
[ ]*46[ ]+kandnq %k1, %k1, %k5
|
||||
#pass
|
||||
3
gas/testsuite/gas/i386/optimize-6a.s
Normal file
3
gas/testsuite/gas/i386/optimize-6a.s
Normal file
@@ -0,0 +1,3 @@
|
||||
# Check instructions with optimized encoding
|
||||
|
||||
.include "optimize-6.s"
|
||||
@@ -1,40 +0,0 @@
|
||||
#source: optimize-6.s
|
||||
#as: -O2 -march=+noavx+noavx512vl
|
||||
#objdump: -drw
|
||||
#name: optimized encoding 6c with -O2
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: 62 f1 f5 4f 55 e9 vandnpd %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 f5 48 55 e9 vandnpd %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 74 4f 55 e9 vandnps %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 74 48 55 e9 vandnps %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 75 4f df e9 vpandnd %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 75 48 df e9 vpandnd %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 f5 4f df e9 vpandnq %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 f5 48 df e9 vpandnq %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 f5 4f 57 e9 vxorpd %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 f5 48 57 e9 vxorpd %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 74 4f 57 e9 vxorps %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 74 48 57 e9 vxorps %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 75 4f ef e9 vpxord %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 75 48 ef e9 vpxord %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 f5 4f ef e9 vpxorq %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 f5 48 ef e9 vpxorq %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 75 4f f8 e9 vpsubb %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 75 48 f8 e9 vpsubb %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 75 4f f9 e9 vpsubw %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 75 48 f9 e9 vpsubw %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 75 4f fa e9 vpsubd %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 75 48 fa e9 vpsubd %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: 62 f1 f5 4f fb e9 vpsubq %zmm1,%zmm1,%zmm5\{%k7\}
|
||||
+[a-f0-9]+: 62 f1 f5 48 fb e9 vpsubq %zmm1,%zmm1,%zmm5
|
||||
+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
|
||||
+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
|
||||
+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
|
||||
+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
|
||||
#pass
|
||||
@@ -1,12 +0,0 @@
|
||||
#as: -O2 -march=+noavx
|
||||
#objdump: -drw
|
||||
#name: optimized encoding 7 with -O2
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
|
||||
#pass
|
||||
12
gas/testsuite/gas/i386/optimize-7.l
Normal file
12
gas/testsuite/gas/i386/optimize-7.l
Normal file
@@ -0,0 +1,12 @@
|
||||
.*: Assembler messages:
|
||||
.*:6: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check instructions with optimized encoding
|
||||
[ ]*2[ ]+
|
||||
[ ]*3[ ]+\.allow_index_reg
|
||||
[ ]*4[ ]+\.text
|
||||
[ ]*5[ ]+_start:
|
||||
[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
|
||||
#pass
|
||||
@@ -1,60 +0,0 @@
|
||||
#source: x86-64-optimize-7.s
|
||||
#as: -O2 -march=+noavx
|
||||
#objdump: -drw
|
||||
#name: x86-64 optimized encoding 7a with -O2
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 08 55 f9 vandnpd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 08 55 c1 vandnpd %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 f5 00 55 c9 vandnpd %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 74 08 55 f9 vandnps %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 74 08 55 c1 vandnps %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 74 00 55 c9 vandnps %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 08 df f9 vpandnd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 08 df c1 vpandnd %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 75 00 df c9 vpandnd %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 08 df f9 vpandnq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 08 df c1 vpandnq %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 f5 00 df c9 vpandnq %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 08 57 f9 vxorpd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 08 57 c1 vxorpd %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 f5 00 57 c9 vxorpd %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 74 08 57 f9 vxorps %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 74 08 57 c1 vxorps %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 74 00 57 c9 vxorps %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 08 ef f9 vpxord %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 08 ef c1 vpxord %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 75 00 ef c9 vpxord %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 08 ef f9 vpxorq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 08 ef c1 vpxorq %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 f5 00 ef c9 vpxorq %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 08 f8 f9 vpsubb %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 08 f8 c1 vpsubb %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 75 00 f8 c9 vpsubb %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 08 f9 f9 vpsubw %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 08 f9 c1 vpsubw %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 75 00 f9 c9 vpsubw %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 08 fa f9 vpsubd %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 75 08 fa c1 vpsubd %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 75 00 fa c9 vpsubd %xmm17,%xmm17,%xmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 08 fb f9 vpsubq %xmm1,%xmm1,%xmm15
|
||||
+[a-f0-9]+: 62 e1 f5 08 fb c1 vpsubq %xmm1,%xmm1,%xmm16
|
||||
+[a-f0-9]+: 62 b1 f5 00 fb c9 vpsubq %xmm17,%xmm17,%xmm1
|
||||
#pass
|
||||
123
gas/testsuite/gas/i386/x86-64-optimize-7a.l
Normal file
123
gas/testsuite/gas/i386/x86-64-optimize-7a.l
Normal file
@@ -0,0 +1,123 @@
|
||||
.*: Assembler messages:
|
||||
.*:6: Error: .*
|
||||
.*:7: Error: .*
|
||||
.*:8: Error: .*
|
||||
.*:9: Error: .*
|
||||
.*:11: Error: .*
|
||||
.*:12: Error: .*
|
||||
.*:13: Error: .*
|
||||
.*:14: Error: .*
|
||||
.*:16: Error: .*
|
||||
.*:17: Error: .*
|
||||
.*:18: Error: .*
|
||||
.*:19: Error: .*
|
||||
.*:21: Error: .*
|
||||
.*:22: Error: .*
|
||||
.*:23: Error: .*
|
||||
.*:24: Error: .*
|
||||
.*:26: Error: .*
|
||||
.*:27: Error: .*
|
||||
.*:28: Error: .*
|
||||
.*:29: Error: .*
|
||||
.*:31: Error: .*
|
||||
.*:32: Error: .*
|
||||
.*:33: Error: .*
|
||||
.*:34: Error: .*
|
||||
.*:36: Error: .*
|
||||
.*:37: Error: .*
|
||||
.*:38: Error: .*
|
||||
.*:39: Error: .*
|
||||
.*:41: Error: .*
|
||||
.*:42: Error: .*
|
||||
.*:43: Error: .*
|
||||
.*:44: Error: .*
|
||||
.*:46: Error: .*
|
||||
.*:47: Error: .*
|
||||
.*:48: Error: .*
|
||||
.*:49: Error: .*
|
||||
.*:51: Error: .*
|
||||
.*:52: Error: .*
|
||||
.*:53: Error: .*
|
||||
.*:54: Error: .*
|
||||
.*:56: Error: .*
|
||||
.*:57: Error: .*
|
||||
.*:58: Error: .*
|
||||
.*:59: Error: .*
|
||||
.*:61: Error: .*
|
||||
.*:62: Error: .*
|
||||
.*:63: Error: .*
|
||||
.*:64: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
|
||||
[ ]*2[ ]+
|
||||
[ ]*3[ ]+\.include "x86-64-optimize-7\.s"
|
||||
[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
|
||||
[ ]*2[ ]+
|
||||
[ ]*3[ ]+\.allow_index_reg
|
||||
[ ]*4[ ]+\.text
|
||||
[ ]*5[ ]+_start:
|
||||
[ ]*6[ ]+vandnpd %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*7[ ]+vandnpd %zmm1, %zmm1, %zmm15
|
||||
[ ]*8[ ]+vandnpd %zmm1, %zmm1, %zmm16
|
||||
[ ]*9[ ]+vandnpd %zmm17, %zmm17, %zmm1
|
||||
[ ]*10[ ]+
|
||||
[ ]*11[ ]+vandnps %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*12[ ]+vandnps %zmm1, %zmm1, %zmm15
|
||||
[ ]*13[ ]+vandnps %zmm1, %zmm1, %zmm16
|
||||
[ ]*14[ ]+vandnps %zmm17, %zmm17, %zmm1
|
||||
[ ]*15[ ]+
|
||||
[ ]*16[ ]+vpandnd %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*17[ ]+vpandnd %zmm1, %zmm1, %zmm15
|
||||
[ ]*18[ ]+vpandnd %zmm1, %zmm1, %zmm16
|
||||
[ ]*19[ ]+vpandnd %zmm17, %zmm17, %zmm1
|
||||
[ ]*20[ ]+
|
||||
[ ]*21[ ]+vpandnq %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*22[ ]+vpandnq %zmm1, %zmm1, %zmm15
|
||||
[ ]*23[ ]+vpandnq %zmm1, %zmm1, %zmm16
|
||||
[ ]*24[ ]+vpandnq %zmm17, %zmm17, %zmm1
|
||||
[ ]*25[ ]+
|
||||
[ ]*26[ ]+vxorpd %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*27[ ]+vxorpd %zmm1, %zmm1, %zmm15
|
||||
[ ]*28[ ]+vxorpd %zmm1, %zmm1, %zmm16
|
||||
[ ]*29[ ]+vxorpd %zmm17, %zmm17, %zmm1
|
||||
[ ]*30[ ]+
|
||||
[ ]*31[ ]+vxorps %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*32[ ]+vxorps %zmm1, %zmm1, %zmm15
|
||||
[ ]*33[ ]+vxorps %zmm1, %zmm1, %zmm16
|
||||
[ ]*34[ ]+vxorps %zmm17, %zmm17, %zmm1
|
||||
[ ]*35[ ]+
|
||||
[ ]*36[ ]+vpxord %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*37[ ]+vpxord %zmm1, %zmm1, %zmm15
|
||||
[ ]*38[ ]+vpxord %zmm1, %zmm1, %zmm16
|
||||
[ ]*39[ ]+vpxord %zmm17, %zmm17, %zmm1
|
||||
[ ]*40[ ]+
|
||||
[ ]*41[ ]+vpxorq %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*42[ ]+vpxorq %zmm1, %zmm1, %zmm15
|
||||
[ ]*43[ ]+vpxorq %zmm1, %zmm1, %zmm16
|
||||
[ ]*44[ ]+vpxorq %zmm17, %zmm17, %zmm1
|
||||
[ ]*45[ ]+
|
||||
[ ]*46[ ]+vpsubb %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*47[ ]+vpsubb %zmm1, %zmm1, %zmm15
|
||||
[ ]*48[ ]+vpsubb %zmm1, %zmm1, %zmm16
|
||||
[ ]*49[ ]+vpsubb %zmm17, %zmm17, %zmm1
|
||||
[ ]*50[ ]+
|
||||
[ ]*51[ ]+vpsubw %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*52[ ]+vpsubw %zmm1, %zmm1, %zmm15
|
||||
[ ]*53[ ]+vpsubw %zmm1, %zmm1, %zmm16
|
||||
[ ]*54[ ]+vpsubw %zmm17, %zmm17, %zmm1
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*55[ ]+
|
||||
[ ]*56[ ]+vpsubd %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*57[ ]+vpsubd %zmm1, %zmm1, %zmm15
|
||||
[ ]*58[ ]+vpsubd %zmm1, %zmm1, %zmm16
|
||||
[ ]*59[ ]+vpsubd %zmm17, %zmm17, %zmm1
|
||||
[ ]*60[ ]+
|
||||
[ ]*61[ ]+vpsubq %zmm1, %zmm1, %zmm15\{%k7\}
|
||||
[ ]*62[ ]+vpsubq %zmm1, %zmm1, %zmm15
|
||||
[ ]*63[ ]+vpsubq %zmm1, %zmm1, %zmm16
|
||||
[ ]*64[ ]+vpsubq %zmm17, %zmm17, %zmm1
|
||||
#pass
|
||||
3
gas/testsuite/gas/i386/x86-64-optimize-7a.s
Normal file
3
gas/testsuite/gas/i386/x86-64-optimize-7a.s
Normal file
@@ -0,0 +1,3 @@
|
||||
# Check 64bit instructions with optimized encoding
|
||||
|
||||
.include "x86-64-optimize-7.s"
|
||||
@@ -1,60 +0,0 @@
|
||||
#source: x86-64-optimize-7.s
|
||||
#as: -O2 -march=+noavx+noavx512vl
|
||||
#objdump: -drw
|
||||
#name: x86-64 optimized encoding 7c with -O2
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: 62 71 f5 4f 55 f9 vandnpd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 48 55 f9 vandnpd %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 55 c1 vandnpd %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 55 c9 vandnpd %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 74 4f 55 f9 vandnps %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 74 48 55 f9 vandnps %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 74 48 55 c1 vandnps %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 74 40 55 c9 vandnps %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 75 4f df f9 vpandnd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 48 df f9 vpandnd %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 df c1 vpandnd %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 75 40 df c9 vpandnd %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f df f9 vpandnq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 48 df f9 vpandnq %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 df c1 vpandnq %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 df c9 vpandnq %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f 57 f9 vxorpd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 48 57 f9 vxorpd %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 57 c1 vxorpd %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 57 c9 vxorpd %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 74 4f 57 f9 vxorps %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 74 48 57 f9 vxorps %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 74 48 57 c1 vxorps %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 74 40 57 c9 vxorps %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 75 4f ef f9 vpxord %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 48 ef f9 vpxord %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 ef c1 vpxord %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 75 40 ef c9 vpxord %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f ef f9 vpxorq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 48 ef f9 vpxorq %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 ef c1 vpxorq %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 ef c9 vpxorq %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 75 4f f8 f9 vpsubb %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 48 f8 f9 vpsubb %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 f8 c1 vpsubb %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 75 40 f8 c9 vpsubb %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 75 4f f9 f9 vpsubw %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 48 f9 f9 vpsubw %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 f9 c1 vpsubw %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 75 40 f9 c9 vpsubw %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 75 4f fa f9 vpsubd %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 75 48 fa f9 vpsubd %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 75 48 fa c1 vpsubd %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 75 40 fa c9 vpsubd %zmm17,%zmm17,%zmm1
|
||||
+[a-f0-9]+: 62 71 f5 4f fb f9 vpsubq %zmm1,%zmm1,%zmm15\{%k7\}
|
||||
+[a-f0-9]+: 62 71 f5 48 fb f9 vpsubq %zmm1,%zmm1,%zmm15
|
||||
+[a-f0-9]+: 62 e1 f5 48 fb c1 vpsubq %zmm1,%zmm1,%zmm16
|
||||
+[a-f0-9]+: 62 b1 f5 40 fb c9 vpsubq %zmm17,%zmm17,%zmm1
|
||||
#pass
|
||||
@@ -1,12 +0,0 @@
|
||||
#as: -O2 -march=+noavx
|
||||
#objdump: -drw
|
||||
#name: x86-64 optimized encoding 8 with -O2
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
+[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
|
||||
#pass
|
||||
12
gas/testsuite/gas/i386/x86-64-optimize-8.l
Normal file
12
gas/testsuite/gas/i386/x86-64-optimize-8.l
Normal file
@@ -0,0 +1,12 @@
|
||||
.*: Assembler messages:
|
||||
.*:6: Error: .*
|
||||
GAS LISTING .*
|
||||
|
||||
|
||||
[ ]*1[ ]+\# Check 64bit instructions with optimized encoding
|
||||
[ ]*2[ ]+
|
||||
[ ]*3[ ]+\.allow_index_reg
|
||||
[ ]*4[ ]+\.text
|
||||
[ ]*5[ ]+_start:
|
||||
[ ]*6[ ]+vmovdqa32 %ymm1, %ymm2
|
||||
#pass
|
||||
@@ -1,3 +1,10 @@
|
||||
2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR gas/24359
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
|
||||
CPU_ANY_AVX2_FLAGS.
|
||||
* i386-init.h: Regenerated.
|
||||
|
||||
2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
PR gas/24348
|
||||
|
||||
@@ -322,7 +322,7 @@ static initializer cpu_flag_init[] =
|
||||
{ "CPU_ANY_AVX_FLAGS",
|
||||
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
|
||||
{ "CPU_ANY_AVX2_FLAGS",
|
||||
"CpuAVX2" },
|
||||
"CPU_ANY_AVX512F_FLAGS|CpuAVX2" },
|
||||
{ "CPU_ANY_AVX512F_FLAGS",
|
||||
"CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG" },
|
||||
{ "CPU_ANY_AVX512CD_FLAGS",
|
||||
|
||||
@@ -1132,18 +1132,18 @@
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX512F_FLAGS \
|
||||
|
||||
Reference in New Issue
Block a user