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x86-64: Dwarf2 register numbers for %bnd<N>

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I don't see why we shouldn't record them when they have been allocated,
even if they're (bogusly) named as reserved in the ABI right now.
This commit is contained in:
Jan Beulich
2024-01-19 10:19:15 +01:00
parent eea4357967
commit 633789901c
2 changed files with 8 additions and 8 deletions
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8
opcodes/i386-reg.tbl
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@@ -353,10 +353,10 @@ tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
// Bound registers for MPX
bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
bnd2, Class=RegBND, 0, 2, Dw2Inval, 128
bnd3, Class=RegBND, 0, 3, Dw2Inval, 129
// No Class=Reg will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
rip, Qword, RegRex64, RegIP, Dw2Inval, 16

8
opcodes/i386-tbl.h
View File

@@ -44881,19 +44881,19 @@ static const reg_entry i386_regtab[] =
{ "bnd0",
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
0, 0, { Dw2Inval, Dw2Inval } },
0, 0, { Dw2Inval, 126 } },
{ "bnd1",
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
0, 1, { Dw2Inval, Dw2Inval } },
0, 1, { Dw2Inval, 127 } },
{ "bnd2",
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
0, 2, { Dw2Inval, Dw2Inval } },
0, 2, { Dw2Inval, 128 } },
{ "bnd3",
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
0, 3, { Dw2Inval, Dw2Inval } },
0, 3, { Dw2Inval, 129 } },
{ "rip",
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },