mirror of
https://github.com/bminor/binutils-gdb.git
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x86: Eliminate unnecessary {evex} prefixes
For several instructions including vps{l,r}l{d,q,w,dq} and vpsra{d,w},
their VEX part do not have the following version:
vpsrlw $0x1f,(%r15,%rcx,4),%xmm0
Thus, {evex} prefix should not be inserted when their second operand is
memory, while we still need them for register as second operand. Add a
new macro %ME to solve this problem.
For vpsraq, there is no VEX version, so the {evex} prefix should always
be eliminated.
gas/ChangeLog:
PR binutils/32403
* testsuite/gas/i386/i386.exp: Run new test.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/evex-only.d: New test.
* testsuite/gas/i386/evex-only.s: Ditto.
* testsuite/gas/i386/x86-64-evex-only.d: Ditto.
* testsuite/gas/i386/x86-64-evex-only.s: Ditto.
opcodes/ChangeLog:
PR binutils/32403
* i386-dis-evex-reg.h: Use %ME instead of %XE for vps{l,r}l{w,dq}
and vpsraw. Split table for vpsra{d,q}.
* i386-dis-evex-w.h: Use %ME instead of %XE for vps{l,r}l{d,q}
and vpsrad. Eliminate vpsraq {evex} prefix.
* i386-dis-evex.h: Split table for vpsra{d,q}.
* i386-dis.c: (EVEX_W_0F72_R_4): New.
(EVEX_W_0FE2): Ditto.
(struct dis386): Add comment for %ME.
(putop): Handle %ME.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
This commit is contained in:
H.J. Lu
24
gas/testsuite/gas/i386/evex-only.d
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24
gas/testsuite/gas/i386/evex-only.d
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@@ -0,0 +1,24 @@
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#objdump: -dw
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#name: AVX512 instructions do not need {evex} prefix with memory
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*62 f1 7d 08 71 14 88 1f\s+vpsrlw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 71 24 88 1f\s+vpsraw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 71 34 88 1f\s+vpsllw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 72 24 88 1f\s+vpsrad\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 fd 08 72 24 88 1f\s+vpsraq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 fd 08 72 e1 1f\s+vpsraq\s+\$0x1f,%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 f1 f5 08 e2 04 88\s+vpsraq\s+\(%eax,%ecx,4\),%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 f1 f5 08 e2 c2\s+vpsraq\s+%xmm2,%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 73 1c 88 1f\s+vpsrldq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 73 3c 88 1f\s+vpslldq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 72 14 88 1f\s+vpsrld\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 7d 08 72 34 88 1f\s+vpslld\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 fd 08 73 14 88 1f\s+vpsrlq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 fd 08 73 34 88 1f\s+vpsllq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
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#pass
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18
gas/testsuite/gas/i386/evex-only.s
Normal file
18
gas/testsuite/gas/i386/evex-only.s
Normal file
@@ -0,0 +1,18 @@
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# Check instructions do not need {evex} prefix under memory operand
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.text
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_start:
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vpsrlw $0x1f,(%eax,%ecx,4),%xmm0
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vpsraw $0x1f,(%eax,%ecx,4),%xmm0
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vpsllw $0x1f,(%eax,%ecx,4),%xmm0
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vpsrad $0x1f,(%eax,%ecx,4),%xmm0
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vpsraq $0x1f,(%eax,%ecx,4),%xmm0
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vpsraq $0x1f,%xmm1,%xmm0
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vpsraq (%eax,%ecx,4),%xmm1,%xmm0
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vpsraq %xmm2,%xmm1,%xmm0
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vpsrldq $0x1f,(%eax,%ecx,4),%xmm0
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vpslldq $0x1f,(%eax,%ecx,4),%xmm0
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vpsrld $0x1f,(%eax,%ecx,4),%xmm0
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vpslld $0x1f,(%eax,%ecx,4),%xmm0
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vpsrlq $0x1f,(%eax,%ecx,4),%xmm0
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vpsllq $0x1f,(%eax,%ecx,4),%xmm0
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@@ -294,6 +294,7 @@ if [gas_32_check] then {
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run_dump_test "evex-lig-2"
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run_dump_test "evex-wig1"
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run_dump_test "evex-wig1-intel"
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run_dump_test "evex-only"
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run_dump_test "evex-no-scale-32"
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run_dump_test "sse2avx"
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run_dump_test "unaligned-vector-move"
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24
gas/testsuite/gas/i386/x86-64-evex-only.d
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24
gas/testsuite/gas/i386/x86-64-evex-only.d
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@@ -0,0 +1,24 @@
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#objdump: -dw
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#name: x86-64 AVX512 instructions do not need {evex} prefix with memory
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*62 d1 7d 08 71 14 8f 1f\s+vpsrlw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 71 24 8f 1f\s+vpsraw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 71 34 8f 1f\s+vpsllw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 72 24 8f 1f\s+vpsrad\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 fd 08 72 24 8f 1f\s+vpsraq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 f1 fd 08 72 e1 1f\s+vpsraq\s+\$0x1f,%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 d1 f5 08 e2 04 8f\s+vpsraq\s+\(%r15,%rcx,4\),%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 f1 f5 08 e2 c2\s+vpsraq\s+%xmm2,%xmm1,%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 73 1c 8f 1f\s+vpsrldq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 73 3c 8f 1f\s+vpslldq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 72 14 8f 1f\s+vpsrld\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 7d 08 72 34 8f 1f\s+vpslld\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 fd 08 73 14 8f 1f\s+vpsrlq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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\s*[a-f0-9]+:\s*62 d1 fd 08 73 34 8f 1f\s+vpsllq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
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#pass
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18
gas/testsuite/gas/i386/x86-64-evex-only.s
Normal file
18
gas/testsuite/gas/i386/x86-64-evex-only.s
Normal file
@@ -0,0 +1,18 @@
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# Check instructions do not need {evex} prefix under memory operand
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.text
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_start:
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vpsrlw $0x1f,(%r15,%rcx,4),%xmm0
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vpsraw $0x1f,(%r15,%rcx,4),%xmm0
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vpsllw $0x1f,(%r15,%rcx,4),%xmm0
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vpsrad $0x1f,(%r15,%rcx,4),%xmm0
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vpsraq $0x1f,(%r15,%rcx,4),%xmm0
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vpsraq $0x1f,%xmm1,%xmm0
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vpsraq (%r15,%rcx,4),%xmm1,%xmm0
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vpsraq %xmm2,%xmm1,%xmm0
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vpsrldq $0x1f,(%r15,%rcx,4),%xmm0
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vpslldq $0x1f,(%r15,%rcx,4),%xmm0
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vpsrld $0x1f,(%r15,%rcx,4),%xmm0
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vpslld $0x1f,(%r15,%rcx,4),%xmm0
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vpsrlq $0x1f,(%r15,%rcx,4),%xmm0
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vpsllq $0x1f,(%r15,%rcx,4),%xmm0
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@@ -242,6 +242,7 @@ run_dump_test "x86-64-evex-lig-2"
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run_dump_test "x86-64-evex-wig1"
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run_dump_test "x86-64-evex-wig1-intel"
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run_dump_test "x86-64-evex-wig2"
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run_dump_test "x86-64-evex-only"
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run_dump_test "evex-no-scale-64"
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run_dump_test "x86-64-sse2avx"
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run_dump_test "x86-64-unaligned-vector-move"
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@@ -2,11 +2,11 @@
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "%XEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "%XEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "%XEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F72 */
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{
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@@ -14,7 +14,7 @@
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{ "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ VEX_W_TABLE (EVEX_W_0F72_R_2) },
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{ Bad_Opcode },
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{ "%XEvpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ VEX_W_TABLE (EVEX_W_0F72_R_4) },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F72_R_6) },
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},
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@@ -23,11 +23,11 @@
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_2) },
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{ "%XEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_6) },
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{ "%XEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F38C6_L_2 */
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{
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@@ -50,21 +50,26 @@
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},
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/* EVEX_W_0F72_R_2 */
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{
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{ "%XEvpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F72_R_4 */
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{
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{ "%MEvpsrad", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "vpsraq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F72_R_6 */
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{
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{ "%XEvpslld", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpslld", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F73_R_2 */
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{
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{ Bad_Opcode },
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{ "%XEvpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F73_R_6 */
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{
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{ Bad_Opcode },
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{ "%XEvpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "%MEvpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* EVEX_W_0F76 */
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{
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@@ -149,6 +154,11 @@
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{ Bad_Opcode },
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{ VEX_LEN_TABLE (VEX_LEN_0FD6) },
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},
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/* EVEX_W_0FE2 */
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{
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{ "%XEvpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
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{ "vpsraq", { XM, Vex, EXxmm }, PREFIX_DATA },
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},
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/* EVEX_W_0FE6_P_1 */
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{
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{ "%XEvcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
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@@ -256,7 +256,7 @@ static const struct dis386 evex_table[][256] = {
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/* E0 */
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{ "%XEvpavgb", { XM, Vex, EXx }, PREFIX_DATA },
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{ "%XEvpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
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{ "%XEvpsra%DQ", { XM, Vex, EXxmm }, PREFIX_DATA },
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{ VEX_W_TABLE (EVEX_W_0FE2) },
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{ "%XEvpavgw", { XM, Vex, EXx }, PREFIX_DATA },
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{ "%XEvpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
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{ "%XEvpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
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@@ -1673,6 +1673,7 @@ enum
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EVEX_W_0F6F_P_3,
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EVEX_W_0F70_P_2,
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EVEX_W_0F72_R_2,
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EVEX_W_0F72_R_4,
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EVEX_W_0F72_R_6,
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EVEX_W_0F73_R_2,
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EVEX_W_0F73_R_6,
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@@ -1693,6 +1694,7 @@ enum
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EVEX_W_0FD3,
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EVEX_W_0FD4,
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EVEX_W_0FD6,
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EVEX_W_0FE2,
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EVEX_W_0FE6_P_1,
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EVEX_W_0FE7,
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EVEX_W_0FF2,
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@@ -1837,6 +1839,8 @@ struct dis386 {
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"XV" => print "{vex} " pseudo prefix
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"XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
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is used by an EVEX-encoded (AVX512VL) instruction.
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"ME" => Similar to "XE", but only print "{evex} " when there is no
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memory operand.
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"NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
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pseudo prefix when instructions without NF, EGPR and VVVV,
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"NE" => don't print "{evex} " pseudo prefix for some special instructions
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@@ -10619,6 +10623,10 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
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{
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switch (last[0])
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{
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case 'M':
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if (ins->modrm.mod != 3)
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break;
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/* Fall through. */
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case 'X':
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if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
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|| (ins->rex2 & 7)
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