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Snap. Gets through igen's checks.

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This commit is contained in:
Andrew Cagney
1997-10-09 08:38:22 +00:00
parent 8782bfcfc4
commit 49a6eed58a
1 changed files with 104 additions and 322 deletions
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426
sim/mips/mips.igen
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@@ -22,6 +22,9 @@
:option:32:insn-specifying-widths:true
// Generate separate simulators for each target
:option::multi-sim:true
// Models known by this simulator
:model::mipsI:mipsI:
@@ -565,7 +568,7 @@
}
000000,********************,001101:SPECIAL:32::BREAK
000000,20.CODE,001101:SPECIAL:32::BREAK
"break"
*mipsI:
*mipsII:
@@ -583,7 +586,7 @@
}
0100,ZZ!1!3,26.COP_FUN:NORMAL:32::COP0
0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
"cop<ZZ> <COP_FUN>"
*mipsI:
*mipsII:
@@ -1304,7 +1307,7 @@
}
1101,ZZ,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
@@ -1680,7 +1683,7 @@
}
1100,ZZ,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
@@ -2261,7 +2264,7 @@
}
1111,ZZ,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsII:
*mipsIII:
@@ -2714,7 +2717,7 @@
}
1110,ZZ,5.RS,5.RT,16.OFFSET:NORMAL:32::SWCz
1110,ZZ!0!1!3,5.RS,5.RT,16.OFFSET:NORMAL:32::SWCz
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsII:
@@ -4054,7 +4057,7 @@
010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE)"
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
{
unsigned32 instruction = instruction_0;
@@ -4088,7 +4091,7 @@
010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
"round.l.%S<FMT> f<FD>, f<FS>"
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
// start-sanitize-r5900
@@ -4113,7 +4116,7 @@
010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
"round.w.%S<FMT> f<FD>, f<FS>"
"round.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
@@ -4376,7 +4379,7 @@
010000,01000,00001,16.OFFSET:COP0:32::BC0TL
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
"bc0tl <OFFSET>"
*mipsI:
*mipsII:
@@ -4443,8 +4446,8 @@
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000000:COP0:32::MFBPC
"mfbpc r<RT>"
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
"mfc0 r<RT>, r<RD> # <REGX>"
*mipsI:
*mipsII:
*mipsIII:
@@ -4454,217 +4457,8 @@
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000000:COP0:32::MFC0
"mfc0 r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000100:COP0:32::MFDAB
"mfdab r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000101:COP0:32::MFDABM
"mfdabm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000110:COP0:32::MFDVB
"mfdv r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000111:COP0:32::MFDVBM
"mfdvm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000010:COP0:32::MFIAB
"mfiab r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11000,00000000011:COP0:32::MFIABM
"mfiabm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11001,00000,5.REG,1:COP0:32::MFPC
"mfpc r<RT>, <REG>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00000,5.RT,11001,00000,5.REG,0:COP0:32::MFPS
"mfps r<RT>, <REG>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000000:COP0:32::MTBPC
"mtbpc r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,5.RD,00000000000:COP0:32::MTC0
"mtc0 r<RT>, r<RD>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000100:COP0:32::MTDAB
"mtdab r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000101:COP0:32::MTDABM
"mtdabm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000110:COP0:32::MTDVB
"mtdvb r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000111:COP0:32::MTDVBM
"mtdvbm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000010:COP0:32::MTIAB
"mtiab r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11000,00000000011:COP0:32::MTIABM
"mtiabm r<RT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11001,00000,5.REG,1:COP0:32::MTPC
"mtpc r<RT>, r<REG>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11001,00000,5.REG,0:COP0:32::MTPCM
"mtpcm r<RT>, r<REG>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
010000,00100,5.RT,11001,00000,5.REG,0:COP0:32::MTPS
"mtps r<RT>, r<REG>"
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
"mtc0 r<RT>, r<RD> # <REGX>"
*mipsI:
*mipsII:
*mipsIII:
@@ -7455,35 +7249,7 @@
// end-sanitize-r5900
000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
{
CHECKHILO("Multiply-Add");
{
unsigned64 temp = (op1 * op2);
LO = LO + temp;
}
}
}
011101,26.INSTR_INDEX:NORMAL:32::JALX
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
@@ -7617,32 +7383,6 @@
}
// end-sanitize-r5900
000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
*mipsIII:
*mipsIV:
// start-sanitize-r5900
*r5900:
// end-sanitize-r5900
*r3900:
// start-sanitize-tx19
*tx19:
// end-sanitize-tx19
{
unsigned32 instruction = instruction_0;
t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
{
CHECKHILO("Multiply-Add");
{
unsigned64 temp = (op1 * op2);
temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
}
}
}
// start-sanitize-r5900
0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1
@@ -9939,58 +9679,100 @@
// start-sanitize-cygnus-never
// What is this instruction?
//111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
//*mipsI:
//*mipsII:
//*mipsIII:
//*mipsIV:
//// start-sanitize-r5900
//*r5900:
//// end-sanitize-r5900
//*r3900:
//// start-sanitize-tx19
//*tx19:
//// end-sanitize-tx19
//{
// unsigned32 instruction = instruction_0;
// t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
// t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
// t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
// {
// if (CoProcPresent(3))
// SignalException(CoProcessorUnusable);
// else
// SignalException(ReservedInstruction,instruction);
// }
//}
// // FIXME FIXME FIXME What is this instruction?
// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
// *mipsI:
// *mipsII:
// *mipsIII:
// *mipsIV:
// // start-sanitize-r5900
// *r5900:
// // end-sanitize-r5900
// *r3900:
// // start-sanitize-tx19
// *tx19:
// // end-sanitize-tx19
// {
// unsigned32 instruction = instruction_0;
// t_reg offset UNUSED = SIGNEXTEND((t_reg)((instruction >> 0) & 0x0000FFFF),16);
// t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
// t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
// {
// if (CoProcPresent(3))
// SignalException(CoProcessorUnusable);
// else
// SignalException(ReservedInstruction,instruction);
// }
// }
// end-sanitize-cygnus-never
// start-sanitize-cygnus-never
// FIXME FIXME FIXME What is this?
//11100,******,00001:RR:16::SDBBP
//*mips16:
//{
// unsigned32 instruction = instruction_0;
// if (have_extendval)
// SignalException (ReservedInstruction, instruction);
// {
// SignalException(DebugBreakPoint,instruction);
// }
//}
// // FIXME FIXME FIXME What is this?
// 11100,******,00001:RR:16::SDBBP
// *mips16:
// {
// unsigned32 instruction = instruction_0;
// if (have_extendval)
// SignalException (ReservedInstruction, instruction);
// {
// SignalException(DebugBreakPoint,instruction);
// }
// }
// end-sanitize-cygnus-never
// start-sanitize-cygnus-never
// FIXME FIXME FIXME What is this?
000000,********************,001110:SPECIAL:32::SDBBP
//*r3900:
//{
// unsigned32 instruction = instruction_0;
// {
// SignalException(DebugBreakPoint,instruction);
// }
//}
// // FIXME FIXME FIXME What is this?
// 000000,********************,001110:SPECIAL:32::SDBBP
// *r3900:
// {
// unsigned32 instruction = instruction_0;
// {
// SignalException(DebugBreakPoint,instruction);
// }
// }
// end-sanitize-cygnus-never
// start-sanitize-cygnus-never
// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
// // isn't yet reconized by this simulator.
// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
// *vr4100:
// {
// unsigned32 instruction = instruction_0;
// t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
// t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
// {
// CHECKHILO("Multiply-Add");
// {
// unsigned64 temp = (op1 * op2);
// temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
// LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
// HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
// }
// }
// }
// end-sanitize-cygnus-never
// start-sanitize-cygnus-never
// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
// // isn't yet reconized by this simulator.
// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
// *vr4100:
// {
// unsigned32 instruction = instruction_0;
// t_reg op2 UNUSED = GPR[((instruction >> 16) & 0x0000001F)];
// t_reg op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
// {
// CHECKHILO("Multiply-Add");
// {
// unsigned64 temp = (op1 * op2);
// LO = LO + temp;
// }
// }
// }
// start-sanitize-cygnus-never