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x86/APX: make .insn extended-EVEX capable
So far tricks had to be played to use .insn to encode extended-EVEX insns; the X4 bit couldn't be controlled at all. Extend the syntax just enough to cover all features, taking care to reject invalid feature combinations (albeit aiming at being as lax there as possible, to offer users as much flexibility as we can - we don't, after all, know what future will bring). In a pre-existing testcase replace all but one .byte; the one that needs to remain wants to have EVEX.U clear in a way that's neither controllable via AVX10/256 embedded rounding (would otherwise also set EVEX.ND), nor via the index register (EVEX.X4), as there's no memory operand. For one of the converted instances ModR/M.mod needs correcting: An 8-bit displacement requires that to be 1, not 2. Also adjust source comments to better represent what the bad insns mimic.
This commit is contained in:
Jan Beulich
@@ -2125,6 +2125,59 @@ check_Scc_OszcOperations (const char *l)
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/* Skip '{'. */
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suffix_string++;
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/* For .insn require 'scc=' as the first element. */
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if (dot_insn ())
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{
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char *copy;
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valueT val;
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while (is_whitespace (*suffix_string))
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suffix_string++;
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if (strncasecmp (suffix_string, "scc", 3) == 0)
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suffix_string += 3;
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else
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{
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as_bad (_("unrecognized pseudo-suffix"));
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return -1;
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}
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while (is_whitespace (*suffix_string))
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suffix_string++;
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if (*suffix_string == '=')
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suffix_string++;
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else
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{
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as_bad (_("unrecognized pseudo-suffix"));
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return -1;
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}
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copy = xstrdup (suffix_string);
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/* No need to save/restore input_line_pointer; that's done in the
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caller already. */
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input_line_pointer = copy;
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val = get_absolute_expression ();
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suffix_string += input_line_pointer - copy;
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free (copy);
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if (val > 0xf)
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{
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as_bad (_("scc= value must be between 0 and 15 (decimal)"));
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return -1;
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}
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i.scc = val;
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/* Permit dfv= to be absent (implying all flag values being zero). */
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if (*suffix_string == '}')
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return suffix_string + 1 - l;
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if (*suffix_string != ',')
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goto bad;
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suffix_string++;
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}
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/* Parse 'dfv='. */
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while (is_whitespace (*suffix_string))
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suffix_string++;
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@@ -2197,6 +2250,7 @@ check_Scc_OszcOperations (const char *l)
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suffix_string ++;
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}
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bad:
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as_bad (_("missing `}' or `,' in pseudo-suffix"));
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return -1;
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}
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@@ -4573,7 +4627,7 @@ build_rex2_prefix (void)
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| z| L'L | b | `v | aaa |
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*/
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static bool
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build_apx_evex_prefix (void)
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build_apx_evex_prefix (bool force_nd)
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{
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/* To mimic behavior for legacy insns, transform use of DATA16 and REX64 into
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their embedded-prefix representations. */
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@@ -4620,7 +4674,8 @@ build_apx_evex_prefix (void)
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/* Encode the NDD bit of the instruction promoted from the legacy
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space. ZU shares the same bit with NDD. */
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if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_MAP4)
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|| i.tm.opcode_modifier.operandconstraint == ZERO_UPPER)
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|| i.tm.opcode_modifier.operandconstraint == ZERO_UPPER
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|| force_nd)
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i.vex.bytes[3] |= 0x10;
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/* Encode SCC and oszc flags bits. */
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@@ -7462,7 +7517,7 @@ i386_assemble (char *line)
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if (is_apx_evex_encoding ())
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{
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if (!build_apx_evex_prefix ())
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if (!build_apx_evex_prefix (false))
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return;
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}
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else if (i.tm.opcode_modifier.vex)
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@@ -10972,7 +11027,8 @@ build_modrm_byte (void)
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if (i.tm.operand_types[op].bitfield.baseindex)
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break;
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if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4)
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if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None)
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+ (i.tm.opcode_modifier.operandconstraint == SCC) == 4)
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{
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expressionS *exp;
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@@ -10984,10 +11040,12 @@ build_modrm_byte (void)
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2. 4 operands: 4 register operands or 3 register operands
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plus 1 memory operand, with VexXDS.
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3. Other equivalent combinations when coming from s_insn(). */
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gas_assert (i.tm.opcode_modifier.vexvvvv
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&& i.tm.opcode_modifier.vexw);
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gas_assert (dot_insn ()
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|| i.tm.operand_types[dest].bitfield.class == RegSIMD);
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if (!dot_insn ())
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{
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gas_assert (i.tm.opcode_modifier.vexvvvv
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&& i.tm.opcode_modifier.vexw);
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gas_assert (i.tm.operand_types[dest].bitfield.class == RegSIMD);
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}
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/* Of the first two non-immediate operands the one with the template
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not allowing for a memory one is encoded in the immediate operand. */
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@@ -13275,7 +13333,8 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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const char *end;
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unsigned int j;
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valueT val;
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bool vex = false, xop = false, evex = false;
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bool vex = false, xop = false;
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enum { evex_none, evex_basic, evex_nd } evex = evex_none;
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struct last_insn *last_insn;
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init_globals ();
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@@ -13324,7 +13383,7 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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else if (startswith (line, "EVEX")
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&& (line[4] == '.' || is_whitespace (line[4])))
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{
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evex = true;
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evex = evex_basic;
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line += 4;
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}
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@@ -13543,6 +13602,20 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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line += 3;
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}
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if (line > end && evex && *line == '.')
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{
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if (line[1] == 'N' && line[2] == 'D')
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{
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evex = evex_nd;
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line += 3;
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}
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else if (line[1] == 'Z' && line[2] == 'U')
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{
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i.tm.opcode_modifier.operandconstraint = ZERO_UPPER;
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line += 3;
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}
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}
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if (line > end && *line && !is_whitespace (*line))
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{
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/* Improve diagnostic a little. */
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@@ -13612,6 +13685,25 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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}
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}
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if (evex == evex_basic && *line == '{')
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{
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int length = check_Scc_OszcOperations (line);
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if (length > 0)
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{
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line += length;
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if (is_whitespace (*line))
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++line;
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if (i.tm.opcode_modifier.operandconstraint)
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{
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as_bad (_("SCC/OSZC specifier cannot be used here"));
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goto bad;
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}
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i.tm.opcode_modifier.operandconstraint = SCC;
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}
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}
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/* Parse operands, if any, before evaluating encoding space. */
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if (*line == ',')
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{
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@@ -13713,7 +13805,8 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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/* Enforce certain constraints on operands. */
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switch (i.reg_operands + i.mem_operands
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+ (i.tm.extension_opcode != None))
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+ (i.tm.extension_opcode != None)
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+ (i.tm.opcode_modifier.operandconstraint == SCC))
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{
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case 0:
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if (i.short_form)
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@@ -13728,9 +13821,13 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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as_bad (_("too few register/memory operands"));
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goto done;
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}
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break;
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/* Fall through. */
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case 2:
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if (evex == evex_nd)
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{
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as_bad (_("too few register/memory operands"));
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goto done;
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}
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break;
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case 4:
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@@ -13743,9 +13840,12 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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}
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/* Fall through. */
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case 3:
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if (i.tm.opcode_modifier.operandconstraint == SCC)
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break;
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if (pp.encoding != encoding_default)
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{
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i.tm.opcode_modifier.vexvvvv = i.tm.extension_opcode == None
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i.tm.opcode_modifier.vexvvvv = (i.tm.extension_opcode == None
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&& evex != evex_nd)
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? VexVVVV_SRC1 : VexVVVV_DST;
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break;
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}
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@@ -14043,6 +14143,13 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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if (vex || xop)
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{
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if (is_apx_evex_encoding ())
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{
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as_bad (_("APX functionality cannot be used with %s encodings"),
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vex ? "VEX" : "XOP");
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goto done;
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}
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if (!i.tm.opcode_modifier.vex)
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i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
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@@ -14054,7 +14161,36 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
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if (!i.tm.opcode_modifier.evex)
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i.tm.opcode_modifier.evex = EVEXLIG;
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build_evex_prefix ();
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/* To keep earlier .insn uses working as far as possible, take the
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legacy path when opcode space is 4 bits wide (impossible to encode in
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extended EVEX), and when no "extended" syntax elements are used. */
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if ((!is_apx_evex_encoding () || i.insn_opcode_space > 7)
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&& evex == evex_basic
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&& !i.tm.opcode_modifier.operandconstraint)
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build_evex_prefix ();
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else if (i.insn_opcode_space > 7)
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{
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as_bad (_("opcode space cannot be larger than 7"));
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goto done;
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}
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else if (evex == evex_nd && (i.broadcast.type || i.broadcast.bytes))
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{
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as_bad (_("ND and broadcast cannot be used at the same time"));
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goto done;
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}
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else if (pp.has_nf && i.mask.reg)
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{
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as_bad (_("{nf} and masking cannot be used at the same time"));
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goto done;
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}
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else if (i.tm.opcode_modifier.operandconstraint == SCC
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&& (pp.has_nf || i.mask.reg))
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{
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as_bad (_("SCC cannot be used at the same time {nf} / masking"));
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goto done;
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}
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else if (!build_apx_evex_prefix (evex == evex_nd))
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goto done;
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i.rex &= REX_OPCODE;
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}
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else
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@@ -702,7 +702,7 @@ operand, as long as there is one.
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syntax tries to resemble that used in documentation:
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@itemize @bullet
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@item @code{VEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}]
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@item @code{EVEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}]
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@item @code{EVEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}][@code{.@var{opt}}]
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@item @code{XOP}@var{space}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{w}}]
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@end itemize
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@@ -717,10 +717,11 @@ only) @code{512} as well as @code{L0} / @code{L1} for VEX / XOP and
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@item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M31}
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for VEX
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@item @code{08}...@code{1f} for XOP
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@item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M15}
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@item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M7}
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for EVEX
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@end itemize
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@item @var{w} can be @code{WIG}, @code{W0}, or @code{W1}
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@item @var{opt} can be @code{ND} or @code{ZU}
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@end itemize
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Defaults:
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@@ -808,6 +809,12 @@ be suffixed by @code{@{:d@var{n}@}} to specify the size (in bytes).
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This can be combined with an embedded broadcast specifier:
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@samp{8(%eax)@{1to8:d8@}}.
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For SCC EVEX the @code{@{dfv=@}} specifier used by ordinary insns is
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extended and immediately follows the opcode specifier. The extension
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is that the SCC value needs to be specified and goes first, as in
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@code{@{scc=@var{n},dfv=...@}}. Unlike for ordinary insns @code{dfv=}
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may be omitted for brevity.
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@cindex @code{noopt} directive
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@item .noopt
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Disable instruction size optimization.
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@@ -63,4 +63,13 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 62 f5 fd 58 5a 40 01[ ]+vcvtpd2ph (0x)?8\(%rax\)\{1to8\},%xmm0
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[ ]*[a-f0-9]+: 62 f5 7c 48 5a 40 01[ ]+vcvtph2pd 0x10\(%rax\),%zmm0
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[ ]*[a-f0-9]+: 62 f5 7c 58 5a 40 01[ ]+vcvtph2pd (0x)?2\(%rax\)\{1to8\},%zmm0
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[ ]*[a-f0-9]+: 62 e4 7c 08 8b 00[ ]+movrs \(%rax\),%r16d
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[ ]*[a-f0-9]+: 62 fc 7c 08 8b 00[ ]+movrs \(%r16\),%eax
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[ ]*[a-f0-9]+: 62 f4 78 08 8b 04 00[ ]+movrs \(%rax,%r16(,1)?\),%eax
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[ ]*[a-f0-9]+: 62 fc 7c 08 60 c0[ ]+movbe %r16d,%eax
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[ ]*[a-f0-9]+: 62 f4 7c 0c 01 c0[ ]+\{nf\} add %eax,%eax
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[ ]*[a-f0-9]+: 62 f4 7c 18 01 c0[ ]+add %eax,%eax,%eax
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[ ]*[a-f0-9]+: 62 f4 ec 18 ff f1[ ]+push2p %rcx,%rdx
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[ ]*[a-f0-9]+: 62 f4 7f 18 42 c0[ ]+setzub %al
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[ ]*[a-f0-9]+: 62 f4 44 0b 39 c0[ ]+ccmpf \{dfv=of\} %eax,%eax
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#pass
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@@ -104,3 +104,24 @@ insn:
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# vcvtph2pd
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.insn EVEX.M5.W0 0x5a, 16(%rax){:d16}, %zmm0
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.insn EVEX.M5.W0 0x5a, 2(%rax){1to8:d2}, %zmm0
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# movrs (APX)
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.insn EVEX.L0.NP.M4 0x8b, (%rax), %r16d
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.insn EVEX.L0.NP.M4 0x8b, (%r16), %eax
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.insn EVEX.L0.NP.M4 0x8b, (%rax,%r16), %eax
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# movbe (APX)
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.insn EVEX.L0.NP.M4 0x60, %r16d, %eax
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# add (APX)
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.insn {nf} EVEX.L0.NP.M4 0x01, %eax, %eax
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.insn EVEX.L0.NP.M4.ND 0x01, %eax, %eax, %eax
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# push2p
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.insn EVEX.L0.NP.M4.W1.ND 0xff/6, %rcx, %rdx
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# setzub
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.insn EVEX.L0.F2.M4.ZU 0x42/0, %eax
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# ccmpf
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.insn EVEX.L0.NP.M4 0x39 {scc=0b1011,dfv=of}, %eax, %eax
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@@ -12,7 +12,7 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+:[ ]+c7[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+62 fc 7f 08 60[ ]+\(bad\)
|
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[ ]*[a-f0-9]+:[ ]+c7[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+62 e2 f9 41 91 84[ ]+vpgatherqq \(bad\),%zmm16\{%k1\}
|
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[ ]*[a-f0-9]+:[ ]+62 e2 f9 41 91 44[ ]+vpgatherqq \(bad\),%zmm16\{%k1\}
|
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[ ]*[a-f0-9]+:[ ]+cd ff[ ]+int \$0xff
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[ ]*[a-f0-9]+:[ ]+62 fd 7d 08 60[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+c7[ ]+.*
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|
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@@ -9,9 +9,8 @@ _start:
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#movbe %r23w,%ax set EVEX.pp = f2.
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.insn EVEX.L0.f2.M12.W0 0x60, %di, %ax
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#VSIB vpgatherqq (%rbp,%zmm17,8),%zmm16{%k1} set EVEX.P[10] == 0
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.byte 0x62, 0xe2, 0xf9, 0x41, 0x91, 0x84, 0xcd
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.byte 0xff
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#VSIB vpgatherqq -8(%rbp,%zmm17,8),%zmm16{%k1} set EVEX.U = 0.
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.insn EVEX.512.66.0f38.W1 0x91, -8(%rbp,%r17,8){:d8}, %zmm16{%k1}, %r16
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|
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#EVEX_MAP4 movbe %r23w,%ax set EVEX.mm == 0b01.
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.insn EVEX.L0.66.M13.W0 0x60, %di, %ax
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@@ -38,11 +37,11 @@ _start:
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#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[20](EVEX.b) == 0b1
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.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx){1to8}, %rcx
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||||
|
||||
#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
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||||
.byte 0x62, 0xf4, 0xe4, 0x08, 0xff, 0x04, 0x08
|
||||
#{evex} inc (%rax,%rcx), %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
|
||||
.insn EVEX.L0.NP.M4 0xff/0, (%rax,%rcx), %rbx
|
||||
|
||||
# pop2 %rdi, %r8 set EVEX.ND=0.
|
||||
.byte 0x62, 0xf4, 0x3c, 0x08, 0x8f, 0xc7
|
||||
.insn EVEX.L0.NP.M4.W0 0x8f/0, %rdi, %r8
|
||||
|
||||
# pop2 %rax, %rax
|
||||
.insn EVEX.L0.NP.M4.W0 0x8f/0, %rax, {sae}, %rax
|
||||
@@ -59,7 +58,7 @@ _start:
|
||||
#EVEX_MAP4 movbe %r18w,%ax set EVEX.nf = 1.
|
||||
.insn EVEX.L0.66.M12.W0 0x60, %di, %ax {%k4}
|
||||
|
||||
# EVEX_MAP4 movbe %r23w,%ax set EVEX.P[10] = 0.
|
||||
# EVEX_MAP4 movbe %r23w,%ax set EVEX.U = 0.
|
||||
.byte 0x62, 0xfc, 0x79, 0x08, 0x60, 0xc7
|
||||
|
||||
# ccmps {dfv=of,sf,zf,cf} %r15, %rdx set EVEX.ND = 1.
|
||||
|
||||
Reference in New Issue
Block a user