Update version number for maintenance release.

FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/CLICommands/CLI-commands.c

@@ -0,0 +1,666 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes, just to make the stats available to the CLI
+commands. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+#ifndef  configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+	#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that prints out IP address information.
+ */
+static portBASE_TYPE prvDisplayIPConfig( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that prints out the gathered demo debug stats.
+ */
+static portBASE_TYPE prvDisplayIPDebugStats( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that sends an ICMP ping request to an IP address.
+ */
+static portBASE_TYPE prvPingCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+#endif
+
+/* Structure that defines the "ip-config" command line command. */
+static const CLI_Command_Definition_t xIPConfig =
+{
+	( const int8_t * const ) "ip-config",
+	( const int8_t * const ) "ip-config:\r\n Displays IP address configuration\r\n\r\n",
+	prvDisplayIPConfig,
+	0
+};
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+	/* Structure that defines the "ip-debug-stats" command line command. */
+	static const CLI_Command_Definition_t xIPDebugStats =
+	{
+		( const int8_t * const ) "ip-debug-stats", /* The command string to type. */
+		( const int8_t * const ) "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n",
+		prvDisplayIPDebugStats, /* The function to run. */
+		0 /* No parameters are expected. */
+	};
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+/* Structure that defines the "run-time-stats" command line command.   This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+	( const int8_t * const ) "run-time-stats", /* The command string to type. */
+	( const int8_t * const ) "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n",
+	prvRunTimeStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command.  This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+	( const int8_t * const ) "task-stats", /* The command string to type. */
+	( const int8_t * const ) "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n",
+	prvTaskStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command.  This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+	( const int8_t * const ) "echo-3-parameters",
+	( const int8_t * const ) "echo-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n\r\n",
+	prvThreeParameterEchoCommand, /* The function to run. */
+	3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command.  This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+	( const int8_t * const ) "echo-parameters",
+	( const int8_t * const ) "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n",
+	prvParameterEchoCommand, /* The function to run. */
+	-1 /* The user can enter any number of commands. */
+};
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+	/* Structure that defines the "ping" command line command.  This takes an IP
+	address or host name and (optionally) the number of bytes to ping as
+	parameters. */
+	static const CLI_Command_Definition_t xPing =
+	{
+		( const int8_t * const ) "ping",
+		( const int8_t * const ) "ping <ipaddress> <optional:bytes to send>:\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n",
+		prvPingCommand, /* The function to run. */
+		-1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */
+	};
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	/* Structure that defines the "trace" command line command.  This takes a single
+	parameter, which can be either "start" or "stop". */
+	static const CLI_Command_Definition_t xStartStopTrace =
+	{
+		( const int8_t * const ) "trace",
+		( const int8_t * const ) "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n",
+		prvStartStopTraceCommand, /* The function to run. */
+		1 /* One parameter is expected.  Valid values are "start" and "stop". */
+	};
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterCLICommands( void )
+{
+	/* Register all the command line commands defined immediately above. */
+	FreeRTOS_CLIRegisterCommand( &xTaskStats );
+	FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+	FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+	FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+	FreeRTOS_CLIRegisterCommand( &xIPDebugStats );
+	FreeRTOS_CLIRegisterCommand( &xIPConfig );
+
+	#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+	{
+		FreeRTOS_CLIRegisterCommand( &xPing );
+	}
+	#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+	#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+		FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t *const pcHeader = ( int8_t * ) "Task          State  Priority  Stack	#\r\n************************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t * const pcHeader = ( int8_t * ) "Task            Abs Time      % Time\r\n****************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Return the parameter string. */
+		memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+		sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+		strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+		strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+		/* If this is the last of the three parameters then there are no more
+		strings to return after this one. */
+		if( lParameterNumber == 3L )
+		{
+			/* If this is the last of the three parameters then there are no more
+			strings to return after this one. */
+			xReturn = pdFALSE;
+			lParameterNumber = 0L;
+		}
+		else
+		{
+			/* There are more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		if( pcParameter != NULL )
+		{
+			/* Return the parameter string. */
+			memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+			sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+			strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+			strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+			/* There might be more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+		else
+		{
+			/* No more parameters were found.  Make sure the write buffer does
+			not contain a valid string. */
+			pcWriteBuffer[ 0 ] = 0x00;
+
+			/* No more data to return. */
+			xReturn = pdFALSE;
+
+			/* Start over the next time this command is executed. */
+			lParameterNumber = 0;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+	static portBASE_TYPE prvPingCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	int8_t * pcParameter;
+	portBASE_TYPE lParameterStringLength, xReturn;
+	uint32_t ulIPAddress, ulBytesToPing;
+	const uint32_t ulDefaultBytesToPing = 8UL;
+	int8_t cBuffer[ 16 ];
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		/* Start with an empty string. */
+		pcWriteBuffer[ 0 ] = 0x00;
+
+		/* Obtain the number of bytes to ping. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										2,						/* Return the second parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		if( pcParameter == NULL )
+		{
+			/* The number of bytes was not specified, so default it. */
+			ulBytesToPing = ulDefaultBytesToPing;
+		}
+		else
+		{
+			ulBytesToPing = atol( ( const char * ) pcParameter );
+		}
+
+		/* Obtain the IP address string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Attempt to obtain the IP address.   If the first character is not a
+		digit, assume the host name has been passed in. */
+		if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) )
+		{
+			ulIPAddress = FreeRTOS_inet_addr( ( const uint8_t * ) pcParameter );
+		}
+		else
+		{
+			/* Terminate the host name. */
+			pcParameter[ lParameterStringLength ] = 0x00;
+
+			/* Attempt to resolve host. */
+			ulIPAddress = FreeRTOS_gethostbyname( ( uint8_t * ) pcParameter );
+		}
+
+		/* Convert IP address, which may have come from a DNS lookup, to string. */
+		FreeRTOS_inet_ntoa( ulIPAddress, ( char * ) cBuffer );
+
+		if( ulIPAddress != 0 )
+		{
+			xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY );
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+
+		if( xReturn == pdFALSE )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "%s", "Could not send ping request\r\n" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn );
+		}
+
+		return pdFALSE;
+	}
+	/*-----------------------------------------------------------*/
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+
+	static portBASE_TYPE prvDisplayIPDebugStats( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	static portBASE_TYPE xIndex = -1;
+	extern xExampleDebugStatEntry_t xIPTraceValues[];
+	portBASE_TYPE xReturn;
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		xIndex++;
+
+		if( xIndex < xExampleDebugStatEntries() )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "%s %d\r\n", ( char * ) xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* Reset the index for the next time it is called. */
+			xIndex = -1;
+
+			/* Ensure nothing remains in the write buffer. */
+			pcWriteBuffer[ 0 ] = 0x00;
+			xReturn = pdFALSE;
+		}
+
+		return xReturn;
+	}
+	/*-----------------------------------------------------------*/
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+static portBASE_TYPE prvDisplayIPConfig( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+static portBASE_TYPE xIndex = 0;
+portBASE_TYPE xReturn;
+uint32_t ulAddress;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	switch( xIndex )
+	{
+		case 0 :
+			FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nIP address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 1 :
+			FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nNet mask " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 2 :
+			FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nGateway address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 3 :
+			FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nDNS server address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		default :
+			ulAddress = 0;
+			sprintf( ( char * ) pcWriteBuffer, "\r\n\r\n" );
+			xReturn = pdFALSE;
+			xIndex = 0;
+			break;
+	}
+
+	if( ulAddress != 0 )
+	{
+		FreeRTOS_inet_ntoa( ulAddress, ( ( char * ) &( pcWriteBuffer[ strlen( ( char * ) pcWriteBuffer ) ] ) ) );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	int8_t *pcParameter;
+	portBASE_TYPE lParameterStringLength;
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* There are only two valid parameter values. */
+		if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )
+		{
+			/* Start or restart the trace. */
+			vTraceStop();
+			vTraceClear();
+			vTraceStart();
+
+			sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
+		}
+		else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )
+		{
+			/* End the trace, if one is running. */
+			vTraceStop();
+			sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+		}
+
+		/* There is no more data to return after this single string, so return
+		pdFALSE. */
+		return pdFALSE;
+	}
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */

FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.c

@@ -0,0 +1,401 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+/******************************************************************************
+ *
+ * See the following web page for essential TwoEchoClient.c usage and 
+ * configuration details:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml
+ *
+ ******************************************************************************/
+
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+UDP includes. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+/* Small delay used between attempts to obtain a zero copy buffer. */
+#define echoTINY_DELAY	( ( portTickType ) 2 )
+
+/* The echo tasks create a socket, send out a number of echo requests
+(listening for each echo reply), then close the socket again before
+starting over.  This delay is used between each iteration to ensure the
+network does not get too congested.  The delay is shorter when the Windows
+simulator is used because simulated time is slower than real time. */
+#ifdef _WINDOWS_
+	#define echoLOOP_DELAY	( ( portTickType ) 10 / portTICK_RATE_MS )
+#else
+	#define echoLOOP_DELAY	( ( portTickType ) 150 / portTICK_RATE_MS )
+#endif /* _WINDOWS_ */
+
+#if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1
+	/* When the trace recorder code is included user events are generated to
+	mark the sending and receiving of the echoed data (only in the zero copy
+	task. */
+	#define echoMARK_SEND_IN_TRACE_BUFFER( x ) vTraceUserEvent( x )
+	traceLabel xZeroCopySendEvent, xZeroCopyReceiveEvent;
+
+#else
+	/* When the trace recorder code is not included just #define away the call
+	to post the user event. */
+	#define echoMARK_SEND_IN_TRACE_BUFFER( x )
+	#define xZeroCopySendEvent 0
+	#define xZeroCopyReceiveEvent 0
+#endif
+
+/* The echo server is assumed to be on port 7, which is the standard echo
+protocol port. */
+#define echoECHO_PORT	( 7 )
+
+/*
+ * Uses a socket to send data to, then receive data from, the standard echo
+ * port number 7.  prvEchoClientTask() uses the standard interface.
+ * prvZeroCopyEchoClientTask() uses the zero copy interface.
+ */
+static void prvEchoClientTask( void *pvParameters );
+static void prvZeroCopyEchoClientTask( void *pvParameters );
+
+/* The receive timeout is set shorter when the windows simulator is used
+because simulated time is slower than real time. */
+#ifdef _WINDOWS_
+	const portTickType xReceiveTimeOut = 50 / portTICK_RATE_MS;
+#else
+	const portTickType xReceiveTimeOut = 500 / portTICK_RATE_MS;
+#endif
+
+/*-----------------------------------------------------------*/
+
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority )
+{
+	/* Create the echo client task that does not use the zero copy interface. */
+	xTaskCreate( 	prvEchoClientTask,						/* The function that implements the task. */
+					( const signed char * const ) "Echo0",	/* Just a text name for the task to aid debugging. */
+					usTaskStackSize,						/* The stack size is defined in FreeRTOSIPConfig.h. */
+					NULL,									/* The task parameter, not used in this case. */
+					uxTaskPriority,							/* The priority assigned to the task is defined in FreeRTOSConfig.h. */
+					NULL );									/* The task handle is not used. */
+
+	/* Create the echo client task that does use the zero copy interface. */
+	xTaskCreate( 	prvZeroCopyEchoClientTask,				/* The function that implements the task. */
+					( const signed char * const ) "Echo1",	/* Just a text name for the task to aid debugging. */
+					usTaskStackSize,						/* The stack size is defined in FreeRTOSIPConfig.h. */
+					NULL,									/* The task parameter, not used in this case. */
+					uxTaskPriority,							/* The priority assigned to the task is defined in FreeRTOSConfig.h. */
+					NULL );									/* The task handle is not used. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvEchoClientTask( void *pvParameters )
+{
+xSocket_t xSocket;
+struct freertos_sockaddr xEchoServerAddress;
+int8_t cTxString[ 25 ], cRxString[ 25 ]; /* Make sure the stack is large enough to hold these.  Turn on stack overflow checking during debug to be sure. */
+int32_t lLoopCount = 0UL;
+const int32_t lMaxLoopCount = 50;
+volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL;
+uint32_t xAddressLength = sizeof( xEchoServerAddress );
+
+	/* Remove compiler warning about unused parameters. */
+	( void ) pvParameters;
+
+	/* Echo requests are sent to the echo server.  The address of the echo
+	server is configured by the constants configECHO_SERVER_ADDR0 to
+	configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */
+	xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT );
+	xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0,
+															configECHO_SERVER_ADDR1,
+															configECHO_SERVER_ADDR2,
+															configECHO_SERVER_ADDR3 );
+
+	for( ;; )
+	{
+		/* Create a socket. */
+		xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP );
+		configASSERT( xSocket != FREERTOS_INVALID_SOCKET );
+
+		/* Set a time out so a missing reply does not cause the task to block
+		indefinitely. */
+		FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) );
+
+		/* Send a number of echo requests. */
+		for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ )
+		{
+			/* Create the string that is sent to the echo server. */
+			sprintf( ( char * ) cTxString, "Message number %u\r\n", ulTxCount );
+
+			/* Send the string to the socket.  ulFlags is set to 0, so the zero
+			copy interface is not used.  That means the data from cTxString is
+			copied into a network buffer inside FreeRTOS_sendto(), and cTxString
+			can be reused as soon as FreeRTOS_sendto() has returned.  1 is added
+			to ensure the NULL string terminator is sent as part of the message. */
+			FreeRTOS_sendto( xSocket,				/* The socket being sent to. */
+							( void * ) cTxString,	/* The data being sent. */
+							strlen( ( const char * ) cTxString ) + 1, /* The length of the data being sent. */
+							0,						/* ulFlags with the FREERTOS_ZERO_COPY bit clear. */
+							&xEchoServerAddress,	/* The destination address. */
+							sizeof( xEchoServerAddress ) );
+
+			/* Keep a count of how many echo requests have been transmitted so
+			it can be compared to the number of echo replies received.  It would
+			be expected to loose at least one to an ARP message the first time
+			the	connection is created. */
+			ulTxCount++;
+
+			/* Receive data echoed back to the socket.  ulFlags is zero, so the
+			zero copy option is not being used and the received data will be
+			copied into the buffer pointed to by cRxString.  xAddressLength is
+			not actually used (at the time of writing this comment, anyway) by
+			FreeRTOS_recvfrom(), but is set appropriately in case future
+			versions do use it. */
+			memset( ( void * ) cRxString, 0x00, sizeof( cRxString ) );
+			FreeRTOS_recvfrom(	xSocket,				/* The socket being received from. */
+								cRxString,				/* The buffer into which the received data will be written. */
+								sizeof( cRxString ),	/* The size of the buffer provided to receive the data. */
+								0,						/* ulFlags with the FREERTOS_ZERO_COPY bit clear. */
+								&xEchoServerAddress,	/* The address from where the data was sent (the source address). */
+								&xAddressLength );
+
+			/* Compare the transmitted string to the received string. */
+			if( strcmp( ( char * ) cRxString, ( char * ) cTxString ) == 0 )
+			{
+				/* The echo reply was received without error. */
+				ulRxCount++;
+			}
+		};
+
+		/* Pause for a short while to ensure the network is not too
+		congested. */
+		vTaskDelay( echoLOOP_DELAY );
+
+		/* Close this socket before looping back to create another. */
+		FreeRTOS_closesocket( xSocket );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvZeroCopyEchoClientTask( void *pvParameters )
+{
+xSocket_t xSocket;
+struct freertos_sockaddr xEchoServerAddress;
+static int8_t cTxString[ 40 ];
+int32_t lLoopCount = 0UL;
+volatile uint32_t ulRxCount = 0UL, ulTxCount = 0UL;
+uint32_t xAddressLength = sizeof( xEchoServerAddress );
+int32_t lReturned;
+uint8_t *pucUDPPayloadBuffer;
+
+const int32_t lMaxLoopCount = 50;
+const uint8_t * const pucStringToSend = ( const uint8_t * const ) "Zero copy message number";
+/* The buffer is large enough to hold the string, a number, and the string terminator. */
+const size_t xBufferLength = strlen( ( char * ) pucStringToSend ) + 15;
+
+	#if ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS == 1
+	{
+		/* When the trace recorder code is included user events are generated to
+		mark the sending and receiving of the echoed data (only in the zero copy
+		task). */
+		xZeroCopySendEvent = xTraceOpenLabel( "ZeroCopyTx" );
+		xZeroCopyReceiveEvent = xTraceOpenLabel( "ZeroCopyRx" );
+	}
+	#endif /* ipconfigINCLUDE_EXAMPLE_FREERTOS_PLUS_TRACE_CALLS */
+
+	/* Remove compiler warning about unused parameters. */
+	( void ) pvParameters;
+
+	/* Delay for a little while to ensure the task is out of synch with the
+	other echo task implemented above. */
+	vTaskDelay( echoLOOP_DELAY >> 1 );
+
+	/* Echo requests are sent to the echo server.  The address of the echo
+	server is configured by the constants configECHO_SERVER_ADDR0 to
+	configECHO_SERVER_ADDR3 in FreeRTOSConfig.h. */
+	xEchoServerAddress.sin_port = FreeRTOS_htons( echoECHO_PORT );
+	xEchoServerAddress.sin_addr = FreeRTOS_inet_addr_quick( configECHO_SERVER_ADDR0,
+															configECHO_SERVER_ADDR1,
+															configECHO_SERVER_ADDR2,
+															configECHO_SERVER_ADDR3 );
+
+	for( ;; )
+	{
+		/* Create a socket. */
+		xSocket = FreeRTOS_socket( FREERTOS_AF_INET, FREERTOS_SOCK_DGRAM, FREERTOS_IPPROTO_UDP );
+		configASSERT( xSocket != FREERTOS_INVALID_SOCKET );
+
+		/* Set a time out so a missing reply does not cause the task to block
+		indefinitely. */
+		FreeRTOS_setsockopt( xSocket, 0, FREERTOS_SO_RCVTIMEO, &xReceiveTimeOut, sizeof( xReceiveTimeOut ) );
+
+		/* Send a number of echo requests. */
+		for( lLoopCount = 0; lLoopCount < lMaxLoopCount; lLoopCount++ )
+		{
+			/* This task is going to send using the zero copy interface.  The
+			data being sent is therefore written directly into a buffer that is
+			passed by reference into the FreeRTOS_sendto() function.  First
+			obtain a buffer of adequate size from the IP stack.  Although a max
+			delay is used, the actual delay will be capped to
+			ipconfigMAX_SEND_BLOCK_TIME_TICKS, hence the test to ensure a buffer
+			was actually obtained. */
+			pucUDPPayloadBuffer = ( uint8_t * ) FreeRTOS_GetUDPPayloadBuffer( xBufferLength, portMAX_DELAY );
+
+			if( pucUDPPayloadBuffer != NULL )
+			{
+				/* A buffer was successfully obtained.  Create the string that is
+				sent to the echo server.  Note the string is written directly
+				into the buffer obtained from the IP stack. */
+				sprintf( ( char * ) pucUDPPayloadBuffer, "%s %u\r\n", ( const char * ) "Zero copy message number", ulTxCount );
+
+				/* Also copy the string into a local buffer so it can be compared
+				with the string that is later received back from the echo server. */
+				strcpy( ( char * ) cTxString, ( char * ) pucUDPPayloadBuffer );
+
+				/* Pass the buffer into the send function.  ulFlags has the
+				FREERTOS_ZERO_COPY bit set so the IP stack will take control of
+				the	buffer, rather than copy data out of the buffer. */
+				echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopySendEvent );
+				lReturned = FreeRTOS_sendto( 	xSocket,					/* The socket being sent to. */
+												( void * ) pucUDPPayloadBuffer,	/* The buffer being passed into the IP stack. */
+												strlen( ( const char * ) cTxString ) + 1, /* The length of the data being sent.  Plus 1 to ensure the null terminator is part of the data. */
+												FREERTOS_ZERO_COPY,			/* ulFlags with the zero copy bit is set. */
+												&xEchoServerAddress,		/* Where the data is being sent. */
+												sizeof( xEchoServerAddress ) );
+
+				if( lReturned == 0 )
+				{
+					/* The send operation failed, so this task is still
+					responsible	for the buffer obtained from the IP stack.  To
+					ensure the buffer is not lost it must either be used again,
+					or, as in this case, returned to the IP stack using
+					FreeRTOS_ReleaseUDPPayloadBuffer().  pucUDPPayloadBuffer can
+					be safely re-used to receive from the socket below once the
+					buffer has been returned to the stack. */
+					FreeRTOS_ReleaseUDPPayloadBuffer( ( void * ) pucUDPPayloadBuffer );
+				}
+				else
+				{
+					/* The send was successful so the IP stack is now managing
+					the	buffer pointed to by pucUDPPayloadBuffer, and the IP
+					stack will return the buffer once it has been sent.
+					pucUDPPayloadBuffer can	be safely re-used to receive from
+					the socket below. */
+				}
+
+				/* Keep a count of how many echo requests have been transmitted
+				so it can be compared to the number of echo replies received.
+				It would be expected to loose at least one to an ARP message the
+				first time the connection is created. */
+				ulTxCount++;
+
+				/* Receive data on the socket.  ulFlags has the zero copy bit set
+				(FREERTOS_ZERO_COPY) indicating to the stack that a reference to
+				the	received data should be passed out to this task using the
+				second parameter to the FreeRTOS_recvfrom() call.  When this is
+				done the IP stack is no longer responsible for releasing the
+				buffer, and	the task *must* return the buffer to the stack when
+				it is no longer	needed.  By default the receive block time is
+				portMAX_DELAY. */
+				echoMARK_SEND_IN_TRACE_BUFFER( xZeroCopyReceiveEvent );
+				lReturned = FreeRTOS_recvfrom(	xSocket,					/* The socket to receive from. */
+												( void * ) &pucUDPPayloadBuffer,  /* pucUDPPayloadBuffer will be set to point to the buffer that already contains the received data. */
+												0,							/* Ignored because the zero copy interface is being used. */
+												FREERTOS_ZERO_COPY,			/* ulFlags with the FREERTOS_ZERO_COPY bit set. */
+												&xEchoServerAddress,		/* The address from which the data was sent. */
+												&xAddressLength );
+
+				if( lReturned > 0 )
+				{
+					/* Compare the string sent to the echo server with the string
+					received back from the echo server. */
+					if( strcmp( ( char * ) pucUDPPayloadBuffer, ( char * ) cTxString ) == 0 )
+					{
+						/* The strings matched. */
+						ulRxCount++;
+					}
+
+					/* The buffer that contains the data passed out of the stack
+					*must* be returned to the stack. */
+					FreeRTOS_ReleaseUDPPayloadBuffer( pucUDPPayloadBuffer );
+				}
+			}
+		}
+
+		/* Pause for a short while to ensure the network is not too
+		congested. */
+		vTaskDelay( echoLOOP_DELAY );
+
+		/* Close this socket before looping back to create another. */
+		FreeRTOS_closesocket( xSocket );
+	}
+}
+/*-----------------------------------------------------------*/
+

FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/EchoClients/TwoEchoClients.h

@@ -0,0 +1,75 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef TWO_ECHO_CLIENTS_H
+#define TWO_ECHO_CLIENTS_H
+
+/*
+ * Create the two UDP echo client tasks.  One task uses the standard interface
+ * to send to and receive from an echo server.  The other task uses the zero
+ * copy interface to send to and receive from an echo server.
+ */
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );
+
+#endif /* TWO_ECHO_CLIENTS_H */

FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.c

@@ -0,0 +1,186 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* 
+ * This file, along with DemoIPTrace.h, provides a basic example use of the
+ * FreeRTOS+UDP trace macros.  The statistics gathered here can be viewed in
+ * the command line interface.
+ * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */ 
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+UDP includes. */
+#include "FreeRTOS_UDP_IP.h"
+#include "DemoIPTrace.h"
+
+/* It is possible to remove the trace macros using the 
+configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */
+#if configINCLUDE_DEMO_DEBUG_STATS == 1
+
+/*
+ * Each row in the xIPTraceValues[] table contains a pointer to a function that
+ * updates the value for that row.  Rows that latch the lowest value point to
+ * this function (for example, this function can be used to latch the lowest
+ * number of network buffers that were available during the execution of the
+ * stack).
+ */
+static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount );
+
+/*
+ * Each row in the xIPTraceValues[] table contains a pointer to a function that
+ * updates the value for that row.  Rows that simply increment an event count
+ * point to this function.
+ */
+static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount );
+
+
+xExampleDebugStatEntry_t xIPTraceValues[] =
+{
+	/* Comment out array entries to remove individual trace items. */
+
+	{ iptraceID_NETWORK_BUFFER_OBTAINED,			( const uint8_t * const ) "Lowest ever available network buffers",				prvStoreLowest, 0xffffUL },
+	{ iptraceID_NETWORK_EVENT_RECEIVED,				( const uint8_t * const ) "Lowest ever free space in network event queue",		prvStoreLowest, 0xffffUL },
+	{ iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER,	( const uint8_t * const ) "Count of failed attempts to obtain a network buffer",prvIncrementEventCount, 0 },
+	{ iptraceID_ARP_TABLE_ENTRY_EXPIRED,			( const uint8_t * const ) "Count of expired ARP entries",						prvIncrementEventCount, 0 },
+	{ iptraceID_PACKET_DROPPED_TO_GENERATE_ARP,		( const uint8_t * const ) "Count of packets dropped to generate ARP",			prvIncrementEventCount, 0 },
+	{ iptraceID_FAILED_TO_CREATE_SOCKET,			( const uint8_t * const ) "Count of failures to create a socket",				prvIncrementEventCount, 0 },
+	{ iptraceID_RECVFROM_DISCARDING_BYTES,			( const uint8_t * const ) "Count of times recvfrom() has discarding bytes",		prvIncrementEventCount, 0 },
+	{ iptraceID_ETHERNET_RX_EVENT_LOST,				( const uint8_t * const ) "Count of lost Ethenret Rx events (event queue full?)",prvIncrementEventCount, 0 },
+	{ iptraceID_STACK_TX_EVENT_LOST,				( const uint8_t * const ) "Count of lost IP stack events (event queue full?)",	prvIncrementEventCount, 0 },
+	{ ipconfigID_BIND_FAILED,						( const uint8_t * const ) "Count of failed calls to bind()",					prvIncrementEventCount, 0 },
+	{ iptraceID_NETWORK_INTERFACE_TRANSMIT,			( const uint8_t * const ) "Count of transmitted packets",						prvIncrementEventCount, 0 },
+	{ iptraceID_RECVFROM_TIMEOUT,					( const uint8_t * const ) "Count of receive timeouts",							prvIncrementEventCount, 0 },
+	{ iptraceID_SENDTO_DATA_TOO_LONG,				( const uint8_t * const ) "Count of failed sends due to oversized payload",		prvIncrementEventCount, 0 },
+	{ iptraceID_SENDTO_SOCKET_NOT_BOUND,			( const uint8_t * const ) "Count of failed sends due to unbound socket",		prvIncrementEventCount, 0 },
+	{ iptraceID_NO_BUFFER_FOR_SENDTO,				( const uint8_t * const ) "Count of failed transmits due to timeout",			prvIncrementEventCount, 0 },
+	{ iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR,			( const uint8_t * const ) "Number of times task had to wait to obtain a DMA Tx descriptor", prvIncrementEventCount, 0 },
+	{ iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP,		( const uint8_t * const ) "Failed to notify select group",						prvIncrementEventCount, 0 }
+};
+
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xExampleDebugStatEntries( void )
+{
+	/* Return the number of entries in the xIPTraceValues[] table. */
+	return ( portBASE_TYPE ) ( sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t ) );
+}
+/*-----------------------------------------------------------*/
+
+void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue )
+{
+portBASE_TYPE xIndex;
+const portBASE_TYPE xEntries = sizeof( xIPTraceValues ) / sizeof( xExampleDebugStatEntry_t );
+
+	/* Update an entry in the xIPTraceValues[] table.  Each row in the table
+	includes a pointer to a function that performs the actual update.  This
+	function just executes the update function from that table row. */
+	for( xIndex = 0; xIndex < xEntries; xIndex++ )
+	{
+		if( xIPTraceValues[ xIndex ].ucIdentifier == ucIdentifier )
+		{
+			xIPTraceValues[ xIndex ].vPerformAction( &( xIPTraceValues[ xIndex ].ulData ), ulValue );
+			break;
+		}
+	}
+
+	configASSERT( xIndex != xEntries );
+}
+/*-----------------------------------------------------------*/
+
+static void prvIncrementEventCount( uint32_t *pulCurrentValue, uint32_t ulCount )
+{
+	/* Each row in the xIPTraceValues[] table contains a pointer to a function
+	that updates the value for that row.  Rows that simply increment an event
+	count point to this function. */
+	( void ) ulCount;
+	( *pulCurrentValue )++;
+}
+/*-----------------------------------------------------------*/
+
+static void prvStoreLowest( uint32_t *pulCurrentValue, uint32_t ulCount )
+{
+	/* Each row in the xIPTraceValues[] table contains a pointer to a function
+	that updates the value for that row.  Rows that latch the lowest value
+	point to this function (for example, this function can be used to latch
+	the lowest number of network buffers that were available during the
+	execution of the stack). */
+	if( ulCount < *pulCurrentValue )
+	{
+		*pulCurrentValue = ulCount;
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */
+
+
+
+

FreeRTOS-Plus/Demo/Common/FreeRTOS_Plus_UDP_Demos/TraceMacros/Example1/DemoIPTrace.h

@@ -0,0 +1,154 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * This file, along with DemoIPTrace.h, provides a basic example use of the
+ * FreeRTOS+UDP trace macros.  The statistics gathered here can be viewed in
+ * the command line interface.
+ * See http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml
+ */
+
+#ifndef DEMO_IP_TRACE_MACROS_H
+#define DEMO_IP_TRACE_MACROS_H
+
+typedef void ( *vTraceAction_t )( uint32_t *, uint32_t );
+
+/* Type that defines each statistic being gathered. */
+typedef struct ExampleDebugStatEntry
+{
+	uint8_t ucIdentifier;					/* Unique identifier for statistic. */
+	const uint8_t * const pucDescription;	/* Text description for the statistic. */
+	vTraceAction_t vPerformAction;			/* Action to perform when the statistic is updated (increment counter, store minimum value, store maximum value, etc. */
+	uint32_t ulData; 						/* The meaning of this data is dependent on the trace macro ID. */
+} xExampleDebugStatEntry_t;
+
+/* Unique identifiers used to locate the entry for each trace macro in the
+xIPTraceValues[] table defined in DemoIPTrace.c. */
+#define iptraceID_NETWORK_BUFFER_OBTAINED					1
+#define iptraceID_NETWORK_BUFFER_OBTAINED_FROM_ISR			2
+#define iptraceID_NETWORK_EVENT_RECEIVED					3
+#define iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER			4
+#define iptraceID_ARP_TABLE_ENTRY_EXPIRED					5
+#define iptraceID_PACKET_DROPPED_TO_GENERATE_ARP			6
+#define iptraceID_FAILED_TO_CREATE_SOCKET					7
+#define iptraceID_RECVFROM_DISCARDING_BYTES					8
+#define iptraceID_ETHERNET_RX_EVENT_LOST					9
+#define iptraceID_STACK_TX_EVENT_LOST						10
+#define ipconfigID_BIND_FAILED								11
+#define iptraceID_NETWORK_INTERFACE_TRANSMIT				12
+#define iptraceID_RECVFROM_TIMEOUT							13
+#define iptraceID_SENDTO_DATA_TOO_LONG						14
+#define iptraceID_SENDTO_SOCKET_NOT_BOUND					15
+#define iptraceID_NO_BUFFER_FOR_SENDTO						16
+#define iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR				17
+#define iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP				18
+
+/* It is possible to remove the trace macros using the
+configINCLUDE_DEMO_DEBUG_STATS setting in FreeRTOSIPConfig.h. */
+#if configINCLUDE_DEMO_DEBUG_STATS == 1
+
+	/* The trace macro definitions themselves.  Any trace macros left undefined
+	will default to be empty macros. */
+	#define iptraceNETWORK_BUFFER_OBTAINED( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
+	#define iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxBufferAddress ) vExampleDebugStatUpdate( iptraceID_NETWORK_BUFFER_OBTAINED, uxQueueMessagesWaiting( ( xQueueHandle ) xNetworkBufferSemaphore ) )
+
+	#define iptraceNETWORK_EVENT_RECEIVED( eEvent )	{																				\
+														uint16_t usSpace;															\
+															usSpace = ( uint16_t ) uxQueueMessagesWaiting( xNetworkEventQueue );	\
+															/* Minus one as an event was removed before the space was queried. */	\
+															usSpace = ( ipconfigEVENT_QUEUE_LENGTH - usSpace ) - 1;					\
+															vExampleDebugStatUpdate( iptraceID_NETWORK_EVENT_RECEIVED, usSpace );	\
+														}
+
+	#define iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER()					vExampleDebugStatUpdate( iptraceID_FAILED_TO_OBTAIN_NETWORK_BUFFER, 0 )
+	#define iptraceARP_TABLE_ENTRY_EXPIRED( ulIPAddress )				vExampleDebugStatUpdate( iptraceID_ARP_TABLE_ENTRY_EXPIRED, 0 )
+	#define iptracePACKET_DROPPED_TO_GENERATE_ARP( ulIPAddress )		vExampleDebugStatUpdate( iptraceID_PACKET_DROPPED_TO_GENERATE_ARP, 0 )
+	#define iptraceFAILED_TO_CREATE_SOCKET()							vExampleDebugStatUpdate( iptraceID_FAILED_TO_CREATE_SOCKET, 0 )
+	#define iptraceRECVFROM_DISCARDING_BYTES( xNumberOfBytesDiscarded )	vExampleDebugStatUpdate( iptraceID_RECVFROM_DISCARDING_BYTES, 0 )
+	#define iptraceETHERNET_RX_EVENT_LOST()								vExampleDebugStatUpdate( iptraceID_ETHERNET_RX_EVENT_LOST, 0 )
+	#define iptraceSTACK_TX_EVENT_LOST( xEvent )						vExampleDebugStatUpdate( iptraceID_STACK_TX_EVENT_LOST, 0 )
+	#define iptraceBIND_FAILED( xSocket, usPort )						vExampleDebugStatUpdate( ipconfigID_BIND_FAILED, 0 )
+	#define iptraceNETWORK_INTERFACE_TRANSMIT()							vExampleDebugStatUpdate( iptraceID_NETWORK_INTERFACE_TRANSMIT, 0 )
+	#define iptraceRECVFROM_TIMEOUT()									vExampleDebugStatUpdate( iptraceID_RECVFROM_TIMEOUT, 0 )
+	#define iptraceSENDTO_DATA_TOO_LONG()								vExampleDebugStatUpdate( iptraceID_SENDTO_DATA_TOO_LONG, 0 )
+	#define iptraceSENDTO_SOCKET_NOT_BOUND()							vExampleDebugStatUpdate( iptraceID_SENDTO_SOCKET_NOT_BOUND, 0 )
+	#define iptraceNO_BUFFER_FOR_SENDTO()								vExampleDebugStatUpdate( iptraceID_NO_BUFFER_FOR_SENDTO, 0 )
+	#define iptraceWAITING_FOR_TX_DMA_DESCRIPTOR()						vExampleDebugStatUpdate( iptraceID_WAIT_FOR_TX_DMA_DESCRIPTOR, 0 )
+	#define iptraceFAILED_TO_NOTIFY_SELECT_GROUP( xSocket )				vExampleDebugStatUpdate( iptraceID_FAILED_TO_NOTIFY_SELECT_GROUP, 0 )
+
+	/*
+	 * The function that updates a line in the xIPTraceValues table.
+	 */
+	void vExampleDebugStatUpdate( uint8_t ucIdentifier, uint32_t ulValue );
+
+	/*
+	 * Returns the number of entries in the xIPTraceValues table.
+	 */
+	portBASE_TYPE xExampleDebugStatEntries( void );
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS == 1 */
+
+
+#endif /* DEMO_IP_TRACE_MACROS_H */
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/CLI-commands.c

@@ -1,67 +1,65 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
 /* FreeRTOS includes. */
@@ -74,6 +72,12 @@
 /* FreeRTOS+Trace includes. */
 #include "trcUser.h"
 
+/*
+ * Writes trace data to a disk file when the trace recording is stopped.
+ * This function will simply overwrite any trace files that already exist.
+ */
+static void prvSaveTraceFile( void );
+
 /*
  * Defines a command that returns a table showing the state of each task at the
  * time the command is called.
@@ -93,13 +97,13 @@ static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWrit
 static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
 
 /*
- * Defines a command that can take a variable number of parameters.  Each 
+ * Defines a command that can take a variable number of parameters.  Each
  * parameter is echoes back one at a time.
  */
 static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
 
 /*
- * Defines a command that starts/stops events being recorded for offline viewing 
+ * Defines a command that starts/stops events being recorded for offline viewing
  * in FreeRTOS+Trace.
  */
 static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
@@ -122,8 +126,8 @@ static const CLI_Command_Definition_t xTaskStats =
 	0 /* No parameters are expected. */
 };
 
-/* Structure that defines the "echo_3_parameters" command line command.  This 
-takes exactly three parameters that the command simply echos back one at a 
+/* Structure that defines the "echo_3_parameters" command line command.  This
+takes exactly three parameters that the command simply echos back one at a
 time. */
 static const CLI_Command_Definition_t xThreeParameterEcho =
 {
@@ -133,8 +137,8 @@ static const CLI_Command_Definition_t xThreeParameterEcho =
 	3 /* Three parameters are expected, which can take any value. */
 };
 
-/* Structure that defines the "echo_parameters" command line command.  This 
-takes a variable number of parameters that the command simply echos back one at 
+/* Structure that defines the "echo_parameters" command line command.  This
+takes a variable number of parameters that the command simply echos back one at
 a time. */
 static const CLI_Command_Definition_t xParameterEcho =
 {
@@ -172,7 +176,7 @@ static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBu
 const int8_t *const pcHeader = ( int8_t * ) "Task          State  Priority  Stack	#\r\n************************************************\r\n";
 
 	/* Remove compile time warnings about unused parameters, and check the
-	write buffer is not NULL.  NOTE - for simplicity, this example assumes the 
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
 	write buffer length is adequate, so does not check for buffer overflows. */
 	( void ) pcCommandString;
 	( void ) xWriteBufferLen;
@@ -193,7 +197,7 @@ static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWrit
 const int8_t * const pcHeader = ( int8_t * ) "Task            Abs Time      % Time\r\n****************************************\r\n";
 
 	/* Remove compile time warnings about unused parameters, and check the
-	write buffer is not NULL.  NOTE - for simplicity, this example assumes the 
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
 	write buffer length is adequate, so does not check for buffer overflows. */
 	( void ) pcCommandString;
 	( void ) xWriteBufferLen;
@@ -216,7 +220,7 @@ portBASE_TYPE lParameterStringLength, xReturn;
 static portBASE_TYPE lParameterNumber = 0;
 
 	/* Remove compile time warnings about unused parameters, and check the
-	write buffer is not NULL.  NOTE - for simplicity, this example assumes the 
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
 	write buffer length is adequate, so does not check for buffer overflows. */
 	( void ) pcCommandString;
 	( void ) xWriteBufferLen;
@@ -240,7 +244,7 @@ static portBASE_TYPE lParameterNumber = 0;
 	{
 		/* Obtain the parameter string. */
 		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
-									( 
+									(
 										pcCommandString,		/* The command string itself. */
 										lParameterNumber,		/* Return the next parameter. */
 										&lParameterStringLength	/* Store the parameter string length. */
@@ -283,7 +287,7 @@ portBASE_TYPE lParameterStringLength, xReturn;
 static portBASE_TYPE lParameterNumber = 0;
 
 	/* Remove compile time warnings about unused parameters, and check the
-	write buffer is not NULL.  NOTE - for simplicity, this example assumes the 
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
 	write buffer length is adequate, so does not check for buffer overflows. */
 	( void ) pcCommandString;
 	( void ) xWriteBufferLen;
@@ -307,7 +311,7 @@ static portBASE_TYPE lParameterNumber = 0;
 	{
 		/* Obtain the parameter string. */
 		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
-									( 
+									(
 										pcCommandString,		/* The command string itself. */
 										lParameterNumber,		/* Return the next parameter. */
 										&lParameterStringLength	/* Store the parameter string length. */
@@ -349,7 +353,7 @@ int8_t *pcParameter;
 portBASE_TYPE lParameterStringLength;
 
 	/* Remove compile time warnings about unused parameters, and check the
-	write buffer is not NULL.  NOTE - for simplicity, this example assumes the 
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
 	write buffer length is adequate, so does not check for buffer overflows. */
 	( void ) pcCommandString;
 	( void ) xWriteBufferLen;
@@ -357,7 +361,7 @@ portBASE_TYPE lParameterStringLength;
 
 	/* Obtain the parameter string. */
 	pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
-								( 
+								(
 									pcCommandString,		/* The command string itself. */
 									1,						/* Return the first parameter. */
 									&lParameterStringLength	/* Store the parameter string length. */
@@ -372,7 +376,7 @@ portBASE_TYPE lParameterStringLength;
 		/* Start or restart the trace. */
 		vTraceStop();
 		vTraceClear();
-		vTraceStart();
+		uiTraceStart();
 
 		sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
 	}
@@ -380,7 +384,8 @@ portBASE_TYPE lParameterStringLength;
 	{
 		/* End the trace, if one is running. */
 		vTraceStop();
-		sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
+		sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording and dumping log to disk.\r\n" );
+		prvSaveTraceFile();
 	}
 	else
 	{
@@ -393,4 +398,21 @@ portBASE_TYPE lParameterStringLength;
 }
 /*-----------------------------------------------------------*/
 
+static void prvSaveTraceFile( void )
+{
+FILE* pxOutputFile;
+
+	fopen_s( &pxOutputFile, "Trace.dump", "wb");
+
+	if( pxOutputFile != NULL )
+	{
+		fwrite( RecorderDataPtr, sizeof( RecorderDataType ), 1, pxOutputFile );
+		fclose( pxOutputFile );
+		printf( "\r\nTrace output saved to Trace.dump\r\n" );
+	}
+	else
+	{
+		printf( "\r\nFailed to create trace dump file\r\n" );
+	}
+}
 

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/FreeRTOSConfig.h

@@ -1,72 +1,73 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
+
 #ifndef FREERTOS_CONFIG_H
 #define FREERTOS_CONFIG_H
 
+#include <stdint.h>
+
 /*-----------------------------------------------------------
  * Application specific definitions.
  *
@@ -80,7 +81,7 @@
 
 #define configUSE_PREEMPTION			1
 #define configUSE_IDLE_HOOK				1
-#define configUSE_TICK_HOOK				0
+#define configUSE_TICK_HOOK				1
 #define configTICK_RATE_HZ				( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
 #define configMINIMAL_STACK_SIZE		( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */
 #define configTOTAL_HEAP_SIZE			( ( size_t ) 0 ) /* This parameter has no effect when heap_3.c is included in the project. */
@@ -124,6 +125,12 @@ to exclude the API function. */
 #define INCLUDE_uxTaskGetStackHighWaterMark	1
 #define INCLUDE_xTaskGetSchedulerState		1
 
+/* This demo makes use of one or more example stats formatting functions.  These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form.  See the notes in the implementation of vTaskList() within 
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS	1
+
 /* Run time stats gathering definitions. */
 unsigned long ulGetRunTimeCounterValue( void );
 void vConfigureTimerForRunTimeStats( void );
@@ -149,7 +156,6 @@ take up unnecessary RAM. */
 
 
 /* Include the FreeRTOS+Trace FreeRTOS trace macro definitions. */
-#include "trcHooks.h"
-
+#include "trcKernelPort.h"
 
 #endif /* FREERTOS_CONFIG_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/READ_ME.url

@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Run-time-stats-utils.c

@@ -0,0 +1,140 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * Utility functions required to gather run time statistics.  See:
+ * http://www.freertos.org/rtos-run-time-stats.html
+ *
+ * Note that this is a simulated port, where simulated time is a lot slower than
+ * real time, therefore the run time counter values have no real meaningful
+ * units.
+ *
+ * Also note that it is assumed this demo is going to be used for short periods
+ * of time only, and therefore timer overflows are not handled.
+*/
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+
+/* FreeRTOS+Trace includes. */
+#include "trcUser.h"
+
+/* Variables used in the creation of the run time stats time base.  Run time
+stats record how much time each task spends in the Running state. */
+static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL;
+
+/*-----------------------------------------------------------*/
+
+void vConfigureTimerForRunTimeStats( void )
+{
+LARGE_INTEGER liPerformanceCounterFrequency, liInitialRunTimeValue;
+
+	/* Initialise the variables used to create the run time stats time base.
+	Run time stats record how much time each task spends in the Running
+	state. */
+
+	if( QueryPerformanceFrequency( &liPerformanceCounterFrequency ) == 0 )
+	{
+		llTicksPerHundedthMillisecond = 1;
+	}
+	else
+	{
+		/* How many times does the performance counter increment in 1/100th
+		millisecond. */
+		llTicksPerHundedthMillisecond = liPerformanceCounterFrequency.QuadPart / 100000LL;
+
+		/* What is the performance counter value now, this will be subtracted
+		from readings taken at run time. */
+		QueryPerformanceCounter( &liInitialRunTimeValue );
+		llInitialRunTimeCounterValue = liInitialRunTimeValue.QuadPart;
+	}
+}
+/*-----------------------------------------------------------*/
+
+unsigned long ulGetRunTimeCounterValue( void )
+{
+LARGE_INTEGER liCurrentCount;
+unsigned long ulReturn;
+
+	/* What is the performance counter value now? */
+	QueryPerformanceCounter( &liCurrentCount );
+
+	/* Subtract the performance counter value reading taken when the
+	application started to get a count from that reference point, then
+	scale to (simulated) 1/100ths of a millisecond. */
+	if( llTicksPerHundedthMillisecond == 0 )
+	{
+		/* The trace macros can call this function before the kernel has been
+		started, in which case llTicksPerHundedthMillisecond will not have been
+		initialised. */
+		ulReturn = 0;
+	}
+	else
+	{
+		ulReturn = ( unsigned long ) ( ( liCurrentCount.QuadPart - llInitialRunTimeCounterValue ) / llTicksPerHundedthMillisecond );
+	}
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcConfig.h

@@ -1,6 +1,6 @@
 /*******************************************************************************
- * FreeRTOS+Trace v2.2.2 Recorder Library
- * Percepio AB, www.percepio.se
+ * Tracealyzer v2.4.1 Recorder Library
+ * Percepio AB, www.percepio.com
  *
  * trcConfig.h
  *
@@ -9,12 +9,12 @@
  * appropriate for your system, and if necessary adjust these. Most likely, you 
  * will need to adjust the NTask, NISR, NQueue, NMutex and NSemaphore values to 
  * reflect the number of such objects in your system. These may be 
- * overapproximated, although larger values values implies more RAM usage.
+ * over-approximated, although larger values values implies more RAM usage.
  *
  * Terms of Use
  * This software is copyright Percepio AB. The recorder library is free for
  * use together with Percepio products. You may distribute the recorder library
- * in its original form, including modifications in trcPort.c and trcPort.h
+ * in its original form, including modifications in trcHardwarePort.c/.h
  * given that these modification are clearly marked as your own modifications
  * and documented in the initial comment section of these source files. 
  * This software is the intellectual property of Percepio AB and may not be 
@@ -36,17 +36,15 @@
  * damages, or the exclusion of implied warranties or limitations on how long an 
  * implied warranty may last, so the above limitations may not apply to you.
  *
- * FreeRTOS+Trace is available as Free Edition and in two premium editions.
- * You may use the premium features during 30 days for evaluation.
- * Download FreeRTOS+Trace at http://www.percepio.se/index.php?page=downloads
- *
- * Copyright Percepio AB, 2012.
- * www.percepio.se
+ * Copyright Percepio AB, 2013.
+ * www.percepio.com
  ******************************************************************************/
 
 #ifndef TRCCONFIG_H
 #define TRCCONFIG_H
 
+#include <stdint.h>
+
 /*******************************************************************************
  * CONFIGURATION RELATED TO CAPACITY AND ALLOCATION 
  ******************************************************************************/
@@ -61,11 +59,30 @@
  * vTracePrintF may use multiple records depending on the number of data args.
  ******************************************************************************/
 
-#if WIN32
-    #define EVENT_BUFFER_SIZE 3000
-#else
-    #define EVENT_BUFFER_SIZE 1000 /* Adjust wrt. to available RAM */
-#endif
+#define EVENT_BUFFER_SIZE 4000 /* Adjust wrt. to available RAM */
+
+
+/*******************************************************************************
+ * USE_LINKER_PRAGMA
+ *
+ * Macro which should be defined as an integer value, default is 0.
+ *
+ * If this is 1, the header file "recorderdata_linker_pragma.h" is included just
+ * before the declaration of RecorderData (in trcBase.c), i.e., the trace data 
+ * structure. This allows the user to specify a pragma with linker options. 
+ *
+ * Example (for IAR Embedded Workbench and NXP LPC17xx):
+ * #pragma location="AHB_RAM_MEMORY"
+ * 
+ * This example instructs the IAR linker to place RecorderData in another RAM 
+ * bank, the AHB RAM. This can also be used for other compilers with a similar
+ * pragmas for linker options.
+ * 
+ * Note that this only applies if using static allocation, see below.
+ ******************************************************************************/
+
+#define USE_LINKER_PRAGMA 0
+
 
 /*******************************************************************************
  * SYMBOL_TABLE_SIZE
@@ -80,6 +97,43 @@
  ******************************************************************************/
 #define SYMBOL_TABLE_SIZE 1000
 
+/*******************************************************************************
+ * USE_SEPARATE_USER_EVENT_BUFFER
+ *
+ * Macro which should be defined as an integer value.
+ * Default is zero (0).
+ *
+ * This enables and disables the use of the separate user event buffer.
+ *
+ * Note: When using the separate user event buffer, you may get an artificial
+ * task instance named "Unknown actor". This is added as a placeholder when the 
+ * user event history is longer than the task scheduling history.
+ ******************************************************************************/
+#define USE_SEPARATE_USER_EVENT_BUFFER 0
+
+/*******************************************************************************
+ * USER_EVENT_BUFFER_SIZE
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the capacity of the user event buffer, in number of slots.
+ * A single user event can use between 1 and X slots, depending on the data.
+ *
+ * Only in use if USE_SEPARATE_USER_EVENT_BUFFER is set to 1.
+ ******************************************************************************/
+#define USER_EVENT_BUFFER_SIZE 500
+
+/*******************************************************************************
+ * USER_EVENT_CHANNELS
+ *
+ * Macro which should be defined as an integer value.
+ *
+ * This defines the number of allowed user event channels.
+ *
+ * Only in use if USE_SEPARATE_USER_EVENT_BUFFER is set to 1.
+ ******************************************************************************/
+#define CHANNEL_FORMAT_PAIRS 32
+
 /*******************************************************************************
  * NTask, NISR, NQueue, NSemaphore, NMutex
  *
@@ -95,32 +149,33 @@
  *
  * Using too small values will give an error message through the vTraceError
  * routine, which makes the error message appear when opening the trace data
- * in FreeRTOS+Trace. If you are using the recorder status monitor task,
+ * in Tracealyzer. If you are using the recorder status monitor task,
  * any error messages are displayed in console prints, assuming that the
- * print macro has been defined properly (vConsolePrintMessage).
+ * print macro has been defined properly (vConsolePrintMessage). 
+ *
+ * It can be wise to start with very large values for these constants, 
+ * unless you are very confident on these numbers. Then do a recording and
+ * check the actual usage in Tracealyzer. This is shown by selecting
+ * View -> Trace Details -> Resource Usage -> Object Table
  * 
- * NOTE 2: If you include the monitor task (USE_TRACE_PROGRESS_MONITOR_TASK)
- * make sure to dimension NTask with this task accounted for.
+ * NOTE 2: Remember to account for all tasks created by the kernel, such as the 
+ * IDLE task, timer task, and any tasks created by other 3rd party 
+ * software components, such as communication stacks. The recorder also has an 
+ * optional monitor task to account for, if this is used.
+ * Moreover, one task slot is used to indicate "(startup)", i.e., a fictive 
+ * task that represent the time before the scheduler starts. 
+ * NTask should thus be at least 2-3 slots larger than your application task count.
  *
- * Also remember to account for all tasks created by FreeRTOS, such as the 
- * IDLE task, the FreeRTOS timer task, and any tasks created by other 3rd party 
- * software components, such as communication stacks.
- * Moreover, one task slot is used to indicate "(startup)", i.e., a "task" that 
- * represent the time before the first task starts. NTask should thus be at 
- * least 2-3 slots larger than your application task count.
- *
- * NOTE 3: The FreeRTOS timer task creates a Queue, that should be accounted 
- * for in NQueue.
  ******************************************************************************/
 #define NTask             15
-#define NISR              4
-#define NQueue            3
-#define NSemaphore        4
-#define NMutex            2
+#define NISR              15
+#define NQueue            15
+#define NSemaphore        15
+#define NMutex            15
 
 /* Maximum object name length for each class (includes zero termination) */
-#define NameLenTask       configMAX_TASK_NAME_LEN
-#define NameLenISR        10
+#define NameLenTask       15
+#define NameLenISR        15
 #define NameLenQueue      15
 #define NameLenSemaphore  15
 #define NameLenMutex      15
@@ -130,12 +185,12 @@
  *
  * Macro which should be defined as a string.
  *
- * This string is stored in the trace and displayed in FreeRTOS+Trace. Can be
+ * This string is stored in the trace and displayed in Tracealyzer. Can be
  * used to store, e.g., system version or build date. This is also used to store
  * internal error messages from the recorder, which if occurs overwrites the
  * value defined here. This may be maximum 256 chars.
  *****************************************************************************/
-#define TRACE_DESCRIPTION "FreeRTOS+Trace Demo"
+#define TRACE_DESCRIPTION "Tracealyzer Recorder Test Program"
 
 /******************************************************************************
  * TRACE_DESCRIPTION_MAX_LENGTH
@@ -173,6 +228,33 @@
  * CONFIGURATION REGARDING WHAT CODE/FEATURES TO INCLUDE
  *****************************************************************************/
 
+/******************************************************************************
+ * USE_TRACE_ASSERT
+ *
+ * Macro which should be defined as either zero (0) or one (1). 
+ * Default is 0.
+ *
+ * If this is one (1), the TRACE_ASSERT macro will verify that a condition is 
+ * true. If the condition is false, vTraceError() will be called.
+ *****************************************************************************/
+#define USE_TRACE_ASSERT 1
+
+/******************************************************************************
+ * INCLUDE_FLOAT_SUPPORT
+ *
+ * Macro which should be defined as either zero (0) or one (1). 
+ * Default is 1.
+ *
+ * If this is zero (0), all references to floating point values are removed,
+ * in case floating point values are not supported by the platform used.
+ * Floating point values are only used in vTracePrintF and its subroutines, to 
+ * store float (%f) or double (%lf) argments. 
+ *
+ * Note: vTracePrintF can still be used with integer and string arguments in
+ * either case.
+ *****************************************************************************/
+#define INCLUDE_FLOAT_SUPPORT 0
+
 /******************************************************************************
  * INCLUDE_USER_EVENTS
  *
@@ -185,11 +267,34 @@
  * much faster than a printf and can therefore be used in timing critical code.
  * See vTraceUserEvent() and vTracePrintF() in trcUser.h
  * 
- * Note that FreeRTOS+Trace Standard Edition or Professional Edition is required
- * for User Events, they are not displayed in FreeRTOS+Trace Free Edition.
+ * Note that Tracealyzer Standard Edition or Professional Edition is required
+ * for User Events, they are not displayed in Tracealyzer Free Edition.
  *****************************************************************************/
 #define INCLUDE_USER_EVENTS 1
 
+/*****************************************************************************
+ * INCLUDE_READY_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1). 
+ * Default is 1.
+ *
+ * If this is zero (0), the code for recording Ready events is 
+ * excluded. Note, this will make it impossible to calculate the correct
+ * response times.
+ *****************************************************************************/
+#define INCLUDE_READY_EVENTS 1
+
+/*****************************************************************************
+ * INCLUDE_NEW_TIME_EVENTS
+ *
+ * Macro which should be defined as either zero (0) or one (1). 
+ * Default is 0.
+ *
+ * If this is zero (1), events will be generated whenever the os clock is
+ * increased.
+ *****************************************************************************/
+#define INCLUDE_NEW_TIME_EVENTS 0
+
 /*****************************************************************************
  * INCLUDE_ISR_TRACING
  *
@@ -197,10 +302,11 @@
  * Default is 1.
  *
  * If this is zero (0), the code for recording Interrupt Service Routines is 
- * excluded to reduce code size. Note, recording ISRs require that you insert
- * calls to vTraceStoreISRBegin and vTraceStoreISREnd in your interrupt handlers.
- * There is no automatic recording of ISRs like for task scheduling, since 
- * FreeRTOS does not have a central interrupt dispatcher.
+ * excluded to reduce code size.
+ * 
+ * Note, if the kernel has no central interrupt dispatcher, recording ISRs 
+ * require that you insert calls to vTraceStoreISRBegin and vTraceStoreISREnd 
+ * in your interrupt handlers.
  *****************************************************************************/
 #define INCLUDE_ISR_TRACING 1
 
@@ -211,43 +317,42 @@
  * Default is 1.
  *
  * This must be enabled (1) if tasks, queues or other 
- * traced kernel objects are deleted at runtime, e.g., using vTaskDelete or 
- * vQueueDelete. If no deletes are made, this can be set to 0 in order to
- * exclude the delete-handling code. 
+ * traced kernel objects are deleted at runtime. If no deletes are made, this 
+ * can be set to 0 in order to exclude the delete-handling code.
  *****************************************************************************/
-#define INCLUDE_OBJECT_DELETE 1
+#define INCLUDE_OBJECT_DELETE 0
 
 /******************************************************************************
  * CONFIGURATION RELATED TO BEHAVIOR
  *****************************************************************************/
 
 /******************************************************************************
- * RECORDER_STORE_MODE
+ * TRACE_RECORDER_STORE_MODE
  *
  * Macro which should be defined as one of:
- * - STORE_MODE_RING_BUFFER
- * - STORE_MODE_STOP_WHEN_FULL
- * Default is STORE_MODE_RING_BUFFER.
+ * - TRACE_STORE_MODE_RING_BUFFER
+ * - TRACE_STORE_MODE_STOP_WHEN_FULL
+ * Default is TRACE_STORE_MODE_RING_BUFFER.
  *
- * With RECORDER_STORE_MODE set to STORE_MODE_RING_BUFFER, the events are stored
- * in a ring buffer, i.e., where the oldest events are overwritten when the
- * buffer becomes full. This allows you to get the last events leading up to an
- * interesting state, e.g., an error, without having a large trace buffer for
- * string the whole run since startup. In this mode, the recorder can run
+ * With TRACE_RECORDER_STORE_MODE set to TRACE_STORE_MODE_RING_BUFFER, the events are 
+ * stored in a ring buffer, i.e., where the oldest events are overwritten when 
+ * the buffer becomes full. This allows you to get the last events leading up 
+ * to an interesting state, e.g., an error, without having a large trace buffer
+ * for string the whole run since startup. In this mode, the recorder can run
  * "forever" as the buffer never gets full, i.e., in the sense that it always
  * has room for more events.
  *
- * To fetch the trace in mode STORE_MODE_RING_BUFFER, you need to first halt the
+ * To fetch the trace in mode TRACE_STORE_MODE_RING_BUFFER, you need to first halt the
  * system using your debugger and then do a RAM dump, or to explicitly stop the
  * recorder using vTraceStop() and then store/upload the trace data using a
- * FreeRTOS task that you need to provide yourself. The trace data is found in
- * the struct RecorderData, initialized in trcBase.c.
+ * task that you need to provide yourself. The trace data is found in the struct
+ * RecorderData, initialized in trcBase.c.
  *
  * Note that, if you upload the trace using a RAM dump, i.e., when the system is 
  * halted on a breakpoint or by a debugger command, there is no need to stop the 
  * recorder first.
  *
- * When RECORDER_STORE_MODE is STORE_MODE_STOP_WHEN_FULL, the recording is
+ * When TRACE_RECORDER_STORE_MODE is TRACE_STORE_MODE_STOP_WHEN_FULL, the recording is
  * stopped when the buffer becomes full. When the recorder stops itself this way
  * vTracePortEnd() is called which allows for custom actions, such as triggering
  * a task that stores the trace buffer, i.e., in case taking a RAM dump
@@ -255,12 +360,8 @@
  * saves the trace to file directly, but this is not recommended in a real-time
  * system since the scheduler is blocked during the processing of vTracePortEnd.
  *****************************************************************************/
-#ifndef WIN32
-#define RECORDER_STORE_MODE STORE_MODE_RING_BUFFER
-#else
-/* Default in the Win32 demo */
-#define RECORDER_STORE_MODE STORE_MODE_STOP_WHEN_FULL
-#endif
+
+#define TRACE_RECORDER_STORE_MODE TRACE_STORE_MODE_RING_BUFFER
 
 /******************************************************************************
  * STOP_AFTER_N_EVENTS
@@ -287,27 +388,21 @@
  *
  * For tasks with "infinite" main loops (non-terminating tasks), the concept
  * of a task instance has no clear definition, it is an application-specific
- * thing. FreeRTOS+Trace allows you to define Instance Finish Events (IFEs),
+ * thing. Tracealyzer allows you to define Instance Finish Events (IFEs),
  * which marks the point in a cyclic task when the "task instance" ends.
  * The IFE is a blocking kernel call, typically in the main loop of a task
  * which typically reads a message queue, waits for a semaphore or performs
  * an explicit delay.
  *
- * If USE_IMPLICIT_IFE_RULES is one (1), the following FreeRTOS kernel calls
- * are considered by default to be IFEs (Implicit IFEs):
- *  - vTaskDelay
- *  - vTaskDelayUntil
- *  - vTaskSuspend
- *  - xQueueReceive (blocking cases only)
- *  - xSemaphoreTake (blocking cases only)
+ * If USE_IMPLICIT_IFE_RULES is one (1), the kernel macros (trcKernelPort.h)
+ * will define what kernel calls are considered by default to be IFEs.
  *
- * However, Implicit IFEs only applies to blocking kernel calls. If an
- * xQueueReceive reads a message without blocking, it does not create a new
+ * However, Implicit IFEs only applies to blocking kernel calls. If a
+ * service reads a message without blocking, it does not create a new
  * instance since no blocking occurred.
  *
- * Moreover, the actual IFE might sometimes be another blocking call such as
- * xQueueSend or xSemaphoreGive. We therefore allow for user-defined
- * Explicit IFEs by calling
+ * Moreover, the actual IFE might sometimes be another blocking call. We 
+ * therefore allow for user-defined Explicit IFEs by calling
  *
  *     vTraceTaskInstanceIsFinished()
  *
@@ -315,8 +410,8 @@
  * additional event but instead stores the service code and object handle
  * of the IFE call as properties of the task.
  *
- * If using Explicit IFEs and the task also calls an Implicit IFE like
- * vTaskDelay, this may result in additional incorrect task instances.
+ * If using Explicit IFEs and the task also calls an Implicit IFE, this may 
+ * result in additional incorrect task instances.
  * This is solved by disabling the Implicit IFEs for the task, by adding
  * a call to
  * 
@@ -390,13 +485,13 @@
  * be mapped to your console "printf" routine. The task is named TraceMon but 
  * is intentionally excluded from the demo trace.
  *
- * Default is 1000 FreeRTOS ticks (typically 1 second). On the Windows port, a 
- * lower value is suggested since the Windows port runs very slowly, often 20-40
- * times slower than the simulated FreeRTOS time.
+ * Default is 1000 ticks (typically 1 second). On the Windows port, a lower 
+ * value is suggested since the Windows port runs very slowly, often 20-40
+ * times slower than the simulated time.
  *
  * See vTraceMonitorTask in trcUser.c
  *****************************************************************************/
-#if WIN32
+#ifdef WIN32
     #define TRACE_PROGRESS_MONITOR_TASK_PERIOD 100
 #else
     #define TRACE_PROGRESS_MONITOR_TASK_PERIOD 1000

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/Trace_Recorder_Configuration/trcHardwarePort.h

@@ -1,11 +1,11 @@
 /******************************************************************************* 
- * FreeRTOS+Trace v2.2.3 Recorder Library
- * Percepio AB, www.percepio.se
+ * Tracealyzer v2.4.1 Recorder Library
+ * Percepio AB, www.percepio.com
  *
- * trcPort.h
+ * trcHardwarePort.h
  *
- * Contains together with trcPort.c all portability issues of the trace recorder 
- * library.
+ * Contains together with trcHardwarePort.c all hardware portability issues of 
+ * the trace recorder library.
  *
  * Terms of Use
  * This software is copyright Percepio AB. The recorder library is free for
@@ -32,20 +32,16 @@
  * damages, or the exclusion of implied warranties or limitations on how long an 
  * implied warranty may last, so the above limitations may not apply to you.
  *
- * FreeRTOS+Trace is available as Free Edition and in two premium editions.
- * You may use the premium features during 30 days for evaluation.
- * Download FreeRTOS+Trace at http://www.percepio.se/index.php?page=downloads
- *
- * Copyright Percepio AB, 2012.
- * www.percepio.se
+ * Copyright Percepio AB, 2013.
+ * www.percepio.com
  ******************************************************************************/
 
 #ifndef TRCPORT_H
 #define TRCPORT_H
 
-#include "trcBase.h"
+#include "trcKernelPort.h"
 
-/* If FreeRTOS Win32 port */
+/* If Win32 port */
 #ifdef WIN32
 
    #undef _WIN32_WINNT
@@ -76,90 +72,101 @@
  * A hardware independent fallback option for event timestamping. Provides low 
  * resolution timestamps based on the OS tick.
  * This may be used on the Win32 port, but may also be used on embedded hardware 
- * platforms. Note that this gives suboptimal display in FreeRTOS+Trace. All 
- * time durations will be truncated to the OS tick frequency, typically 1 KHz. 
- * This means that a task or ISR that executes in less than 1 ms get an exection 
- * time of zero. They are however still visible in FreeRTOS+Trace. 
+ * platforms. All time durations will be truncated to the OS tick frequency, 
+ * typically 1 KHz. This means that a task or ISR that executes in less than 
+ * 1 ms get an execution time of zero.
  *
  * PORT_Win32
- * "Accurate" timestamping based on the Windows permance counter. Note that
- * this gives the host machine time, not the simulated FreeRTOS time (tick 
- * count). The timing of the Win32 FreeRTOS build is not real-time, since it 
- * depends on the scheduling and tick rate of Windows, which is very slow.
+ * "Accurate" timestamping based on the Windows performance counter. Note that
+ * this gives the host machine time.
  *
- * Officially supported hardware specific ports included are:
+ * Officially supported hardware timer ports:
  * - PORT_Atmel_AT91SAM7
+ * - PORT_Atmel_UC3A0
  * - PORT_ARM_CortexM 
  * - PORT_Renesas_RX600
+ * - PORT_Microchip_dsPIC_AND_PIC24
  *
  * We also provide several "unofficial" hardware-specific ports. There have 
  * been developed by external contributors, and have not yet been verified 
  * by Percepio AB. Let us know if you have problems getting these to work.
  * 
- * Unoffical hardware specific ports provided are:
+ * Unofficial hardware specific ports provided are:
  * - PORT_TEXAS_INSTRUMENTS_TMS570
  * - PORT_TEXAS_INSTRUMENTS_MSP430
  * - PORT_MICROCHIP_PIC32
- * - PORT_MICROCHIP_dsPIC_AND_PIC24
  * - PORT_XILINX_PPC405
  * - PORT_XILINX_PPC440
+ * - PORT_XILINX_MICROBLAZE
+ * - PORT_NXP_LPC210X
  *
- ******************************************************************************/
+ *****************************************************************************/
 
 #define PORT_NOT_SET                          -1
 
-/* Officially supported ports */
+/*** Officially supported hardware timer ports *******************************/
 #define PORT_HWIndependent                     0
 #define PORT_Win32                             1
 #define PORT_Atmel_AT91SAM7                    2
-#define PORT_ARM_CortexM                       3
-#define PORT_Renesas_RX600                     4
+#define PORT_Atmel_UC3A0                       3
+#define PORT_ARM_CortexM                       4
+#define PORT_Renesas_RX600                     5
+#define PORT_Microchip_dsPIC_AND_PIC24         6
 
-/* Unofficial ports, provided by external developers and not yet verified */
-#define PORT_TEXAS_INSTRUMENTS_TMS570          5
-#define PORT_TEXAS_INSTRUMENTS_MSP430          6
-#define PORT_MICROCHIP_PIC32                   7
-#define PORT_MICROCHIP_dsPIC_AND_PIC24         8
-#define PORT_XILINX_PPC405                     9
-#define PORT_XILINX_PPC440                    10
+/*** Unofficial ports, provided by external developers, not yet verified *****/
+#define PORT_TEXAS_INSTRUMENTS_TMS570          7
+#define PORT_TEXAS_INSTRUMENTS_MSP430          8
+#define PORT_MICROCHIP_PIC32                   9
+#define PORT_XILINX_PPC405                    10
+#define PORT_XILINX_PPC440                    11
+#define PORT_XILINX_MICROBLAZE                12
+#define PORT_NXP_LPC210X                      13
 
 /*** Select your port here! **************************************************/
-#define SELECTED_PORT PORT_NOT_SET
+#define SELECTED_PORT PORT_Win32
 /*****************************************************************************/
 
+#if (SELECTED_PORT == PORT_NOT_SET) 
+#error "You need to define SELECTED_PORT here!"
+#endif
+
 /*******************************************************************************
  * IRQ_PRIORITY_ORDER
  *
  * Macro which should be defined as an integer of 0 or 1.
  *
- * This should be 0 if lower irq priority values implies higher priority 
+ * This should be 0 if lower IRQ priority values implies higher priority 
  * levels, such as on ARM Cortex M. If the opposite scheme is used, i.e., 
- * if higher irq priority values means higher priority, this should be 1.
+ * if higher IRQ priority values means higher priority, this should be 1.
  *
  * This setting is not critical. It is used only to sort and colorize the 
  * interrupts in priority order, in case you record interrupts using
  * the vTraceStoreISRBegin and vTraceStoreISREnd routines.
  *
  * We provide this setting for some hardware architectures below:
- * - ARM Cortex M:      0  (lower irq priority values are more significant)
- * - Atmel AT91SAM7x:   1  (higher irq priority values are more significant)
- * - Renesas RX62N:     1  (higher irq priority values are more significant)
- * - Microchip PIC24:   0  (lower irq priority values are more significant)
- * - Microchip dsPIC:   0  (lower irq priority values are more significant)
- * - TI TMS570 (ARM Cortex R4F): 0  (lower irq priority values are more significant)
- * - Freescale HCS08:   0  (lower irq priority values are more significant)
- * - Freescale HCS12:   0  (lower irq priority values are more significant)
- * - Freescale ColdFire:   1  (higher irq priority values are more significant)
+ * - ARM Cortex M:       0 (lower IRQ priority values are more significant)
+ * - Atmel AT91SAM7x:    1 (higher IRQ priority values are more significant)
+ * - Atmel AVR32:        1 (higher IRQ priority values are more significant)
+ * - Renesas RX600:      1 (higher IRQ priority values are more significant)
+ * - Microchip PIC24:    0 (lower IRQ priority values are more significant)
+ * - Microchip dsPIC:    0 (lower IRQ priority values are more significant)
+ * - TI TMS570:          0 (lower IRQ priority values are more significant)
+ * - Freescale HCS08:    0 (lower IRQ priority values are more significant)
+ * - Freescale HCS12:    0 (lower IRQ priority values are more significant)
+ * - PowerPC 405:        0 (lower IRQ priority values are more significant)
+ * - PowerPC 440:        0 (lower IRQ priority values are more significant)
+ * - Freescale ColdFire: 1 (higher IRQ priority values are more significant)
+ * - NXP LPC210x:        0 (lower IRQ priority values are more significant)
+ * - MicroBlaze:        0  (lower IRQ priority values are more significant)
  *
  * If your chip is not on the above list, and you perhaps know this detail by 
- * heart, please inform us by e-mail to support@percepio.se.
- ******************************************************************************/
-#define IRQ_PRIORITY_ORDER 0
-
-/*******************************************************************************
- * HWTC macros
- * 
- * These four macros provides a hardware isolation layer, representing a 
+ * heart, please inform us by e-mail to support@percepio.com.
+ *
+ ******************************************************************************
+ *
+ * HWTC Macros 
+ *
+ * These four HWTC macros provides a hardware isolation layer representing a 
  * generic hardware timer/counter used for driving the operating system tick, 
  * such as the SysTick feature of ARM Cortex M3/M4, or the PIT of the Atmel 
  * AT91SAM7X.
@@ -187,23 +194,16 @@
  * (where the SysTick runs at the core clock frequency), the "differential 
  * timestamping" used in the recorder will more frequently insert extra XTS 
  * events to store the timestamps, which increases the event buffer usage. 
- * In such cases, to reduce the number of XTS events and thereby get a longer 
+ * In such cases, to reduce the number of XTS events and thereby get longer 
  * traces, you use HWTC_DIVISOR to scale down the timestamps and frequency.
  * Assuming a OS tick rate of 1 KHz, it is suggested to keep the effective timer
  * frequency below 65 MHz to avoid an excessive amount of XTS events. Thus, a
  * Cortex M chip running at 72 MHZ should use a HWTC_DIVISOR of 2, while a 
  * faster chip require a higher HWTC_DIVISOR value. 
  *
- * The HWTC macros and uiTracePortGetTimeStamp is the main porting issue
+ * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
  * or the trace recorder library. Typically you should not need to change
- * the code of uiTracePortGetTimeStamp if using the HWTC macros.
- *
- * OFFER FROM PERCEPIO:
- * For silicon companies and non-corporate FreeRTOS users (researchers, students,
- * hobbyists or early-phase startups) we have an attractive offer: 
- * Provide a hardware timer port and get a FREE single-user licence for
- * FreeRTOS+Trace Professional Edition. Read more about this offer at 
- * www.percepio.se or contact us directly at support@percepio.se.
+ * the code of vTracePortGetTimeStamp if using the HWTC macros.
  *
  ******************************************************************************/
 
@@ -214,13 +214,17 @@
     #define HWTC_PERIOD 0
     #define HWTC_DIVISOR 1
     
+    #define IRQ_PRIORITY_ORDER 1  // Please update according to your hardware...
+
 #elif (SELECTED_PORT == PORT_HWIndependent)
     
     #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
     #define HWTC_COUNT 0
     #define HWTC_PERIOD 1
     #define HWTC_DIVISOR 1
-    
+
+    #define IRQ_PRIORITY_ORDER 1  // Please update according to your hardware...
+
 #elif (SELECTED_PORT == PORT_Atmel_AT91SAM7)
 
     /* HWTC_PERIOD is hardcoded for AT91SAM7X256-EK Board (48 MHz)
@@ -231,6 +235,19 @@
     #define HWTC_PERIOD 2995 
     #define HWTC_DIVISOR 1
 
+    #define IRQ_PRIORITY_ORDER 1  // higher IRQ priority values are more significant
+
+#elif (SELECTED_PORT == PORT_Atmel_UC3A0) 
+  
+    /* For Atmel AVR32 (AT32UC3A) */
+  
+    #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
+    #define HWTC_COUNT sysreg_read(AVR32_COUNT)
+    #define HWTC_PERIOD ( TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ )
+    #define HWTC_DIVISOR 1    
+
+    #define IRQ_PRIORITY_ORDER 1  // higher IRQ priority values are more significant
+
 #elif (SELECTED_PORT == PORT_ARM_CortexM)
 
     /* For all chips using ARM Cortex M cores */
@@ -239,6 +256,8 @@
     #define HWTC_COUNT (*((uint32_t*)0xE000E018))
     #define HWTC_PERIOD ((*(uint32_t*)0xE000E014) + 1)
     #define HWTC_DIVISOR 2
+    
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
 
 #elif (SELECTED_PORT == PORT_Renesas_RX600)    
 
@@ -246,9 +265,40 @@
 
     #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
     #define HWTC_COUNT (CMT0.CMCNT)
-    #define HWTC_PERIOD ((((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/8))
+    #define HWTC_PERIOD ((((TRACE_PERIPHERAL_CLOCK_HZ/TRACE_TICK_RATE_HZ)-1)/8))
     #define HWTC_DIVISOR 1
 
+    #define IRQ_PRIORITY_ORDER 1  // higher IRQ priority values are more significant
+
+#elif (SELECTED_PORT == PORT_Microchip_dsPIC_AND_PIC24) 
+
+    /* For Microchip PIC24 and dsPIC (16 bit) */
+
+    /* Note: The trace library was originally designed for 32-bit MCUs, and is slower
+       than intended on 16-bit MCUs. Storing an event on a PIC24 takes about 70 µs. 
+       In comparison, 32-bit MCUs are often 10-20 times faster. If recording overhead 
+       becomes a problem on PIC24, use the filters to exclude less interesting tasks 
+       or system calls. */
+
+    #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
+    #define HWTC_COUNT (TMR1)
+    #define HWTC_PERIOD (PR1+1)
+    #define HWTC_DIVISOR 1
+
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
+
+#elif (SELECTED_PORT == PORT_NXP_LPC210X)
+    /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
+    
+    /* Tested with LPC2106, but should work with most LPC21XX chips. */
+      
+    #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
+    #define HWTC_COUNT  *((uint32_t *)0xE0004008 )
+    #define HWTC_PERIOD ( TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ ) 
+    #define HWTC_DIVISOR 1    
+
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
+
 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_TMS570)
     /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
 
@@ -260,14 +310,18 @@
     #define HWTC_PERIOD (RTIUDCP0)
     #define HWTC_DIVISOR 1
 
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
+
 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_MSP430)
     /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
 
     #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
     #define HWTC_COUNT (TA0R)
-    #define HWTC_PERIOD configCPU_CLOCKS_PER_TICK      
+    #define HWTC_PERIOD TRACE_CPU_CLOCKS_PER_TICK      
     #define HWTC_DIVISOR 1
 
+    #define IRQ_PRIORITY_ORDER 1  // higher IRQ priority values are more significant
+
 #elif (SELECTED_PORT == PORT_MICROCHIP_PIC32)
     /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
 
@@ -276,21 +330,17 @@
     #define HWTC_PERIOD (ReadPeriod1()+1) /* Should be available in BSP */
     #define HWTC_DIVISOR 1
 
-#elif (SELECTED_PORT == PORT_MICROCHIP_dsPIC_AND_PIC24) 
-    /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
-
-    #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
-    #define HWTC_COUNT (PR1)
-    #define HWTC_PERIOD ((configCPU_CLOCK_HZ/portTIMER_PRESCALE)/configTICK_RATE_HZ)
-    #define HWTC_DIVISOR 1
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
 
 #elif (SELECTED_PORT == PORT_XILINX_PPC405) 
     /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
 
     #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
     #define HWTC_COUNT  mfspr( 0x3db)
-    #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ )
-    #define HWTC_DIVISOR 1    
+    #define HWTC_PERIOD ( TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ )
+    #define HWTC_DIVISOR 1
+
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
 
 #elif (SELECTED_PORT == PORT_XILINX_PPC440) 
     /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
@@ -299,41 +349,63 @@
     
     #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
     #define HWTC_COUNT  mfspr( 0x016 )
-    #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ )
+    #define HWTC_PERIOD ( TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ )
     #define HWTC_DIVISOR 1    
 
-#else
-#error "SELECTED_PORT is not set, or had unsupported value!"
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
+    
+#elif (SELECTED_PORT == PORT_XILINX_MICROBLAZE)
+    /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
+
+    /* This should work with most Microblaze configurations.
+     * It uses the AXI Timer 0 - the tick interrupt source.
+     * If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.
+     */
+    #include "xtmrctr_l.h"
+
+    #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
+    #define HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
+    #define HWTC_PERIOD ( TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ )
+    #define HWTC_DIVISOR 16
+
+    #define IRQ_PRIORITY_ORDER 0  // lower IRQ priority values are more significant
+
+#elif (SELECTED_PORT != PORT_NOT_SET)
+
+    #error "SELECTED_PORT had unsupported value!"
+    #define SELECTED_PORT PORT_NOT_SET
+
 #endif
 
-#ifndef HWTC_COUNT_DIRECTION
-#error "HWTC_COUNT_DIRECTION is not set!"
-#endif 
-
-#ifndef HWTC_COUNT
-#error "HWTC_COUNT is not set!"    
-#endif 
-
-#ifndef HWTC_PERIOD
-#error "HWTC_PERIOD is not set!"
-#endif 
-
-#ifndef HWTC_DIVISOR
-#error "HWTC_DIVISOR is not set!"    
-#endif 
-
-#ifndef IRQ_PRIORITY_ORDER
-#error "IRQ_PRIORITY_ORDER is not set!"
-#endif 
-
-#if (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
-#error "IRQ_PRIORITY_ORDER has bad value!"
-#endif 
-
-#if (HWTC_DIVISOR < 1)
-#error "HWTC_DIVISOR must be a non-zero positive value!"
-#endif 
+#if (SELECTED_PORT != PORT_NOT_SET)
+    
+    #ifndef HWTC_COUNT_DIRECTION
+    #error "HWTC_COUNT_DIRECTION is not set!"
+    #endif 
+    
+    #ifndef HWTC_COUNT
+    #error "HWTC_COUNT is not set!"    
+    #endif 
+    
+    #ifndef HWTC_PERIOD
+    #error "HWTC_PERIOD is not set!"
+    #endif 
+    
+    #ifndef HWTC_DIVISOR
+    #error "HWTC_DIVISOR is not set!"    
+    #endif 
+    
+    #ifndef IRQ_PRIORITY_ORDER
+    #error "IRQ_PRIORITY_ORDER is not set!"
+    #elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
+    #error "IRQ_PRIORITY_ORDER has bad value!"
+    #endif 
+    
+    #if (HWTC_DIVISOR < 1)
+    #error "HWTC_DIVISOR must be a non-zero positive value!"
+    #endif 
 
+#endif
 /*******************************************************************************
  * vTraceConsoleMessage
  *
@@ -341,26 +413,25 @@
  * This needs to be correctly defined to see status reports from the trace 
  * status monitor task (this is defined in trcUser.c).
  ******************************************************************************/         
+#if (SELECTED_PORT == PORT_Atmel_AT91SAM7)
+/* Port specific includes */
+#include "console.h"
+#endif
+
 #define vTraceConsoleMessage(x)
 
 /*******************************************************************************
- * uiTracePortGetTimeStamp
+ * vTracePortGetTimeStamp
  *
  * Returns the current time based on the HWTC macros which provide a hardware
  * isolation layer towards the hardware timer/counter.
  *
- * The HWTC macros and uiTracePortGetTimeStamp is the main porting issue
+ * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
  * or the trace recorder library. Typically you should not need to change
- * the code of uiTracePortGetTimeStamp if using the HWTC macros.
+ * the code of vTracePortGetTimeStamp if using the HWTC macros.
  *
- * OFFER FROM PERCEPIO:
- * For silicon companies and non-corporate FreeRTOS users (researchers, 
- * students, hobbyists or early-phase startups) we have an attractive offer: 
- * Provide a hardware timer port and get a FREE single-user licence for
- * FreeRTOS+Trace Professional Edition. Read more about this offer at 
- * www.percepio.se or contact us directly at support@percepio.se.
  ******************************************************************************/
-uint32_t uiTracePortGetTimeStamp(void);
+void vTracePortGetTimeStamp(uint32_t *puiTimestamp);
 
 /*******************************************************************************
  * vTracePortEnd
@@ -392,6 +463,12 @@ void vTracePortSetOutFile(char* path);
  ******************************************************************************/
 void vTracePortSave(void);
 
+#else
+
+#define vTraceConsoleMessage(x)
+#define vTracePortSetOutFile(path)
+#define vTracePortSave(void)
+
 #endif
 
 #endif

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/UDPCommandServer.c

@@ -0,0 +1,258 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#pragma comment( lib, "ws2_32.lib" )
+
+/* Win32 includes. */
+#include <WinSock2.h>
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE	60
+
+/* Dimensions the buffer into which string outputs can be placed. */
+#define cmdMAX_OUTPUT_SIZE	1024
+
+/* Dimensions the buffer passed to the recvfrom() call. */
+#define cmdSOCKET_INPUT_BUFFER_SIZE 60
+
+/*
+ * Open and configure the UDP socket.
+ */
+static SOCKET prvOpenUDPSocket( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Task that provides the input and output for the FreeRTOS+CLI command
+ * interpreter.  In this case a UDP port is used.  See the URL in the comments
+ * within main.c for the location of the online documentation.
+ */
+void vUDPCommandInterpreterTask( void *pvParameters )
+{
+long lBytes, lByte;
+signed char cInChar, cInputIndex = 0;
+static signed char cInputString[ cmdMAX_INPUT_SIZE ], cOutputString[ cmdMAX_OUTPUT_SIZE ], cLocalBuffer[ cmdSOCKET_INPUT_BUFFER_SIZE ];
+portBASE_TYPE xMoreDataToFollow;
+volatile int iErrorCode = 0;
+struct sockaddr_in xClient;
+int xClientAddressLength = sizeof( struct sockaddr_in );
+SOCKET xSocket;
+
+	/* Just to prevent compiler warnings. */
+	( void ) pvParameters;
+
+	/* Attempt to open the socket. */
+	xSocket = prvOpenUDPSocket();
+
+	if( xSocket != INVALID_SOCKET )
+	{
+		for( ;; )
+		{
+			/* Wait for incoming data on the opened socket. */
+			lBytes = recvfrom( xSocket, cLocalBuffer, sizeof( cLocalBuffer ), 0, ( struct sockaddr * ) &xClient, &xClientAddressLength );
+
+			if( lBytes == SOCKET_ERROR )
+			{
+				/* Something went wrong, but it is not handled by this simple
+				example. */
+				iErrorCode = WSAGetLastError();
+			}
+			else
+			{
+				/* Process each received byte in turn. */
+				lByte = 0;
+				while( lByte < lBytes )
+				{
+					/* The next character in the input buffer. */
+					cInChar = cLocalBuffer[ lByte ];
+					lByte++;
+
+					/* Newline characters are taken as the end of the command
+					string. */
+					if( cInChar == '\n' )
+					{
+						/* Process the input string received prior to the
+						newline. */
+						do
+						{
+							/* Pass the string to FreeRTOS+CLI. */
+							xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE );
+
+							/* Send the output generated by the command's
+							implementation. */
+							sendto( xSocket, cOutputString,  strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+
+						} while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */
+
+						/* All the strings generated by the command processing
+						have been sent.  Clear the input string ready to receive
+						the next command. */
+						cInputIndex = 0;
+						memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+						/* Transmit a spacer, just to make the command console
+						easier to read. */
+						sendto( xSocket, "\r\n",  strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
+					}
+					else
+					{
+						if( cInChar == '\r' )
+						{
+							/* Ignore the character.  Newlines are used to
+							detect the end of the input string. */
+						}
+						else if( cInChar == '\b' )
+						{
+							/* Backspace was pressed.  Erase the last character
+							in the string - if any. */
+							if( cInputIndex > 0 )
+							{
+								cInputIndex--;
+								cInputString[ cInputIndex ] = '\0';
+							}
+						}
+						else
+						{
+							/* A character was entered.  Add it to the string
+							entered so far.  When a \n is entered the complete
+							string will be passed to the command interpreter. */
+							if( cInputIndex < cmdMAX_INPUT_SIZE )
+							{
+								cInputString[ cInputIndex ] = cInChar;
+								cInputIndex++;
+							}
+						}
+					}
+				}
+			}
+		}
+	}
+	else
+	{
+		/* The socket could not be opened. */
+		vTaskDelete( NULL );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static SOCKET prvOpenUDPSocket( void )
+{
+WSADATA xWSAData;
+WORD wVersionRequested;
+struct sockaddr_in xServer;
+SOCKET xSocket = INVALID_SOCKET;
+
+	wVersionRequested = MAKEWORD( 2, 2 );
+
+	/* Prepare to use WinSock. */
+	if( WSAStartup( wVersionRequested, &xWSAData ) != 0 )
+	{
+		fprintf( stderr, "Could not open Windows connection.\n" );
+	}
+	else
+	{
+		xSocket = socket( AF_INET, SOCK_DGRAM, 0 );
+		if( xSocket == INVALID_SOCKET)
+		{
+			fprintf( stderr, "Could not create socket.\n" );
+			WSACleanup();
+		}
+		else
+		{
+			/* Zero out the server structure. */
+			memset( ( void * ) &xServer, 0x00, sizeof( struct sockaddr_in ) );
+
+			/* Set family and port. */
+			xServer.sin_family = AF_INET;
+			xServer.sin_port = htons( configUDP_CLI_PORT_NUMBER );
+
+			/* Assign the loopback address */
+			xServer.sin_addr.S_un.S_un_b.s_b1 = 127;
+			xServer.sin_addr.S_un.S_un_b.s_b2 = 0;
+			xServer.sin_addr.S_un.S_un_b.s_b3 = 0;
+			xServer.sin_addr.S_un.S_un_b.s_b4 = 1;
+
+			/* Bind the address to the socket. */
+			if( bind( xSocket, ( struct sockaddr * ) &xServer, sizeof( struct sockaddr_in ) ) == -1 )
+			{
+				fprintf( stderr, "Could not socket to port %d.\n", configUDP_CLI_PORT_NUMBER );
+				closesocket( xSocket );
+				xSocket = INVALID_SOCKET;
+				WSACleanup();
+			}
+		}
+	}
+
+	return xSocket;
+}
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj

@@ -54,7 +54,7 @@
     </Midl>
     <ClCompile>
       <Optimization>Disabled</Optimization>
-      <AdditionalIncludeDirectories>..\..\FreeRTOS-Plus-Trace\Include;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\FreeRTOS-Plus-CLI;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <AdditionalIncludeDirectories>..\..\Source\FreeRTOS-Plus-Trace\Include;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;..\..\Source\FreeRTOS-Plus-CLI;.\Trace_Recorder_Configuration;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
       <PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions)</PreprocessorDefinitions>
       <MinimalRebuild>true</MinimalRebuild>
       <BasicRuntimeChecks>EnableFastChecks</BasicRuntimeChecks>
@@ -128,17 +128,18 @@
     </Bscmake>
   </ItemDefinitionGroup>
   <ItemGroup>
-    <ClCompile Include="..\..\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c" />
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcBase.c" />
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcKernel.c" />
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcPort.c" />
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcUser.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\list.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MemMang\heap_3.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MSVC-MingW\port.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\queue.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\tasks.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\timers.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcBase.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcHardwarePort.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcKernel.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcKernelPort.c" />
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcUser.c" />
     <ClCompile Include="CLI-commands.c" />
     <ClCompile Include="main.c">
       <AdditionalIncludeDirectories Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
@@ -149,16 +150,15 @@
     <ClCompile Include="UDPCommandServer.c" />
   </ItemGroup>
   <ItemGroup>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcBase.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcConfig.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcHooks.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcKernel.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcPort.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcTypes.h" />
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcUser.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcBase.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcHooks.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcKernel.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcKernelPort.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcTypes.h" />
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcUser.h" />
     <ClInclude Include="FreeRTOSConfig.h" />
     <ClInclude Include="Trace_Recorder_Configuration\trcConfig.h" />
-    <ClInclude Include="Trace_Recorder_Configuration\trcPort.h" />
+    <ClInclude Include="Trace_Recorder_Configuration\trcHardwarePort.h" />
   </ItemGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
   <ImportGroup Label="ExtensionTargets">

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/WIN32.vcxproj.filters

@@ -28,12 +28,10 @@
     <Filter Include="FreeRTOS+\FreeRTOS+Trace\Include">
       <UniqueIdentifier>{e17028e8-51ed-45af-8aa4-22ade709b3fb}</UniqueIdentifier>
     </Filter>
-    <Filter Include="FreeRTOS+\FreeRTOS+Trace\Configuration Files">
-      <UniqueIdentifier>{c0e94729-2842-4a9f-8549-a84a12f6f755}</UniqueIdentifier>
-    </Filter>
     <Filter Include="FreeRTOS\Configuration Files">
       <UniqueIdentifier>{19ff1a34-36de-4c48-9d10-3fb1fa0d1fa4}</UniqueIdentifier>
-      <Extensions>h;hpp;hxx;hm;inl</Extensions>
+      <Extensions>
+      </Extensions>
     </Filter>
     <Filter Include="FreeRTOS+\FreeRTOS+CLI">
       <UniqueIdentifier>{fd43c0ed-fdbc-437f-a5a3-c50399690bd7}</UniqueIdentifier>
@@ -64,21 +62,6 @@
     <ClCompile Include="..\..\..\FreeRTOS\Source\tasks.c">
       <Filter>FreeRTOS\Source</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcUser.c">
-      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
-    </ClCompile>
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcBase.c">
-      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
-    </ClCompile>
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcKernel.c">
-      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
-    </ClCompile>
-    <ClCompile Include="..\..\FreeRTOS-Plus-Trace\trcPort.c">
-      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
-    </ClCompile>
-    <ClCompile Include="..\..\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c">
-      <Filter>FreeRTOS+\FreeRTOS+CLI</Filter>
-    </ClCompile>
     <ClCompile Include="UDPCommandServer.c">
       <Filter>Demo App Source</Filter>
     </ClCompile>
@@ -88,36 +71,51 @@
     <ClCompile Include="Run-time-stats-utils.c">
       <Filter>Demo App Source</Filter>
     </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-CLI\FreeRTOS_CLI.c">
+      <Filter>FreeRTOS+\FreeRTOS+CLI</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcUser.c">
+      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcBase.c">
+      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcKernel.c">
+      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcHardwarePort.c">
+      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\Source\FreeRTOS-Plus-Trace\trcKernelPort.c">
+      <Filter>FreeRTOS+\FreeRTOS+Trace</Filter>
+    </ClCompile>
   </ItemGroup>
   <ItemGroup>
     <ClInclude Include="FreeRTOSConfig.h">
       <Filter>FreeRTOS\Configuration Files</Filter>
     </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcUser.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcBase.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcHooks.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcKernel.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcTypes.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcConfig.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Configuration Files</Filter>
-    </ClInclude>
-    <ClInclude Include="..\..\FreeRTOS-Plus-Trace\Include\trcPort.h">
-      <Filter>FreeRTOS+\FreeRTOS+Trace\Configuration Files</Filter>
-    </ClInclude>
-    <ClInclude Include="Trace_Recorder_Configuration\trcPort.h">
+    <ClInclude Include="Trace_Recorder_Configuration\trcConfig.h">
       <Filter>Demo App Source\Trace Recorder Configuration</Filter>
     </ClInclude>
-    <ClInclude Include="Trace_Recorder_Configuration\trcConfig.h">
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcUser.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcBase.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcHooks.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcKernel.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcTypes.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="..\..\Source\FreeRTOS-Plus-Trace\Include\trcKernelPort.h">
+      <Filter>FreeRTOS+\FreeRTOS+Trace\Include</Filter>
+    </ClInclude>
+    <ClInclude Include="Trace_Recorder_Configuration\trcHardwarePort.h">
       <Filter>Demo App Source\Trace Recorder Configuration</Filter>
     </ClInclude>
   </ItemGroup>

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator/main.c

@@ -1,67 +1,65 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
 /*
@@ -76,18 +74,21 @@
  * meaningful units.  See the documentation page for the Windows simulator for
  * an explanation of the slow timing:
  * http://www.freertos.org/FreeRTOS-Windows-Simulator-Emulator-for-Visual-Studio-and-Eclipse-MingW.html
+ *
+ * Documentation for this demo can be found on:
+ * http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_Trace/Free_RTOS_Plus_Trace_CLI_Example.shtml
  ******************************************************************************
  *
- * This is a simple FreeRTOS Windows simulator project that makes it easy to 
+ * This is a simple FreeRTOS Windows simulator project that makes it easy to
  * evaluate FreeRTOS+CLI and FreeRTOS+Trace on a standard desktop PC, without
  * any external hardware or interfaces being required.
  *
- * To keep everything as simple as possible, the command line interface is 
+ * To keep everything as simple as possible, the command line interface is
  * accessed through a UDP socket on the default Windows loopback IP address of
  * 127.0.0.1.  Full instructions are provided on the documentation page
  * referenced above.
  *
- * Commands are provided to both start and stop a FreeRTOS+Trace recording.  
+ * Commands are provided to both start and stop a FreeRTOS+Trace recording.
  * Stopping a recording will result in the recorded data being saved to the
  * hard disk, ready for viewing in the FreeRTOS+Trace graphical user interface.
  * Again, full instructions are provided on the documentation page referenced
@@ -100,14 +101,9 @@
  * priority of the queue receive task is above that of the queue send task, so
  * it pre-empts the queue send task as soon as it leaves the Blocked state.  It
  * then consumes the message from the queue and prints "message received" to
- * the screen before returning to block on the queue once again.  This 
+ * the screen before returning to block on the queue once again.  This
  * sequencing is clearly visible in the recorded FreeRTOS+Trace data.
  *
- * Finally, a trace monitoring task is also created that prints out a message
- * when it determines that the status of the trace has changed since it last
- * executed.  It prints out a message when the trace has started, when the
- * trace has stopped, and periodically when the trace is executing.
- *
  */
 
 /* Standard includes. */
@@ -127,7 +123,7 @@
 #define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
 #define mainUDP_CLI_TASK_PRIORITY			( tskIDLE_PRIORITY )
 
-/* The rate at which data is sent to the queue.  The (simulated) 50ms value is 
+/* The rate at which data is sent to the queue.  The (simulated) 50ms value is
 converted to ticks using the portTICK_RATE_MS constant. */
 #define mainQUEUE_SEND_FREQUENCY_MS			( 50 / portTICK_RATE_MS )
 
@@ -140,7 +136,7 @@ the queue empty. */
 
 /*
  * The queue send and receive tasks as described in the comments at the top of
- * this file. 
+ * this file.
  */
 static void prvQueueReceiveTask( void *pvParameters );
 static void prvQueueSendTask( void *pvParameters );
@@ -159,16 +155,27 @@ extern void vRegisterCLICommands( void );
 /* The queue used by both tasks. */
 static xQueueHandle xQueue = NULL;
 
+/* The user trace event posted to the trace recording on each tick interrupt.
+Note tick events will not appear in the trace recording with regular period
+because this project runs in a Windows simulator, and does not therefore
+exhibit deterministic behaviour. */
+traceLabel xTickTraceUserEvent;
+
 /*-----------------------------------------------------------*/
 
 int main( void )
 {
 const uint32_t ulLongTime_ms = 250UL;
 
+	/* Initialise the trace recorder and create the label used to post user
+	events to the trace recording on each tick interrupt. */
+	vTraceInitTraceData();
+	xTickTraceUserEvent = xTraceOpenLabel( "tick" );
+
 	/* Create the queue used to pass messages from the queue send task to the
 	queue receive task. */
 	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
-	
+
 	/* Give the queue a name for the FreeRTOS+Trace log. */
 	vTraceSetQueueName( xQueue, "DemoQ" );
 
@@ -187,10 +194,6 @@ const uint32_t ulLongTime_ms = 250UL;
 	is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */
 	xTaskCreate( vUDPCommandInterpreterTask, ( signed char * ) "CLI", configMINIMAL_STACK_SIZE, NULL, mainUDP_CLI_TASK_PRIORITY, NULL );
 
-	/* Create the task that monitors the trace recording status, printing
-	periodic information to the display. */
-	vTraceStartStatusMonitor();
-
 	/* Register commands with the FreeRTOS+CLI command interpreter. */
 	vRegisterCLICommands();
 
@@ -201,7 +204,7 @@ const uint32_t ulLongTime_ms = 250UL;
 	line will never be reached.  If the following line does execute, then
 	there was insufficient FreeRTOS heap memory available for the idle and/or
 	timer tasks	to be created.  See the memory management section on the
-	FreeRTOS web site for more details (this is standard text that is not not 
+	FreeRTOS web site for more details (this is standard text that is not not
 	really applicable to the Win32 simulator port). */
 	for( ;; )
 	{
@@ -228,8 +231,8 @@ const unsigned long ulValueToSend = 100UL;
 		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
 
 		/* Send to the queue - causing the queue receive task to unblock and
-		write a message to the display.  0 is used as the block time so the 
-		sending operation will not block - it shouldn't need to block as the 
+		write a message to the display.  0 is used as the block time so the
+		sending operation will not block - it shouldn't need to block as the
 		queue should always	be empty at this point in the code, and it is an
 		error if it is not. */
 		xQueueSend( xQueue, &ulValueToSend, 0U );
@@ -252,7 +255,7 @@ unsigned long ulReceivedValue;
 		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
 
 		/*  To get here something must have been received from the queue, but
-		is it the expected value?  If it is, write the message to the 
+		is it the expected value?  If it is, write the message to the
 		display before looping back to block on the queue again. */
 		if( ulReceivedValue == 100UL )
 		{
@@ -268,7 +271,7 @@ void vApplicationIdleHook( void )
 const unsigned long ulMSToSleep = 5;
 
 	/* This function is called on each cycle of the idle task if
-	configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h.  Sleep to reduce CPU 
+	configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h.  Sleep to reduce CPU
 	load. */
 	Sleep( ulMSToSleep );
 }
@@ -286,3 +289,12 @@ const unsigned long ulLongSleep = 1000UL;
 }
 /*-----------------------------------------------------------*/
 
+void vApplicationTickHook( void )
+{
+	/* Write a user event to the trace log.  
+	Note tick events will not appear in the trace recording with regular period
+	because this project runs in a Windows simulator, and does not therefore
+	exhibit deterministic behaviour. */
+	vTraceUserEvent( xTickTraceUserEvent );					
+}
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/FreeRTOSConfig.h

@@ -1,67 +1,65 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
 #ifndef FREERTOS_CONFIG_H

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/READ_ME.url

@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/CyaSSL/FreeRTOS_CyaSSL_Example.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPClientTask.c

@@ -1,67 +1,65 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
 #pragma comment( lib, "ws2_32.lib" )

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/SecureTCPServerTask.c

@@ -1,67 +1,65 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
-     *    FreeRTOS tutorial books are available in pdf and paperback.        *
-     *    Complete, revised, and edited pdf reference manuals are also       *
-     *    available.                                                         *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
      *                                                                       *
-     *    Purchasing FreeRTOS documentation will not only help you, by       *
-     *    ensuring you get running as quickly as possible and with an        *
-     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
-     *    the FreeRTOS project to continue with its mission of providing     *
-     *    professional grade, cross platform, de facto standard solutions    *
-     *    for microcontrollers - completely free of charge!                  *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
      *                                                                       *
-     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
-     *                                                                       *
-     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *    Thank you!                                                         *
      *                                                                       *
     ***************************************************************************
 
-
     This file is part of the FreeRTOS distribution.
 
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
-    distribute a combined work that includes FreeRTOS without being obliged to
-    provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
 */
 
 #pragma comment( lib, "ws2_32.lib" )

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj

@@ -54,7 +54,7 @@
     </Midl>
     <ClCompile>
       <Optimization>Disabled</Optimization>
-      <AdditionalIncludeDirectories>..\..\CyaSSL;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
+      <AdditionalIncludeDirectories>..\..\Source\CyaSSL;..\..\..\FreeRTOS\Source\include;..\..\..\FreeRTOS\Source\portable\MSVC-MingW;.;%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
       <PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;_WIN32_WINNT=0x0500;WINVER=0x400;_CRT_SECURE_NO_WARNINGS;SIZEOF_LONG_LONG=8;%(PreprocessorDefinitions)</PreprocessorDefinitions>
       <MinimalRebuild>true</MinimalRebuild>
       <BasicRuntimeChecks>EnableFastChecks</BasicRuntimeChecks>
@@ -128,32 +128,32 @@
     </Bscmake>
   </ItemDefinitionGroup>
   <ItemGroup>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\aes.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\arc4.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\asn.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\coding.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\des3.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\dh.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\dsa.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\hc128.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\hmac.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\integer.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\logging.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\md4.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\md5.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\memory.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\misc.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\pwdbased.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\rabbit.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\random.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\rsa.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\sha.c" />
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\sha256.c" />
-    <ClCompile Include="..\..\CyaSSL\src\internal.c" />
-    <ClCompile Include="..\..\CyaSSL\src\io.c" />
-    <ClCompile Include="..\..\CyaSSL\src\keys.c" />
-    <ClCompile Include="..\..\CyaSSL\src\ssl.c" />
-    <ClCompile Include="..\..\CyaSSL\src\tls.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\aes.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\arc4.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\asn.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\coding.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\des3.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dh.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dsa.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hc128.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hmac.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\integer.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\logging.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md4.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md5.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\memory.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\misc.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\pwdbased.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rabbit.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\random.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rsa.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha256.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\src\internal.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\src\io.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\src\keys.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\src\ssl.c" />
+    <ClCompile Include="..\..\Source\CyaSSL\src\tls.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\list.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MemMang\heap_3.c" />
     <ClCompile Include="..\..\..\FreeRTOS\Source\portable\MSVC-MingW\port.c" />

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/WIN32.vcxproj.filters

@@ -51,82 +51,82 @@
     <ClCompile Include="..\..\..\FreeRTOS\Source\tasks.c">
       <Filter>FreeRTOS\Source</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\src\internal.c">
+    <ClCompile Include="..\..\Source\CyaSSL\src\internal.c">
       <Filter>FreeRTOS+\CyaSSL</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\src\io.c">
+    <ClCompile Include="..\..\Source\CyaSSL\src\io.c">
       <Filter>FreeRTOS+\CyaSSL</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\src\keys.c">
+    <ClCompile Include="..\..\Source\CyaSSL\src\keys.c">
       <Filter>FreeRTOS+\CyaSSL</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\src\ssl.c">
+    <ClCompile Include="..\..\Source\CyaSSL\src\ssl.c">
       <Filter>FreeRTOS+\CyaSSL</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\src\tls.c">
+    <ClCompile Include="..\..\Source\CyaSSL\src\tls.c">
       <Filter>FreeRTOS+\CyaSSL</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\aes.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\aes.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\arc4.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\arc4.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\asn.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\asn.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\coding.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\coding.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\des3.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\des3.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\dh.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dh.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\dsa.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\dsa.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\hc128.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hc128.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\hmac.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\hmac.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\integer.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\integer.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\logging.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\logging.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\md4.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md4.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\md5.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\md5.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\memory.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\memory.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\misc.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\misc.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\pwdbased.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\pwdbased.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\rabbit.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rabbit.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\random.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\random.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\rsa.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\rsa.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\sha256.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha256.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\CyaSSL\ctaocrypt\src\sha.c">
+    <ClCompile Include="..\..\Source\CyaSSL\ctaocrypt\src\sha.c">
       <Filter>FreeRTOS+\CyaSSL\ctaocrypt</Filter>
     </ClCompile>
     <ClCompile Include="SecureTCPServerTask.c">

FreeRTOS-Plus/Demo/FreeRTOS_Plus_CyaSSL_Windows_Simulator/main.c

@@ -0,0 +1,140 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include "task.h"
+
+/* This application is using the FreeRTOS Windows simulator, which uses the
+FreeRTOS scheduler to schedule FreeRTOS task within the Windows environment.
+The Windows environment must not be allowed to block any Windows threads that
+are running FreeRTOS tasks, unless the FreeRTOS task is running at the FreeRTOS
+idle priority.  For simplicity, this demo uses the Windows TCP/IP stack, the
+API for which can cause Windows threads to block.  Therefore, any FreeRTOS task
+that makes calls to the Windows TCP/IP stack must be assigned the idle priority.
+Note this is only a restriction of the simulated Windows environment - real
+FreeRTOS ports do not have this restriction. */
+#define mainSECURE_SERVER_TASK_PRIORITY		( tskIDLE_PRIORITY )
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the server side.
+ */
+extern void vSecureTCPServerTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+const uint32_t ulLongTime_ms = 250UL;
+
+	/* Create the TCP server task.  This will itself create the client task
+	once it has completed the CyaSSL initialisation. */
+	xTaskCreate( vSecureTCPServerTask, ( signed char * ) "Server", configMINIMAL_STACK_SIZE, NULL, mainSECURE_SERVER_TASK_PRIORITY, NULL );
+
+	/* Start the task running. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the idle and/or
+	timer tasks	to be created.  See the memory management section on the
+	FreeRTOS web site for more details (this is standard text that is not not 
+	really applicable to the Win32 simulator port). */
+	for( ;; )
+	{
+		Sleep( ulLongTime_ms );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+const unsigned long ulMSToSleep = 5;
+
+	/* This function is called on each cycle of the idle task if
+	configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h.  Sleep to reduce CPU 
+	load. */
+	Sleep( ulMSToSleep );
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( void )
+{
+const unsigned long ulLongSleep = 1000UL;
+
+	taskDISABLE_INTERRUPTS();
+	for( ;; )
+	{
+		Sleep( ulLongSleep );
+	}
+}
+/*-----------------------------------------------------------*/
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/FreeRTOSConfig.h

@@ -0,0 +1,177 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 
+    Integrity Systems, who sell the code with commercial support, 
+    indemnification and middleware, under the OpenRTOS brand.
+    
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 
+    engineered and independently SIL3 certified version for use in safety and 
+    mission critical applications that require provable dependability.
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *
+ * The bottom of this file contains some constants specific to running the UDP
+ * stack in this demo.  Constants specific to FreeRTOS+UDP itself (rather than
+ * the demo) are contained in FreeRTOSIPConfig.h.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION			1
+#define configMAX_PRIORITIES			( ( unsigned portBASE_TYPE ) 7 )
+#define configTICK_RATE_HZ				( 1000 ) /* In this non-real time simulated environment the tick frequency has to be at least a multiple of the Win32 tick frequency, and therefore very slow. */
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 60 ) /* In this simulated case, the stack only has to hold one small structure as the real stack is part of the Win32 thread. */
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 32U * 1024U ) )
+#define configMAX_TASK_NAME_LEN			( 7 )
+#define configUSE_TRACE_FACILITY		1
+#define configUSE_16_BIT_TICKS			0
+#define configIDLE_SHOULD_YIELD			1
+#define configUSE_CO_ROUTINES 			0
+#define configUSE_MUTEXES				1
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configQUEUE_REGISTRY_SIZE		0
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configUSE_ALTERNATIVE_API		0
+
+/* Hook function related definitions. */
+#define configUSE_TICK_HOOK				0
+#define configUSE_IDLE_HOOK				1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configCHECK_FOR_STACK_OVERFLOW	0 /* Not applicable to the Win32 port. */
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		5
+#define configTIMER_TASK_STACK_DEPTH	( configMINIMAL_STACK_SIZE * 2 )
+
+/* Run time stats gathering definitions. */
+unsigned long ulGetRunTimeCounterValue( void );
+void vConfigureTimerForRunTimeStats( void );
+#define configGENERATE_RUN_TIME_STATS	1
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vConfigureTimerForRunTimeStats()
+#define portGET_RUN_TIME_COUNTER_VALUE() ulGetRunTimeCounterValue()
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		0
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_uxTaskGetStackHighWaterMark	1
+#define INCLUDE_xTaskGetSchedulerState		1
+#define INCLUDE_xTimerGetTimerTaskHandle	0
+#define INCLUDE_xTaskGetIdleTaskHandle		0
+#define INCLUDE_xQueueGetMutexHolder		1
+
+/* This demo makes use of one or more example stats formatting functions.  These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form.  See the notes in the implementation of vTaskList() within 
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS	1
+
+/* Assert call defined for debug builds. */
+#ifdef _DEBUG
+	extern void vAssertCalled( const char *pcFile, unsigned long ulLine );
+	#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ )
+#endif /* _DEBUG */
+
+
+
+/* Application specific definitions follow. **********************************/
+
+/* The UDP port to use for incoming command inputs.  The outgoing port is
+set to ( configUDP_CLI_PORT_NUMBER + 1 ). */
+#define configUDP_CLI_PORT_NUMBER	5001
+
+/* The size of the global output buffer that is available for use when there
+are multiple command interpreters running at once (for example, one on a UART
+and one on TCP/IP).  This is done to prevent an output buffer being defined by
+each implementation - which would waste RAM.  In this case, there is only one
+command interpreter running, and it has its own local output buffer, so the
+global buffer is just set to be one byte long as it is not used and should not
+take up unnecessary RAM. */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 1
+
+#endif /* FREERTOS_CONFIG_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_fat_sl.h

@@ -0,0 +1,67 @@
+/*
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS.  It is not, in itself, part of
+ * the FreeRTOS kernel.  FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS.  FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product.  Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful.  You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'.  FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_FAT_SL_H
+#define _CONFIG_FAT_SL_H
+
+#include "../version/ver_fat_sl.h"
+#if VER_FAT_SL_MAJOR != 3 || VER_FAT_SL_MINOR != 2
+ #error Incompatible FAT_SL version number!
+#endif
+
+#include "../api/api_mdriver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************************************************************
+**
+**  FAT SL user settings
+**
+**************************************************************************/
+#define F_SECTOR_SIZE           512u  /* Disk sector size. */
+#define F_FS_THREAD_AWARE       1     /* Set to one if the file system will be access from more than one task. */
+#define F_MAXPATH               64    /* Maximum length a file name (including its full path) can be. */
+#define F_MAX_LOCK_WAIT_TICKS   20    /* The maximum number of RTOS ticks to wait when attempting to obtain a lock on the file system when F_FS_THREAD_AWARE is set to 1. */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CONFIG_FAT_SL_H */
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/ConfigurationFiles/config_mdriver_ram.h

@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS+FAT FS V1.0.0 (C) 2013 HCC Embedded
+ *
+ * FreeRTOS+FAT SL is an complementary component provided to Real Time Engineers
+ * Ltd. by HCC Embedded for use with FreeRTOS.  It is not, in itself, part of
+ * the FreeRTOS kernel.  FreeRTOS+FAT SL is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS.  FreeRTOS+FAT SL uses a dual
+ * license model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+FAT SL is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+FAT SL into
+ * proprietary software for redistribution in any form must first obtain a
+ * commercial license - and in-so-doing support the maintenance, support and
+ * further development of the FreeRTOS+FAT SL product.  Commercial licenses can
+ * be obtained from http://shop.freertos.org and do not require any source files
+ * to be changed.
+ *
+ * FreeRTOS+FAT SL is distributed in the hope that it will be useful.  You
+ * cannot use FreeRTOS+FAT SL unless you agree that you use the software 'as
+ * is'.  FreeRTOS+FAT SL is provided WITHOUT ANY WARRANTY; without even the
+ * implied warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A
+ * PARTICULAR PURPOSE. Real Time Engineers Ltd. and HCC Embedded disclaims all
+ * conditions and terms, be they implied, expressed, or statutory.
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+#ifndef _CONFIG_MDRIVER_RAM_H_
+#define _CONFIG_MDRIVER_RAM_H_
+
+#include "../version/ver_mdriver_ram.h"
+#if VER_MDRIVER_RAM_MAJOR != 1 || VER_MDRIVER_RAM_MINOR != 2
+ #error Incompatible MDRIVER_RAM version number!
+#endif
+
+#define MDRIVER_RAM_SECTOR_SIZE   512       /* Sector size */
+
+#define MDRIVER_RAM_VOLUME0_SIZE  (128 * 1024) /* defintion for size of ramdrive0 */
+
+#define MDRIVER_MEM_LONG_ACCESS   1         /* set this value to 1 if 32bit access available */
+
+#endif /* ifndef _CONFIG_MDRIVER_RAM_H_ */
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-Releated-CLI-commands.c

@@ -0,0 +1,618 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems, who sell the code with commercial support,
+    indemnification and middleware, under the OpenRTOS brand.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+#include "test.h"
+
+#ifdef _WINDOWS_
+	#define snprintf _snprintf
+#endif
+
+#define cliNEW_LINE		"\r\n"
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/*
+ * Print out information on a single file.
+ */
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct );
+
+/*
+ * Copies an existing file into a newly created file.
+ */
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
+							int32_t lSourceFileLength,
+							int8_t *pcDestinationFile,
+							int8_t *pxWriteBuffer,
+							size_t xWriteBufferLen );
+
+/*
+ * Implements the DIR command.
+ */
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the CD command.
+ */
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the DEL command.
+ */
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the TYPE command.
+ */
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the COPY command.
+ */
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the TEST command.
+ */
+static portBASE_TYPE prvTESTFSCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/* Structure that defines the DIR command line command, which lists all the
+files in the current directory. */
+static const CLI_Command_Definition_t xDIR =
+{
+	( const int8_t * const ) "dir", /* The command string to type. */
+	( const int8_t * const ) "\r\ndir:\r\n Lists the files in the current directory\r\n",
+	prvDIRCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the CD command line command, which changes the
+working directory. */
+static const CLI_Command_Definition_t xCD =
+{
+	( const int8_t * const ) "cd", /* The command string to type. */
+	( const int8_t * const ) "\r\ncd <dir name>:\r\n Changes the working directory\r\n",
+	prvCDCommand, /* The function to run. */
+	1 /* One parameter is expected. */
+};
+
+/* Structure that defines the TYPE command line command, which prints the
+contents of a file to the console. */
+static const CLI_Command_Definition_t xTYPE =
+{
+	( const int8_t * const ) "type", /* The command string to type. */
+	( const int8_t * const ) "\r\ntype <filename>:\r\n Prints file contents to the terminal\r\n",
+	prvTYPECommand, /* The function to run. */
+	1 /* One parameter is expected. */
+};
+
+/* Structure that defines the DEL command line command, which deletes a file. */
+static const CLI_Command_Definition_t xDEL =
+{
+	( const int8_t * const ) "del", /* The command string to type. */
+	( const int8_t * const ) "\r\ndel <filename>:\r\n deletes a file or directory\r\n",
+	prvDELCommand, /* The function to run. */
+	1 /* One parameter is expected. */
+};
+
+/* Structure that defines the COPY command line command, which deletes a file. */
+static const CLI_Command_Definition_t xCOPY =
+{
+	( const int8_t * const ) "copy", /* The command string to type. */
+	( const int8_t * const ) "\r\ncopy <source file> <dest file>:\r\n Copies <source file> to <dest file>\r\n",
+	prvCOPYCommand, /* The function to run. */
+	2 /* Two parameters are expected. */
+};
+
+/* Structure that defines the TEST command line command, which executes some
+file system driver tests. */
+static const CLI_Command_Definition_t xTEST_FS =
+{
+	( const int8_t * const ) "test-fs", /* The command string to type. */
+	( const int8_t * const ) "\r\ntest-fs:\r\n Executes file system tests.  ALL FILES WILL BE DELETED!!!\r\n",
+	prvTESTFSCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/*-----------------------------------------------------------*/
+
+void vRegisterFileSystemCLICommands( void )
+{
+	/* Register all the command line commands defined immediately above. */
+	FreeRTOS_CLIRegisterCommand( &xDIR );
+	FreeRTOS_CLIRegisterCommand( &xCD );
+	FreeRTOS_CLIRegisterCommand( &xTYPE );
+	FreeRTOS_CLIRegisterCommand( &xDEL );
+	FreeRTOS_CLIRegisterCommand( &xCOPY );
+	FreeRTOS_CLIRegisterCommand( &xTEST_FS );
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTYPECommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn = pdTRUE;
+static F_FILE *pxFile = NULL;
+int iChar;
+size_t xByte;
+size_t xColumns = 50U;
+
+	/* Ensure there is always a null terminator after each character written. */
+	memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+
+	/* Ensure the buffer leaves space for the \r\n. */
+	configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+	xWriteBufferLen -= strlen( cliNEW_LINE );
+
+	if( xWriteBufferLen < xColumns )
+	{
+		/* Ensure the loop that uses xColumns as an end condition does not
+		write off the end of the buffer. */
+		xColumns = xWriteBufferLen;
+	}
+
+	if( pxFile == NULL )
+	{
+		/* The file has not been opened yet.  Find the file name. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Attempt to open the requested file. */
+		pxFile = f_open( ( const char * ) pcParameter, "r" );
+	}
+
+	if( pxFile != NULL )
+	{
+		/* Read the next chunk of data from the file. */
+		for( xByte = 0; xByte < xColumns; xByte++ )
+		{
+			iChar = f_getc( pxFile );
+
+			if( iChar == -1 )
+			{
+				/* No more characters to return. */
+				f_close( pxFile );
+				pxFile = NULL;
+				break;
+			}
+			else
+			{
+				pcWriteBuffer[ xByte ] = ( int8_t ) iChar;
+			}
+		}
+	}
+
+	if( pxFile == NULL )
+	{
+		/* Either the file was not opened, or all the data from the file has
+		been returned and the file is now closed. */
+		xReturn = pdFALSE;
+	}
+
+	strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCDCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+size_t xStringLength;
+
+	/* Obtain the parameter string. */
+	pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+								(
+									pcCommandString,		/* The command string itself. */
+									1,						/* Return the first parameter. */
+									&xParameterStringLength	/* Store the parameter string length. */
+								);
+
+	/* Sanity check something was returned. */
+	configASSERT( pcParameter );
+
+	/* Attempt to move to the requested directory. */
+	ucReturned = f_chdir( ( char * ) pcParameter );
+
+	if( ucReturned == F_NO_ERROR )
+	{
+		sprintf( ( char * ) pcWriteBuffer, "In: " );
+		xStringLength = strlen( ( const char * ) pcWriteBuffer );
+		f_getcwd( ( char * ) &( pcWriteBuffer[ xStringLength ] ), ( unsigned char ) ( xWriteBufferLen - xStringLength ) );
+	}
+	else
+	{
+		sprintf( ( char * ) pcWriteBuffer, "Error" );
+	}
+
+	strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDIRCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+static F_FIND *pxFindStruct = NULL;
+unsigned char ucReturned;
+portBASE_TYPE xReturn = pdFALSE;
+
+	/* This assumes pcWriteBuffer is long enough. */
+	( void ) pcCommandString;
+
+	/* Ensure the buffer leaves space for the \r\n. */
+	configASSERT( xWriteBufferLen > ( strlen( cliNEW_LINE ) * 2 ) );
+	xWriteBufferLen -= strlen( cliNEW_LINE );
+
+	if( pxFindStruct == NULL )
+	{
+		/* This is the first time this function has been executed since the Dir
+		command was run.  Create the find structure. */
+		pxFindStruct = ( F_FIND * ) pvPortMalloc( sizeof( F_FIND ) );
+
+		if( pxFindStruct != NULL )
+		{
+			ucReturned = f_findfirst( "*.*", pxFindStruct );
+
+			if( ucReturned == F_NO_ERROR )
+			{
+				prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+				xReturn = pdPASS;
+			}
+			else
+			{
+				snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Error: f_findfirst() failed." );
+			}
+		}
+		else
+		{
+			snprintf( ( char * ) pcWriteBuffer, xWriteBufferLen, "Failed to allocate RAM (using heap_4.c will prevent fragmentation)." );
+		}
+	}
+	else
+	{
+		/* The find struct has already been created.  Find the next file in
+		the directory. */
+		ucReturned = f_findnext( pxFindStruct );
+
+		if( ucReturned == F_NO_ERROR )
+		{
+			prvCreateFileInfoString( pcWriteBuffer, pxFindStruct );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* There are no more files.  Free the find structure. */
+			vPortFree( pxFindStruct );
+			pxFindStruct = NULL;
+
+			/* No string to return. */
+			pcWriteBuffer[ 0 ] = 0x00;
+		}
+	}
+
+	strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvDELCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength;
+unsigned char ucReturned;
+
+	/* This function assumes xWriteBufferLen is large enough! */
+	( void ) xWriteBufferLen;
+
+	/* Obtain the parameter string. */
+	pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+								(
+									pcCommandString,		/* The command string itself. */
+									1,						/* Return the first parameter. */
+									&xParameterStringLength	/* Store the parameter string length. */
+								);
+
+	/* Sanity check something was returned. */
+	configASSERT( pcParameter );
+
+	/* Attempt to delete the file. */
+	ucReturned = f_delete( ( const char * ) pcParameter );
+
+	if( ucReturned == F_NO_ERROR )
+	{
+		sprintf( ( char * ) pcWriteBuffer, "%s was deleted", pcParameter );
+	}
+	else
+	{
+		sprintf( ( char * ) pcWriteBuffer, "Error" );
+	}
+
+	strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTESTFSCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+unsigned portBASE_TYPE uxOriginalPriority;
+
+	/* Avoid compiler warnings. */
+	( void ) xWriteBufferLen;
+	( void ) pcCommandString;
+
+	/* Limitations in the interaction with the Windows TCP/IP stack require
+	the command console to run at the idle priority.  Raise the priority for
+	the duration of the tests to ensure there are not multiple switches to the
+	idle task as in the simulated environment the idle task hook function may
+	include a (relatively) long delay. */
+	uxOriginalPriority = uxTaskPriorityGet( NULL );
+	vTaskPrioritySet( NULL, configMAX_PRIORITIES - 1 );
+
+	f_dotest( 0 );
+
+	/* Reset back to the original priority. */
+	vTaskPrioritySet( NULL, uxOriginalPriority );
+
+	sprintf( ( char * ) pcWriteBuffer, "%s", "Test results were sent to Windows console" );
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvCOPYCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcSourceFile, *pcDestinationFile;
+portBASE_TYPE xParameterStringLength;
+long lSourceLength, lDestinationLength = 0;
+
+	/* Obtain the name of the destination file. */
+	pcDestinationFile = ( int8_t * ) FreeRTOS_CLIGetParameter
+								(
+									pcCommandString,		/* The command string itself. */
+									2,						/* Return the second parameter. */
+									&xParameterStringLength	/* Store the parameter string length. */
+								);
+
+	/* Sanity check something was returned. */
+	configASSERT( pcDestinationFile );
+
+	/* Obtain the name of the source file. */
+	pcSourceFile = ( int8_t * ) FreeRTOS_CLIGetParameter
+								(
+									pcCommandString,		/* The command string itself. */
+									1,						/* Return the first parameter. */
+									&xParameterStringLength	/* Store the parameter string length. */
+								);
+
+	/* Sanity check something was returned. */
+	configASSERT( pcSourceFile );
+
+	/* Terminate the string. */
+	pcSourceFile[ xParameterStringLength ] = 0x00;
+
+	/* See if the source file exists, obtain its length if it does. */
+	lSourceLength = f_filelength( ( const char * ) pcSourceFile );
+
+	if( lSourceLength == 0 )
+	{
+		sprintf( ( char * ) pcWriteBuffer, "Source file does not exist" );
+	}
+	else
+	{
+		/* See if the destination file exists. */
+		lDestinationLength = f_filelength( ( const char * ) pcDestinationFile );
+
+		if( lDestinationLength != 0 )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Error: Destination file already exists" );
+		}
+	}
+
+	/* Continue only if the source file exists and the destination file does
+	not exist. */
+	if( ( lSourceLength != 0 ) && ( lDestinationLength == 0 ) )
+	{
+		if( prvPerformCopy( pcSourceFile, lSourceLength, pcDestinationFile, pcWriteBuffer, xWriteBufferLen ) == pdPASS )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Copy made" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Error during copy" );
+		}
+	}
+
+	strcat( ( char * ) pcWriteBuffer, cliNEW_LINE );
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvPerformCopy( int8_t *pcSourceFile,
+							int32_t lSourceFileLength,
+							int8_t *pcDestinationFile,
+							int8_t *pxWriteBuffer,
+							size_t xWriteBufferLen )
+{
+int32_t lBytesRead = 0, lBytesToRead, lBytesRemaining;
+F_FILE *pxFile;
+portBASE_TYPE xReturn = pdPASS;
+
+	/* NOTE:  Error handling has been omitted for clarity. */
+
+	while( lBytesRead < lSourceFileLength )
+	{
+		/* How many bytes are left? */
+		lBytesRemaining = lSourceFileLength - lBytesRead;
+
+		/* How many bytes should be read this time around the loop.  Can't
+		read more bytes than will fit into the buffer. */
+		if( lBytesRemaining > ( long ) xWriteBufferLen )
+		{
+			lBytesToRead = ( long ) xWriteBufferLen;
+		}
+		else
+		{
+			lBytesToRead = lBytesRemaining;
+		}
+
+		/* Open the source file, seek past the data that has already been
+		read from the file, read the next block of data, then close the
+		file again so the destination file can be opened. */
+		pxFile = f_open( ( const char * ) pcSourceFile, "r" );
+		if( pxFile != NULL )
+		{
+			f_seek( pxFile, lBytesRead, F_SEEK_SET );
+			f_read( pxWriteBuffer, lBytesToRead, 1, pxFile );
+			f_close( pxFile );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			break;
+		}
+
+		/* Open the destination file and write the block of data to the end of
+		the file. */
+		pxFile = f_open( ( const char * ) pcDestinationFile, "a" );
+		if( pxFile != NULL )
+		{
+			f_write( pxWriteBuffer, lBytesToRead, 1, pxFile );
+			f_close( pxFile );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			break;
+		}
+
+		lBytesRead += lBytesToRead;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateFileInfoString( int8_t *pcBuffer, F_FIND *pxFindStruct )
+{
+const char *pcWritableFile = "writable file", *pcReadOnlyFile = "read only file", *pcDirectory = "directory";
+const char * pcAttrib;
+
+	/* Point pcAttrib to a string that describes the file. */
+	if( ( pxFindStruct->attr & F_ATTR_DIR ) != 0 )
+	{
+		pcAttrib = pcDirectory;
+	}
+	else if( pxFindStruct->attr & F_ATTR_READONLY )
+	{
+		pcAttrib = pcReadOnlyFile;
+	}
+	else
+	{
+		pcAttrib = pcWritableFile;
+	}
+
+	/* Create a string that includes the file name, the file size and the
+	attributes string. */
+	sprintf( ( char * ) pcBuffer, "%s [%s] [size=%d]", pxFindStruct->filename, pcAttrib, pxFindStruct->filesize );
+}

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/File-system-demo.c

@@ -0,0 +1,381 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems, who sell the code with commercial support,
+    indemnification and middleware, under the OpenRTOS brand.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+*/
+
+/*******************************************************************************
+ * See the URL in the comments within main.c for the location of the online
+ * documentation.
+ ******************************************************************************/
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* File system includes. */
+#include "fat_sl.h"
+#include "api_mdriver_ram.h"
+
+/* 8.3 format, plus null terminator. */
+#define fsMAX_FILE_NAME_LEN				13
+
+/* The number of bytes read/written to the example files at a time. */
+#define fsRAM_BUFFER_SIZE 				200
+
+/* The number of bytes written to the file that uses f_putc() and f_getc(). */
+#define fsPUTC_FILE_SIZE				100
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+void vCreateAndVerifySampleFiles( void );
+
+/*
+ * Create a set of example files in the root directory of the volume using
+ * f_write().
+ */
+static void prvCreateDemoFilesUsing_f_write( void );
+
+/*
+ * Use f_read() to read back and verify the files that were created by
+ * prvCreateDemoFilesUsing_f_write().
+ */
+static void prvVerifyDemoFileUsing_f_read( void );
+
+/*
+ * Create an example file in a sub-directory using f_putc().
+ */
+static void prvCreateDemoFileUsing_f_putc( void );
+
+/*
+ * Use f_getc() to read back and verify the file that was created by
+ * prvCreateDemoFileUsing_f_putc().
+ */
+static void prvVerifyDemoFileUsing_f_getc( void );
+
+/*-----------------------------------------------------------*/
+
+/* A buffer used to both create content to write to disk, and read content back
+from a disk.  Note there is no mutual exclusion on this buffer. */
+static char cRAMBuffer[ fsRAM_BUFFER_SIZE ];
+
+/* Names of directories that are created. */
+static const char *pcRoot = "/", *pcDirectory1 = "SUB1", *pcDirectory2 = "SUB2", *pcFullPath = "/SUB1/SUB2";
+
+/*-----------------------------------------------------------*/
+
+void vCreateAndVerifySampleFiles( void )
+{
+unsigned char ucStatus;
+
+	/* First create the volume. */
+	ucStatus = f_initvolume( ram_initfunc );
+
+	/* It is expected that the volume is not formatted. */
+	if( ucStatus == F_ERR_NOTFORMATTED )
+	{
+		/* Format the created volume. */
+		ucStatus = f_format( F_FAT12_MEDIA );
+	}
+
+	if( ucStatus == F_NO_ERROR )
+	{
+		/* Create a set of files using f_write(). */
+		prvCreateDemoFilesUsing_f_write();
+
+		/* Read back and verify the files that were created using f_write(). */
+		prvVerifyDemoFileUsing_f_read();
+
+		/* Create sub directories two deep then create a file using putc. */
+		prvCreateDemoFileUsing_f_putc();
+
+		/* Read back and verify the file created by
+		prvCreateDemoFileUsing_f_putc(). */
+		prvVerifyDemoFileUsing_f_getc();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFilesUsing_f_write( void )
+{
+portBASE_TYPE xFileNumber, xWriteNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsWritten;
+F_FILE *pxFile;
+
+	/* Create xMaxFiles files.  Each created file will be
+	( xFileNumber * fsRAM_BUFFER_SIZE ) bytes in length, and filled
+	with a different repeating character. */
+	for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+	{
+		/* Generate a file name. */
+		sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+		/* Obtain the current working directory and print out the file name and
+		the	directory into which the file is being written. */
+		f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+		printf( "Creating file %s in %s\r\n", cFileName, cRAMBuffer );
+
+		/* Open the file, creating the file if it does not already exist. */
+		pxFile = f_open( cFileName, "w" );
+		configASSERT( pxFile );
+
+		/* Fill the RAM buffer with data that will be written to the file.  This
+		is just a repeating ascii character that indicates the file number. */
+		memset( cRAMBuffer, ( int ) ( '0' + xFileNumber ), fsRAM_BUFFER_SIZE );
+
+		/* Write the RAM buffer to the opened file a number of times.  The
+		number of times the RAM buffer is written to the file depends on the
+		file number, so the length of each created file will be different. */
+		for( xWriteNumber = 0; xWriteNumber < xFileNumber; xWriteNumber++ )
+		{
+			lItemsWritten = f_write( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+			configASSERT( lItemsWritten == 1 );
+		}
+
+		/* Close the file so another file can be created. */
+		f_close( pxFile );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_read( void )
+{
+portBASE_TYPE xFileNumber, xReadNumber;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+const portBASE_TYPE xMaxFiles = 5;
+long lItemsRead, lChar;
+F_FILE *pxFile;
+
+	/* Read back the files that were created by
+	prvCreateDemoFilesUsing_f_write(). */
+	for( xFileNumber = 1; xFileNumber <= xMaxFiles; xFileNumber++ )
+	{
+		/* Generate the file name. */
+		sprintf( cFileName, "root%03d.txt", xFileNumber );
+
+		/* Obtain the current working directory and print out the file name and
+		the	directory from which the file is being read. */
+		f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+		printf( "Reading file %s from %s\r\n", cFileName, cRAMBuffer );
+
+		/* Open the file for reading. */
+		pxFile = f_open( cFileName, "r" );
+		configASSERT( pxFile );
+
+		/* Read the file into the RAM buffer, checking the file contents are as
+		expected.  The size of the file depends on the file number. */
+		for( xReadNumber = 0; xReadNumber < xFileNumber; xReadNumber++ )
+		{
+			/* Start with the RAM buffer clear. */
+			memset( cRAMBuffer, 0x00, fsRAM_BUFFER_SIZE );
+
+			lItemsRead = f_read( cRAMBuffer, fsRAM_BUFFER_SIZE, 1, pxFile );
+			configASSERT( lItemsRead == 1 );
+
+			/* Check the RAM buffer is filled with the expected data.  Each
+			file contains a different repeating ascii character that indicates
+			the number of the file. */
+			for( lChar = 0; lChar < fsRAM_BUFFER_SIZE; lChar++ )
+			{
+				configASSERT( cRAMBuffer[ lChar ] == ( '0' + ( char ) xFileNumber ) );
+			}
+		}
+
+		/* Close the file. */
+		f_close( pxFile );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCreateDemoFileUsing_f_putc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "In directory %s\r\n", cRAMBuffer );
+
+	/* Create a sub directory. */
+	ucReturn = f_mkdir( pcDirectory1 );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Move into the created sub-directory. */
+	ucReturn = f_chdir( pcDirectory1 );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "In directory %s\r\n", cRAMBuffer );
+
+	/* Create a subdirectory in the new directory. */
+	ucReturn = f_mkdir( pcDirectory2 );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Move into the directory just created - now two directories down from
+	the root. */
+	ucReturn = f_chdir( pcDirectory2 );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "In directory %s\r\n", cRAMBuffer );
+	configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
+
+	/* Generate the file name. */
+	sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+	/* Print out the file name and the directory into which the file is being
+	written. */
+	printf( "Writing file %s in %s\r\n", cFileName, cRAMBuffer );
+
+	pxFile = f_open( cFileName, "w" );
+
+	/* Create a file 1 byte at a time.  The file is filled with incrementing
+	ascii characters starting from '0'. */
+	for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+	{
+		iReturned = f_putc( ( ( int ) '0' + iByte ), pxFile );
+		configASSERT( iReturned ==  ( ( int ) '0' + iByte ) );
+	}
+
+	/* Finished so close the file. */
+	f_close( pxFile );
+
+	/* Move back to the root directory. */
+	ucReturn = f_chdir( "../.." );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "Back in root directory %s\r\n", cRAMBuffer );
+	configASSERT( strcmp( ( const char * ) cRAMBuffer, pcRoot ) == 0 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvVerifyDemoFileUsing_f_getc( void )
+{
+unsigned char ucReturn;
+int iByte, iReturned;
+F_FILE *pxFile;
+char cFileName[ fsMAX_FILE_NAME_LEN ];
+
+	/* Move into the directory in which the file was created. */
+	ucReturn = f_chdir( pcFullPath );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "Back in directory %s\r\n", cRAMBuffer );
+	configASSERT( strcmp( ( const char * ) cRAMBuffer, pcFullPath ) == 0 );
+
+	/* Generate the file name. */
+	sprintf( cFileName, "%s.txt", pcDirectory2 );
+
+	/* Print out the file name and the directory from which the file is being
+	read. */
+	printf( "Reading file %s in %s\r\n", cFileName, cRAMBuffer );
+
+	/* This time the file is opened for reading. */
+	pxFile = f_open( cFileName, "r" );
+
+	/* Read the file 1 byte at a time. */
+	for( iByte = 0; iByte < fsPUTC_FILE_SIZE; iByte++ )
+	{
+		iReturned = f_getc( pxFile );
+		configASSERT( iReturned ==  ( ( int ) '0' + iByte ) );
+	}
+
+	/* Finished so close the file. */
+	f_close( pxFile );
+
+	/* Move back to the root directory. */
+	ucReturn = f_chdir( "../.." );
+	configASSERT( ucReturn == F_NO_ERROR );
+
+	/* Obtain and print out the working directory. */
+	f_getcwd( cRAMBuffer, fsRAM_BUFFER_SIZE );
+	printf( "Back in root directory %s\r\n", cRAMBuffer );
+}
+
+
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/FreeRTOS_Plus_FAT_SL_with_CLI.sln

@@ -0,0 +1,20 @@
+
+Microsoft Visual Studio Solution File, Format Version 11.00
+# Visual C++ Express 2010
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WIN32", "WIN32.vcxproj", "{C686325E-3261-42F7-AEB1-DDE5280E1CEB}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Release|Win32 = Release|Win32
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.ActiveCfg = Debug|Win32
+		{C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Debug|Win32.Build.0 = Debug|Win32
+		{C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.ActiveCfg = Release|Win32
+		{C686325E-3261-42F7-AEB1-DDE5280E1CEB}.Release|Win32.Build.0 = Release|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/READ_ME.url

@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=http://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Run-time-stats-utils.c

@@ -1,6 +1,8 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
@@ -27,41 +29,47 @@
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
     distribute a combined work that includes FreeRTOS without being obliged to
     provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 
+    Integrity Systems, who sell the code with commercial support, 
+    indemnification and middleware, under the OpenRTOS brand.
+    
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 
+    engineered and independently SIL3 certified version for use in safety and 
+    mission critical applications that require provable dependability.
 */
 
 /*
@@ -79,9 +87,6 @@
 /* FreeRTOS includes. */
 #include <FreeRTOS.h>
 
-/* FreeRTOS+Trace includes. */
-#include "trcUser.h"
-
 /* Variables used in the creation of the run time stats time base.  Run time 
 stats record how much time each task spends in the Running state. */
 static long long llInitialRunTimeCounterValue = 0LL, llTicksPerHundedthMillisecond = 0LL;

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/Sample-CLI-commands.c

@@ -0,0 +1,426 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions, 
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High 
+    Integrity Systems, who sell the code with commercial support, 
+    indemnification and middleware, under the OpenRTOS brand.
+    
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety 
+    engineered and independently SIL3 certified version for use in safety and 
+    mission critical applications that require provable dependability.
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+#ifndef  configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+	#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+#endif
+
+/* Structure that defines the "run-time-stats" command line command.   This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+	( const int8_t * const ) "run-time-stats", /* The command string to type. */
+	( const int8_t * const ) "\r\nrun-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n",
+	prvRunTimeStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command.  This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+	( const int8_t * const ) "task-stats", /* The command string to type. */
+	( const int8_t * const ) "\r\ntask-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n",
+	prvTaskStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command.  This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+	( const int8_t * const ) "echo-3-parameters",
+	( const int8_t * const ) "\r\necho-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n",
+	prvThreeParameterEchoCommand, /* The function to run. */
+	3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command.  This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+	( const int8_t * const ) "echo-parameters",
+	( const int8_t * const ) "\r\necho-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n",
+	prvParameterEchoCommand, /* The function to run. */
+	-1 /* The user can enter any number of commands. */
+};
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	/* Structure that defines the "trace" command line command.  This takes a single
+	parameter, which can be either "start" or "stop". */
+	static const CLI_Command_Definition_t xStartStopTrace =
+	{
+		( const int8_t * const ) "trace",
+		( const int8_t * const ) "\r\ntrace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n",
+		prvStartStopTraceCommand, /* The function to run. */
+		1 /* One parameter is expected.  Valid values are "start" and "stop". */
+	};
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterSampleCLICommands( void )
+{
+	/* Register all the command line commands defined immediately above. */
+	FreeRTOS_CLIRegisterCommand( &xTaskStats );
+	FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+	FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+	FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+
+	#if( configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1 )
+	{
+		FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t *const pcHeader = ( int8_t * ) "Task          State  Priority  Stack	#\r\n************************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t * const pcHeader = ( int8_t * ) "Task            Abs Time      % Time\r\n****************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Return the parameter string. */
+		memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+		sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+		strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+		strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+		/* If this is the last of the three parameters then there are no more
+		strings to return after this one. */
+		if( lParameterNumber == 3L )
+		{
+			/* If this is the last of the three parameters then there are no more
+			strings to return after this one. */
+			xReturn = pdFALSE;
+			lParameterNumber = 0L;
+		}
+		else
+		{
+			/* There are more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		if( pcParameter != NULL )
+		{
+			/* Return the parameter string. */
+			memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+			sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+			strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+			strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+			/* There might be more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+		else
+		{
+			/* No more parameters were found.  Make sure the write buffer does
+			not contain a valid string. */
+			pcWriteBuffer[ 0 ] = 0x00;
+
+			/* No more data to return. */
+			xReturn = pdFALSE;
+
+			/* Start over the next time this command is executed. */
+			lParameterNumber = 0;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	int8_t *pcParameter;
+	portBASE_TYPE lParameterStringLength;
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* There are only two valid parameter values. */
+		if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )
+		{
+			/* Start or restart the trace. */
+			vTraceStop();
+			vTraceClear();
+			vTraceStart();
+
+			sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
+		}
+		else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )
+		{
+			/* End the trace, if one is running. */
+			vTraceStop();
+			sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+		}
+
+		/* There is no more data to return after this single string, so return
+		pdFALSE. */
+		return pdFALSE;
+	}
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/UDPCommandServer.c

@@ -1,6 +1,8 @@
 /*
-    FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
 
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
 
     ***************************************************************************
      *                                                                       *
@@ -27,43 +29,50 @@
     FreeRTOS is free software; you can redistribute it and/or modify it under
     the terms of the GNU General Public License (version 2) as published by the
     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
-    >>>NOTE<<< The modification to the GPL is included to allow you to
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
     distribute a combined work that includes FreeRTOS without being obliged to
     provide the source code for proprietary components outside of the FreeRTOS
-    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
-    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-    more details. You should have received a copy of the GNU General Public
-    License and the FreeRTOS license exception along with FreeRTOS; if not it
-    can be viewed here: http://www.freertos.org/a00114.html and also obtained
-    by writing to Richard Barry, contact details for whom are available on the
-    FreeRTOS WEB site.
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
 
     1 tab == 4 spaces!
-    
+
     ***************************************************************************
      *                                                                       *
      *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?                                      *
+     *    not run, what could be wrong?"                                     *
      *                                                                       *
      *    http://www.FreeRTOS.org/FAQHelp.html                               *
      *                                                                       *
     ***************************************************************************
 
-    
-    http://www.FreeRTOS.org - Documentation, training, latest information, 
-    license and contact details.
-    
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool.
 
-    Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell 
-    the code with commercial support, indemnification, and middleware, under 
-    the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also
-    provide a safety engineered and independently SIL3 certified version under 
-    the SafeRTOS brand: http://www.SafeRTOS.com.
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems, who sell the code with commercial support,
+    indemnification and middleware, under the OpenRTOS brand.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
 */
 
+
 #pragma comment( lib, "ws2_32.lib" )
 
 /* Win32 includes. */
@@ -73,6 +82,10 @@
 #include "FreeRTOS.h"
 #include "task.h"
 
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+
 /* FreeRTOS+CLI includes. */
 #include "FreeRTOS_CLI.h"
 
@@ -85,6 +98,9 @@
 /* Dimensions the buffer passed to the recvfrom() call. */
 #define cmdSOCKET_INPUT_BUFFER_SIZE 60
 
+/* DEL acts as a backspace. */
+#define cmdASCII_DEL		( 0x7F )
+
 /*
  * Open and configure the UDP socket.
  */
@@ -92,10 +108,11 @@ static SOCKET prvOpenUDPSocket( void );
 
 /*-----------------------------------------------------------*/
 
-/* 
+/*
  * Task that provides the input and output for the FreeRTOS+CLI command
- * interpreter.  In this case a UDP port is used.  See the URL in the comments
- * within main.c for the location of the online documentation.
+ * interpreter.  In this case a WinSock UDP port is used for convenience as this
+ * demo runs in a simulated environment on a Windows PC.  See the URL in the
+ * comments within main.c for the location of the online documentation.
  */
 void vUDPCommandInterpreterTask( void *pvParameters )
 {
@@ -128,7 +145,7 @@ SOCKET xSocket;
 				iErrorCode = WSAGetLastError();
 			}
 			else
-			{				
+			{
 				/* Process each received byte in turn. */
 				lByte = 0;
 				while( lByte < lBytes )
@@ -141,25 +158,25 @@ SOCKET xSocket;
 					string. */
 					if( cInChar == '\n' )
 					{
-						/* Process the input string received prior to the 
+						/* Process the input string received prior to the
 						newline. */
 						do
 						{
 							/* Pass the string to FreeRTOS+CLI. */
 							xMoreDataToFollow = FreeRTOS_CLIProcessCommand( cInputString, cOutputString, cmdMAX_OUTPUT_SIZE );
-							
+
 							/* Send the output generated by the command's
 							implementation. */
 							sendto( xSocket, cOutputString,  strlen( cOutputString ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
 
 						} while( xMoreDataToFollow != pdFALSE ); /* Until the command does not generate any more output. */
 
-						/* All the strings generated by the command processing 
-						have been sent.  Clear the input string ready to receive 
+						/* All the strings generated by the command processing
+						have been sent.  Clear the input string ready to receive
 						the next command. */
 						cInputIndex = 0;
 						memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
-						
+
 						/* Transmit a spacer, just to make the command console
 						easier to read. */
 						sendto( xSocket, "\r\n",  strlen( "\r\n" ), 0, ( SOCKADDR * ) &xClient, xClientAddressLength );
@@ -168,12 +185,12 @@ SOCKET xSocket;
 					{
 						if( cInChar == '\r' )
 						{
-							/* Ignore the character.  Newlines are used to 
+							/* Ignore the character.  Newlines are used to
 							detect the end of the input string. */
 						}
-						else if( cInChar == '\b' )
+						else if( ( cInChar == '\b' ) || ( cInChar == cmdASCII_DEL ) )
 						{
-							/* Backspace was pressed.  Erase the last character 
+							/* Backspace was pressed.  Erase the last character
 							in the string - if any. */
 							if( cInputIndex > 0 )
 							{
@@ -195,7 +212,7 @@ SOCKET xSocket;
 					}
 				}
 			}
-		} 
+		}
 	}
 	else
 	{

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj

@@ -0,0 +1,183 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
+  <ItemGroup Label="ProjectConfigurations">
+    <ProjectConfiguration Include="Debug|Win32">
+      <Configuration>Debug</Configuration>
+      <Platform>Win32</Platform>
+    </ProjectConfiguration>
+    <ProjectConfiguration Include="Release|Win32">
+      <Configuration>Release</Configuration>
+      <Platform>Win32</Platform>
+    </ProjectConfiguration>
+  </ItemGroup>
+  <PropertyGroup Label="Globals">
+    <ProjectGuid>{C686325E-3261-42F7-AEB1-DDE5280E1CEB}</ProjectGuid>
+    <ProjectName>RTOSDemo</ProjectName>
+  </PropertyGroup>
+  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
+    <ConfigurationType>Application</ConfigurationType>
+    <UseOfMfc>false</UseOfMfc>
+    <CharacterSet>MultiByte</CharacterSet>
+  </PropertyGroup>
+  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
+    <ConfigurationType>Application</ConfigurationType>
+    <UseOfMfc>false</UseOfMfc>
+    <CharacterSet>MultiByte</CharacterSet>
+  </PropertyGroup>
+  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
+  <ImportGroup Label="ExtensionSettings">
+  </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+    <Import Project="$(VCTargetsPath)Microsoft.CPP.UpgradeFromVC60.props" />
+  </ImportGroup>
+  <ImportGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="PropertySheets">
+    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
+    <Import Project="$(VCTargetsPath)Microsoft.CPP.UpgradeFromVC60.props" />
+  </ImportGroup>
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FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/WIN32.vcxproj.user

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+</Project>

FreeRTOS-Plus/Demo/FreeRTOS_Plus_FAT_SL_and_CLI_Windows_Simulator/main.c

@@ -0,0 +1,237 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT
+    http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+
+    >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+    details. You should have received a copy of the GNU General Public License
+    and the FreeRTOS license exception along with FreeRTOS; if not itcan be
+    viewed here: http://www.freertos.org/a00114.html and also obtained by
+    writing to Real Time Engineers Ltd., contact details for whom are available
+    on the FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, and our new
+    fully thread aware and reentrant UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems, who sell the code with commercial support,
+    indemnification and middleware, under the OpenRTOS brand.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+*/
+
+/******************************************************************************
+ *
+ * This demo is described on the following web page:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+ *
+ ******************************************************************************/
+
+/* Standard includes. */
+#include <stdio.h>
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* File system includes. */
+#include "config_fat_sl.h"
+
+/* Priorities at which the tasks are created. */
+#define mainUDP_CLI_TASK_PRIORITY			( tskIDLE_PRIORITY )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Register the generic commands that can be used with FreeRTOS+CLI.
+ */
+extern void vRegisterSampleCLICommands( void );
+
+/*
+ * Register the file system commands that can be used with FreeRTOS+CLI.
+ */
+extern void vRegisterFileSystemCLICommands( void );
+
+/*
+ * The task that implements the UDP command interpreter using FreeRTOS+CLI.
+ */
+extern void vUDPCommandInterpreterTask( void *pvParameters );
+
+/*
+ * Creates and verifies different files on the volume, demonstrating the use of
+ * various different API functions.
+ */
+extern void vCreateAndVerifySampleFiles( void );
+
+/*-----------------------------------------------------------*/
+
+/******************************************************************************
+ *
+ * This demo is described on the following web page:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_FAT_SL/Demos/File_System_Win32_Simulator_demo.shtml
+ *
+ ******************************************************************************/
+
+int main( void )
+{
+const uint32_t ulLongTime_ms = 250UL;
+
+	/* If the file system is only going to be accessed from one task then
+	F_FS_THREAD_AWARE can be set to 0 and the set of example files are created
+	before the RTOS scheduler is started.  If the file system is going to be
+	access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
+	the	set of sample files are created from the idle task hook function
+	vApplicationIdleHook() - which is defined in this file. */
+	#if F_FS_THREAD_AWARE == 0
+	{
+		/* Initialise the drive and file system, then create a few example
+		files.  The output from this function just goes to the stdout window,
+		allowing the output to be viewed when the UDP command console is not
+		connected. */
+		vCreateAndVerifySampleFiles();
+	}
+	#endif
+
+	/* Register generic commands with the FreeRTOS+CLI command interpreter. */
+	vRegisterSampleCLICommands();
+
+	/* Register file system related commands with the FreeRTOS+CLI command
+	interpreter. */
+	vRegisterFileSystemCLICommands();
+
+	/* Create the task that handles the CLI on a UDP port.  The port number
+	is set using the configUDP_CLI_PORT_NUMBER setting in FreeRTOSConfig.h. */
+	xTaskCreate( vUDPCommandInterpreterTask, 	/* The function that implements the command interpreter IO handling. */
+				( signed char * ) "CLI", 		/* The name of the task - just to assist debugging. */
+				configMINIMAL_STACK_SIZE, NULL, /* The size of the stack allocated to the task. */
+				mainUDP_CLI_TASK_PRIORITY, 		/* The priority at which the task will run. */
+				NULL );							/* A handle to the task is not required, so NULL is passed. */
+
+	/* Start the RTOS scheduler. */
+	vTaskStartScheduler();
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the idle and/or
+	timer tasks	to be created.  See the memory management section on the
+	FreeRTOS web site for more details (this is standard text that is not not
+	really applicable to the Win32 simulator port). */
+	for( ;; )
+	{
+		Sleep( ulLongTime_ms );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+const unsigned long ulMSToSleep = 5;
+
+	/* If the file system is only going to be accessed from one task then
+	F_FS_THREAD_AWARE can be set to 0 and the set of example files is created
+	before the RTOS scheduler is started.  If the file system is going to be
+	access from more than one task then F_FS_THREAD_AWARE must be set to 1 and
+	the	set of sample files are created from the idle task hook function. */
+	#if F_FS_THREAD_AWARE == 1
+	{
+		static portBASE_TYPE xCreatedSampleFiles = pdFALSE;
+
+		/* Initialise the drive and file system, then create a few example
+		files.  The output from this function just goes to the stdout window,
+		allowing the output to be viewed when the UDP command console is not
+		connected. */
+		if( xCreatedSampleFiles == pdFALSE )
+		{
+			vCreateAndVerifySampleFiles();
+			xCreatedSampleFiles = pdTRUE;
+		}
+	}
+	#endif
+
+	/* This function is called on each cycle of the idle task if
+	configUSE_IDLE_HOOK is set to 1 in FreeRTOSConfig.h.  Sleep to reduce CPU
+	load. */
+	Sleep( ulMSToSleep );
+}
+/*-----------------------------------------------------------*/
+
+void vAssertCalled( const char *pcFile, unsigned long ulLine )
+{
+	printf( "ASSERT FAILED: File %s, line %u\r\n", pcFile, ulLine );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c, heap_2.c or heap_4.c are used, then the
+	size of the heap available to pvPortMalloc() is defined by
+	configTOTAL_HEAP_SIZE in FreeRTOSConfig.h, and the xPortGetFreeHeapSize()
+	API function can be used to query the size of free heap space that remains
+	(although it does not provide information on how the remaining heap might
+	be fragmented). */
+	taskDISABLE_INTERRUPTS();
+	for( ;; );
+}
+
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.cproject

@@ -0,0 +1,229 @@
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+<?fileVersion 4.0.0?>
+
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+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+							<builder buildPath="${workspace_loc:/FreeRTOS_UDP_Demo/Debug}" id="com.crt.advproject.builder.exe.debug.710857417" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug">
+								<outputEntries>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
+									<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Release"/>
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+							</builder>
+							<tool id="com.crt.advproject.cpp.exe.debug.359174792" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
+							<tool id="com.crt.advproject.gcc.exe.debug.517029683" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
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+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+									<listOptionValue builtIn="false" value="__USE_CMSIS"/>
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+									<listOptionValue builtIn="false" value="CORE_M3"/>
+									<listOptionValue builtIn="false" value="__LPC18XX__"/>
+								</option>
+								<option id="gnu.c.compiler.option.misc.other.732935978" name="Other flags" superClass="gnu.c.compiler.option.misc.other" value="-c -fmessage-length=0 -fno-builtin -ffunction-sections -fdata-sections -Wextra" valueType="string"/>
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+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/FreeRTOS_Plus_Trace_Recorder/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/ThirdParty/FreeRTOS_Plus_Trace_Recorder/Trace_Recorder_Configuration}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS_Plus_CLI}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Examples/include}&quot;"/>
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+							<tool id="com.crt.advproject.link.cpp.exe.debug.1490011469" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug"/>
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+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_0="" property_2="LPC1850A_4350A_SPIFI.cfx" property_3="NXP" property_4="LPC1830" property_count="5" version="1"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC1830" match_id="0x0" name="LPC1830" stub="crt_emu_lpc18_43_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC1830&lt;/name&gt;&#13;
+&lt;family&gt;LPC18xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
+&lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
+&lt;clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" type="RAM"/&gt;&#13;
+&lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" edited="true" id="SPIFlash" location="0x14000000" size="0x400000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="RamLoc96" location="0x10000000" size="0x18000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="RamLoc40" location="0x10080000" size="0xa000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB32" location="0x20000000" size="0x8000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB16" location="0x20008000" size="0x4000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/&gt;&#13;
+&lt;peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/&gt;&#13;
+&lt;peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/&gt;&#13;
+&lt;peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/&gt;&#13;
+&lt;peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/&gt;&#13;
+&lt;peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/&gt;&#13;
+&lt;peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/&gt;&#13;
+&lt;peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&lt;name gcc_name="cortex-m3"&gt;Cortex-M3&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;link href="nxp_lpc18xx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/FreeRTOS_UDP_Demo"/>
+		</configuration>
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/FreeRTOS_UDP_Demo"/>
+		</configuration>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.56486929;com.crt.advproject.config.exe.debug.56486929.;com.crt.advproject.gcc.exe.debug.517029683;com.crt.advproject.compiler.input.927112517">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.56486929;com.crt.advproject.config.exe.debug.56486929.;com.crt.advproject.gas.exe.debug.281614531;com.crt.advproject.assembler.input.1243504913">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.crt.advproject.GCCManagedMakePerProjectProfile"/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+</cproject>

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.project

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>FreeRTOS_UDP_Demo</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.cdt.codan.core.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+useParentScope=false

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/.settings/org.eclipse.ltk.core.refactoring.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CLI-commands.c

@@ -0,0 +1,666 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+ /******************************************************************************
+ *
+ * See the following URL for information on the commands defined in this file:
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Ethernet_Related_CLI_Commands.shtml
+ *
+ ******************************************************************************/
+
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+/* FreeRTOS+CLI includes. */
+#include "FreeRTOS_CLI.h"
+
+/* FreeRTOS+UDP includes, just to make the stats available to the CLI
+commands. */
+#include "FreeRTOS_UDP_IP.h"
+#include "FreeRTOS_Sockets.h"
+
+#ifndef  configINCLUDE_TRACE_RELATED_CLI_COMMANDS
+	#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+#endif
+
+
+/*
+ * Implements the run-time-stats command.
+ */
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the task-stats command.
+ */
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-three-parameters command.
+ */
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the echo-parameters command.
+ */
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that prints out IP address information.
+ */
+static portBASE_TYPE prvDisplayIPConfig( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that prints out the gathered demo debug stats.
+ */
+static portBASE_TYPE prvDisplayIPDebugStats( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Defines a command that sends an ICMP ping request to an IP address.
+ */
+static portBASE_TYPE prvPingCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+
+/*
+ * Implements the "trace start" and "trace stop" commands;
+ */
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString );
+#endif
+
+/* Structure that defines the "ip-config" command line command. */
+static const CLI_Command_Definition_t xIPConfig =
+{
+	( const int8_t * const ) "ip-config",
+	( const int8_t * const ) "ip-config:\r\n Displays IP address configuration\r\n\r\n",
+	prvDisplayIPConfig,
+	0
+};
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+	/* Structure that defines the "ip-debug-stats" command line command. */
+	static const CLI_Command_Definition_t xIPDebugStats =
+	{
+		( const int8_t * const ) "ip-debug-stats", /* The command string to type. */
+		( const int8_t * const ) "ip-debug-stats:\r\n Shows some IP stack stats useful for debug - an example only.\r\n\r\n",
+		prvDisplayIPDebugStats, /* The function to run. */
+		0 /* No parameters are expected. */
+	};
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+/* Structure that defines the "run-time-stats" command line command.   This
+generates a table that shows how much run time each task has */
+static const CLI_Command_Definition_t xRunTimeStats =
+{
+	( const int8_t * const ) "run-time-stats", /* The command string to type. */
+	( const int8_t * const ) "run-time-stats:\r\n Displays a table showing how much processing time each FreeRTOS task has used\r\n\r\n",
+	prvRunTimeStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "task-stats" command line command.  This generates
+a table that gives information on each task in the system. */
+static const CLI_Command_Definition_t xTaskStats =
+{
+	( const int8_t * const ) "task-stats", /* The command string to type. */
+	( const int8_t * const ) "task-stats:\r\n Displays a table showing the state of each FreeRTOS task\r\n\r\n",
+	prvTaskStatsCommand, /* The function to run. */
+	0 /* No parameters are expected. */
+};
+
+/* Structure that defines the "echo_3_parameters" command line command.  This
+takes exactly three parameters that the command simply echos back one at a
+time. */
+static const CLI_Command_Definition_t xThreeParameterEcho =
+{
+	( const int8_t * const ) "echo-3-parameters",
+	( const int8_t * const ) "echo-3-parameters <param1> <param2> <param3>:\r\n Expects three parameters, echos each in turn\r\n\r\n",
+	prvThreeParameterEchoCommand, /* The function to run. */
+	3 /* Three parameters are expected, which can take any value. */
+};
+
+/* Structure that defines the "echo_parameters" command line command.  This
+takes a variable number of parameters that the command simply echos back one at
+a time. */
+static const CLI_Command_Definition_t xParameterEcho =
+{
+	( const int8_t * const ) "echo-parameters",
+	( const int8_t * const ) "echo-parameters <...>:\r\n Take variable number of parameters, echos each in turn\r\n\r\n",
+	prvParameterEchoCommand, /* The function to run. */
+	-1 /* The user can enter any number of commands. */
+};
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+	/* Structure that defines the "ping" command line command.  This takes an IP
+	address or host name and (optionally) the number of bytes to ping as
+	parameters. */
+	static const CLI_Command_Definition_t xPing =
+	{
+		( const int8_t * const ) "ping",
+		( const int8_t * const ) "ping <ipaddress> <optional:bytes to send>:\r\n for example, ping 192.168.0.3 8, or ping www.example.com\r\n\r\n",
+		prvPingCommand, /* The function to run. */
+		-1 /* Ping can take either one or two parameter, so the number of parameters has to be determined by the ping command implementation. */
+	};
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	/* Structure that defines the "trace" command line command.  This takes a single
+	parameter, which can be either "start" or "stop". */
+	static const CLI_Command_Definition_t xStartStopTrace =
+	{
+		( const int8_t * const ) "trace",
+		( const int8_t * const ) "trace [start | stop]:\r\n Starts or stops a trace recording for viewing in FreeRTOS+Trace\r\n\r\n",
+		prvStartStopTraceCommand, /* The function to run. */
+		1 /* One parameter is expected.  Valid values are "start" and "stop". */
+	};
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */
+
+/*-----------------------------------------------------------*/
+
+void vRegisterCLICommands( void )
+{
+	/* Register all the command line commands defined immediately above. */
+	FreeRTOS_CLIRegisterCommand( &xTaskStats );
+	FreeRTOS_CLIRegisterCommand( &xRunTimeStats );
+	FreeRTOS_CLIRegisterCommand( &xThreeParameterEcho );
+	FreeRTOS_CLIRegisterCommand( &xParameterEcho );
+	FreeRTOS_CLIRegisterCommand( &xIPDebugStats );
+	FreeRTOS_CLIRegisterCommand( &xIPConfig );
+
+	#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+	{
+		FreeRTOS_CLIRegisterCommand( &xPing );
+	}
+	#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+	#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+		FreeRTOS_CLIRegisterCommand( & xStartStopTrace );
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvTaskStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t *const pcHeader = ( int8_t * ) "Task          State  Priority  Stack	#\r\n************************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskList( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvRunTimeStatsCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+const int8_t * const pcHeader = ( int8_t * ) "Task            Abs Time      % Time\r\n****************************************\r\n";
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	/* Generate a table of task stats. */
+	strcpy( ( char * ) pcWriteBuffer, ( char * ) pcHeader );
+	vTaskGetRunTimeStats( pcWriteBuffer + strlen( ( char * ) pcHeader ) );
+
+	/* There is no more data to return after this single string, so return
+	pdFALSE. */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvThreeParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The three parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Return the parameter string. */
+		memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+		sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+		strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+		strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+		/* If this is the last of the three parameters then there are no more
+		strings to return after this one. */
+		if( lParameterNumber == 3L )
+		{
+			/* If this is the last of the three parameters then there are no more
+			strings to return after this one. */
+			xReturn = pdFALSE;
+			lParameterNumber = 0L;
+		}
+		else
+		{
+			/* There are more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE prvParameterEchoCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+int8_t *pcParameter;
+portBASE_TYPE xParameterStringLength, xReturn;
+static portBASE_TYPE lParameterNumber = 0;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	if( lParameterNumber == 0 )
+	{
+		/* The first time the function is called after the command has been
+		entered just a header string is returned. */
+		sprintf( ( char * ) pcWriteBuffer, "The parameters were:\r\n" );
+
+		/* Next time the function is called the first parameter will be echoed
+		back. */
+		lParameterNumber = 1L;
+
+		/* There is more data to be returned as no parameters have been echoed
+		back yet. */
+		xReturn = pdPASS;
+	}
+	else
+	{
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										lParameterNumber,		/* Return the next parameter. */
+										&xParameterStringLength	/* Store the parameter string length. */
+									);
+
+		if( pcParameter != NULL )
+		{
+			/* Return the parameter string. */
+			memset( pcWriteBuffer, 0x00, xWriteBufferLen );
+			sprintf( ( char * ) pcWriteBuffer, "%d: ", ( int ) lParameterNumber );
+			strncat( ( char * ) pcWriteBuffer, ( const char * ) pcParameter, xParameterStringLength );
+			strncat( ( char * ) pcWriteBuffer, "\r\n", strlen( "\r\n" ) );
+
+			/* There might be more parameters to return after this one. */
+			xReturn = pdTRUE;
+			lParameterNumber++;
+		}
+		else
+		{
+			/* No more parameters were found.  Make sure the write buffer does
+			not contain a valid string. */
+			pcWriteBuffer[ 0 ] = 0x00;
+
+			/* No more data to return. */
+			xReturn = pdFALSE;
+
+			/* Start over the next time this command is executed. */
+			lParameterNumber = 0;
+		}
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ipconfigSUPPORT_OUTGOING_PINGS == 1
+
+	static portBASE_TYPE prvPingCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	int8_t * pcParameter;
+	portBASE_TYPE lParameterStringLength, xReturn;
+	uint32_t ulIPAddress, ulBytesToPing;
+	const uint32_t ulDefaultBytesToPing = 8UL;
+	int8_t cBuffer[ 16 ];
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		/* Start with an empty string. */
+		pcWriteBuffer[ 0 ] = 0x00;
+
+		/* Obtain the number of bytes to ping. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										2,						/* Return the second parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		if( pcParameter == NULL )
+		{
+			/* The number of bytes was not specified, so default it. */
+			ulBytesToPing = ulDefaultBytesToPing;
+		}
+		else
+		{
+			ulBytesToPing = atol( ( const char * ) pcParameter );
+		}
+
+		/* Obtain the IP address string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* Attempt to obtain the IP address.   If the first character is not a
+		digit, assume the host name has been passed in. */
+		if( ( *pcParameter >= '0' ) && ( *pcParameter <= '9' ) )
+		{
+			ulIPAddress = FreeRTOS_inet_addr( ( const uint8_t * ) pcParameter );
+		}
+		else
+		{
+			/* Terminate the host name. */
+			pcParameter[ lParameterStringLength ] = 0x00;
+
+			/* Attempt to resolve host. */
+			ulIPAddress = FreeRTOS_gethostbyname( ( uint8_t * ) pcParameter );
+		}
+
+		/* Convert IP address, which may have come from a DNS lookup, to string. */
+		FreeRTOS_inet_ntoa( ulIPAddress, ( char * ) cBuffer );
+
+		if( ulIPAddress != 0 )
+		{
+			xReturn = FreeRTOS_SendPingRequest( ulIPAddress, ( uint16_t ) ulBytesToPing, portMAX_DELAY );
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+
+		if( xReturn == pdFALSE )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "%s", "Could not send ping request\r\n" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Ping sent to %s with identifier %d\r\n", cBuffer, xReturn );
+		}
+
+		return pdFALSE;
+	}
+	/*-----------------------------------------------------------*/
+
+#endif /* ipconfigSUPPORT_OUTGOING_PINGS */
+
+#if configINCLUDE_DEMO_DEBUG_STATS != 0
+
+	static portBASE_TYPE prvDisplayIPDebugStats( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	static portBASE_TYPE xIndex = -1;
+	extern xExampleDebugStatEntry_t xIPTraceValues[];
+	portBASE_TYPE xReturn;
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		xIndex++;
+
+		if( xIndex < xExampleDebugStatEntries() )
+		{
+			sprintf( ( char * ) pcWriteBuffer, "%s %d\r\n", ( char * ) xIPTraceValues[ xIndex ].pucDescription, ( int ) xIPTraceValues[ xIndex ].ulData );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* Reset the index for the next time it is called. */
+			xIndex = -1;
+
+			/* Ensure nothing remains in the write buffer. */
+			pcWriteBuffer[ 0 ] = 0x00;
+			xReturn = pdFALSE;
+		}
+
+		return xReturn;
+	}
+	/*-----------------------------------------------------------*/
+
+#endif /* configINCLUDE_DEMO_DEBUG_STATS */
+
+static portBASE_TYPE prvDisplayIPConfig( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+{
+static portBASE_TYPE xIndex = 0;
+portBASE_TYPE xReturn;
+uint32_t ulAddress;
+
+	/* Remove compile time warnings about unused parameters, and check the
+	write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+	write buffer length is adequate, so does not check for buffer overflows. */
+	( void ) pcCommandString;
+	( void ) xWriteBufferLen;
+	configASSERT( pcWriteBuffer );
+
+	switch( xIndex )
+	{
+		case 0 :
+			FreeRTOS_GetAddressConfiguration( &ulAddress, NULL, NULL, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nIP address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 1 :
+			FreeRTOS_GetAddressConfiguration( NULL, &ulAddress, NULL, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nNet mask " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 2 :
+			FreeRTOS_GetAddressConfiguration( NULL, NULL, &ulAddress, NULL );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nGateway address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		case 3 :
+			FreeRTOS_GetAddressConfiguration( NULL, NULL, NULL, &ulAddress );
+			sprintf( ( char * ) pcWriteBuffer, "\r\nDNS server address " );
+			xReturn = pdTRUE;
+			xIndex++;
+			break;
+
+		default :
+			ulAddress = 0;
+			sprintf( ( char * ) pcWriteBuffer, "\r\n\r\n" );
+			xReturn = pdFALSE;
+			xIndex = 0;
+			break;
+	}
+
+	if( ulAddress != 0 )
+	{
+		FreeRTOS_inet_ntoa( ulAddress, ( ( char * ) &( pcWriteBuffer[ strlen( ( char * ) pcWriteBuffer ) ] ) ) );
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+
+	static portBASE_TYPE prvStartStopTraceCommand( int8_t *pcWriteBuffer, size_t xWriteBufferLen, const int8_t *pcCommandString )
+	{
+	int8_t *pcParameter;
+	portBASE_TYPE lParameterStringLength;
+
+		/* Remove compile time warnings about unused parameters, and check the
+		write buffer is not NULL.  NOTE - for simplicity, this example assumes the
+		write buffer length is adequate, so does not check for buffer overflows. */
+		( void ) pcCommandString;
+		( void ) xWriteBufferLen;
+		configASSERT( pcWriteBuffer );
+
+		/* Obtain the parameter string. */
+		pcParameter = ( int8_t * ) FreeRTOS_CLIGetParameter
+									(
+										pcCommandString,		/* The command string itself. */
+										1,						/* Return the first parameter. */
+										&lParameterStringLength	/* Store the parameter string length. */
+									);
+
+		/* Sanity check something was returned. */
+		configASSERT( pcParameter );
+
+		/* There are only two valid parameter values. */
+		if( strncmp( ( const char * ) pcParameter, "start", strlen( "start" ) ) == 0 )
+		{
+			/* Start or restart the trace. */
+			vTraceStop();
+			vTraceClear();
+			vTraceStart();
+
+			sprintf( ( char * ) pcWriteBuffer, "Trace recording (re)started.\r\n" );
+		}
+		else if( strncmp( ( const char * ) pcParameter, "stop", strlen( "stop" ) ) == 0 )
+		{
+			/* End the trace, if one is running. */
+			vTraceStop();
+			sprintf( ( char * ) pcWriteBuffer, "Stopping trace recording.\r\n" );
+		}
+		else
+		{
+			sprintf( ( char * ) pcWriteBuffer, "Valid parameters are 'start' and 'stop'.\r\n" );
+		}
+
+		/* There is no more data to return after this single string, so return
+		pdFALSE. */
+		return pdFALSE;
+	}
+
+#endif /* configINCLUDE_TRACE_RELATED_CLI_COMMANDS */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/CreateProjectDirectoryStructure.bat

@@ -0,0 +1,81 @@
+REM This file should be executed from the command line prior to the first
+REM build.  It will be necessary to refresh the Eclipse project once the
+REM .bat file has been executed (normally just press F5 to refresh).
+
+REM Copies all the required files from their location within the standard
+REM FreeRTOS directory structure to under the Eclipse project directory.
+REM This permits the Eclipse project to be used in 'managed' mode and without
+REM having to setup any linked resources.
+
+REM Standard paths
+SET FREERTOS_SOURCE=..\..\..\FreeRTOS\Source
+SET FREERTOS_UDP_SOURCE=..\..\Source\FreeRTOS-Plus-UDP
+SET FREERTOS_CLI_SOURCE=..\..\Source\FreeRTOS-Plus-CLI
+set FREERTOS_TRACE_RECORDER_SOURCE=..\..\Source\FreeRTOS-Plus-Trace
+
+REM Have the files already been copied?
+IF EXIST FreeRTOS_Source Goto END
+
+    REM Create the required directory structure.
+    MD FreeRTOS_Source
+    MD FreeRTOS_Source\include
+    MD FreeRTOS_Source\portable\
+	MD FreeRTOS_Source\portable\GCC
+    MD FreeRTOS_Source\portable\GCC\ARM_CM3
+    MD FreeRTOS_Source\portable\MemMang
+	MD FreeRTOS_Plus_UDP
+	MD FreeRTOS_Plus_UDP\include
+	MD FreeRTOS_Plus_UDP\portable
+	MD FreeRTOS_Plus_UDP\portable\Compiler
+	MD FreeRTOS_Plus_UDP\portable\Compiler\GCC
+	MD FreeRTOS_Plus_UDP\portable\BufferManagement
+	MD FreeRTOS_Plus_UDP\portable\NetworkInterface
+	MD FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
+	MD FreeRTOS_Plus_CLI
+	MD Examples\Ethernet
+
+    REM Copy the core kernel files into the SDK projects directory
+    copy %FREERTOS_SOURCE%\tasks.c FreeRTOS_Source
+    copy %FREERTOS_SOURCE%\queue.c FreeRTOS_Source
+    copy %FREERTOS_SOURCE%\list.c FreeRTOS_Source
+    copy %FREERTOS_SOURCE%\timers.c FreeRTOS_Source
+
+    REM Copy the common header files into the SDK projects directory
+    copy %FREERTOS_SOURCE%\include\*.* FreeRTOS_Source\include
+
+    REM Copy the portable layer files into the projects directory
+    copy %FREERTOS_SOURCE%\portable\GCC\ARM_CM3\*.* FreeRTOS_Source\portable\GCC\ARM_CM3
+
+    REM Copy the memory allocation file into the project's directory
+    copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS_Source\portable\MemMang
+
+	REM Copy the FreeRTOS+UDP core files
+	copy %FREERTOS_UDP_SOURCE%\*.c FreeRTOS_Plus_UDP
+	copy %FREERTOS_UDP_SOURCE%\include\*.h FreeRTOS_Plus_UDP
+	copy %FREERTOS_UDP_SOURCE%\readme.txt FreeRTOS_Plus_UDP
+	copy %FREERTOS_UDP_SOURCE%\include\*.* FreeRTOS_Plus_UDP\include
+
+	REM Copy the FreeRTOS+UDP portable layer files
+	copy %FREERTOS_UDP_SOURCE%\portable\NetworkInterface\LPC18xx\Using_CMSISv2p10_LPC18xx_DriverLib\*.* FreeRTOS_Plus_UDP\portable\NetworkInterface\LPC18xx
+	copy %FREERTOS_UDP_SOURCE%\portable\BufferManagement\BufferAllocation_2.c FreeRTOS_Plus_UDP\portable\BufferManagement
+	copy %FREERTOS_UDP_SOURCE%\portable\Compiler\GCC\*.* FreeRTOS_Plus_UDP\portable\Compiler\GCC
+
+	REM Copy the FreeRTOS+CLI files
+	copy %FREERTOS_CLI_SOURCE%\*.* FreeRTOS_Plus_CLI
+	
+	REM Copy the FreeRTOS+Trace recorder files
+	copy %FREERTOS_TRACE_RECORDER_SOURCE%\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder
+	copy %FREERTOS_TRACE_RECORDER_SOURCE%\include\*.* ThirdParty\FreeRTOS_Plus_Trace_Recorder\include
+
+	REM Copy the echo client example implementation
+	copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.c Examples\Ethernet
+	copy ..\Common\FreeRTOS_Plus_UDP_Demos\EchoClients\TwoEchoClients.h Examples\include
+
+	REM Copy the example IP trace macro implementation
+	copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.c Examples\Ethernet
+	copy ..\Common\FreeRTOS_Plus_UDP_Demos\TraceMacros\Example1\DemoIPTrace.h Examples\include
+
+	REM Copy the CLI commands implementation into the project directory.
+	copy ..\Common\FreeRTOS_Plus_UDP_Demos\CLICommands\CLI-commands.c .
+
+: END

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/USB_CDC/CDCCommandConsole.c

@@ -0,0 +1,325 @@
+/*
+    FreeRTOS V7.1.0 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS tutorial books are available in pdf and paperback.        *
+     *    Complete, revised, and edited pdf reference manuals are also       *
+     *    available.                                                         *
+     *                                                                       *
+     *    Purchasing FreeRTOS documentation will not only help you, by       *
+     *    ensuring you get running as quickly as possible and with an        *
+     *    in-depth knowledge of how to use FreeRTOS, it will also help       *
+     *    the FreeRTOS project to continue with its mission of providing     *
+     *    professional grade, cross platform, de facto standard solutions    *
+     *    for microcontrollers - completely free of charge!                  *
+     *                                                                       *
+     *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
+     *                                                                       *
+     *    Thank you for using FreeRTOS, and thank you for your support!      *
+     *                                                                       *
+    ***************************************************************************
+
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+    >>>NOTE<<< The modification to the GPL is included to allow you to
+    distribute a combined work that includes FreeRTOS without being obliged to
+    provide the source code for proprietary components outside of the FreeRTOS
+    kernel.  FreeRTOS is distributed in the hope that it will be useful, but
+    WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+    more details. You should have received a copy of the GNU General Public
+    License and the FreeRTOS license exception along with FreeRTOS; if not it
+    can be viewed here: http://www.freertos.org/a00114.html and also obtained
+    by writing to Richard Barry, contact details for whom are available on the
+    FreeRTOS WEB site.
+
+    1 tab == 4 spaces!
+
+    http://www.FreeRTOS.org - Documentation, latest information, license and
+    contact details.
+
+    http://www.SafeRTOS.com - A version that is certified for use in safety
+    critical systems.
+
+    http://www.OpenRTOS.com - Commercial support, development, porting,
+    licensing and training services.
+*/
+
+/*
+ * NOTE:  This file uses a third party USB CDC driver.
+ */
+
+/* Standard includes. */
+#include "string.h"
+#include "stdio.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Driver includes. */
+#include "usbhw.h"
+#include "cdcuser.h"
+#include "usbcfg.h"
+#include "usbuser.h"
+
+/* Example includes. */
+#include "FreeRTOS_CLI.h"
+#include "CDCCommandConsole.h"
+
+/* Dimensions the buffer into which input characters are placed. */
+#define cmdMAX_INPUT_SIZE		50
+
+/* The maximum time in ticks to wait for the CDC access mutex. */
+#define cmdMAX_MUTEX_WAIT		( 200 / portTICK_RATE_MS )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The task that implements the command console processing.
+ */
+static void prvCDCCommandConsoleTask( void *pvParameters );
+
+/*
+ * Obtain a character from the CDC input.  The calling task will be held in the
+ * Blocked state (so other tasks can execute) until a character is avilable.
+ */
+int8_t cGetCDCChar( void );
+
+/*
+ * Initialise the third party virtual comport files driver
+ */
+static void prvSetupUSBDrivers( void );
+
+/*-----------------------------------------------------------*/
+
+/* 'Given' by the CDC interrupt to unblock the receiving task when new data
+is available. */
+static xSemaphoreHandle xNewDataSemaphore = NULL;
+
+/* Used to guard access to the CDC output, which is used by more than one
+task. */
+static xSemaphoreHandle xCDCMutex = NULL;
+
+/* Const messages output by the command console. */
+static const uint8_t * const pcWelcomeMessage = ( uint8_t * ) "FreeRTOS command server.\r\nType Help to view a list of registered commands.\r\n\r\n>";
+static const uint8_t * const pcEndOfOutputMessage = ( uint8_t * ) "\r\n[Press ENTER to execute the previous command again]\r\n>";
+static const uint8_t * const pcNewLine = ( uint8_t * ) "\r\n";
+
+/*-----------------------------------------------------------*/
+
+void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority )
+{
+	/* Create the semaphores and mutexes used by the CDC to task interface. */
+	xCDCMutex = xSemaphoreCreateMutex();
+	vSemaphoreCreateBinary( xNewDataSemaphore );
+	configASSERT( xCDCMutex );
+	configASSERT( xNewDataSemaphore );
+
+	/* Add the semaphore and mutex to the queue registry for viewing in the
+	kernel aware state viewer. */
+	vQueueAddToRegistry( xCDCMutex, ( signed char * ) "CDCMu" );
+	vQueueAddToRegistry( xNewDataSemaphore, ( signed char * ) "CDCDat" );
+
+	/* Create that task that handles the console itself. */
+	xTaskCreate( 	prvCDCCommandConsoleTask,			/* The task that implements the command console. */
+					( const int8_t * const ) "CDCCmd",	/* Text name assigned to the task.  This is just to assist debugging.  The kernel does not use this name itself. */
+					usStackSize,						/* The size of the stack allocated to the task. */
+					NULL,								/* The parameter is not used, so NULL is passed. */
+					uxPriority,							/* The priority allocated to the task. */
+					NULL );								/* A handle is not required, so just pass NULL. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvCDCCommandConsoleTask( void *pvParameters )
+{
+int8_t cRxedChar, cInputIndex = 0, *pcOutputString;
+static int8_t cInputString[ cmdMAX_INPUT_SIZE ], cLastInputString[ cmdMAX_INPUT_SIZE ];
+portBASE_TYPE xReturned;
+
+	( void ) pvParameters;
+
+	/* Obtain the address of the output buffer.  Note there is no mutual
+	exclusion on this buffer as it is assumed only one command console
+	interface will be used at any one time. */
+	pcOutputString = FreeRTOS_CLIGetOutputBuffer();
+
+	/* Initialise the virtual com port (CDC) interface. */
+	prvSetupUSBDrivers();
+
+	/* Send the welcome message.  This probably won't be seen as the console
+	will not have been connected yet. */
+	USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcWelcomeMessage, strlen( ( const char * ) pcWelcomeMessage ) );
+
+	for( ;; )
+	{
+		/* No characters received yet for the current input string. */
+		cRxedChar = 0;
+
+		/* Only interested in reading one character at a time. */
+		cRxedChar = cGetCDCChar();
+
+		if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+		{
+			/* Echo the character back. */
+			USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) &cRxedChar, sizeof( uint8_t ) );
+
+			/* Was it the end of the line? */
+			if( cRxedChar == '\n' || cRxedChar == '\r' )
+			{
+				/* Just to space the output from the input. */
+				USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcNewLine, strlen( ( const char * ) pcNewLine ) );
+
+				/* See if the command is empty, indicating that the last command is
+				to be executed again. */
+				if( cInputIndex == 0 )
+				{
+					/* Copy the last command back into the input string. */
+					strcpy( ( char * ) cInputString, ( char * ) cLastInputString );
+				}
+
+				/* Pass the received command to the command interpreter.  The
+				command interpreter is called repeatedly until it returns pdFALSE
+				(indicating there is no more output) as it might generate more than
+				one string. */
+				do
+				{
+					/* Get the next output string from the command interpreter. */
+					xReturned = FreeRTOS_CLIProcessCommand( cInputString, pcOutputString, configCOMMAND_INT_MAX_OUTPUT_SIZE );
+
+					/* Write the generated string to the CDC. */
+					USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcOutputString, strlen( ( const char * ) pcOutputString ) );
+					vTaskDelay( 1 );
+
+				} while( xReturned != pdFALSE );
+
+				/* All the strings generated by the input command have been sent.
+				Clear the input	string ready to receive the next command.  Remember
+				the command that was just processed first in case it is to be
+				processed again. */
+				strcpy( ( char * ) cLastInputString, ( char * ) cInputString );
+				cInputIndex = 0;
+				memset( cInputString, 0x00, cmdMAX_INPUT_SIZE );
+
+				USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pcEndOfOutputMessage, strlen( ( const char * ) pcEndOfOutputMessage ) );
+			}
+			else
+			{
+				if( cRxedChar == '\r' )
+				{
+					/* Ignore the character. */
+				}
+				else if( cRxedChar == '\b' )
+				{
+					/* Backspace was pressed.  Erase the last character in the
+					string - if any. */
+					if( cInputIndex > 0 )
+					{
+						cInputIndex--;
+						cInputString[ cInputIndex ] = '\0';
+					}
+				}
+				else
+				{
+					/* A character was entered.  Add it to the string
+					entered so far.  When a \n is entered the complete
+					string will be passed to the command interpreter. */
+					if( ( cRxedChar >= ' ' ) && ( cRxedChar <= '~' ) )
+					{
+						if( cInputIndex < cmdMAX_INPUT_SIZE )
+						{
+							cInputString[ cInputIndex ] = cRxedChar;
+							cInputIndex++;
+						}
+					}
+				}
+			}
+
+			/* Must ensure to give the mutex back. */
+			xSemaphoreGive( xCDCMutex );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vOutputString( const uint8_t * const pucMessage )
+{
+	if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+	{
+		USB_WriteEP( CDC_DEP_IN, ( uint8_t * ) pucMessage, strlen( ( const char * ) pucMessage ) );
+		xSemaphoreGive( xCDCMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+int8_t cGetCDCChar( void )
+{
+int32_t lAvailableBytes, xBytes = 0;
+int8_t cInputChar;
+
+	do
+	{
+		/* Are there any characters already available? */
+		CDC_OutBufAvailChar( &lAvailableBytes );
+		if( lAvailableBytes > 0 )
+		{
+			if( xSemaphoreTake( xCDCMutex, cmdMAX_MUTEX_WAIT ) == pdPASS )
+			{
+				/* Attempt to read one character. */
+				xBytes = 1;
+				xBytes = CDC_RdOutBuf( ( char * ) &cInputChar, &xBytes );
+
+				xSemaphoreGive( xCDCMutex );
+			}
+		}
+
+		if( xBytes == 0 )
+		{
+			/* A character was not available.  Wait until signalled by the
+			CDC Rx callback function that new data has arrived. */
+			xSemaphoreTake( xNewDataSemaphore, portMAX_DELAY );
+		}
+
+	} while( xBytes == 0 );
+
+	return cInputChar;
+}
+/*-----------------------------------------------------------*/
+
+/* Callback function executed by the USB interrupt when new data arrives. */
+void vCDCNewDataNotify( void )
+{
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+
+	configASSERT( xNewDataSemaphore );
+
+	/* 'Give' the semaphore that signals the arrival of new data to the command
+	console task. */
+	xSemaphoreGiveFromISR( xNewDataSemaphore, &xHigherPriorityTaskWoken );
+	portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupUSBDrivers( void )
+{
+LPC_USBDRV_INIT_T xUSBCallback;
+
+	/* Initialise the callback structure. */
+	memset( ( void * ) &xUSBCallback, 0, sizeof( LPC_USBDRV_INIT_T ) );
+	xUSBCallback.USB_Reset_Event = USB_Reset_Event;
+	xUSBCallback.USB_P_EP[ 0 ] = USB_EndPoint0;
+	xUSBCallback.USB_P_EP[ 1 ] = USB_EndPoint1;
+	xUSBCallback.USB_P_EP[ 2 ] = USB_EndPoint2;
+	xUSBCallback.ep0_maxp = USB_MAX_PACKET0;
+
+	/* Initialise then connect the USB. */
+	USB_Init( &xUSBCallback );
+	USB_Connect( pdTRUE );
+}

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/CDCCommandConsole.h

@@ -0,0 +1,77 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef CDC_COMMAND_CONSOLE_H
+#define CDC_COMMAND_CONSOLE_H
+
+/*
+ * Create the task that implements a command console using the USB virtual com
+ * port driver for intput and output.
+ */
+void vCDCCommandConsoleStart( uint16_t usStackSize, unsigned portBASE_TYPE uxPriority );
+
+#endif /* CDC_COMMAND_CONSOLE_H */
+
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Examples/include/TwoEchoClients.h

@@ -0,0 +1,75 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef TWO_ECHO_CLIENTS_H
+#define TWO_ECHO_CLIENTS_H
+
+/*
+ * Create the two UDP echo client tasks.  One task uses the standard interface
+ * to send to and receive from an echo server.  The other task uses the zero
+ * copy interface to send to and receive from an echo server.
+ */
+void vStartEchoClientTasks( uint16_t usTaskStackSize, unsigned portBASE_TYPE uxTaskPriority );
+
+#endif /* TWO_ECHO_CLIENTS_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/Flash_map.xml

@@ -0,0 +1,12 @@
+<info flash_driver='LPC1850A_4350A_SPIFI.cfx'>
+ <chip>
+  <memory id='Flash' type='Flash' is_ro='true' can_program='true'></memory>
+  <memory id='RAM' type='RAM'></memory>
+   <memoryInstance id='SPIFlash' derived_from='Flash' location='0x14000000' size='0x400000'  edited='true'/>
+   <memoryInstance id='RamLoc96' derived_from='RAM' location='0x10000000' size='0x18000'  edited='true'/>
+   <memoryInstance id='RamLoc40' derived_from='RAM' location='0x10080000' size='0xa000'  edited='true'/>
+   <memoryInstance id='RamAHB32' derived_from='RAM' location='0x20000000' size='0x8000'  edited='true'/>
+   <memoryInstance id='RamAHB16' derived_from='RAM' location='0x20008000' size='0x4000'  edited='true'/>
+   <memoryInstance id='RamAHB_ETB16' derived_from='RAM' location='0x2000c000' size='0x4000'  edited='true'/>
+ </chip>
+</info>

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSConfig.h

@@ -0,0 +1,283 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <stdint.h>
+extern uint32_t SystemCoreClock;
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ * http://www.freertos.org/a00110.html
+ *
+ * The bottom of this file contains some constants specific to running the UDP
+ * stack in this demo.  Constants specific to FreeRTOS+UDP itself (rather than
+ * the demo) are contained in FreeRTOSIPConfig.h.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION			1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_TICKLESS_IDLE			0
+#define configMAX_PRIORITIES			( 7 )
+#define configCPU_CLOCK_HZ				( SystemCoreClock )
+#define configTICK_RATE_HZ				100
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 300 )
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 40 * 1024 ) ) /* Has not effect in this demo as the heap is manually pointed to AHB RAM. */
+#define configMAX_TASK_NAME_LEN			( 12 )
+#define configIDLE_SHOULD_YIELD			0
+#define configQUEUE_REGISTRY_SIZE		10
+#define configUSE_TRACE_FACILITY		1
+#define configUSE_16_BIT_TICKS			0
+#define configUSE_MUTEXES				1
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+#define configUSE_COUNTING_SEMAPHORES 	1
+#define configUSE_ALTERNATIVE_API 		0
+#define configUSE_RECURSIVE_MUTEXES		1
+
+/* Hook function related definitions. */
+#define configUSE_TICK_HOOK				0
+#define configUSE_IDLE_HOOK				0
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configCHECK_FOR_STACK_OVERFLOW	2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		5
+#define configTIMER_TASK_STACK_DEPTH	configMINIMAL_STACK_SIZE
+
+/* Run time stats gathering definitions. */
+void vMainConfigureTimerForRunTimeStats( void );
+uint32_t ulMainGetRunTimeCounterValue( void );
+#define configGENERATE_RUN_TIME_STATS	1
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() vMainConfigureTimerForRunTimeStats()
+#define portGET_RUN_TIME_COUNTER_VALUE() ulMainGetRunTimeCounterValue()
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		0
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_uxTaskGetStackHighWaterMark	1
+#define INCLUDE_xTimerGetTimerTaskHandle	0
+#define INCLUDE_xTaskGetIdleTaskHandle		0
+#define INCLUDE_xQueueGetMutexHolder		1
+
+/* This demo makes use of one or more example stats formatting functions.  These
+format the raw data provided by the uxTaskGetSystemState() function in to human
+readable ASCII form.  See the notes in the implementation of vTaskList() within 
+FreeRTOS/Source/tasks.c for limitations. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS	1
+
+/* Assert statement defined for debug builds. */
+#ifdef DEBUG
+	#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+#endif
+
+/* Interrupt priority configuration settings follow.
+http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+
+/* Use the system definition for the number of interrupt priorities, if there
+is one */
+#ifdef __NVIC_PRIO_BITS
+	#define configPRIO_BITS       __NVIC_PRIO_BITS
+#else
+	#define configPRIO_BITS       5        /* 32 priority levels */
+#endif
+
+/* The maximum priority an interrupt that uses an interrupt safe FreeRTOS API
+function can have.  Note that lower priority have numerically higher values.  */
+#define configMAX_LIBRARY_INTERRUPT_PRIORITY	( 5 )
+
+/* The minimum possible interrupt priority. */
+#define configMIN_LIBRARY_INTERRUPT_PRIORITY	( 31 )
+
+/* The lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY 		( configMIN_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Priority 5, or 248 as only the top five bits are implemented. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configMAX_LIBRARY_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler SVC_Handler
+#define xPortPendSVHandler PendSV_Handler
+#define xPortSysTickHandler SysTick_Handler
+
+
+
+
+/*
+ * DEMO APPLICATION SPECIFIC DEFINITIONS FOLLOW FROM HERE
+ */
+
+/* Set to 1 to include "trace start" and "trace stop" CLI commands.  These
+commands start and stop the FreeRTOS+Trace recording. */
+#define configINCLUDE_TRACE_RELATED_CLI_COMMANDS 0
+
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command
+interpreter.  See the FreeRTOS+CLI documentation for more information:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE		1024
+
+/* The priority used by the Ethernet MAC driver interrupt. */
+#define configMAC_INTERRUPT_PRIORITY		( configMAX_LIBRARY_INTERRUPT_PRIORITY )
+
+/* If configINCLUDE_DEMO_DEBUG_STATS is set to one, then a few basic IP trace
+macros are defined to gather some UDP stack statistics that can then be viewed
+through the CLI interface.  See
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Trace.shtml*/
+#define configINCLUDE_DEMO_DEBUG_STATS 1
+
+/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
+The DMA uses a chain of descriptors to reference Ethernet buffers, and provide
+information on the state of each buffer (full/empty/error/etc.).
+configNUM_RX_ETHERNET_DMA_DESCRIPTORS defines the total number of receive
+descriptors (descriptors that point to buffers into which the DMA will write
+packets received from the network).  An Ethernet buffer is assigned to each
+descriptor.  Having too few descriptors will impact reliability because the DMA
+will have to drop packets that are received when there are no receive
+descriptors free.  It is however only necessary to have a couple of free
+descriptors at a time, and having more wastes the RAM used by the Ethernet
+buffers that are surplus to requirements. */
+#define configNUM_RX_ETHERNET_DMA_DESCRIPTORS	4
+
+/* The LPC1830 Ethernet peripheral uses a DMA to transmit and receive packets.
+The DMA uses a chain of descriptors to reference Ethernet buffers that are
+waiting to be sent onto the network.  configNUM_TX_ETHERNET_DMA_DESCRIPTORS
+defines the total number of transmit descriptors.  An Ethernet buffer is
+not assigned to a transmit descriptor until data is actually sent, but will
+remain assigned to the descriptor until the descriptor is re-used.  It is not
+necessary to have many transmit descriptors as the IP stack task will be held
+in the Blocked state (so other tasks can run) until a descriptor becomes
+available if it attempts to transmit when all the descriptors are in use.  See
+the iptraceWAITING_FOR_TX_DMA_DESCRIPTOR() IP trace macro. */
+#define configNUM_TX_ETHERNET_DMA_DESCRIPTORS	1
+
+/* The address of an echo server that will be used by the two demo echo client
+tasks.
+http://FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/Common_Echo_Clients.shtml */
+#define configECHO_SERVER_ADDR0	172
+#define configECHO_SERVER_ADDR1 25
+#define configECHO_SERVER_ADDR2 218
+#define configECHO_SERVER_ADDR3 103
+
+/* MAC address configuration.  In a deployed production system this would
+probably be read from an EEPROM.  In the demo it is just hard coded.  Make sure
+each node on the network has a unique MAC address. */
+#define configMAC_ADDR0	0x00
+#define configMAC_ADDR1	0x01
+#define configMAC_ADDR2	0x02
+#define configMAC_ADDR3	0x03
+#define configMAC_ADDR4	0x04
+#define configMAC_ADDR5	0x08
+
+/* Default IP address configuration.  Used in ipconfigUSE_DNS is set to 0, or
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configIP_ADDR0		172
+#define configIP_ADDR1		25
+#define configIP_ADDR2		218
+#define configIP_ADDR3		200
+
+/* Default gateway IP address configuration.  Used in ipconfigUSE_DNS is set to
+0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configGATEWAY_ADDR0	192
+#define configGATEWAY_ADDR1	168
+#define configGATEWAY_ADDR2	1
+#define configGATEWAY_ADDR3	1
+
+/* Default DNS server configuration.  OpenDNS addresses are 208.67.222.222 and
+208.67.220.220.  Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set
+to 1 but a DNS server cannot be contacted.*/
+#define configDNS_SERVER_ADDR0 	208
+#define configDNS_SERVER_ADDR1 	67
+#define configDNS_SERVER_ADDR2 	222
+#define configDNS_SERVER_ADDR3 	222
+
+/* Defalt netmask configuration.  Used in ipconfigUSE_DNS is set to 0, or
+ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */
+#define configNET_MASK0		255
+#define configNET_MASK1		255
+#define configNET_MASK2		255
+#define configNET_MASK3		0
+
+#if configINCLUDE_TRACE_RELATED_CLI_COMMANDS == 1
+	/* Only include the trace macro definitions required by FreeRTOS+Trace if
+	the trace start and trace stop CLI commands are included. */
+	#include "trcKernelPort.h"
+#endif
+
+#endif /* FREERTOS_CONFIG_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/FreeRTOSIPConfig.h

@@ -0,0 +1,232 @@
+/*
+ * FreeRTOS+UDP V1.0.0 (C) 2013 Real Time Engineers ltd.
+ *
+ * FreeRTOS+UDP is an add-on component to FreeRTOS.  It is not, in itself, part
+ * of the FreeRTOS kernel.  FreeRTOS+UDP is licensed separately from FreeRTOS,
+ * and uses a different license to FreeRTOS.  FreeRTOS+UDP uses a dual license
+ * model, information on which is provided below:
+ *
+ * - Open source licensing -
+ * FreeRTOS+UDP is a free download and may be used, modified and distributed
+ * without charge provided the user adheres to version two of the GNU General
+ * Public license (GPL) and does not remove the copyright notice or this text.
+ * The GPL V2 text is available on the gnu.org web site, and on the following
+ * URL: http://www.FreeRTOS.org/gpl-2.0.txt
+ *
+ * - Commercial licensing -
+ * Businesses and individuals who wish to incorporate FreeRTOS+UDP into
+ * proprietary software for redistribution in any form must first obtain a
+ * (very) low cost commercial license - and in-so-doing support the maintenance,
+ * support and further development of the FreeRTOS+UDP product.  Commercial
+ * licenses can be obtained from http://shop.freertos.org and do not require any
+ * source files to be changed.
+ *
+ * FreeRTOS+UDP is distributed in the hope that it will be useful.  You cannot
+ * use FreeRTOS+UDP unless you agree that you use the software 'as is'.
+ * FreeRTOS+UDP is provided WITHOUT ANY WARRANTY; without even the implied
+ * warranties of NON-INFRINGEMENT, MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ * PURPOSE. Real Time Engineers Ltd. disclaims all conditions and terms, be they
+ * implied, expressed, or statutory.
+ *
+ * 1 tab == 4 spaces!
+ *
+ * http://www.FreeRTOS.org
+ * http://www.FreeRTOS.org/FreeRTOS-Plus
+ *
+ */
+
+/*****************************************************************************
+ *
+ * See the following URL for configuration information.
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/UDP_IP_Configuration.shtml
+ *
+ *****************************************************************************/
+
+#ifndef FREERTOS_IP_CONFIG_H
+#define FREERTOS_IP_CONFIG_H
+
+/* The IP stack executes it its own task (although any application task can make
+use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY
+sets the priority of the task that executes the IP stack.  The priority is a
+standard FreeRTOS task priority so can take any value from 0 (the lowest
+priority) to (configMAX_PRIORITIES - 1) (the highest priority).
+configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in
+FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to
+the priority assigned to the task executing the IP stack relative to the
+priority assigned to tasks that use the IP stack. */
+#define ipconfigUDP_TASK_PRIORITY			( configMAX_PRIORITIES - 2 )
+
+/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+UDP
+task.  This setting is less important when the FreeRTOS Win32 simulator is used
+as the Win32 simulator only stores a fixed amount of information on the task
+stack.  FreeRTOS includes optional stack overflow detection, see:
+http://www.freertos.org/Stacks-and-stack-overflow-checking.html */
+#define ipconfigUDP_TASK_STACK_SIZE_WORDS	( configMINIMAL_STACK_SIZE * 3 )
+
+/* ipconfigRAND32() is called by the IP stack to generate a random number that
+is then used as a DHCP transaction number.  Random number generation is performed
+via this macro to allow applications to use their own random number generation
+method.  For example, it might be possible to generate a random number by
+sampling noise on an analogue input. */
+#define ipconfigRAND32()	1
+
+/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+UDP will call the
+network event hook at the appropriate times.  If ipconfigUSE_NETWORK_EVENT_HOOK
+is not set to 1 then the network event hook will never be called.  See
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml
+*/
+#define ipconfigUSE_NETWORK_EVENT_HOOK 1
+
+/* Sockets have a send block time attribute.  If FreeRTOS_sendto() is called but
+a network buffer cannot be obtained then the calling task is held in the Blocked
+state (so other tasks can continue to executed) until either a network buffer
+becomes available or the send block time expires.  If the send block time expires
+then the send operation is aborted.  The maximum allowable send block time is
+capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS.  Capping the
+maximum allowable send block time prevents prevents a deadlock occurring when
+all the network buffers are in use and the tasks that process (and subsequently
+free) the network buffers are themselves blocked waiting for a network buffer.
+ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks.  A time in
+milliseconds can be converted to a time in ticks by dividing the time in
+milliseconds by portTICK_RATE_MS. */
+#define ipconfigMAX_SEND_BLOCK_TIME_TICKS ( 20 / portTICK_RATE_MS )
+
+/* If ipconfigUSE_DHCP is 1 then FreeRTOS+UDP will attempt to retrieve an IP
+address, netmask, DNS server address and gateway address from a DHCP server.  If
+ipconfigUSE_DHCP is 0 then FreeRTOS+UDP will use a static IP address.  The
+stack will revert to using the static IP address even when ipconfigUSE_DHCP is
+set to 1 if a valid configuration cannot be obtained from a DHCP server for any
+reason.  The static configuration used is that passed into the stack by the
+FreeRTOS_IPInit() function call. */
+#define ipconfigUSE_DHCP	1
+
+/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at
+increasing time intervals until either a reply is received from a DHCP server
+and accepted, or the interval between transmissions reaches
+ipconfigMAXIMUM_DISCOVER_TX_PERIOD.  The IP stack will revert to using the
+static IP address passed as a parameter to FreeRTOS_IPInit() if the
+re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without
+a DHCP reply being received. */
+#ifdef _WINDOWS_
+	/* The windows simulated time is not real time so the max delay is much
+	shorter. */
+	#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD		( 999 / portTICK_RATE_MS )
+#else
+	#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD		( 120000 / portTICK_RATE_MS )
+#endif /* _WINDOWS_ */
+
+/* The ARP cache is a table that maps IP addresses to MAC addresses.  The IP
+stack can only send a UDP message to a remove IP address if it knowns the MAC
+address associated with the IP address, or the MAC address of the router used to
+contact the remote IP address.  When a UDP message is received from a remote IP
+address the MAC address and IP address are added to the ARP cache.  When a UDP
+message is sent to a remote IP address that does not already appear in the ARP
+cache then the UDP message is replaced by a ARP message that solicits the
+required MAC address information.  ipconfigARP_CACHE_ENTRIES defines the maximum
+number of entries that can exist in the ARP table at any one time. */
+#define ipconfigARP_CACHE_ENTRIES		6
+
+/* ARP requests that do not result in an ARP response will be re-transmitted a
+maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is
+aborted. */
+#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 )
+
+/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP
+table being created or refreshed and the entry being removed because it is stale.
+New ARP requests are sent for ARP cache entries that are nearing their maximum
+age.  ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is
+equal to 1500 seconds (or 25 minutes). */
+#define ipconfigMAX_ARP_AGE			150
+
+/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling
+routines, which are relatively large.  To save code space the full
+FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster
+alternative called FreeRTOS_inet_addr_quick() is provided.  FreeRTOS_inet_addr()
+takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter.
+FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets
+(for example, 192, 168, 0, 1) as its parameters.  If
+ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and
+FreeRTOS_indet_addr_quick() are available.  If ipconfigINCLUDE_FULL_INET_ADDR is
+not set to 1 then only FreeRTOS_indet_addr_quick() is available. */
+#define ipconfigINCLUDE_FULL_INET_ADDR	1
+
+/* ipconfigNUM_NETWORK_BUFFERS defines the total number of network buffer that
+are available to the IP stack.  The total number of network buffers is limited
+to ensure the total amount of RAM that can be consumed by the IP stack is capped
+to a pre-determinable value. */
+#define ipconfigNUM_NETWORK_BUFFERS		10
+
+/* A FreeRTOS queue is used to send events from application tasks to the IP
+stack.  ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can
+be queued for processing at any one time.  The event queue must be a minimum of
+5 greater than the total number of network buffers. */
+#define ipconfigEVENT_QUEUE_LENGTH		( ipconfigNUM_NETWORK_BUFFERS + 5 )
+
+/* The address of a socket is the combination of its IP address and its port
+number.  FreeRTOS_bind() is used to manually allocate a port number to a socket
+(to 'bind' the socket to a port), but manual binding is not normally necessary
+for client sockets (those sockets that initiate outgoing connections rather than
+wait for incoming connections on a known port number).  If
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling
+FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP
+stack automatically binding the socket to a port number from the range
+socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff.  If
+ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto()
+on a socket that has not yet been bound will result in the send operation being
+aborted. */
+#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1
+
+/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */
+#define updconfigIP_TIME_TO_LIVE		128
+
+/* If ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is set to 1 then UDP packets that
+contain more data than will fit in a single network frame will be fragmented
+across multiple IP packets.  Also see the ipconfigNETWORK_MTU setting.  If
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
+be divisible by 8.  Setting ipconfigCAN_FRAGMENT_OUTGOING_PACKETS to 1 will
+increase both the code size and execution time. */
+#define ipconfigCAN_FRAGMENT_OUTGOING_PACKETS 0
+
+/* The MTU is the maximum number of bytes the payload of a network frame can
+contain.  For normal Ethernet V2 frames the maximum MTU is 1500.  Setting a
+lower value can save RAM, depending on the buffer management scheme used.  If
+ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must
+be divisible by 8. */
+#define ipconfigNETWORK_MTU 586
+
+/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver.  DNS is used
+through the FreeRTOS_gethostbyname() API function. */
+#define ipconfigUSE_DNS		1
+
+/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will
+generate replies to incoming ICMP echo (ping) requests. */
+#define ipconfigREPLY_TO_INCOMING_PINGS				1
+
+/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the
+FreeRTOS_SendPingRequest() API function is available. */
+#define ipconfigSUPPORT_OUTGOING_PINGS				1
+
+/* Used for stack testing only, and must be implemented in the network
+interface. */
+#define updconfigLOOPBACK_ETHERNET_PACKETS	0
+
+/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames
+that are not in Ethernet II format will be dropped.  This option is included for
+potential future IP stack developments. */
+#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1
+
+/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the
+responsibility of the Ethernet interface to filter out packets that are of no
+interest.  If the Ethernet interface does not implement this functionality, then
+set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack
+perform the filtering instead (it is much less efficient for the stack to do it
+because the packet will already have been passed into the stack).  If the
+Ethernet driver does all the necessary filtering in hardware then software
+filtering can be removed by using a value other than 1 or 0. */
+#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES	2
+
+/* The example IP trace macros are included here so the definitions are
+available in all the FreeRTOS+UDP source files. */
+#include "DemoIPTrace.h"
+
+#endif /* FREERTOS_IP_CONFIG_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/LEDs.c

@@ -0,0 +1,136 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Simple LED IO functions.  LED 0 is toggled by a timer every half second. */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "timers.h"
+
+/* Library includes. */
+#include "lpc18xx_gpio.h"
+#include "lpc18xx_scu.h"
+#include "lpc18xx_cgu.h"
+
+#define ledTOGGLE_RATE	( 500 / portTICK_RATE_MS )
+
+#define ledLED0_PORT	1
+#define ledLED0_BIT		( 1UL << 11UL )
+
+#define ledLED1_PORT	2
+#define ledLED1_BIT		( 1UL << 12UL )
+
+/*
+ * Toggles an LED just to show the application is running.
+ */
+static void prvLEDToggleTimerCallback( xTimerHandle xTimer );
+
+/*-----------------------------------------------------------*/
+
+void vLEDsInitialise( void )
+{
+static xTimerHandle xLEDToggleTimer = NULL;
+
+	/* Set the LED pin-muxing and configure as output. */
+	scu_pinmux( 0x2 , 11, MD_PUP, FUNC0 );
+	scu_pinmux( 0x2 , 12, MD_PUP, FUNC0 );
+	GPIO_SetDir( ledLED0_PORT, ledLED0_BIT, 1 );
+	GPIO_SetDir( ledLED1_PORT, ledLED1_BIT, 1 );
+
+    /* Create the timer used to toggle LED0. */
+	xLEDToggleTimer = xTimerCreate(	( const int8_t * ) "LEDTmr", 	/* Just a text name to associate with the timer, useful for debugging, but not used by the kernel. */
+								ledTOGGLE_RATE,						/* The period of the timer. */
+								pdTRUE,								/* This timer will autoreload, so uxAutoReload is set to pdTRUE. */
+								NULL,								/* The timer ID is not used, so can be set to NULL. */
+								prvLEDToggleTimerCallback );		/* The callback function executed each time the timer expires. */
+
+    /* Sanity check that the timer was actually created. */
+    configASSERT( xLEDToggleTimer );
+
+    /* Start the timer.  If this is called before the scheduler is started then
+    the block time will automatically get changed to 0 (from portMAX_DELAY). */
+    xTimerStart( xLEDToggleTimer, portMAX_DELAY );
+}
+/*-----------------------------------------------------------*/
+
+static void prvLEDToggleTimerCallback( xTimerHandle xTimer )
+{
+static uint8_t ucState = 0;
+
+	/* Remove compiler warnings. */
+	( void ) xTimer;
+
+	/* Just toggle an LED to show the program is running. */
+	if( ucState == 0 )
+	{
+		GPIO_SetValue( ledLED0_PORT, ledLED0_BIT );
+	}
+	else
+	{
+		GPIO_ClearValue( ledLED0_PORT, ledLED0_BIT );
+	}
+
+	ucState = !ucState;
+}
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/README_FIRST.txt

@@ -0,0 +1,11 @@
+This demo is documented on the following web page:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/Embedded_Ethernet_Examples/RTOS_UDP_and_CLI_LPC1830_NGX.shtml
+
+The FreeRTOS+UDP API is documented on the following web page:
+http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/FreeRTOS_UDP_API_Functions.shtml
+
+Other information, including a FreeRTOS+UDP primer, a description of the 
+directory structure, and a glossary of networking terminology, can be found in 
+the FreeRTOS+UDP portal:
+http://www.FreeRTOS.org/udp
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/RunTimeStatsTimer.c

@@ -0,0 +1,135 @@
+/*
+    FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>! a combined work that includes FreeRTOS without being obliged to provide
+    >>! the source code for proprietary components outside of the FreeRTOS
+    >>! kernel.
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+
+/* Utility functions to implement run time stats on Cortex-M CPUs.  The collected
+run time data can be viewed through the CLI interface.  See the following URL for
+more information on run time stats:
+http://www.freertos.org/rtos-run-time-stats.html */
+
+/* Addresses of registers in the Cortex-M debug hardware. */
+#define rtsDWT_CYCCNT 			( *( ( unsigned long * ) 0xE0001004 ) )
+#define rtsDWT_CONTROL 			( *( ( unsigned long * ) 0xE0001000 ) )
+#define rtsSCB_DEMCR 			( *( ( unsigned long * ) 0xE000EDFC ) )
+#define rtsTRCENA_BIT			( 0x01000000UL )
+#define rtsCOUNTER_ENABLE_BIT	( 0x01UL )
+
+/* Simple shift divide for scaling to avoid an overflow occurring too soon.  The
+number of bits to shift depends on the clock speed. */
+#define runtimeSLOWER_CLOCK_SPEEDS	( 70000000UL )
+#define runtimeSHIFT_13				13
+#define runtimeOVERFLOW_BIT_13		( 1UL << ( 32UL - runtimeSHIFT_13 ) )
+#define runtimeSHIFT_14				14
+#define runtimeOVERFLOW_BIT_14		( 1UL << ( 32UL - runtimeSHIFT_14 ) )
+
+/*-----------------------------------------------------------*/
+
+void vMainConfigureTimerForRunTimeStats( void )
+{
+	/* Enable TRCENA. */
+	rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
+
+	/* Reset counter. */
+	rtsDWT_CYCCNT = 0;
+
+	/* Enable counter. */
+	rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulMainGetRunTimeCounterValue( void )
+{
+static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
+unsigned long ulValueNow;
+
+	ulValueNow = rtsDWT_CYCCNT;
+
+	/* Has the value overflowed since it was last read. */
+	if( ulValueNow < ulLastCounterValue )
+	{
+		ulOverflows++;
+	}
+	ulLastCounterValue = ulValueNow;
+
+	/* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant
+	but instead map to a variable that holds the clock speed. */
+
+	/* There is no prescale on the counter, so simulate in software. */
+	if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS )
+	{
+		ulValueNow >>= runtimeSHIFT_13;
+		ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows );
+	}
+	else
+	{
+		ulValueNow >>= runtimeSHIFT_14;
+		ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows );
+	}
+
+	return ulValueNow;
+}
+/*-----------------------------------------------------------*/
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_cmsis/cmsis_readme.txt

@@ -0,0 +1,44 @@
+CMSIS : Cortex Microcontroller Software Interface Standard
+==========================================================
+
+Introduction
+~~~~~~~~~~~~
+CMSIS defines for a Cortex-M Microcontroller System:
+
+    * A common way to access peripheral registers and a 
+      common way to define exception vectors.
+    * The register names of the Core Peripherals and the 
+      names of the Core Exception Vectors.
+    * An device independent interface for RTOS Kernels 
+      including a debug channel.
+
+By using CMSIS compliant software components, the user can 
+easier re-use template code. CMSIS is intended to enable the
+combination of software components from multiple middleware 
+vendors. 
+
+This project contains appropriate files for this MCU family 
+taken from CMSIS. A full copy of the CMSIS files, together
+with additional information on CMSIS can be found at:
+
+  http://www.onarm.com/
+  http://www.arm.com/
+
+Documentation
+~~~~~~~~~~~~~
+The standard CMSIS documentation can be found within the
+Code Red IDE help system, via:
+
+Help -> Help Contents -> Code Red Product Documentation -> CMSIS
+
+More information on the use of CMSIS within the Code Red IDE
+can be found in the Support area of the Code Red website at
+
+  http://www.code-red-tech.com/
+
+At the time of writing, the CMSIS FAQ can be found directly
+at:
+
+  http://support.code-red-tech.com/CodeRedWiki/Support4CMSIS
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/LPC1800CMSIS_ReleaseNotes.txt

@@ -0,0 +1,325 @@
+RELEASE CMSIS for REV A 20111209
+1/ New LPC18xx.h header file. Changes GPIO structure.
+2/ Addition of lpc18xx_emc.c and lpc18xx_emc.h to configure memory on Hitex board.
+3/ Addition of spifi_rom_api.h, spifi_drv_M3.lib and SPIFI_ROM_support.doc SPIFI driver package
+4/ Updated SPIFI programming driver for Keil MDK which uses the SPIFI lib
+5/ New BOOTFAST example shows how to boot from external flash or QSPI and ramp to 180 MHz
+
+RELEASE CMSIS for REV A 20111130
+1./ lpc18xx_lcd.h LCD_CFG_type add member pcd, lpc18xx_lcd.c add init pcd in LCD_Init function
+2./ protect MAX and MIN macro in lpc_types.h
+3./ Add getPC function to ARM,GNU, IAR startup_lpc18xx.s
+4./ Add VTOR init in SystemInit function
+5./ Change All ADC examples to use ADC port 0
+6./ These example: CortexM3_Mpu, Pwr_DeepPowerDown, Timer_FreqMeasure, SCT_SimpleMatch and all USBDEV_ROM examples Keil project was adjusted
+7./ SDRAM example and LCD example was changed not to use uint64_t in NS2CLK function
+8./ Nvic_VectorTableRelocation.c
+removed: 
+#if __RAM_MODE__//Run in RAM mode
+  memcpy((void *)VTOR_OFFSET, (const void *)0x10000000, 256*4);
+#else
+  memcpy((void *)VTOR_OFFSET, (const void *)0x1C000000, 256*4);
+#endif
+
+added:
+memcpy((void *)VTOR_OFFSET, (const void *)(getPC()& 0xFF000000), 256*4);
+9./ Pwr_PowerDown change method for testing this feature
+
+
+RELEASE CMSIS for REV A 20111028
+1./ Add GNU support
+2./ Addition of new Keil flash drivers for eFlash and SPIFI
+3./ Change of Keil projects to support eFlash and SPIFI operation
+
+PRE-RELEASE CMSIS for REV A 20111011
+1/ PowerDown Example IAR issue fixed
+2/ Upgraded CMSIS to version 2.10
+3/ Upgraded Core header to Rev A
+4/ lpc18xx_can.h remove all bitrates from 8Mhz, add bitrates from 12Mhz
+	/** Bitrate: 100K */
+	#define CAN_BITRATE100K12MHZ           0x00004509
+	/** Bitrate: 125K */
+	#define CAN_BITRATE125K12MHZ           0x00004507
+	/** Bitrate: 250K */
+	#define CAN_BITRATE250K12MHZ           0x00004503
+	/** Bitrate: 500K */
+	#define CAN_BITRATE500K12MHZ            0x00004501
+	/** Bitrate: 1000K */
+	#define CAN_BITRATE1000K12MHZ          0x00004500
+5./ lpc18xx_cgu.* add PLL audio clock, modify alloc connect table and CGU_Entity_ControlReg_Offset
+6./ lpc18xx_evrt.h
+	add EVRT_SRC_SDIO
+7./ lpc18xx_i2s.h separate LPC_I2S0 and LPC_I2S1
+8./ lpc18xx_scu.h
+	redefine, add pin modes and add pin functions 4->7
+9./ debug_frmwrk.c
+	changed pin mode for UART RXD0 and UART RXD1
+10./ lpc_can.c replace LPC_CAN by LPC_CAN0
+11./ lpc18xx_i2c.* replace i2c pin configurations
+12./ lpc18xx_ssp.c down default clock speed to 100kHz
+13./ Examples\CCAN\CCan_SimpleTxRx\CCan_SimpleTxRx.c change RD pin mode to enable input buffer
+14./ Examples\EMAC\Emac_EasyWeb\emac.c
+		replace MII and RMII pin setting by source from CodeBundle
+15./ Examples\EMC\Emc_Sdram\SDRAM_Init.c and Examples\EMC\Emc_NorFlash\SST39VF320.c
+		replace EMC pin setting to be compatible with Rev A
+16./ Examples\I2S\I2s_Audio\I2s_Audio.c
+		replace I2S pin setting to be compatible with Rev A
+		replace I2S to I2S0
+17./ Examples\LCD\Lcd_Demo\IS42S16400D.c
+		replace EMC pin setting to be compatible with Rev A
+18./ Examples\SSP\All SSP examples: replace SSP pin setting to be compatible with Rev A
+19./ Timer_Capture and Timer_FreqMeasure: replace Capture input pin setting to be compatible with Rev A
+20./ Examples\UART\All UART examples: replace UART pin setting to be compatible with Rev A
+21./ Examples\USBDEV\USB_*\usbhw.c
+		replace USB pin setting to be compatible with Rev A
+		correct clock in Init function
+
+RELEASE: LPC1800CMSIS_20110829
+1./ Add GNU Support
+modify pasting in can.c to be compatible with GCC
+
+RELEASE: LPC1800CMSIS_20110729
+1./ IAR flash support is moved to Tools folder
+2./ ADC.h fixed macro ADC_CR_BITACC
+3./ I2S.h fixed comment
+	from #endif /* LPC17XX_SSP_H_ */
+	to #endif /* LPC18XX_I2S_H_ */
+4./ ADC.c fix ADC_Init Clock by rounding clk div value
+5./ i2s.c fixed some comment
+6./ EMC Nor Flash renamed file  flash programing function
+7./ SDRAM can run at MAX EMC Speed
+8./ Removed flash programing support for LHF00L28
+
+RELEASE: LPC1800CMSIS_20110627
+1./ Fix abstract
+2./ Fix I2S FreqConfig mistake
+3./ Add DFU Driver and App
+
+
+RELEASE: LPC1800CMSIS_20110613
+1./ Add DSP Document
+2./ Speed Up External FLash Mode
+3./ Add IAR Flash Support
+4./ Fix GPDMA Flash transfer issue in IAR
+5./ Set default taget is EXFLASH(Keil only)
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110603
+1./ Add DSP_lib into Core folder
+2./ Update core_cmFunc.h and core_cmInstr.h for solving conflict with IAR EWARM version 6.20 or later
+3./ add IAR startup file and IAR support files in Core\DeviceSupport\NXP\LPC18xx
+4./ Modify SystemInit function to support RAM mode
+	#if (__RAM_MODE__)
+    	SCB->VTOR = 0x10000000;
+	#endif
+5./ Modify CCU1 and CCU2 struct in LPC18xx.h
+6./ Fix bug in uart_set_divisors function
+7./ Change UART clock source from XTAL to PLL1 in uart driver
+8./ Fix RTC bugs
+9./ Modify lpc18xx_GPDMA.c to support IAR compiler
+10./ Modify lpc18xx_cgu.c to support IAR compiler
+11./ Update lpc_types.h to support IAR compiler
+12./ Fix bugs in I2S driver
+13./ Remove Warnings
+14./ Change new header, add more comments
+15./ Standalize example, project, output names
+16./ Support IAR EWARM (RAM mode)
+17./ SUpport Hitex Board as default
+18./ Modify hardware configuration in abstract files
+19./ Set default Target to RAM mode
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110514
+1./ Change all Keil example projects from device Cortex M3 to LPC1850
+2./ change all examples to support Hitex board only
+3./ Verify all project option
+4./ separated CGU and PWR into 2 independent drivers
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110421
+1./ Add CAN driver:
+	Drivers/include/lpc18xx_can.h
+	Drivers/source/lpc18xx_can.c
+
+2./ Add CAN example for simple Transceiver
+	Examples\C_CAN\simpleTxRx
+
+3./ Add 4 USB Rom examples:
+	USB_DFU
+	USB_HID
+	USB_MassStorage
+	USB_Composite
+
+4./ Enable _printf function
+	debug_frmwrk.h:
+		uncomment _printf function declaration
+	debug_frmwrk.c:
+		uncomment _printf function
+
+************************************************************************************************************************************************
+RELEASE: LPC1800CMSIS_20110401
+
+1./ Change all Keil example proiects from device NXP LPC1768 to ARM Cortex-M3
+
+2./ Fix bug in I2C driver (customer feedback)
+	Problem description: 
+		I2C_MasterTransferData() is not able to 
+		(1) Send, 
+		(2) doing a repeated Start and 
+		(3) starting to receive with one function call. 
+		Problem is that the repeated start is not generated, but a retransmission of the 
+		last word is startet. 
+	Solve: change 
+		I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; 
+		I2Cx->I2CONSET = I2C_I2CONSET_STA; 
+	to 
+		I2Cx->I2CONSET = I2C_I2CONSET_STA; 
+		I2Cx->I2CONCLR = I2C_I2CONCLR_SIC; 
+		in function I2C_Start ()
+
+3./ lpc18xx_timer.c:
+	Function TIM_ClearIntPending():
+		Change TIMx->IR |= TIM_IR_CLR(IntFlag);
+		To     TIMx->IR = TIM_IR_CLR(IntFlag);
+	Function TIM_ClearIntCapturePending():
+		Change TIMx->IR |= (1<<(4+IntFlag));
+		To     TIMx->IR = (1<<(4+IntFlag));
+	Function TIM_GetCaptureValue(): 
+		Add return 0;
+
+4./ EMC - Nor Flash: remove example build target for FLASH mode as it only can run in RAM mode.
+
+5./ SCT: update Fizzim tool to version 1.1
+
+6./ Tools:
+	Update Flash burning for LHF00L28 and SST39X320X
+
+************************************************************************************************************************************************
+
+RELEASE: LPC1800CMSIS_20110324
+
+1./ Current support hardwares:
+	- NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
+	- Hitex LPC1800 Board through definition 'BOARD_HITEX_LPC1800'
+    Some examples can run on LPC1800 Evaluation board, some can run on Hitex board...Please refer to abstract.txt
+
+2./ Addin new flash support under Tools/Flash/SST39X320X
+
+3./ lpc18xx_evrt.c:
+	Change EVRTx->SET_EN |= (1<<(uint8_t)EVRT_Src);
+	To     EVRTx->SET_EN = (1<<(uint8_t)EVRT_Src);
+	Purpose: prevent clearing other set bits as writing '0' has no effect
+
+4./ Fix ATIMER_WIC example:
+	- Configure 32KHZ osc in lpc18xx_atimer.c
+	- Call the configuration function in atimer_wic.c
+
+5./ Fix RTC_Alarm example:
+	- Configure 32KHZ osc in lpc18xx_rtc.c
+	- Update Rtc_Alarm.c
+
+6./ Add in PWR_PowerDown example
+
+7./ Add in PWR_DeepPowerDown example
+
+8./ All example in PWR are modified to wait for '1' sent from PC's COM port to start
+
+9./ Fix LCD Logic4.3 example to run on Hitex LPC1800 Board
+
+10./ Add in GPDMA Flash_2_Ram_Test example
+
+11./ EMC EXT_SDRAM example: join IS42S16400D.c and MT48LC4M32B2.c into SDRAM_Init.c
+
+12./ lpc18xx_i2s.c: update I2S_FreqConfig() function
+
+************************************************************************************************************************************************
+
+RELEASE: LPC1800CMSIS_20110311
+
+1./ This package is compliant to CMSIS 2.0
+
+2./ Add in 'Tools' folder which contains neccessary material for building project, examples like flash burning,..
+
+3./ Examples are given in Keil uVision 4 project
+
+4./ Current support hardwares:
+	- NXP LPC1800 Evaluation board through definition 'BOARD_NXP_EA'
+
+5./ Examples can run:
+	- RAM (debug) mode
+	- ROM (Flash, stand alone) mode
+		+ External Nor Flash. Flash Part supporting:
+			1) LHF00L28
+
+6./ Each example folder has an 'abstract.txt' file, this is where user can start
+
+7./ Below is list of drivers and examples:
+	- ADC (lpc18xx_adc):
+		+ ADC_Interrupt
+		+ ADC_Polling
+		+ ADC_Burst
+		+ ADC_Dma
+	- ATIMER (lpc18xx_atimer):
+		+ ATIMER_interrupt
+	- PWR (lpc18xx_clkpwr):
+		+ CLKPWR_Sleep
+		+ CLKPWR_DeepSleep
+	- DAC (lpc18xx_dac):
+		+ DAC_WaveGenerator
+		+ DAC_Dma
+	- EMAC (lpc18xx_emac):
+		+ EMAC_EasyWeb
+	- EMC (no driver):
+		+ EXT_SDRAM
+		+ NOR_FLASH
+	- GPDMA (lpc18xx_gpdma):
+		+ GPDMA_Ram2Ram
+		+ GPDMA_LinkList
+	- GPIO (lpc18xx_gpio):
+		+ GPIO_LedBlinky
+	- I2C (lpc18xx_i2c):
+		+ I2C_Master
+	- I2S (lpc18xx_i2s):
+		+ I2S_Audio
+	- LCD (lpc18xx_lcd)
+	- MCPWM (lpc18xx_mcpwm):
+		+ MCPWM_Simple
+	- SCU (lpc18xx_scu)
+	- QEI (lpc18xx_qei):
+		+ QEI_Velo
+	- RIT (lpc18xx_rit):
+		+ RIT_Interrupt
+	- RTC (lpc18xx_rtc):
+		+ RTC_Calib
+		+ RTC_Alarm
+	- SSP (lpc18xx_ssp):
+		+ SSP_SPI
+		+ SSP_Microwire
+		+ SSP_TI
+	- TIMER (lpc18xx_timer):
+		+ TIMER_Capture
+		+ TIMER_MatchInterrupt
+		+ TIMER_FreqMeasure
+	- UART (lpc18xx_uart):
+		+ UART_Autobaud
+		+ UART_Dma
+		+ UART_Interrupt
+		+ UART_Polling
+		+ UART_RS485
+	- SCT(LPC18xx_SCT):
+		+ SCT_Capture
+		+ SCT_Match
+	- WWDT (lpc18xx_wwdt):
+		+ WWDT_Interrupt
+	- CORTEXM3 (no driver):
+		+ CORTEXM3_BitBanding
+		+ CORTEXM3_MPU
+		+ CORTEXM3_PriviledgeMode
+	- USBDEV (no driver):
+		+ USBDEV_VirtualCOM
+		+ USBDEV_MassStorage
+	- NVIC (no driver):
+		+ NVIC_Priority
+		+ NVIC_VecRelocation
+	- EVRT (lpc18xx_evrt)
+		

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/docs_nxp_driverlib/readme.txt

@@ -0,0 +1,9 @@
+NXP's documentation for their peripheral driver library can be found
+as a Microsoft Compiled HTML Help file (.chm) within the LPC18xx 
+CMSIS Standard Peripheral Driver Library download on NXP's website.
+
+At the time of writing, this can be found at the following link:
+
+http://lpcware.com/file_filter/nxp?term_node_tid_depth=All&term_node_tid_depth_1=103
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmFunc.h

@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/core_cmInstr.h

@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/debug_frmwrk.h

@@ -0,0 +1,90 @@
+/**********************************************************************
+* $Id$		debug_frmwrk.h			2011-06-02
+*//**
+* @file		debug_frmwrk.h
+* @brief	Contains some utilities that used for debugging through UART
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup DEBUG_FRMWRK DEBUG FRAMEWORK
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef DEBUG_FRMWRK_H_
+#define DEBUG_FRMWRK_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc18xx_uart.h"
+
+#define VCOM_DEBUG_MESSEGES
+//#define UART_DEBUG_MESSEGES
+
+#define USED_UART_DEBUG_PORT	1
+
+#if (USED_UART_DEBUG_PORT==0)
+#define DEBUG_UART_PORT	LPC_UART0
+#elif (USED_UART_DEBUG_PORT==1)
+#define DEBUG_UART_PORT	LPC_UART1
+#endif
+
+#define _DBG(x)	 	_db_msg((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBG_(x)	_db_msg_((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBC(x)	 	_db_char((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBD(x)	 	_db_dec((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBD16(x)	 _db_dec_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBD32(x)	 _db_dec_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBH(x)	 	_db_hex((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBH16(x)	 _db_hex_16((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DBH32(x)	 _db_hex_32((LPC_USARTn_Type*)DEBUG_UART_PORT, x)
+#define _DG			_db_get_char((LPC_USARTn_Type*)DEBUG_UART_PORT)
+void  lpc_printf (const  char *format, ...);
+
+extern void (*_db_msg)(LPC_USARTn_Type *UARTx, const void *s);
+extern void (*_db_msg_)(LPC_USARTn_Type *UARTx, const void *s);
+extern void (*_db_char)(LPC_USARTn_Type *UARTx, uint8_t ch);
+extern void (*_db_dec)(LPC_USARTn_Type *UARTx, uint8_t decn);
+extern void (*_db_dec_16)(LPC_USARTn_Type *UARTx, uint16_t decn);
+extern void (*_db_dec_32)(LPC_USARTn_Type *UARTx, uint32_t decn);
+extern void (*_db_hex)(LPC_USARTn_Type *UARTx, uint8_t hexn);
+extern void (*_db_hex_16)(LPC_USARTn_Type *UARTx, uint16_t hexn);
+extern void (*_db_hex_32)(LPC_USARTn_Type *UARTx, uint32_t hexn);
+extern uint8_t (*_db_get_char)(LPC_USARTn_Type *UARTx);
+
+void UARTPutChar (LPC_USARTn_Type *UARTx, uint8_t ch);
+void UARTPuts(LPC_USARTn_Type *UARTx, const void *str);
+void UARTPuts_(LPC_USARTn_Type *UARTx, const void *str);
+void UARTPutDec(LPC_USARTn_Type *UARTx, uint8_t decnum);
+void UARTPutDec16(LPC_USARTn_Type *UARTx, uint16_t decnum);
+void UARTPutDec32(LPC_USARTn_Type *UARTx, uint32_t decnum);
+void UARTPutHex (LPC_USARTn_Type *UARTx, uint8_t hexnum);
+void UARTPutHex16 (LPC_USARTn_Type *UARTx, uint16_t hexnum);
+void UARTPutHex32 (LPC_USARTn_Type *UARTx, uint32_t hexnum);
+uint8_t UARTGetChar (LPC_USARTn_Type *UARTx);
+void debug_frmwrk_init(void);
+
+#endif /* DEBUG_FRMWRK_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_adc.h

@@ -0,0 +1,295 @@
+/**********************************************************************
+* $Id$		lpc18xx_adc.h			2011-06-02
+*//**
+* @file		lpc18xx_adc.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for ADC firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup ADC ADC (Analog to Digital Converter)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_ADC_H_
+#define LPC18XX_ADC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/* -------------------------- BIT DEFINITIONS ----------------------------------- */
+/*********************************************************************//**
+ * Macro defines for ADC  control register
+ **********************************************************************/
+/**  Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CH_SEL(n)	((1UL << n))
+/**  The APB clock (PCLK) is divided by (this value plus one)
+* to produce the clock for the A/D */
+#define ADC_CR_CLKDIV(n)	((n<<8))
+/**  Repeated conversions A/D enable bit */
+#define ADC_CR_BURST		((1UL<<16))
+/**  number of accuracy bits */
+#define ADC_CR_BITACC(n)	(((n)<<17))
+/**  ADC convert in power down mode */
+#define ADC_CR_PDN			((1UL<<21))
+/**  Start mask bits */
+#define ADC_CR_START_MASK	((7UL<<24))
+/**  Select Start Mode */
+#define ADC_CR_START_MODE_SEL(SEL)	((SEL<<24))
+/**  Start conversion now */
+#define ADC_CR_START_NOW		((1UL<<24))
+/**  Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
+#define ADC_CR_START_CTOUT15	((2UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
+#define ADC_CR_START_CTOUT8		((3UL<<24))
+/**  Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
+#define ADC_CR_START_ADCTRIG0	((4UL<<24))
+/**  Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
+#define ADC_CR_START_ADCTRIG1	((5UL<<24))
+/**  Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
+#define ADC_CR_START_MCOA2		((6UL<<24))
+/**  Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_CR_EDGE			((1UL<<27))
+
+/*********************************************************************//**
+ * Macro defines for ADC Global Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_GDR_RESULT(n)		(((n>>4)&0xFFF))
+/** These bits contain the channel from which the LS bits were converted */
+#define ADC_GDR_CH(n)			(((n>>24)&0x7))
+/** This bit is 1 in burst mode if the results of one or
+ * more conversions was (were) lost */
+#define ADC_GDR_OVERRUN_FLAG	((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes */
+#define ADC_GDR_DONE_FLAG		((1UL<<31))
+
+/** This bits is used to mask for Channel */
+#define ADC_GDR_CH_MASK		((7UL<<24))
+/*********************************************************************//**
+ * Macro defines for ADC Interrupt register
+ **********************************************************************/
+/** These bits allow control over which A/D channels generate
+ * interrupts for conversion completion */
+#define ADC_INTEN_CH(n)			((1UL<<n))
+/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
+#define ADC_INTEN_GLOBAL		((1UL<<8))
+
+/*********************************************************************//**
+ * Macro defines for ADC Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_DR_RESULT(n)		(((n>>6)&0x3FF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_DR_OVERRUN_FLAG		((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes. It is cleared
+ * when this register is read */
+#define ADC_DR_DONE_FLAG		((1UL<<31))
+
+/*********************************************************************//**
+ * Macro defines for ADC Status register
+**********************************************************************/
+/** These bits mirror the DONE status flags that appear in the result
+ * register for each A/D channel */
+#define ADC_STAT_CH_DONE_FLAG(n)		((n&0xFF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_STAT_CH_OVERRUN_FLAG(n)		(((n>>8)&0xFF))
+/** This bit is the A/D interrupt flag */
+#define ADC_STAT_INT_FLAG				((1UL<<16))
+
+/*********************************************************************//**
+ * Macro defines for ADC Trim register
+**********************************************************************/
+/** Offset trim bits for ADC operation */
+#define ADC_ADCOFFS(n)		(((n&0xF)<<4))
+/** Written to boot code*/
+#define ADC_TRIM(n)		    (((n&0xF)<<8))
+
+/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
+/** Check ADC parameter */
+#define PARAM_ADCx(n)    (((uint32_t *)n)==((uint32_t *)LPC_ADC0) || ((uint32_t *)n)==((uint32_t *)LPC_ADC1))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_START_ON_EDGE_OPT(OPT)    ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_DATA_STATUS(OPT)    ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
+
+/** Check ADC rate parameter */
+#define PARAM_ADC_RATE(rate)	((rate>0)&&(rate<=200000))
+
+/** Check ADC bits accuracy parameter */
+#define PARAM_ADC_BITSACC(x)	((x>=3)&&(x<=10))
+
+/** Check ADC channel selection parameter */
+#define PARAM_ADC_CHANNEL_SELECTION(SEL)	((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
+||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
+||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
+||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
+
+/** Check ADC start option parameter */
+#define PARAM_ADC_START_OPT(OPT)    ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
+||(OPT == ADC_START_ON_CTOUT15)||(OPT == ADC_START_ON_CTOUT8)\
+||(OPT == ADC_START_ON_ADCTRIG0)||(OPT == ADC_START_ON_ADCTRIG1)\
+||(OPT == ADC_START_ON_MCOA2))
+
+/** Check ADC interrupt type parameter */
+#define PARAM_ADC_TYPE_INT_OPT(OPT)    ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
+||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
+||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
+||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
+||(OPT == ADC_ADGINTEN))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup ADC_Public_Types ADC Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief ADC enumeration
+ **********************************************************************/
+/** @brief Channel Selection */
+typedef enum
+{
+	ADC_CHANNEL_0  = 0, /*!<  Channel 0 */
+	ADC_CHANNEL_1,		/*!<  Channel 1 */
+	ADC_CHANNEL_2,		/*!<  Channel 2 */
+	ADC_CHANNEL_3,		/*!<  Channel 3 */
+	ADC_CHANNEL_4,		/*!<  Channel 4 */
+	ADC_CHANNEL_5,		/*!<  Channel 5 */
+	ADC_CHANNEL_6,		/*!<  Channel 6 */
+	ADC_CHANNEL_7		/*!<  Channel 7 */
+}ADC_CHANNEL_SELECTION;
+
+/** @brief Type of start option */
+typedef enum
+{
+	ADC_START_CONTINUOUS =0,	/*!< Continuous mode */
+	ADC_START_NOW,				/*!< Start conversion now */
+	ADC_START_ON_CTOUT15,			/*!< Start conversion when the edge selected
+								 * by bit 27 occurs on CTOUT_15 */
+	ADC_START_ON_CTOUT8,			/*!< Start conversion when the edge selected
+								 * by bit 27 occurs on CTOUT_8 */
+	ADC_START_ON_ADCTRIG0,			/*!< Start conversion when the edge selected
+								 * by bit 27 occurs on ADCTRIG0 */
+	ADC_START_ON_ADCTRIG1,			/*!< Start conversion when the edge selected
+								 * by bit 27 occurs on ADCTRIG1 */
+	ADC_START_ON_MCOA2			/*!< Start conversion when the edge selected
+								  * by bit 27 occurs on Motocon PWM output MCOA2 */
+} ADC_START_OPT;
+
+
+/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
+typedef enum
+{
+	ADC_START_ON_RISING = 0,	/*!< Start conversion on a rising edge
+								*on the selected CAP/MAT signal */
+	ADC_START_ON_FALLING		/*!< Start conversion on a falling edge
+								*on the selected CAP/MAT signal */
+} ADC_START_ON_EDGE_OPT;
+
+/** @brief* ADC type interrupt enum */
+typedef enum
+{
+	ADC_ADINTEN0 = 0,		/*!< Interrupt channel 0 */
+	ADC_ADINTEN1,			/*!< Interrupt channel 1 */
+	ADC_ADINTEN2,			/*!< Interrupt channel 2 */
+	ADC_ADINTEN3,			/*!< Interrupt channel 3 */
+	ADC_ADINTEN4,			/*!< Interrupt channel 4 */
+	ADC_ADINTEN5,			/*!< Interrupt channel 5 */
+	ADC_ADINTEN6,			/*!< Interrupt channel 6 */
+	ADC_ADINTEN7,			/*!< Interrupt channel 7 */
+	ADC_ADGINTEN			/*!< Individual channel/global flag done generate an interrupt */
+}ADC_TYPE_INT_OPT;
+
+/** @brief ADC Data  status */
+typedef enum
+{
+	ADC_DATA_BURST = 0,		/*Burst bit*/
+	ADC_DATA_DONE		 /*Done bit*/
+}ADC_DATA_STATUS;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup ADC_Public_Functions ADC Public Functions
+ * @{
+ */
+/* Init/DeInit ADC peripheral ----------------*/
+void ADC_Init(LPC_ADCn_Type *ADCx, uint32_t rate, uint8_t bits_accuracy);
+void ADC_DeInit(LPC_ADCn_Type *ADCx);
+
+/* Enable/Disable ADC functions --------------*/
+void ADC_BurstCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
+void ADC_PowerdownCmd(LPC_ADCn_Type *ADCx, FunctionalState NewState);
+void ADC_StartCmd(LPC_ADCn_Type *ADCx, uint8_t start_mode);
+void ADC_ChannelCmd (LPC_ADCn_Type *ADCx, uint8_t Channel, FunctionalState NewState);
+
+/* Configure ADC functions -------------------*/
+void ADC_EdgeStartConfig(LPC_ADCn_Type *ADCx, uint8_t EdgeOption);
+void ADC_IntConfig (LPC_ADCn_Type *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
+
+/* Get ADC information functions -------------------*/
+uint16_t ADC_ChannelGetData(LPC_ADCn_Type *ADCx, uint8_t channel);
+FlagStatus ADC_ChannelGetStatus(LPC_ADCn_Type *ADCx, uint8_t channel, uint32_t StatusType);
+uint32_t ADC_GlobalGetData(LPC_ADCn_Type *ADCx);
+FlagStatus	ADC_GlobalGetStatus(LPC_ADCn_Type *ADCx, uint32_t StatusType);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC18XX_ADC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_atimer.h

@@ -0,0 +1,93 @@
+/**********************************************************************
+* $Id$		lpc18xx_atimer.h			2011-06-02
+*//**
+* @file		lpc18xx_atimer.h
+* @brief	Contains all functions support for Alarm Timer firmware
+* 			library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup ATIMER ATIMER (Alarm Timer)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC18XX_ATIMER_H_
+#define __LPC18XX_ATIMER_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup ATIMER_Private_Macros ALARM Timer Private Macros
+ * @{
+ */
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid ALARM TIMER peripheral */
+#define PARAM_ATIMERx(n)	(((uint32_t *)n)==((uint32_t *)LPC_ATIMER))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup ATIMER_Public_Functions ATIMER Public Functions
+ * @{
+ */
+
+
+/* Init/DeInit ATIMER functions -----------*/
+void ATIMER_Init(LPC_ATIMER_Type *ATIMERx, uint32_t PresetValue);
+void ATIMER_DeInit(LPC_ATIMER_Type *ATIMERx);
+
+/* ATIMER interrupt functions -------------*/
+void ATIMER_IntEnable(LPC_ATIMER_Type *ATIMERx);
+void ATIMER_IntDisable(LPC_ATIMER_Type *ATIMERx);
+void ATIMER_ClearIntStatus(LPC_ATIMER_Type *ATIMERx);
+void ATIMER_SetIntStatus(LPC_ATIMER_Type *ATIMERx);
+
+/* ATIMER configuration functions --------*/
+void ATIMER_UpdatePresetValue(LPC_ATIMER_Type *ATIMERx,uint32_t PresetValue);
+uint32_t ATIMER_GetPresetValue(LPC_ATIMER_Type *ATIMERx);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC18XX_ATIMER_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_can.h

@@ -0,0 +1,241 @@
+/**********************************************************************
+* $Id$		lpc18xx_can.h			2011-06-02
+*//**
+* @file		lpc18xx_can.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for CAN firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup C_CAN C_CAN (Controller Area Network)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC18XX_CAN_H
+#define __LPC18XX_CAN_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup C_CAN_Public_Macros  C_CAN Public Macros
+ * @{
+ */
+
+/** In BASIC_MODE IF1 registers are used directly as TX buffer, IF2 registers are used as RX buffer.
+ * If not BASIC_MODE use message objects and IF registers to communicate with message buffers
+ */
+#define BASIC_MODE 		0
+
+/** In Silent Mode, the CAN controller is able to receive valid data frames and valid remote
+ * frames, but it sends only recessive bits on the CAN bus, and it cannot start a transmission
+ */
+#define SILENT_MODE		0
+
+/** In Loop-back Mode, the CAN Core treats its own transmitted messages as received messages
+ * and stores them (if they pass acceptance filtering) into a Receive Buffer.
+ */
+#define LOOPBACK_MODE	0
+
+/** Enables receiving remote frame requests */
+#define REMOTE_ENABLE	1
+
+/**
+ * @}
+ */
+
+/* Private Macros -------------------------------------------------------------- */
+/** @defgroup C_CAN_Private_Macros  C_CAN Private Macros
+ * @{
+ */
+
+/** MAX CAN message obj */
+#define CAN_MSG_OBJ_MAX			0x0020
+/** MAX data length */
+#define CAN_DLC_MAX				8
+
+/********************************************************************//**
+ *  BRP+1 = Fpclk/(CANBitRate * QUANTAValue)
+ * QUANTAValue = 1 + (Tseg1+1) + (Tseg2+1)
+ * QUANTA value varies based on the Fpclk and sample point
+ * e.g. (1) sample point is 87.5%, Fpclk is 48Mhz
+ * the QUANTA should be 16
+ * 		(2) sample point is 90%, Fpclk is 12.5Mhz
+ * the QUANTA should be 10
+ * 		 Fpclk = Fclk /APBDIV
+ * or
+ *  BitRate = Fcclk/(APBDIV * (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1))
+ */
+
+/*********************************************************************//**
+ * @brief CAN Bit Timing Values definitions at 8Mhz
+ **********************************************************************/
+/** Bitrate: 100K */
+#define CAN_BITRATE100K12MHZ           0x00004509
+/** Bitrate: 125K */
+#define CAN_BITRATE125K12MHZ           0x00004507
+/** Bitrate: 250K */
+#define CAN_BITRATE250K12MHZ           0x00004503
+/** Bitrate: 500K */
+#define CAN_BITRATE500K12MHZ            0x00004501
+/** Bitrate: 1000K */
+#define CAN_BITRATE1000K12MHZ          0x00004500
+
+/*********************************************************************//**
+ * @brief CAN Bit Timing Values definitions at 16Mhz
+ **********************************************************************/
+/** Bitrate: 100K */
+#define CAN_BITRATE100K16MHZ          0x00005809
+/** Bitrate: 125K */
+#define CAN_BITRATE125K16MHZ          0x00005807
+/** Bitrate: 250K */
+#define CAN_BITRATE250K16MHZ          0x00005803
+/** Bitrate: 500K */
+#define CAN_BITRATE500K16MHZ          0x00005801
+
+
+/*********************************************************************//**
+ * @brief CAN Bit Timing Values definitions at 24Mhz
+ **********************************************************************/
+/** Bitrate: 100K */
+#define CAN_BITRATE100K24MHZ          0x00007E09
+/** Bitrate: 125K */
+#define CAN_BITRATE125K24MHZ          0x0000450F
+/** Bitrate: 250K */
+#define CAN_BITRATE250K24MHZ          0x00004507
+/** Bitrate: 500K */
+#define CAN_BITRATE500K24MHZ          0x00004503
+/** Bitrate: 1000K */
+#define CAN_BITRATE1000K24MHZ         0x00004501
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CAN_Public_Types CAN Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief CAN enumeration
+ **********************************************************************/
+
+/**
+ * @brief CAN interface register type definition
+ */
+typedef enum CCAN_IFREG
+{
+	CMDREQ = 0,				/**< Command request */
+	CMDMSK = 1,				/**< Command mask */
+	MSK1 = 2,				/**< Mask 1 */
+	MSK2 = 3,				/**< Mask 2 */
+	ARB1 = 4,				/**< Arbitration 1 */
+	ARB2 = 5,				/**< Arbitration 2 */
+	MCTRL = 6,				/**< Message control */
+	DA1 = 7,				/**< Data A1 */
+	DA2 = 8,				/**< Data A2 */
+	DB1 = 9,				/**< Data B1 */
+	DB2 = 10				/**< Data B2 */
+}CCAN_IFREG_Type;
+
+/**
+ * @brief CAN Clock division rate type definition
+ */
+typedef enum CCAN_CLKDIV
+{
+	CLKDIV1		= 0,
+	CLKDIV2		= 1,
+	CLKDIV3		= 2,
+	CLKDIV5		= 3,
+	CLKDIV9		= 4,
+	CLKDIV17	= 5,
+	CLKDIV33	= 6,
+	CLKDIV65	= 7
+}CCAN_CLKDIV_Type;
+
+
+/********************************************************************//**
+* @brief Data structure definition for a CAN message
+**********************************************************************/
+/**
+ * @brief CAN message object structure
+ */
+typedef struct
+{
+    uint32_t	id;		/**< ID of message, if bit 30 is set then this is extended frame */
+    uint32_t 	dlc;	/**< Message data length */
+    uint8_t	data[8]; 	/**< Message data */
+} message_object;
+
+/**
+ * @brief CAN call-back function
+ */
+typedef void (*MSG_CB)(uint32_t msg_no);
+
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CAN_Public_Functions CAN Public Functions
+ * @{
+ */
+
+void CAN_IRQHandler (void);
+void CAN_Init( uint32_t BitClk, CCAN_CLKDIV_Type ClkDiv , MSG_CB Tx_cb, MSG_CB Rx_cb);
+
+void CAN_ConfigureRxMessageObjects( void );
+void CAN_RxInt_MessageProcess( uint8_t MsgObjNo );
+void CAN_TxInt_MessageProcess( uint8_t MsgObjNo );
+
+void CAN_Send(uint8_t msg_no, uint32_t *msg_ptr );
+void CAN_Recv(uint8_t msg_no, uint32_t *msg_ptr, Bool RemoteEnable);
+void CAN_ReadMsg(uint32_t msg_no, message_object* buff);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC18XX_CAN_H */
+
+/**
+ * @}
+ */
+/*****************************************************************************
+**                            End Of File
+******************************************************************************/
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_cgu.h

@@ -0,0 +1,271 @@
+/**********************************************************************
+* $Id$		lpc18xx_cgu.h			2011-06-02
+*//**
+* @file		llpc18xx_cgu.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for Clock Generation and Clock Control firmware
+* 			library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CGU CGU (Clock Generation Unit)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_CGU_H_
+#define LPC18XX_CGU_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros -------------------------------------------------------------- */
+/** @defgroup CGU_Private_Macros CGU Private Macros
+ * @{
+ */
+
+/** Branch clocks from CGU_BASE_SAFE */
+#define CGU_ENTITY_NONE				CGU_ENTITY_NUM
+
+/** Check bit at specific position is clear or not */
+#define ISBITCLR(x,bit) 			((x&(1<<bit))^(1<<bit))
+/** Check bit at specific position is set or not */
+#define ISBITSET(x,bit) 			(x&(1<<bit))
+/** Set mask */
+#define ISMASKSET(x,mask) 			(x&mask)
+
+/** CGU number of clock source */
+#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
+
+/*********************************************************************//**
+ * Macro defines for CGU control mask bit definitions
+ **********************************************************************/
+/** CGU control enable mask bit */
+#define CGU_CTRL_EN_MASK			1
+/** CGU control clock-source mask bit */
+#define CGU_CTRL_SRC_MASK			(0xF<<24)
+/** CGU control auto block mask bit */
+#define CGU_CTRL_AUTOBLOCK_MASK		(1<<11)
+
+/*********************************************************************//**
+ * Macro defines for CGU PLL1 mask bit definitions
+ **********************************************************************/
+/** CGU PLL1 feedback select mask bit */
+#define CGU_PLL1_FBSEL_MASK			(1<<6)
+/** CGU PLL1 Input clock bypass control mask bit */
+#define CGU_PLL1_BYPASS_MASK		(1<<1)
+/** CGU PLL1 direct CCO output mask bit */
+#define CGU_PLL1_DIRECT_MASK		(1<<7)
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CGU_Public_Types CGU Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief CGU enumeration
+ **********************************************************************/
+/*
+ * @brief	CGU clock source enumerate definition
+ */
+typedef enum {
+	/* Clock Source */
+	CGU_CLKSRC_32KHZ_OSC = 0,					/**< 32KHz oscillator clock source 	*/
+	CGU_CLKSRC_IRC,								/**< IRC 12 Mhz clock source 		*/
+	CGU_CLKSRC_ENET_RX_CLK,						/**< Ethernet receive clock source 	*/
+	CGU_CLKSRC_ENET_TX_CLK,						/**< Ethernet transmit clock source */
+	CGU_CLKSRC_GP_CLKIN,						/**< General purpose clock source 	*/
+	CGU_CLKSRC_TCK,								/**< TCK clock source 				*/
+	CGU_CLKSRC_XTAL_OSC,						/**< Crystal oscillator clock source*/
+	CGU_CLKSRC_PLL0,							/**< PLL0 (USB0) clock source		*/
+	CGU_CLKSRC_PLL0_AUDIO,
+	CGU_CLKSRC_PLL1,							/**< PLL1 clock source				*/
+	CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3,		/**< IDIVA clock source				*/
+	CGU_CLKSRC_IDIVB,							/**< IDIVB clock source				*/
+	CGU_CLKSRC_IDIVC,							/**< IDIVC clock source				*/
+	CGU_CLKSRC_IDIVD,							/**< IDIVD clock source				*/
+	CGU_CLKSRC_IDIVE,							/**< IDIVE clock source				*/
+
+	/* Base */
+	CGU_BASE_SAFE,								/**< Base save clock (always on) for WDT */
+	CGU_BASE_USB0,								/**< USB0 base clock 				*/
+	CGU_BASE_USB1 = CGU_BASE_USB0 + 2,			/**< USB1 base clock 				*/
+	CGU_BASE_M3,								/**< ARM Cortex-M3 Core base clock 	*/
+	CGU_BASE_SPIFI,								/**< SPIFI base clock				*/
+	//CGU_BASE_SPI,
+	CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2,		/**< Ethernet PHY Rx base clock		*/
+	CGU_BASE_PHY_TX,							/**< Ethernet PHY Tx base clock		*/
+	CGU_BASE_APB1,								/**< APB peripheral block #1 base clock	*/
+	CGU_BASE_APB3,								/**< APB peripheral block #3 base clock	*/
+	CGU_BASE_LCD,								/**< LCD base clock					*/
+	CGU_BASE_ENET_CSR,
+	CGU_BASE_SDIO,								/**< SDIO base clock				*/
+	CGU_BASE_SSP0,								/**< SSP0 base clock				*/
+	CGU_BASE_SSP1,								/**< SSP1 base clock				*/
+	CGU_BASE_UART0,								/**< UART0 base clock				*/
+	CGU_BASE_UART1,								/**< UART1 base clock				*/
+	CGU_BASE_UART2,								/**< UART2 base clock				*/
+	CGU_BASE_UART3,								/**< UART3 base clock				*/
+	CGU_BASE_CLKOUT,							/**< CLKOUT base clock				*/
+	CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
+	CGU_BASE_OUT0,
+	CGU_BASE_OUT1,
+	CGU_ENTITY_NUM								/**< Number or clock source entity	*/
+} CGU_ENTITY_T;
+
+/*
+ * @brief 	CGU PPL0 mode enumerate definition
+ */
+typedef enum {
+	CGU_PLL0_MODE_1d = 0,
+	CGU_PLL0_MODE_1c,
+	CGU_PLL0_MODE_1b,
+	CGU_PLL0_MODE_1a
+}CGU_PLL0_MODE;
+
+/*
+ * @brief 	CGU peripheral enumerate definition
+ */
+typedef enum {
+	CGU_PERIPHERAL_ADC0 = 0,					/**< ADC0 		*/
+	CGU_PERIPHERAL_ADC1,						/**< ADC1 		*/
+	CGU_PERIPHERAL_AES,							/**< AES		*/
+//	CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
+	CGU_PERIPHERAL_APB1_BUS,					/**< APB1 bus			*/
+	CGU_PERIPHERAL_APB3_BUS,					/**< APB3 bus			*/
+	CGU_PERIPHERAL_CAN,							/**< CAN 				*/
+	CGU_PERIPHERAL_CREG,						/**< CREG				*/
+	CGU_PERIPHERAL_DAC,							/**< DAC				*/
+	CGU_PERIPHERAL_DMA,							/**< DMA				*/
+	CGU_PERIPHERAL_EMC,							/**< EMC				*/
+	CGU_PERIPHERAL_ETHERNET,					/**< Ethernet			*/
+	CGU_PERIPHERAL_ETHERNET_TX, //HIDE			/**< Ethernet transmit 	*/
+	CGU_PERIPHERAL_GPIO,						/**< GPIO				*/
+	CGU_PERIPHERAL_I2C0,						/**< I2C0				*/
+	CGU_PERIPHERAL_I2C1,						/**< I2C1				*/
+	CGU_PERIPHERAL_I2S,							/**< I2S				*/
+	CGU_PERIPHERAL_LCD,							/**< LCD				*/
+	CGU_PERIPHERAL_M3CORE,						/**< ARM Cortex-M3 Core	*/
+	CGU_PERIPHERAL_M3_BUS,						/**< ARM Cortex-M3 Bus	*/
+	CGU_PERIPHERAL_MOTOCON,						/**< Motor Control 		*/
+	CGU_PERIPHERAL_QEI,							/**< QEI				*/
+	CGU_PERIPHERAL_RITIMER,						/**< RIT Timer			*/
+	CGU_PERIPHERAL_SCT,							/**< SCT				*/
+	CGU_PERIPHERAL_SCU,							/**< SCU				*/
+	CGU_PERIPHERAL_SDIO,						/**< SDIO				*/
+	CGU_PERIPHERAL_SPIFI,						/**< SPIFI				*/
+	CGU_PERIPHERAL_SSP0,						/**< SSP0				*/
+	CGU_PERIPHERAL_SSP1,						/**< SSP1				*/
+	CGU_PERIPHERAL_TIMER0,						/**< TIMER 0 			*/
+	CGU_PERIPHERAL_TIMER1,						/**< TIMER 1			*/
+	CGU_PERIPHERAL_TIMER2,						/**< TIMER 2			*/
+	CGU_PERIPHERAL_TIMER3,						/**< TIMER 3			*/
+	CGU_PERIPHERAL_UART0,						/**< UART0				*/
+	CGU_PERIPHERAL_UART1,						/**< UART1				*/
+	CGU_PERIPHERAL_UART2,						/**< UART2				*/
+	CGU_PERIPHERAL_UART3,						/**< UART3				*/
+	CGU_PERIPHERAL_USB0,						/**< USB0				*/
+	CGU_PERIPHERAL_USB1,						/**< USB1				*/
+	CGU_PERIPHERAL_WWDT,						/**< WWDT				*/
+	CGU_PERIPHERAL_NUM
+} CGU_PERIPHERAL_T;
+
+/**
+ *  @brief	CGU error status enumerate definition
+ */
+typedef enum {
+	CGU_ERROR_SUCCESS = 0,
+	CGU_ERROR_CONNECT_TOGETHER,
+	CGU_ERROR_INVALID_ENTITY,
+	CGU_ERROR_INVALID_CLOCK_SOURCE,
+	CGU_ERROR_INVALID_PARAM,
+	CGU_ERROR_FREQ_OUTOF_RANGE
+} CGU_ERROR;
+
+/********************************************************************//**
+* @brief CGU structure definitions
+**********************************************************************/
+/*
+ * @brief	CGU peripheral clock structure
+ */
+typedef struct {
+	uint8_t RegBaseEntity;						/**< Base register address 		*/
+	uint16_t RegBranchOffset;					/**< Branch register offset		*/
+	uint8_t PerBaseEntity;						/**< Base peripheral address	*/
+	uint16_t PerBranchOffset;					/**< Base peripheral offset		*/
+	uint8_t next;								/**< Pointer to next structure	*/
+} CGU_PERIPHERAL_S;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CGU_Public_Functions CGU Public Functions
+ * @{
+ */
+
+/** Clock generate initialize/de-initialize */
+uint32_t	CGU_Init(void);
+uint32_t	CGU_DeInit(void);
+
+/** Clock Generator and Clock Control */
+uint32_t	CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
+uint32_t	CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
+
+/** Clock Source and Base Clock operation */
+uint32_t	CGU_SetXTALOSC(uint32_t ClockFrequency);
+uint32_t	CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
+uint32_t	CGU_SetPLL0(void);
+uint32_t	CGU_SetPLL1(uint32_t mult);
+uint32_t	CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
+uint32_t	CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
+uint32_t	CGU_GetBaseStatus(CGU_ENTITY_T Base);
+void		CGU_UpdateClock(void);
+uint32_t	CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_CGU_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_clkpwr.h

@@ -0,0 +1,219 @@
+/***********************************************************************//**
+ * @file		lpc18xx_clkpwr.h
+ * @brief		Contains all macro definitions and function prototypes
+ * 				support for Clock and Power Control firmware library on LPC18xx
+ * @version		1.0
+ * @date		14. Dec. 2010
+ * @author		NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **************************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR CLKPWR
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_CLKPWR_H_
+#define LPC18XX_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+typedef enum {
+	/* Clock Source */
+	CLKPWR_CLKSRC_32KHZ_OSC = 0,
+	CLKPWR_CLKSRC_IRC,
+	CLKPWR_CLKSRC_ENET_RX_CLK,
+	CLKPWR_CLKSRC_ENET_TX_CLK,
+	CLKPWR_CLKSRC_GP_CLKIN,
+	CLKPWR_CLKSRC_TCK,
+	CLKPWR_CLKSRC_XTAL_OSC,
+	CLKPWR_CLKSRC_PLL0,
+	CLKPWR_CLKSRC_PLL1,
+	CLKPWR_CLKSRC_IDIVA = CLKPWR_CLKSRC_PLL1 + 3,
+	CLKPWR_CLKSRC_IDIVB,
+	CLKPWR_CLKSRC_IDIVC,
+	CLKPWR_CLKSRC_IDIVD,
+	CLKPWR_CLKSRC_IDIVE,
+
+	/* Base */
+	CLKPWR_BASE_SAFE,
+	CLKPWR_BASE_USB0,
+	CLKPWR_BASE_USB1 = CLKPWR_BASE_USB0 + 2,
+	CLKPWR_BASE_M3,
+	CLKPWR_BASE_SPIFI,
+	//CLKPWR_BASE_SPI,
+	CLKPWR_BASE_PHY_RX = CLKPWR_BASE_SPIFI + 2,
+	CLKPWR_BASE_PHY_TX,
+	CLKPWR_BASE_APB1,
+	CLKPWR_BASE_APB3,
+	CLKPWR_BASE_LCD,
+	CLKPWR_BASE_SDIO = CLKPWR_BASE_LCD + 2,
+	CLKPWR_BASE_SSP0,
+	CLKPWR_BASE_SSP1,
+	CLKPWR_BASE_UART0,
+	CLKPWR_BASE_UART1,
+	CLKPWR_BASE_UART2,
+	CLKPWR_BASE_UART3,
+	CLKPWR_BASE_CLKOUT,
+	CLKPWR_ENTITY_NUM
+} CLKPWR_ENTITY_T;
+
+#define CLKPWR_CLKSRC_NUM (CLKPWR_CLKSRC_IDIVE+1)
+
+typedef enum {
+	CLKPWR_PLL0_MODE_1d = 0,
+	CLKPWR_PLL0_MODE_1c,
+	CLKPWR_PLL0_MODE_1b,
+	CLKPWR_PLL0_MODE_1a,
+}CLKPWR_PLL0_MODE;
+
+typedef enum {
+	CLKPWR_PERIPHERAL_ADC0 = 0,
+	CLKPWR_PERIPHERAL_ADC1,
+	CLKPWR_PERIPHERAL_AES,
+//	CLKPWR_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
+	CLKPWR_PERIPHERAL_APB1_BUS,
+	CLKPWR_PERIPHERAL_APB3_BUS,
+	CLKPWR_PERIPHERAL_CAN,
+	CLKPWR_PERIPHERAL_CREG,
+	CLKPWR_PERIPHERAL_DAC,
+	CLKPWR_PERIPHERAL_DMA,
+	CLKPWR_PERIPHERAL_EMC,
+	CLKPWR_PERIPHERAL_ETHERNET,
+	CLKPWR_PERIPHERAL_ETHERNET_TX, //HIDE
+	CLKPWR_PERIPHERAL_GPIO,
+	CLKPWR_PERIPHERAL_I2C0,
+	CLKPWR_PERIPHERAL_I2C1,
+	CLKPWR_PERIPHERAL_I2S,
+	CLKPWR_PERIPHERAL_LCD,
+	CLKPWR_PERIPHERAL_M3CORE,
+	CLKPWR_PERIPHERAL_M3_BUS,
+	CLKPWR_PERIPHERAL_MOTOCON,
+	CLKPWR_PERIPHERAL_QEI,
+	CLKPWR_PERIPHERAL_RITIMER,
+	CLKPWR_PERIPHERAL_SCT,
+	CLKPWR_PERIPHERAL_SCU,
+	CLKPWR_PERIPHERAL_SDIO,
+	CLKPWR_PERIPHERAL_SPIFI,
+	CLKPWR_PERIPHERAL_SSP0,
+	CLKPWR_PERIPHERAL_SSP1,
+	CLKPWR_PERIPHERAL_TIMER0,
+	CLKPWR_PERIPHERAL_TIMER1,
+	CLKPWR_PERIPHERAL_TIMER2,
+	CLKPWR_PERIPHERAL_TIMER3,
+	CLKPWR_PERIPHERAL_UART0,
+	CLKPWR_PERIPHERAL_UART1,
+	CLKPWR_PERIPHERAL_UART2,
+	CLKPWR_PERIPHERAL_UART3,
+	CLKPWR_PERIPHERAL_USB0,
+	CLKPWR_PERIPHERAL_USB1,
+	CLKPWR_PERIPHERAL_WWDT,
+	CLKPWR_PERIPHERAL_NUM
+} CLKPWR_PERIPHERAL_T;
+//typedef CLKPWR_CLK_T CLKPWR_BASE_T;
+
+typedef struct {
+	uint8_t RegBaseEntity;
+	uint16_t RegBranchOffset;
+	uint8_t PerBaseEntity;
+	uint16_t PerBranchOffset;
+	uint8_t next;
+} CLKPWR_PERIPHERAL_S;
+
+typedef enum {
+	CLKPWR_ERROR_SUCCESS = 0,
+	CLKPWR_ERROR_CONNECT_TOGETHER,
+	CLKPWR_ERROR_INVALID_ENTITY,
+	CLKPWR_ERROR_INVALID_CLOCK_SOURCE,
+	CLKPWR_ERROR_INVALID_PARAM,
+	CLKPWR_ERROR_FREQ_OUTOF_RANGE
+} CLKPWR_ERROR;
+
+/* Branch clocks from CLKPWR_BASE_SAFE */
+
+#define CLKPWR_ENTITY_NONE	CLKPWR_ENTITY_NUM
+
+#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
+#define ISBITSET(x,bit) (x&(1<<bit))
+#define ISMASKSET(x,mask) (x&mask)
+
+#define CLKPWR_CTRL_EN_MASK		1
+#define CLKPWR_CTRL_SRC_MASK	(0xF<<24)
+#define CLKPWR_CTRL_AUTOBLOCK_MASK	(1<<11)
+#define CLKPWR_PLL1_FBSEL_MASK	(1<<6)
+#define CLKPWR_PLL1_BYPASS_MASK	(1<<1)
+#define CLKPWR_PLL1_DIRECT_MASK	(1<<7)
+
+#define CLKPWR_SLEEP_MODE_DEEP_SLEEP	0x3F00AA
+#define CLKPWR_SLEEP_MODE_POWER_DOWN	0x3FFCBA
+#define CLKPWR_SLEEP_MODE_DEEP_POWER_DOWN	0x3FFF7F
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+/* Clock Generator */
+
+uint32_t	CLKPWR_ConfigPWR (CLKPWR_PERIPHERAL_T PPType, FunctionalState en);
+
+uint32_t	CLKPWR_GetPCLKFrequency (CLKPWR_PERIPHERAL_T Clock);
+
+/* Clock Source and Base Clock operation */
+uint32_t	CLKPWR_SetXTALOSC(uint32_t ClockFrequency);
+uint32_t	CLKPWR_SetDIV(CLKPWR_ENTITY_T SelectDivider, uint32_t divisor);
+uint32_t	CLKPWR_SetPLL0(void);
+uint32_t	CLKPWR_SetPLL1(uint32_t mult);
+uint32_t	CLKPWR_EnableEntity(CLKPWR_ENTITY_T ClockEntity, uint32_t en);
+uint32_t	CLKPWR_EntityConnect(CLKPWR_ENTITY_T ClockSource, CLKPWR_ENTITY_T ClockEntity);
+uint32_t	CLKPWR_GetBaseStatus(CLKPWR_ENTITY_T Base);
+
+void		CLKPWR_UpdateClock(void);
+uint32_t	CLKPWR_RealFrequencyCompare(CLKPWR_ENTITY_T Clock, CLKPWR_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
+
+uint32_t	CLKPWR_Init(void);
+uint32_t	CLKPWR_DeInit(void);
+
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_dac.h

@@ -0,0 +1,149 @@
+/**********************************************************************
+* $Id$		lpc18xx_dac.h			2011-06-02
+*//**
+* @file		lpc18xx_dac.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for DAC firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup DAC DAC (Digital to Analog Converter)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_DAC_H_
+#define LPC18XX_DAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/** After the selected settling time after this field is written with a
+new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+is VALUE/1024 <20> VREF */
+#define DAC_VALUE(n) 		((uint32_t)((n&0x3FF)<<6))
+/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere */
+#define DAC_BIAS_EN			((uint32_t)(1<<16))
+/** Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n)  ((uint32_t)(n&0xffff))
+
+/** DCAR double buffering */
+#define DAC_DBLBUF_ENA		((uint32_t)(1<<1))
+/** DCAR Time out count enable */
+#define DAC_CNT_ENA			((uint32_t)(1<<2))
+/** DCAR DMA access */
+#define DAC_DMA_ENA			((uint32_t)(1<<3))
+/** DCAR DACCTRL mask bit */
+#define DAC_DACCTRL_MASK	((uint32_t)(0x0F))
+
+/** Macro to determine if it is valid DAC peripheral */
+#define PARAM_DACx(n)	(((uint32_t *)n)==((uint32_t *)LPC_DAC))
+
+/** Macro to check DAC current optional parameter */
+#define	PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
+||(OPTION == DAC_MAX_CURRENT_350uA))
+
+/**
+ * @}
+ */
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup DAC_Public_Types DAC Public Types
+ * @{
+ */
+
+/**
+ * @brief Current option in DAC configuration option */
+typedef enum
+{
+	DAC_MAX_CURRENT_700uA = 0, 	/*!< The settling time of the DAC is 1 us max,
+								and the maximum	current is 700 uA */
+	DAC_MAX_CURRENT_350uA		/*!< The settling time of the DAC is 2.5 us
+								and the maximum current is 350 uA */
+} DAC_CURRENT_OPT;
+
+/**
+ * @brief Configuration for DAC converter control register */
+typedef struct
+{
+
+	uint8_t  DBLBUF_ENA; 		/**<
+	                         		-0: Disable DACR double buffering
+	                         		-1: when bit CNT_ENA, enable DACR double buffering feature
+							 	*/
+	uint8_t  CNT_ENA;			/*!<
+	                         		-0: Time out counter is disable
+	                         		-1: Time out conter is enable
+							 	*/
+	uint8_t  DMA_ENA;			/*!<
+		                         	-0: DMA access is disable
+		                         	-1: DMA burst request
+								*/
+	uint8_t RESERVED;
+
+} DAC_CONVERTER_CFG_Type;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup DAC_Public_Functions DAC Public Functions
+ * @{
+ */
+
+void 	DAC_Init(LPC_DAC_Type *DACx);
+void    DAC_UpdateValue (LPC_DAC_Type *DACx, uint32_t dac_value);
+void    DAC_SetBias (LPC_DAC_Type *DACx,uint32_t bias);
+void    DAC_ConfigDAConverterControl (LPC_DAC_Type *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
+void 	DAC_SetDMATimeOut(LPC_DAC_Type *DACx,uint32_t time_out);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC18XX_DAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_emc.h

@@ -0,0 +1,79 @@
+/**********************************************************************
+* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $		lpc43xx_emc.h		2011-12-07
+*//**
+* @file		lpc43xx_emc.h
+* @brief	Contains all functions support for Clock Generation and Control
+* 			firmware library on lpc43xx
+* @version	1.0
+* @date		07. December. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#define __CRYSTAL        (12000000UL)    /* Crystal Oscillator frequency          */
+#define __PLLMULT		 (15)
+#define __PLLOUTHZ		 (__CRYSTAL * __PLLMULT)
+#define __EMCDIV		 (2)
+#define __EMCHZ			 (__PLLOUTHZ / __EMCDIV)
+
+void MemoryPinInit(void);
+void EMCFlashInit(void);
+
+/* SDRAM Address Base for DYCS0*/
+#define SDRAM_BASE_ADDR 0x28000000
+#define FLASH_BASE_ADDR 0x1C000000
+
+#define EMC_SDRAM_WIDTH_8_BITS		0
+#define EMC_SDRAM_WIDTH_16_BITS		1
+#define EMC_SDRAM_WIDTH_32_BITS		2
+
+#define EMC_SDRAM_SIZE_16_MBITS		0
+#define EMC_SDRAM_SIZE_64_MBITS		1
+#define EMC_SDRAM_SIZE_128_MBITS	2
+#define EMC_SDRAM_SIZE_256_MBITS	3
+#define EMC_SDRAM_SIZE_512_MBITS	4
+
+#define EMC_SDRAM_DATA_BUS_16_BITS	0
+#define EMC_SDRAM_DATA_BUS_32_BITS	1
+
+#define EMC_B_ENABLE 					(1 << 19)
+#define EMC_ENABLE 						(1 << 0)
+#define EMC_CE_ENABLE 					(1 << 0)
+#define EMC_CS_ENABLE 					(1 << 1)
+#define EMC_CLOCK_DELAYED_STRATEGY 		(0 << 0)
+#define EMC_COMMAND_DELAYED_STRATEGY 	(1 << 0)
+#define EMC_COMMAND_DELAYED_STRATEGY2 	(2 << 0)
+#define EMC_COMMAND_DELAYED_STRATEGY3 	(3 << 0)
+#define EMC_INIT(i) 					((i) << 7)
+#define EMC_NORMAL 						(0)
+#define EMC_MODE 						(1)
+#define EMC_PRECHARGE_ALL 				(2)
+#define EMC_NOP 						(3)
+
+/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
+#define SDRAM_SIZE_BYTES		(1024UL * 1024UL * 8UL)
+#define SDRAM_WIDTH				EMC_SDRAM_WIDTH_16_BITS
+#define SDRAM_SIZE_MBITS		EMC_SDRAM_SIZE_64_MBITS
+#define SDRAM_DATA_BUS_BITS		EMC_SDRAM_DATA_BUS_16_BITS			
+#define SDRAM_COL_ADDR_BITS		8		
+#define CLK0_DELAY     0
+
+void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
+void emc_WaitUS(volatile uint32_t us);
+void emc_WaitMS(uint32_t ms);
+
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_evrt.h

@@ -0,0 +1,146 @@
+/**********************************************************************
+* $Id$		lpc18xx_evrt.h			2011-06-02
+*//**
+* @file		lpc18xx_evrt.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for Event Router firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EVRT EVRT (Event Router)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_EVRT_H_
+#define LPC18XX_EVRT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EVRT_Private_Macros EVRT Private Macros
+ * @{
+ */
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid EVRT peripheral */
+#define PARAM_EVRTx(x)	(((uint32_t *)x)==((uint32_t *)LPC_EVENTROUTER))
+
+/* Macro check EVRT source */
+#define PARAM_EVRT_SOURCE(n)	((n==EVRT_SRC_WAKEUP0) || (n==EVRT_SRC_WAKEUP1) \
+|| (n==EVRT_SRC_WAKEUP2) || (n==EVRT_SRC_WAKEUP3) \
+|| (n==EVRT_SRC_ATIMER) || (n==EVRT_SRC_RTC) \
+|| (n==EVRT_SRC_BOD1) || (n==EVRT_SRC_WWDT) \
+|| (n==EVRT_SRC_ETHERNET) || (n==EVRT_SRC_USB0) \
+|| (n==EVRT_SRC_USB1) || (n==EVRT_SRC_CCAN) || (n==EVRT_SRC_SDIO) \
+|| (n==EVRT_SRC_COMBINE_TIMER2) || (n==EVRT_SRC_COMBINE_TIMER6) \
+|| (n==EVRT_SRC_QEI) || (n==EVRT_SRC_COMBINE_TIMER14) \
+|| (n==EVRT_SRC_RESET)) \
+
+/* Macro check EVRT source active type*/
+#define PARAM_EVRT_SOURCE_ACTIVE_TYPE(n) ((n==EVRT_SRC_ACTIVE_LOW_LEVEL) || (n==EVRT_SRC_ACTIVE_HIGH_LEVEL) \
+		 || (n==EVRT_SRC_ACTIVE_FALLING_EDGE) || (n==EVRT_SRC_ACTIVE_RISING_EDGE))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup EVRT_Public_Types EVRT Public Types
+ * @{
+ */
+
+/** @brief EVRT input sources */
+typedef enum {
+	EVRT_SRC_WAKEUP0,				/**< WAKEUP0 event router source		*/
+	EVRT_SRC_WAKEUP1,				/**< WAKEUP1 event router source		*/
+	EVRT_SRC_WAKEUP2,				/**< WAKEUP2 event router source		*/
+	EVRT_SRC_WAKEUP3,				/**< WAKEUP3 event router source		*/
+	EVRT_SRC_ATIMER,				/**< Alarm timer event router source	*/
+	EVRT_SRC_RTC,					/**< RTC event router source			*/
+	EVRT_SRC_BOD1,					/**< BOD event router source			*/
+	EVRT_SRC_WWDT,					/**< WWDT event router source			*/
+	EVRT_SRC_ETHERNET,				/**< Ethernet event router source		*/
+	EVRT_SRC_USB0,					/**< USB0 event router source			*/
+	EVRT_SRC_USB1,					/**< USB1 event router source			*/
+	EVRT_SRC_SDIO,					/**< Reserved							*/
+	EVRT_SRC_CCAN,					/**< C_CAN event router source			*/
+	EVRT_SRC_COMBINE_TIMER2,		/**< Combined timer 2 event router source	*/
+	EVRT_SRC_COMBINE_TIMER6,		/**< Combined timer 6 event router source	*/
+	EVRT_SRC_QEI,					/**< QEI event router source			*/
+	EVRT_SRC_COMBINE_TIMER14,		/**< Combined timer 14 event router source	*/
+	EVRT_SRC_RESERVED1,				/**< Reserved 							*/
+	EVRT_SRC_RESERVED2,				/**< Reserved							*/
+	EVRT_SRC_RESET					/**< Reset event router source			*/
+} EVRT_SRC_ENUM;
+
+
+/** @brief EVRT input sources detecting type */
+typedef enum {
+	EVRT_SRC_ACTIVE_LOW_LEVEL,		/**< Active low level 		*/
+	EVRT_SRC_ACTIVE_HIGH_LEVEL,		/**< Active high level		*/
+	EVRT_SRC_ACTIVE_FALLING_EDGE,	/**< Active falling edge	*/
+	EVRT_SRC_ACTIVE_RISING_EDGE	/**< Active rising edge		*/
+}EVRT_SRC_ACTIVE_TYPE;
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EVRT_Public_Functions EVRT Public Functions
+ * @{
+ */
+
+void EVRT_Init (LPC_EVENTROUTER_Type *EVRTx);
+void EVRT_DeInit(LPC_EVENTROUTER_Type *EVRTx);
+
+void EVRT_ConfigIntSrcActiveType(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, EVRT_SRC_ACTIVE_TYPE type);
+void EVRT_SetUpIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src, FunctionalState state);
+Bool EVRT_IsSourceInterrupting(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
+void EVRT_ClrPendIntSrc(LPC_EVENTROUTER_Type *EVRTx, EVRT_SRC_ENUM EVRT_Src);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_EVRT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_gpdma.h

@@ -0,0 +1,468 @@
+/**********************************************************************
+* $Id$		lpc18xx_gpdma.h		2011-06-02
+*//**
+* @file		lpc18xx_gpdma.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for GPDMA firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPDMA GPDMA (General Purpose DMA)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_GPDMA_H_
+#define LPC18XX_GPDMA_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
+ * @{
+ */
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_SPIFI 			((0UL)) 		/**< SPIFI 				*/
+#define GPDMA_CONN_MAT0_0 			((1UL)) 		/**< MAT0.0 			*/
+#define GPDMA_CONN_UART0_Tx			((2UL)) 		/**< UART0 Tx 			*/
+#define GPDMA_CONN_MAT0_1 			((3UL)) 		/**< MAT0.1 			*/
+#define GPDMA_CONN_UART0_Rx			((4UL)) 		/**< UART0 Rx 			*/
+#define GPDMA_CONN_MAT1_0 			((5UL)) 		/**< MAT1.0 			*/
+#define GPDMA_CONN_UART1_Tx			((6UL)) 		/**< UART1 Tx 			*/
+#define GPDMA_CONN_MAT1_1   		((7UL)) 		/**< MAT1.1 			*/
+#define GPDMA_CONN_UART1_Rx			((8UL)) 		/**< UART1 Rx 			*/
+#define GPDMA_CONN_MAT2_0   		((9UL)) 		/**< MAT2.0 			*/
+#define GPDMA_CONN_UART2_Tx			((10UL)) 		/**< UART2 Tx 			*/
+#define GPDMA_CONN_MAT2_1   		((11UL)) 		/**< MAT2.1 			*/
+#define GPDMA_CONN_UART2_Rx			((12UL)) 		/**< UART2 Rx 			*/
+#define GPDMA_CONN_MAT3_0 			((13UL)) 		/**< MAT3.0 			*/
+#define GPDMA_CONN_UART3_Tx			((14UL)) 		/**< UART3 Tx 			*/
+#define GPDMA_CONN_SCT_0			((15UL)) 		/**< SCT timer channel 0*/
+#define GPDMA_CONN_MAT3_1   		((16UL)) 		/**< MAT3.1 			*/
+#define GPDMA_CONN_UART3_Rx			((17UL)) 		/**< UART3 Rx 			*/
+#define GPDMA_CONN_SCT_1			((18UL)) 		/**< SCT timer channel 1*/
+#define GPDMA_CONN_SSP0_Rx 			((19UL)) 		/**< SSP0 Rx 			*/
+#define GPDMA_CONN_I2S_Channel_0 	((20UL)) 		/**< I2S channel 0 		*/
+#define GPDMA_CONN_SSP0_Tx 			((21UL)) 		/**< SSP0 Tx 			*/
+#define GPDMA_CONN_I2S_Channel_1 	((22UL)) 		/**< I2S channel 1		*/
+#define GPDMA_CONN_SSP1_Rx 			((23UL)) 		/**< SSP1 Rx 			*/
+#define GPDMA_CONN_SSP1_Tx 			((24UL)) 		/**< SSP1 Tx 			*/
+#define GPDMA_CONN_ADC_0			((25UL)) 		/**< ADC 0 				*/
+#define GPDMA_CONN_ADC_1			((26UL)) 		/**< ADC 1 				*/
+#define GPDMA_CONN_DAC 				((27UL)) 		/**< DAC 				*/
+
+/** GPDMA Transfer type definitions */
+#define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA 				((0UL)) 	/**< Memory to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA 				((1UL)) 	/**< Memory to peripheral - DMA control */
+#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA 				((2UL)) 	/**< Peripheral to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA 				((3UL)) 	/**< Source peripheral to destination peripheral - DMA control */
+#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL 	((4UL)) 	/**< Source peripheral to destination peripheral - destination peripheral control */
+#define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL 		((5UL)) 	/**< Memory to peripheral - peripheral control */
+#define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL 		((6UL)) 	/**< Peripheral to memory - peripheral control */
+#define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL		((7UL)) 	/**< Source peripheral to destination peripheral - source peripheral control */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1 	((0UL)) /**< Burst size = 1 */
+#define GPDMA_BSIZE_4 	((1UL)) /**< Burst size = 4 */
+#define GPDMA_BSIZE_8 	((2UL)) /**< Burst size = 8 */
+#define GPDMA_BSIZE_16 	((3UL)) /**< Burst size = 16 */
+#define GPDMA_BSIZE_32 	((4UL)) /**< Burst size = 32 */
+#define GPDMA_BSIZE_64 	((5UL)) /**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE 		((0UL)) /**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD 	((1UL)) /**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD 		((2UL)) /**< Width = 4 bytes */
+
+/** LPC_GPDMA base addresses 	*/
+#define LPC_GPDMACH0_BASE	0x40002100
+#define LPC_GPDMACH1_BASE	0x40002120
+#define LPC_GPDMACH2_BASE	0x40002140
+#define LPC_GPDMACH3_BASE	0x40002160
+#define LPC_GPDMACH4_BASE	0x40002180
+#define LPC_GPDMACH5_BASE	0x400021A0
+#define LPC_GPDMACH6_BASE	0x400021C0
+#define LPC_GPDMACH7_BASE	0x400021E0
+
+/* LPC_GPDMA channels definitions 	*/
+#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACIntStat_Ch(n)			(((1UL<<n)&0xFF))
+#define GPDMA_DMACIntStat_BITMASK		((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Status register
+ **********************************************************************/
+#define GPDMA_DMACIntTCStat_Ch(n)		(((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCStat_BITMASK		((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntTCClear_Ch(n)		(((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCClear_BITMASK	((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Status register
+ **********************************************************************/
+#define GPDMA_DMACIntErrStat_Ch(n)		(((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrStat_BITMASK	((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntErrClr_Ch(n)		(((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrClr_BITMASK		((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Interrupt Terminal Count Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntTCStat_Ch(n)	(((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntTCStat_BITMASK	((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Error Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntErrStat_Ch(n)	(((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntErrStat_BITMASK	((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Enabled Channel register
+ **********************************************************************/
+#define GPDMA_DMACEnbldChns_Ch(n)		(((1UL<<n)&0xFF))
+#define GPDMA_DMACEnbldChns_BITMASK		((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Burst Request register
+ **********************************************************************/
+#define	GPDMA_DMACSoftBReq_Src(n)		(((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftBReq_BITMASK		((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftSReq_Src(n) 		(((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftSReq_BITMASK		((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLBReq_Src(n)		(((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLBReq_BITMASK		((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLSReq_Src(n) 		(((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLSReq_BITMASK		((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Configuration register
+ **********************************************************************/
+#define GPDMA_DMACConfig_E				((0x01))	 /**< DMA Controller enable*/
+#define GPDMA_DMACConfig_M0				((0x02))	 /**< AHB Master 0 endianness configuration*/
+#define GPDMA_DMACConfig_M1				((0x04))	 /**< AHB Master 1 endianness configuration*/
+#define GPDMA_DMACConfig_BITMASK		((0x07))
+
+/*********************************************************************//**
+ * Macro defines for DMA Synchronization register
+ **********************************************************************/
+#define GPDMA_DMACSync_Src(n)			(((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSync_BITMASK			((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Linked List Item registers
+ **********************************************************************/
+/** DMA Channel Linked List Item registers bit mask*/
+#define GPDMA_DMACCxLLI_BITMASK 		((0xFFFFFFFC))
+
+/*********************************************************************//**
+ * Macro defines for DMA channel control registers
+ **********************************************************************/
+#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) 	/**< Transfer size*/
+#define GPDMA_DMACCxControl_SBSize(n)		(((n&0x07)<<12)) 	/**< Source burst size*/
+#define GPDMA_DMACCxControl_DBSize(n)		(((n&0x07)<<15)) 	/**< Destination burst size*/
+#define GPDMA_DMACCxControl_SWidth(n)		(((n&0x07)<<18)) 	/**< Source transfer width*/
+#define GPDMA_DMACCxControl_DWidth(n)		(((n&0x07)<<21)) 	/**< Destination transfer width*/
+#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1	((1UL<<24)) /**< Source AHB master select*/
+#define GPDMA_DMACCxControl_DestTransUseAHBMaster1	((1UL<<25)) /**< Destination AHB master select*/
+#define GPDMA_DMACCxControl_SI				((1UL<<26)) 		/**< Source increment*/
+#define GPDMA_DMACCxControl_DI				((1UL<<27)) 		/**< Destination increment*/
+#define GPDMA_DMACCxControl_Prot1			((1UL<<28)) 		/**< Indicates that the access is in user mode or privileged mode*/
+#define GPDMA_DMACCxControl_Prot2			((1UL<<29)) 		/**< Indicates that the access is bufferable or not bufferable*/
+#define GPDMA_DMACCxControl_Prot3			((1UL<<30)) 		/**< Indicates that the access is cacheable or not cacheable*/
+#define GPDMA_DMACCxControl_I				((1UL<<31)) 		/**< Terminal count interrupt enable bit */
+/** DMA channel control registers bit mask */
+#define GPDMA_DMACCxControl_BITMASK			((0xFCFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Configuration registers
+ **********************************************************************/
+#define GPDMA_DMACCxConfig_E 					((1UL<<0))			/**< DMA control enable*/
+#define GPDMA_DMACCxConfig_SrcPeripheral(n) 	(((n&0x1F)<<1)) 	/**< Source peripheral*/
+#define GPDMA_DMACCxConfig_DestPeripheral(n) 	(((n&0x1F)<<6)) 	/**< Destination peripheral*/
+#define GPDMA_DMACCxConfig_TransferType(n) 		(((n&0x7)<<11)) 	/**< This value indicates the type of transfer*/
+#define GPDMA_DMACCxConfig_IE 					((1UL<<14))			/**< Interrupt error mask*/
+#define GPDMA_DMACCxConfig_ITC 					((1UL<<15)) 		/**< Terminal count interrupt mask*/
+#define GPDMA_DMACCxConfig_L 					((1UL<<16)) 		/**< Lock*/
+#define GPDMA_DMACCxConfig_A 					((1UL<<17)) 		/**< Active*/
+#define GPDMA_DMACCxConfig_H 					((1UL<<18)) 		/**< Halt*/
+/** DMA Channel Configuration registers bit mask */
+#define GPDMA_DMACCxConfig_BITMASK				((0x7FFFF))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check GPDMA channel */
+#define PARAM_GPDMA_CHANNEL(n)	(n<=7)
+
+/* Macros check GPDMA connection type */
+#define PARAM_GPDMA_CONN(n)		((n==GPDMA_CONN_SPIFI) || (n==GPDMA_CONN_DAC) \
+|| (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
+|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
+|| (n==GPDMA_CONN_ADC_0)   || (n==GPDMA_CONN_ADC_1) \
+|| (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \
+|| (n==GPDMA_CONN_SCT_0)   || (n==GPDMA_CONN_SCT_1) \
+|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
+|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
+|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
+|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
+|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
+|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
+|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
+|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
+
+/* Macros check GPDMA burst size type */
+#define PARAM_GPDMA_BSIZE(n)	((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
+|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
+|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
+|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
+
+/* Macros check GPDMA width type */
+#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
+|| (n==GPDMA_WIDTH_WORD))
+
+/* Macros check GPDMA status type */
+#define PARAM_GPDMA_STAT(n)	((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
+|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
+|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
+
+/* Macros check GPDMA transfer type */
+#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \
+||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\
+||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\
+||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))
+
+/* Macros check GPDMA state clear type */
+#define PARAM_GPDMA_STATCLR(n)	((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Types GPDMA Public Types
+ * @{
+ */
+
+/**
+ * @brief GPDMA Channel Registers
+ */
+typedef struct
+{
+  __IO uint32_t CSrcAddr;
+  __IO uint32_t CDestAddr;
+  __IO uint32_t CLLI;
+  __IO uint32_t CControl;
+  __IO uint32_t CConfig;
+} LPC_GPDMACH_TypeDef;
+
+/**
+ * @brief GPDMA Status enumeration
+ */
+typedef enum {
+	GPDMA_STAT_INT,			/**< GPDMA Interrupt Status */
+	GPDMA_STAT_INTTC,		/**< GPDMA Interrupt Terminal Count Request Status */
+	GPDMA_STAT_INTERR,		/**< GPDMA Interrupt Error Status */
+	GPDMA_STAT_RAWINTTC,	/**< GPDMA Raw Interrupt Terminal Count Status */
+	GPDMA_STAT_RAWINTERR,	/**< GPDMA Raw Error Interrupt Status */
+	GPDMA_STAT_ENABLED_CH	/**< GPDMA Enabled Channel Status */
+} GPDMA_Status_Type;
+
+/**
+ * @brief GPDMA Interrupt clear status enumeration
+ */
+typedef enum{
+	GPDMA_STATCLR_INTTC,	/**< GPDMA Interrupt Terminal Count Request Clear */
+	GPDMA_STATCLR_INTERR	/**< GPDMA Interrupt Error Clear */
+}GPDMA_StateClear_Type;
+
+/**
+ * @brief GPDMA Channel configuration structure type definition
+ */
+typedef struct {
+	uint32_t ChannelNum; 	/**< DMA channel number, should be in
+								range from 0 to 7.
+								Note: DMA channel 0 has the highest priority
+								and DMA channel 7 the lowest priority.
+								*/
+	uint32_t TransferSize;	/**< Length/Size of transfer */
+	uint32_t TransferWidth;	/**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
+	uint32_t SrcMemAddr;	/**< Physical Source Address, used in case TransferType is chosen as
+								 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
+	uint32_t DstMemAddr;	/**< Physical Destination Address, used in case TransferType is chosen as
+								 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
+	uint32_t TransferType;	/**< Transfer Type, should be one of the following:
+							- GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control
+							- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control
+							- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control
+							- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control
+							- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control
+							- GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control
+							- GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control
+							- GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:	Source peripheral to destination peripheral - source peripheral control
+							*/
+	uint32_t SrcConn;		/**< Peripheral Source Connection type, used in case TransferType is chosen as
+							GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
+							following:
+							 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+							 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+							 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+							 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+							 - GPDMA_CONN_ADC_0: ADC0
+							 - GPDMA_CONN_ADC_1: ADC1
+							 - GPDMA_CONN_SCT_0: SCT0
+							 - GPDMA_CONN_SCT_1: SCT1
+							 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+							 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+							 - GPDMA_CONN_DAC: DAC
+							 - GPDMA_CONN_SPIFI: SPIFI
+							 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+							 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+							 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+							 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+							 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+							 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+							 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+							 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+							 */
+	uint32_t DstConn;		/**< Peripheral Destination Connection type, used in case TransferType is chosen as
+							GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
+							following:
+							 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+							 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+							 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+							 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+							 - GPDMA_CONN_ADC_0: ADC0
+							 - GPDMA_CONN_ADC_1: ADC1
+							 - GPDMA_CONN_SCT_0: SCT0
+							 - GPDMA_CONN_SCT_1: SCT1
+							 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+							 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+							 - GPDMA_CONN_DAC: DAC
+							 - GPDMA_CONN_SPIFI: SPIFI
+							 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+							 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+							 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+							 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+							 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+							 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+							 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+							 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+							 */
+	uint32_t DMALLI;		/**< Linker List Item structure data address
+							if there's no Linker List, set as '0'
+							*/
+} GPDMA_Channel_CFG_Type;
+
+/**
+ * @brief GPDMA Linker List Item structure type definition
+ */
+typedef struct {
+	uint32_t SrcAddr;	/**< Source Address */
+	uint32_t DstAddr;	/**< Destination address */
+	uint32_t NextLLI;	/**< Next LLI address, otherwise set to '0' */
+	uint32_t Control;	/**< GPDMA Control of this LLI */
+} GPDMA_LLI_Type;
+
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
+ * @{
+ */
+
+void GPDMA_Init(void);
+
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_GPDMA_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_gpio.h

@@ -0,0 +1,186 @@
+/**********************************************************************
+* $Id$		lpc18xx_gpio.h		2011-06-02
+*//**
+* @file		lpc18xx_gpio.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for GPIO firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPIO	GPIO (General Purpose I/O)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_GPIO_H_
+#define LPC18XX_GPIO_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Macros GPIO Public Macros
+ * @{
+ */
+#if 0
+/** General LPC GPIO Base */
+#define LPC_GPIO_BASE	LPC_GPIO0_BASE
+/** Fast GPIO port 0 byte accessible definition */
+#define GPIO0_Byte	((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x00))
+/** Fast GPIO port 1 byte accessible definition */
+#define GPIO1_Byte	((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x20))
+/** Fast GPIO port 2 byte accessible definition */
+#define GPIO2_Byte	((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x40))
+/** Fast GPIO port 3 byte accessible definition */
+#define GPIO3_Byte	((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x60))
+/** Fast GPIO port 4 byte accessible definition */
+#define GPIO4_Byte	((GPIO_Byte_TypeDef *)(LPC_GPIO_BASE+0x80))
+
+
+/** Fast GPIO port 0 half-word accessible definition */
+#define GPIO0_HalfWord	((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x00))
+/** Fast GPIO port 1 half-word accessible definition */
+#define GPIO1_HalfWord	((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x20))
+/** Fast GPIO port 2 half-word accessible definition */
+#define GPIO2_HalfWord	((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x40))
+/** Fast GPIO port 3 half-word accessible definition */
+#define GPIO3_HalfWord	((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x60))
+/** Fast GPIO port 4 half-word accessible definition */
+#define GPIO4_HalfWord	((GPIO_HalfWord_TypeDef *)(LPC_GPIO_BASE+0x80))
+#endif
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Types GPIO Public Types
+ * @{
+ */
+
+/**
+ * @brief Fast GPIO port byte type definition
+ */
+ #if 0
+typedef struct {
+	__IO uint8_t FIODIR[4];		/**< FIO direction register in byte-align */
+	   uint32_t RESERVED0[3];	/**< Reserved */
+	__IO uint8_t FIOMASK[4];	/**< FIO mask register in byte-align */
+	__IO uint8_t FIOPIN[4];		/**< FIO pin register in byte align */
+	__IO uint8_t FIOSET[4];		/**< FIO set register in byte-align */
+	__O  uint8_t FIOCLR[4];		/**< FIO clear register in byte-align */
+} GPIO_Byte_TypeDef;
+#endif
+
+/**
+ * @brief Fast GPIO port half-word type definition
+ */
+ #if 0
+typedef struct {
+	__IO uint16_t FIODIRL;		/**< FIO direction register lower halfword part */
+	__IO uint16_t FIODIRU;		/**< FIO direction register upper halfword part */
+	   uint32_t RESERVED0[3];	/**< Reserved */
+	__IO uint16_t FIOMASKL;		/**< FIO mask register lower halfword part */
+	__IO uint16_t FIOMASKU;		/**< FIO mask register upper halfword part */
+	__IO uint16_t FIOPINL;		/**< FIO pin register lower halfword part */
+	__IO uint16_t FIOPINU;		/**< FIO pin register upper halfword part */
+	__IO uint16_t FIOSETL;		/**< FIO set register lower halfword part */
+	__IO uint16_t FIOSETU;		/**< FIO set register upper halfword part */
+	__O  uint16_t FIOCLRL;		/**< FIO clear register lower halfword part */
+	__O  uint16_t FIOCLRU;		/**< FIO clear register upper halfword part */
+} GPIO_HalfWord_TypeDef;
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPIO_Public_Functions GPIO Public Functions
+ * @{
+ */
+
+/* GPIO style ------------------------------- */
+void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t GPIO_ReadValue(uint8_t portNum);
+
+#ifdef GPIO_INT
+void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
+#endif
+
+
+/* FIO (word-accessible) style ------------------------------- */
+void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t FIO_ReadValue(uint8_t portNum);
+void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
+
+#ifdef GPIO_INT
+void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
+#endif
+
+#if 0
+/* FIO (halfword-accessible) style ------------------------------- */
+void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
+void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
+void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
+
+
+/* FIO (byte-accessible) style ------------------------------- */
+void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
+void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
+void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
+#endif
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_GPIO_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_i2c.h

@@ -0,0 +1,383 @@
+/**********************************************************************
+* $Id$		lpc18xx_i2c.h		2011-06-02
+*//**
+* @file		lpc18xx_i2c.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for I2C firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2C I2C (Inter-Integrated Circuit)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_I2C_H_
+#define LPC18XX_I2C_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*******************************************************************//**
+ * I2C Control Set register description
+ *********************************************************************/
+#define I2C_I2CONSET_AA				((0x04)) /*!< Assert acknowledge flag */
+#define I2C_I2CONSET_SI				((0x08)) /*!< I2C interrupt flag */
+#define I2C_I2CONSET_STO			((0x10)) /*!< STOP flag */
+#define I2C_I2CONSET_STA			((0x20)) /*!< START flag */
+#define I2C_I2CONSET_I2EN			((0x40)) /*!< I2C interface enable */
+
+/*******************************************************************//**
+ * I2C Control Clear register description
+ *********************************************************************/
+/** Assert acknowledge Clear bit */
+#define I2C_I2CONCLR_AAC			((1<<2))
+/** I2C interrupt Clear bit */
+#define I2C_I2CONCLR_SIC			((1<<3))
+/** START flag Clear bit */
+#define I2C_I2CONCLR_STAC			((1<<5))
+/** I2C interface Disable bit */
+#define I2C_I2CONCLR_I2ENC			((1<<6))
+
+/********************************************************************//**
+ * I2C Status Code definition (I2C Status register)
+ *********************************************************************/
+/* Return Code in I2C status register */
+#define I2C_STAT_CODE_BITMASK		((0xF8))
+
+/* I2C return status code definitions ----------------------------- */
+
+/** No relevant information */
+#define I2C_I2STAT_NO_INF						((0xF8))
+
+/* Master transmit mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_TX_START					((0x08))
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_TX_RESTART					((0x10))
+/** SLA+W has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_ACK				((0x18))
+/** SLA+W has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_NACK				((0x20))
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_DAT_ACK					((0x28))
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_DAT_NACK				((0x30))
+/** Arbitration lost in SLA+R/W or Data bytes */
+#define I2C_I2STAT_M_TX_ARB_LOST				((0x38))
+
+/* Master receive mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_RX_START					((0x08))
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_RX_RESTART					((0x10))
+/** Arbitration lost */
+#define I2C_I2STAT_M_RX_ARB_LOST				((0x38))
+/** SLA+R has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_ACK				((0x40))
+/** SLA+R has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_NACK				((0x48))
+/** Data has been received, ACK has been returned */
+#define I2C_I2STAT_M_RX_DAT_ACK					((0x50))
+/** Data has been received, NACK has been return */
+#define I2C_I2STAT_M_RX_DAT_NACK				((0x58))
+
+/* Slave receive mode -------------------------------------------- */
+/** Own slave address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_SLAW_ACK				((0x60))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA			((0x68))
+/** Own SLA+W has been received, ACK returned */
+//#define I2C_I2STAT_S_RX_SLAW_ACK				((0x68))
+
+/** General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_GENCALL_ACK				((0x70))
+
+/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL		((0x78))
+/** General call address has been received, ACK has been returned */
+//#define I2C_I2STAT_S_RX_GENCALL_ACK				((0x78))
+
+/** Previously addressed with own SLV address;
+ * Data has been received, ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK			((0x80))
+/** Previously addressed with own SLA;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK		((0x88))
+/** Previously addressed with General Call;
+ * Data has been received and ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK		((0x90))
+/** Previously addressed with General Call;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK	((0x98))
+/** A STOP condition or repeated START condition has
+ * been received while still addressed as SLV/REC
+ * (Slave Receive) or SLV/TRX (Slave Transmit) */
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX	((0xA0))
+
+/** Slave transmit mode */
+/** Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_SLAR_ACK				((0xA8))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA			((0xB0))
+/** Own SLA+R has been received, ACK has been returned */
+//#define I2C_I2STAT_S_TX_SLAR_ACK				((0xB0))
+
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_S_TX_DAT_ACK					((0xB8))
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_S_TX_DAT_NACK				((0xC0))
+/** Last data byte in I2DAT has been transmitted (AA = 0);
+ ACK has been received */
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK			((0xC8))
+
+/** Time out in case of using I2C slave mode */
+#define I2C_SLAVE_TIME_OUT						0x10000UL
+
+/********************************************************************//**
+ * I2C Data register definition
+ *********************************************************************/
+/** Mask for I2DAT register*/
+#define I2C_I2DAT_BITMASK			((0xFF))
+
+/** Idle data value will be send out in slave mode in case of the actual
+ * expecting data requested from the master is greater than its sending data
+ * length that can be supported */
+#define I2C_I2DAT_IDLE_CHAR			(0xFF)
+
+/********************************************************************//**
+ * I2C Monitor mode control register description
+ *********************************************************************/
+#define I2C_I2MMCTRL_MM_ENA			((1<<0))		/**< Monitor mode enable */
+#define I2C_I2MMCTRL_ENA_SCL		((1<<1))		/**< SCL output enable */
+#define I2C_I2MMCTRL_MATCH_ALL		((1<<2))		/**< Select interrupt register match */
+#define I2C_I2MMCTRL_BITMASK		((0x07))		/**< Mask for I2MMCTRL register */
+
+/********************************************************************//**
+ * I2C Data buffer register description
+ *********************************************************************/
+/** I2C Data buffer register bit mask */
+#define I2DATA_BUFFER_BITMASK		((0xFF))
+
+/********************************************************************//**
+ * I2C Slave Address registers definition
+ *********************************************************************/
+/** General Call enable bit */
+#define I2C_I2ADR_GC				((1<<0))
+/** I2C Slave Address registers bit mask */
+#define I2C_I2ADR_BITMASK			((0xFF))
+
+/********************************************************************//**
+ * I2C Mask Register definition
+ *********************************************************************/
+/** I2C Mask Register mask field */
+#define I2C_I2MASK_MASK(n)			((n&0xFE))
+
+/********************************************************************//**
+ * I2C SCL HIGH duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL HIGH duty cycle Register bit mask */
+#define I2C_I2SCLH_BITMASK			((0xFFFF))
+
+/********************************************************************//**
+ * I2C SCL LOW duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL LOW duty cycle Register bit mask */
+#define I2C_I2SCLL_BITMASK			((0xFFFF))
+
+/* I2C status values */
+#define I2C_SETUP_STATUS_ARBF   (1<<8)	/**< Arbitration false */
+#define I2C_SETUP_STATUS_NOACKF (1<<9)	/**< No ACK returned */
+#define I2C_SETUP_STATUS_DONE   (1<<10)	/**< Status DONE */
+
+/*********************************************************************//**
+ * I2C monitor control configuration defines
+ **********************************************************************/
+#define I2C_MONITOR_CFG_SCL_OUTPUT	I2C_I2MMCTRL_ENA_SCL		/**< SCL output enable */
+#define I2C_MONITOR_CFG_MATCHALL	I2C_I2MMCTRL_MATCH_ALL		/**< Select interrupt register match */
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check I2C slave address */
+#define PARAM_I2C_SLAVEADDR_CH(n)	(n<=3)
+
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_I2Cx(n)	((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)))
+
+/* Macros check I2C monitor configuration type */
+#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
+
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2C_Public_Types I2C Public Types
+ * @{
+ */
+
+/**
+ * @brief I2C Own slave address setting structure
+ */
+typedef struct {
+	uint8_t SlaveAddrChannel;	/**< Slave Address channel in I2C control,
+								should be in range from 0..3
+								*/
+	uint8_t SlaveAddr_7bit;		/**< Value of 7-bit slave address */
+	uint8_t GeneralCallState;	/**< Enable/Disable General Call Functionality
+								when I2C control being in Slave mode, should be:
+								- ENABLE: Enable General Call function.
+								- DISABLE: Disable General Call function.
+								*/
+	uint8_t SlaveAddrMaskValue;	/**< Any bit in this 8-bit value (bit 7:1)
+								which is set to '1' will cause an automatic compare on
+								the corresponding bit of the received address when it
+								is compared to the SlaveAddr_7bit value associated with this
+								mask register. In other words, bits in SlaveAddr_7bit value
+								which are masked are not taken into account in determining
+								an address match
+								*/
+} I2C_OWNSLAVEADDR_CFG_Type;
+
+
+/**
+ * @brief Master transfer setup data structure definitions
+ */
+typedef struct
+{
+  uint32_t          sl_addr7bit;				/**< Slave address in 7bit mode */
+  uint8_t*          tx_data;					/**< Pointer to Transmit data - NULL if data transmit
+													  is not used */
+  uint32_t          tx_length;					/**< Transmit data length - 0 if data transmit
+													  is not used*/
+  uint32_t          tx_count;					/**< Current Transmit data counter */
+  uint8_t*          rx_data;					/**< Pointer to Receive data - NULL if data receive
+													  is not used */
+  uint32_t          rx_length;					/**< Receive data length - 0 if data receive is
+													   not used */
+  uint32_t          rx_count;					/**< Current Receive data counter */
+  uint32_t          retransmissions_max;		/**< Max Re-Transmission value */
+  uint32_t          retransmissions_count;		/**< Current Re-Transmission counter */
+  uint32_t          status;						/**< Current status of I2C activity */
+  void 				(*callback)(void);			/**< Pointer to Call back function when transmission complete
+													used in interrupt transfer mode */
+} I2C_M_SETUP_Type;
+
+
+/**
+ * @brief Slave transfer setup data structure definitions
+ */
+typedef struct
+{
+  uint8_t*          tx_data;					/**< Pointer to transmit data - NULL if data transmit is not used */
+  uint32_t          tx_length;					/**< Transmit data length - 0 if data transmit is not used */
+  uint32_t          tx_count;					/**< Current transmit data counter	*/
+  uint8_t*          rx_data;					/**< Pointer to receive data - NULL if data received is not used */
+  uint32_t          rx_length;					/**< Receive data length - 0 if data receive is not used */
+  uint32_t          rx_count;					/**< Current receive data counter */
+  uint32_t          status;						/**< Current status of I2C activity */
+  void 				(*callback)(void);			/**< Pointer to call-back function when transmission complete
+  													used by interrupt transfer mode */
+} I2C_S_SETUP_Type;
+
+/**
+ * @brief Transfer option type definitions
+ */
+typedef enum {
+	I2C_TRANSFER_POLLING = 0,		/**< Transfer in polling mode */
+	I2C_TRANSFER_INTERRUPT			/**< Transfer in interrupt mode */
+} I2C_TRANSFER_OPT_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2C_Public_Functions I2C Public Functions
+ * @{
+ */
+
+/* I2C Init/DeInit functions ---------- */
+void I2C_Init(LPC_I2Cn_Type *I2Cx, uint32_t clockrate);
+void I2C_DeInit(LPC_I2Cn_Type* I2Cx);
+//void I2C_SetClock (LPC_I2Cn_Type *I2Cx, uint32_t target_clock);
+void I2C_Cmd(LPC_I2Cn_Type* I2Cx, FunctionalState NewState);
+
+/* I2C transfer data functions -------- */
+Status I2C_MasterTransferData(LPC_I2Cn_Type *I2Cx, \
+		I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, \
+		I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+uint32_t I2C_MasterTransferComplete(LPC_I2Cn_Type *I2Cx);
+uint32_t I2C_SlaveTransferComplete(LPC_I2Cn_Type *I2Cx);
+
+
+void I2C_SetOwnSlaveAddr(LPC_I2Cn_Type *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
+uint8_t I2C_GetLastStatusCode(LPC_I2Cn_Type* I2Cx);
+
+/* I2C Monitor functions ---------------*/
+void I2C_MonitorModeConfig(LPC_I2Cn_Type *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
+void I2C_MonitorModeCmd(LPC_I2Cn_Type *I2Cx, FunctionalState NewState);
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2Cn_Type *I2Cx);
+BOOL_8 I2C_MonitorHandler(LPC_I2Cn_Type *I2Cx, uint8_t *buffer, uint32_t size);
+
+/* I2C Interrupt handler functions ------*/
+void I2C_IntCmd (LPC_I2Cn_Type *I2Cx, Bool NewState);
+void I2C_MasterHandler (LPC_I2Cn_Type *I2Cx);
+void I2C_SlaveHandler (LPC_I2Cn_Type *I2Cx);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_I2C_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_i2s.h

@@ -0,0 +1,369 @@
+/**********************************************************************
+* $Id$		lpc18xx_i2s.h		2011-06-02
+*//**
+* @file		lpc18xx_i2s.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for I2S firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2S I2S (Inter-IC Sound)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_I2S_H_
+#define LPC18XX_I2S_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * I2S configuration parameter defines
+ **********************************************************************/
+/** I2S Wordwidth bit */
+#define I2S_WORDWIDTH_8		((uint32_t)(0))
+#define I2S_WORDWIDTH_16	((uint32_t)(1))
+#define I2S_WORDWIDTH_32	((uint32_t)(3))
+/** I2S Channel bit */
+#define I2S_STEREO			((uint32_t)(0))
+#define I2S_MONO			((uint32_t)(1))
+/** I2S Master/Slave mode bit */
+#define I2S_MASTER_MODE		((uint8_t)(0))
+#define I2S_SLAVE_MODE		((uint8_t)(1))
+/** I2S Stop bit */
+#define I2S_STOP_ENABLE		((uint8_t)(1))
+#define I2S_STOP_DISABLE	((uint8_t)(0))
+/** I2S Reset bit */
+#define I2S_RESET_ENABLE	((uint8_t)(1))
+#define I2S_RESET_DISABLE	((uint8_t)(0))
+/** I2S Mute bit */
+#define I2S_MUTE_ENABLE		((uint8_t)(1))
+#define I2S_MUTE_DISABLE	((uint8_t)(0))
+/** I2S Transmit/Receive bit */
+#define I2S_TX_MODE			((uint8_t)(0))
+#define I2S_RX_MODE			((uint8_t)(1))
+/** I2S Clock Select bit */
+#define I2S_CLKSEL_FRDCLK	((uint8_t)(0))
+#define I2S_CLKSEL_MCLK		((uint8_t)(2))
+/** I2S 4-pin Mode bit */
+#define I2S_4PIN_ENABLE 	((uint8_t)(1))
+#define I2S_4PIN_DISABLE 	((uint8_t)(0))
+/** I2S MCLK Enable bit */
+#define I2S_MCLK_ENABLE		((uint8_t)(1))
+#define I2S_MCLK_DISABLE	((uint8_t)(0))
+/** I2S select DMA bit */
+#define I2S_DMA_1			((uint8_t)(0))
+#define I2S_DMA_2			((uint8_t)(1))
+
+/*********************************************************************//**
+ * Macro defines for DAO-Digital Audio Output register
+ **********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAO_WORDWIDTH_8		((uint32_t)(0))		/** 8 bit	*/
+#define I2S_DAO_WORDWIDTH_16	((uint32_t)(1))		/** 16 bit	*/
+#define I2S_DAO_WORDWIDTH_32	((uint32_t)(3))		/** 32 bit	*/
+/** I2S control mono or stereo format */
+#define I2S_DAO_MONO			((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAO_STOP			((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAO_RESET			((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAO_SLAVE			((uint32_t)(1<<5))
+/** I2S word select half period minus one */
+#define I2S_DAO_WS_HALFPERIOD(n)	((uint32_t)(n<<6))
+/** I2S control mute mode */
+#define I2S_DAO_MUTE			((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for DAI-Digital Audio Input register
+**********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAI_WORDWIDTH_8		((uint32_t)(0))		/** 8 bit	*/
+#define I2S_DAI_WORDWIDTH_16	((uint32_t)(1))		/** 16 bit	*/
+#define I2S_DAI_WORDWIDTH_32	((uint32_t)(3))		/** 32 bit	*/
+/** I2S control mono or stereo format */
+#define I2S_DAI_MONO			((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAI_STOP			((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAI_RESET			((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAI_SLAVE			((uint32_t)(1<<5))
+/** I2S word select half period minus one (9 bits)*/
+#define I2S_DAI_WS_HALFPERIOD(n)	((uint32_t)((n&0x1FF)<<6))
+/** I2S control mute mode */
+#define I2S_DAI_MUTE			((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for STAT register (Status Feedback register)
+**********************************************************************/
+/** I2S Status Receive or Transmit Interrupt */
+#define I2S_STATE_IRQ		((uint32_t)(1))
+/** I2S Status Receive or Transmit DMA1 */
+#define I2S_STATE_DMA1		((uint32_t)(1<<1))
+/** I2S Status Receive or Transmit DMA2 */
+#define I2S_STATE_DMA2		((uint32_t)(1<<2))
+/** I2S Status Current level of the Receive FIFO (5 bits)*/
+#define I2S_STATE_RX_LEVEL(n)	((uint32_t)((n&1F)<<8))
+/** I2S Status Current level of the Transmit FIFO (5 bits)*/
+#define I2S_STATE_TX_LEVEL(n)	((uint32_t)((n&1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA1 register (DMA1 Configuration register)
+**********************************************************************/
+/** I2S control DMA1 for I2S receive */
+#define I2S_DMA1_RX_ENABLE		((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA1_TX_ENABLE		((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA1_RX_DEPTH(n)	((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA1_TX_DEPTH(n)	((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA2 register (DMA2 Configuration register)
+**********************************************************************/
+/** I2S control DMA2 for I2S receive */
+#define I2S_DMA2_RX_ENABLE		((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA2_TX_ENABLE		((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA2_RX_DEPTH(n)	((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA2_TX_DEPTH(n)	((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+* Macro defines for IRQ register (Interrupt Request Control register)
+**********************************************************************/
+/** I2S control I2S receive interrupt */
+#define I2S_IRQ_RX_ENABLE		((uint32_t)(1))
+/** I2S control I2S transmit interrupt */
+#define I2S_IRQ_TX_ENABLE		((uint32_t)(1<<1))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_RX_DEPTH(n)		((uint32_t)((n&0x1F)<<8))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_TX_DEPTH(n)		((uint32_t)((n&0x1F)<<16))
+
+/********************************************************************************//**
+ * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
+*********************************************************************************/
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_Y_DIVIDER(n)	((uint32_t)(n&0xFF))
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_X_DIVIDER(n)	((uint32_t)((n&0xFF)<<8))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_Y_DIVIDER(n)	((uint32_t)(n&0xFF))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_X_DIVIDER(n)	((uint32_t)((n&0xFF)<<8))
+
+/*************************************************************************************//**
+ * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
+**************************************************************************************/
+#define I2S_TXBITRATE(n)	((uint32_t)(n&0x3F))
+#define I2S_RXBITRATE(n)	((uint32_t)(n&0x3F))
+
+/**********************************************************************************//**
+ * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
+************************************************************************************/
+/** I2S Transmit select clock source (2 bits)*/
+#define I2S_TXMODE_CLKSEL(n)	((uint32_t)(n&0x03))
+/** I2S Transmit control 4-pin mode */
+#define I2S_TXMODE_4PIN_ENABLE	((uint32_t)(1<<2))
+/** I2S Transmit control the TX_MCLK output */
+#define I2S_TXMODE_MCENA		((uint32_t)(1<<3))
+/** I2S Receive select clock source */
+#define I2S_RXMODE_CLKSEL(n)	((uint32_t)(n&0x03))
+/** I2S Receive control 4-pin mode */
+#define I2S_RXMODE_4PIN_ENABLE	((uint32_t)(1<<2))
+/** I2S Receive control the TX_MCLK output */
+#define I2S_RXMODE_MCENA		((uint32_t)(1<<3))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid I2S peripheral */
+#define PARAM_I2Sx(n)	((((uint32_t *)n)==((uint32_t *)LPC_I2S0)) || (((uint32_t *)n)==((uint32_t *)LPC_I2S1)))
+/** Macro to check Data to send valid */
+#define PRAM_I2S_FREQ(freq)		((freq>=8000)&&(freq <= 96000))
+/* Macro check I2S word width type */
+#define PARAM_I2S_WORDWIDTH(n)	((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
+||(n==I2S_WORDWIDTH_32))
+/* Macro check I2S channel type */
+#define PARAM_I2S_CHANNEL(n)	((n==I2S_STEREO)||(n==I2S_MONO))
+/* Macro check I2S master/slave mode */
+#define PARAM_I2S_WS_SEL(n)		((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
+/* Macro check I2S stop mode */
+#define PARAM_I2S_STOP(n)	((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_RESET(n)	((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_MUTE(n)	((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
+/* Macro check I2S transmit/receive mode */
+#define PARAM_I2S_TRX(n) 		((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
+/* Macro check I2S clock select mode */
+#define PARAM_I2S_CLKSEL(n)		((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
+/* Macro check I2S 4-pin mode */
+#define PARAM_I2S_4PIN(n)	((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
+/* Macro check I2S MCLK mode */
+#define PARAM_I2S_MCLK(n)	((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
+/* Macro check I2S DMA mode */
+#define PARAM_I2S_DMA(n)		((n==I2S_DMA_1)||(n==I2S_DMA_2))
+/* Macro check I2S DMA depth value */
+#define PARAM_I2S_DMA_DEPTH(n)	((n<=31))
+/* Macro check I2S irq level value */
+#define PARAM_I2S_IRQ_LEVEL(n)	((n<=31))
+/* Macro check I2S half-period value */
+#define PARAM_I2S_HALFPERIOD(n)	((n>0)&&(n<512))
+/* Macro check I2S bit-rate value */
+#define PARAM_I2S_BITRATE(n)	((n<=63))
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2S_Public_Types I2S Public Types
+ * @{
+ */
+
+/**
+ * @brief I2S configuration structure definition
+ */
+typedef struct {
+	uint8_t wordwidth;		/** the number of bytes in data as follow:
+								-I2S_WORDWIDTH_8: 8 bit data
+								-I2S_WORDWIDTH_16: 16 bit data
+								-I2S_WORDWIDTH_32: 32 bit data */
+	uint8_t	mono; 			/** Set mono/stereo mode, should be:
+								- I2S_STEREO: stereo mode
+								- I2S_MONO: mono mode */
+	uint8_t stop;			/** Disables accesses on FIFOs, should be:
+								- I2S_STOP_ENABLE: enable stop mode
+								- I2S_STOP_DISABLE: disable stop mode */
+	uint8_t reset;			/** Asynchronously reset tje transmit channel and FIFO, should be:
+								- I2S_RESET_ENABLE: enable reset mode
+								- I2S_RESET_DISABLE: disable reset mode */
+	uint8_t ws_sel;			/** Set Master/Slave mode, should be:
+								- I2S_MASTER_MODE: I2S master mode
+								- I2S_SLAVE_MODE: I2S slave mode */
+	uint8_t mute;			/** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
+								- I2S_MUTE_ENABLE: enable mute mode
+								- I2S_MUTE_DISABLE: disable mute mode */
+	uint8_t Reserved0[2];
+} I2S_CFG_Type;
+
+/**
+ * @brief I2S DMA configuration structure definition
+ */
+typedef struct {
+	uint8_t DMAIndex;		/** Select DMA1 or DMA2, should be:
+								- I2S_DMA_1: DMA1
+								- I2S_DMA_2: DMA2 */
+	uint8_t depth;			/** FIFO level that triggers a DMA request */
+	uint8_t Reserved0[2];
+}I2S_DMAConf_Type;
+
+/**
+ * @brief I2S mode configuration structure definition
+ */
+typedef struct{
+	uint8_t clksel;			/** Clock source selection, should be:
+								- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
+								- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
+	uint8_t fpin;			/** Select four pin mode, should be:
+								- I2S_4PIN_ENABLE: 4-pin enable
+								- I2S_4PIN_DISABLE: 4-pin disable */
+	uint8_t mcena;			/** Select MCLK mode, should be:
+								- I2S_MCLK_ENABLE: MCLK enable for output
+								- I2S_MCLK_DISABLE: MCLK disable for output */
+	uint8_t Reserved;
+}I2S_MODEConf_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2S_Public_Functions I2S Public Functions
+ * @{
+ */
+/* I2S Init/DeInit functions ---------*/
+void I2S_Init(LPC_I2Sn_Type *I2Sx);
+void I2S_DeInit(LPC_I2Sn_Type *I2Sx);
+
+/* I2S configuration functions --------*/
+void I2S_Config(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
+Status I2S_FreqConfig(LPC_I2Sn_Type *I2Sx, uint32_t Freq, uint8_t TRMode);
+void I2S_SetBitRate(LPC_I2Sn_Type *I2Sx, uint8_t bitrate, uint8_t TRMode);
+void I2S_ModeConfig(LPC_I2Sn_Type *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
+uint8_t I2S_GetLevel(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
+
+/* I2S operate functions -------------*/
+void I2S_Send(LPC_I2Sn_Type *I2Sx, uint32_t BufferData);
+uint32_t I2S_Receive(LPC_I2Sn_Type* I2Sx);
+void I2S_Start(LPC_I2Sn_Type *I2Sx);
+void I2S_Pause(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
+void I2S_Mute(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
+void I2S_Stop(LPC_I2Sn_Type *I2Sx, uint8_t TRMode);
+
+/* I2S DMA functions ----------------*/
+void I2S_DMAConfig(LPC_I2Sn_Type *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
+void I2S_DMACmd(LPC_I2Sn_Type *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
+
+/* I2S IRQ functions ----------------*/
+void I2S_IRQCmd(LPC_I2Sn_Type *I2Sx,uint8_t TRMode, FunctionalState NewState);
+void I2S_IRQConfig(LPC_I2Sn_Type *I2Sx, uint8_t TRMode, uint8_t level);
+FunctionalState I2S_GetIRQStatus(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
+uint8_t I2S_GetIRQDepth(LPC_I2Sn_Type *I2Sx,uint8_t TRMode);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC18XX_I2S_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_lcd.h

@@ -0,0 +1,224 @@
+/**********************************************************************
+* $Id$		lpc18xx_lcd.h		2011-06-02
+*//**
+* @file		lpc18xx_lcd.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for LCD Driver
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup LCD LCD
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC18XX_LCD_H_
+#define __LPC18XX_LCD_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup LCD_Private_Macros LCD Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/* LCD control enable bit */
+#define CLCDC_LCDCTRL_ENABLE    _BIT(0)
+/* LCD control power enable bit */
+#define CLCDC_LCDCTRL_PWR       _BIT(11)
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LCD_Public_Types LCD Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief LCD enumeration
+ **********************************************************************/
+
+/** @brief LCD Interrupt Source */
+typedef enum{
+	LCD_INT_FUF = _BIT(1),		/* FIFO underflow bit */
+	LCD_INT_LNBU = _BIT(2),		/* LCD next base address update bit */
+	LCD_INT_VCOMP = _BIT(3),	/* vertical compare bit */
+	LCD_INT_BER = _BIT(4)		/* AHB master error interrupt bit */
+} LCD_INT_SRC;
+
+/** @brief LCD signal polarity */
+typedef enum {
+	LCD_SIGNAL_ACTIVE_HIGH = 0,
+	LCD_SIGNAL_ACTIVE_LOW = 1
+} LCD_SIGNAL_POLARITY_OPT;
+
+/** @brief LCD clock edge polarity */
+typedef enum {
+	LCD_CLK_RISING = 0,
+	LCD_CLK_FALLING= 1
+} LCD_CLK_EDGE_OPT;
+
+/** @brief LCD bits per pixel and pixel format */
+typedef enum {
+	LCD_BPP1 = 0,
+	LCD_BPP2,
+	LCD_BPP4,
+	LCD_BPP8,
+	LCD_BPP16,
+	LCD_BPP24,
+	LCD_BPP16_565,
+	LCD_BPP12_444
+}LCD_PIXEL_FORMAT_OPT;
+
+/** @brief LCD color format */
+typedef enum {
+	LCD_COLOR_FORMAT_RGB = 0,
+	LCD_COLOR_FORMAT_BGR
+}LCD_COLOR_FORMAT_OPT;
+
+
+/*********************************************************************//**
+ * @brief LCD structure definitions
+ **********************************************************************/
+/** @brief LCD Palette entry format */
+typedef struct
+{
+	uint32_t Rl:5;
+	uint32_t Gl:5;
+	uint32_t Bl:5;
+	uint32_t Il:1;
+	uint32_t Ru:5;
+	uint32_t Gu:5;
+	uint32_t Bu:5;
+	uint32_t Iu:1;
+} LCD_PALETTE_ENTRY_Type;
+
+/** @brief LCD cursor format in 1 byte LBBP */
+typedef struct
+{
+	uint8_t Pixel3:2;
+	uint8_t Pixel2:2;
+	uint8_t Pixel1:2;
+	uint8_t Pixel0:2;
+} LCD_CURSOR_PIXEL_Type;
+
+/** @brief LCD cursor size */
+typedef enum
+{
+	LCD_CURSOR_32x32 = 0,
+	LCD_CURSOR_64x64
+} LCD_CURSOR_SIZE_OPT;
+
+/** @brief LCD panel type */
+typedef enum
+{
+	LCD_TFT = 0x02, 	/* standard TFT */
+	LCD_MONO_4 = 0x01,  /* 4-bit STN mono */
+	LCD_MONO_8 = 0x05,  /* 8-bit STN mono */
+	LCD_CSTN = 0x00     /* color STN */
+} LCD_PANEL_OPT;
+
+/** @brief LCD porch configuration structure */
+typedef struct {
+	uint16_t front;		/* front porch setting in clocks */
+	uint16_t back;		/* back porch setting in clocks */
+}LCD_PORCHCFG_Type;
+
+/** @brief LCD configuration structure */
+typedef struct {
+	uint16_t				screen_width;			/* Pixels per line */
+	uint16_t				screen_height;			/* Lines per panel */
+	LCD_PORCHCFG_Type		horizontal_porch;		/* porch setting for horizontal */
+	LCD_PORCHCFG_Type		vertical_porch;			/* porch setting for vertical */
+	uint16_t				HSync_pulse_width;		/* HSYNC pulse width in clocks */
+	uint16_t				VSync_pulse_width;		/* VSYNC pulse width in clocks */
+	uint8_t         		ac_bias_frequency;    	/* AC bias frequency in clocks */
+	LCD_SIGNAL_POLARITY_OPT	HSync_pol;				/* HSYNC polarity */
+	LCD_SIGNAL_POLARITY_OPT	VSync_pol;				/* VSYNC polarity */
+	LCD_CLK_EDGE_OPT		panel_clk_edge;			/* Panel Clock Edge Polarity */
+	LCD_SIGNAL_POLARITY_OPT	OE_pol;					/* Output Enable polarity */
+	uint32_t				line_end_delay;			/* 0 if not use */
+	LCD_PIXEL_FORMAT_OPT	bits_per_pixel;       	/* Maximum bits per pixel the display supports */
+	LCD_PANEL_OPT     		lcd_panel_type;       	/* LCD panel type */
+	LCD_COLOR_FORMAT_OPT	color_format;			/* BGR or RGB */
+	Bool         			dual_panel;           	/* Dual panel, TRUE = dual panel display */
+	uint16_t				pcd;
+} LCD_CFG_Type;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup LCD_Public_Functions LCD Public Functions
+ * @{
+ */
+
+void LCD_Init(LPC_LCD_Type *LCDx, LCD_CFG_Type *LCD_ConfigStruct);
+void LCD_DeInit(LPC_LCD_Type *LCDx);
+
+void LCD_Power(LPC_LCD_Type *LCDx, FunctionalState OnOff);
+void LCD_Enable(LPC_LCD_Type *LCDx, FunctionalState EnDis);
+void LCD_SetFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
+void LCD_SetLPFrameBuffer(LPC_LCD_Type *LCDx, void* buffer);
+void LCD_LoadPalette(LPC_LCD_Type *LCDx, void* palette);
+void LCD_SetInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
+void LCD_ClrInterrupt(LPC_LCD_Type *LCDx, LCD_INT_SRC Int);
+LCD_INT_SRC LCD_GetInterrupt(LPC_LCD_Type *LCDx);
+
+void LCD_Cursor_Config(LPC_LCD_Type *LCDx, LCD_CURSOR_SIZE_OPT cursor_size, Bool sync);
+void LCD_Cursor_WriteImage(LPC_LCD_Type *LCDx, uint8_t cursor_num, void* Image);
+void* LCD_Cursor_GetImageBufferAddress(LPC_LCD_Type *LCDx, uint8_t cursor_num);
+void LCD_Cursor_Enable(LPC_LCD_Type *LCDx, uint8_t cursor_num, FunctionalState OnOff);
+void LCD_Cursor_LoadPalette0(LPC_LCD_Type *LCDx, uint32_t palette_color);
+void LCD_Cursor_LoadPalette1(LPC_LCD_Type *LCDx, uint32_t palette_color);
+void LCD_Cursor_SetInterrupt(LPC_LCD_Type *LCDx);
+void LCD_Cursor_ClrInterrupt(LPC_LCD_Type *LCDx);
+void LCD_Cursor_SetPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
+void LCD_Cursor_SetClipPos(LPC_LCD_Type *LCDx, uint16_t x, uint16_t y);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC18XX_LCD_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_libcfg_default.h

@@ -0,0 +1,192 @@
+/*
+ * Modified for Code Red tools to prevent redefinition of DEBUG macro
+ * 2011/12/29
+ */
+/**********************************************************************
+* $Id$		lpc18xx_libcfg_default.h		2011-06-02
+*//**
+* @file		lpc18xx_libcfg_default.h
+* @brief	Default Library configuration header file
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Library Configuration group ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_LIBCFG_DEFAULT_H_
+#define LPC18XX_LIBCFG_DEFAULT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
+ * @{
+ */
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+   the "CHECK_PARAM" macro in the FW library code */
+
+#ifndef __CODE_RED
+#define DEBUG
+#endif
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* GPIO ------------------------------- */
+#define _GPIO
+
+/* EXTI ------------------------------- */
+#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+#define _UART3
+
+/* SPI ------------------------------- */
+#define _SPI
+
+/* SYSTICK --------------------------- */
+#define _SYSTICK
+
+/* SSP ------------------------------- */
+#define _SSP
+#define _SSP0
+#define _SSP1
+
+
+/* I2C ------------------------------- */
+#define _I2C
+#define _I2C0
+#define _I2C1
+#define _I2C2
+
+/* TIMER ------------------------------- */
+#define _TIM
+
+/* WWDT ------------------------------- */
+#define _WWDT
+
+
+/* GPDMA ------------------------------- */
+#define _GPDMA
+
+
+/* DAC ------------------------------- */
+#define _DAC
+
+/* DAC ------------------------------- */
+#define _ADC
+
+
+/* PWM ------------------------------- */
+#define _PWM
+#define _PWM1
+
+/* RTC ------------------------------- */
+#define _RTC
+
+/* I2S ------------------------------- */
+#define _I2S
+
+/* USB device ------------------------------- */
+#define _USBDEV
+#define _USB_DMA
+
+/* QEI ------------------------------- */
+#define _QEI
+
+/* MCPWM ------------------------------- */
+#define _MCPWM
+
+/* CAN--------------------------------*/
+#define _C_CAN
+
+/* RIT ------------------------------- */
+#define _RIT
+
+/* EMAC ------------------------------ */
+#define _EMAC
+
+/* SCT ------------------------------ */
+#define _SCT
+
+/* LCD ------------------------------ */
+#define _LCD
+
+/* ATIMER ------------------------------ */
+#define _ATIMER
+
+/* RGU ------------------------------ */
+#define _RGU
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef  DEBUG
+/*******************************************************************************
+* @brief		The CHECK_PARAM macro is used for function's parameters check.
+* 				It is used only if the library is compiled in DEBUG mode.
+* @param[in]	expr - If expr is false, it calls check_failed() function
+*                    	which reports the name of the source file and the source
+*                    	line number of the call that failed.
+*                    - If expr is true, it returns no value.
+* @return		None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
+ * @{
+ */
+
+#ifdef  DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LPC18XX_LIBCFG_DEFAULT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_mcpwm.h

@@ -0,0 +1,338 @@
+/**********************************************************************
+* $Id$		lpc18xx_mcpwm.h		2011-06-02
+*//**
+* @file		lpc18xx_mcpwm.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for Motor Control PWM firmware library on LPC18XX
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup MCPWM MCPWM (Motor Control PWM)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_MCPWM_H_
+#define LPC18XX_MCPWM_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
+ * @{
+ */
+/** Edge aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_EDGE_MODE			((uint32_t)(0))
+/** Center aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_CENTER_MODE		((uint32_t)(1))
+
+/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
+#define MCPWM_CHANNEL_PASSIVE_LO		((uint32_t)(0))
+/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
+#define MCPWM_CHANNEL_PASSIVE_HI		((uint32_t)(1))
+
+/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
+ * the six output pins under the control of the bits in this register */
+#define MCPWM_PATENT_A0		((uint32_t)(1<<0))	/**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_PATENT_B0		((uint32_t)(1<<1))	/**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_PATENT_A1		((uint32_t)(1<<2))	/**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_PATENT_B1		((uint32_t)(1<<3))	/**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_PATENT_A2		((uint32_t)(1<<4))	/**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_PATENT_B2		((uint32_t)(1<<5))	/**< MCOB2 tracks internal MCOA0 */
+
+/* Interrupt type in MCPWM */
+/** Limit interrupt for channel (0) */
+#define MCPWM_INTFLAG_LIM0	MCPWM_INT_ILIM(0)
+/** Match interrupt for channel (0) */
+#define MCPWM_INTFLAG_MAT0	MCPWM_INT_IMAT(0)
+/** Capture interrupt for channel (0) */
+#define MCPWM_INTFLAG_CAP0	MCPWM_INT_ICAP(0)
+
+/** Limit interrupt for channel (1) */
+#define MCPWM_INTFLAG_LIM1	MCPWM_INT_ILIM(1)
+/** Match interrupt for channel (1) */
+#define MCPWM_INTFLAG_MAT1	MCPWM_INT_IMAT(1)
+/** Capture interrupt for channel (1) */
+#define MCPWM_INTFLAG_CAP1	MCPWM_INT_ICAP(1)
+
+/** Limit interrupt for channel (2) */
+#define MCPWM_INTFLAG_LIM2	MCPWM_INT_ILIM(2)
+/** Match interrupt for channel (2) */
+#define MCPWM_INTFLAG_MAT2	MCPWM_INT_IMAT(2)
+/** Capture interrupt for channel (2) */
+#define MCPWM_INTFLAG_CAP2	MCPWM_INT_ICAP(2)
+
+/** Fast abort interrupt */
+#define MCPWM_INTFLAG_ABORT	MCPWM_INT_ABORT
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Control register
+ **********************************************************************/
+/* MCPWM Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Control read address
+ * - MCPWM Control set address
+ * - MCPWM Control clear address
+ */
+/**< Stops/starts timer channel n */
+#define MCPWM_CON_RUN(n)		(((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))
+/**< Edge/center aligned operation for channel n */
+#define MCPWM_CON_CENTER(n)		(((n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))
+/**< Select polarity of the MCOAn and MCOBn pin */
+#define MCPWM_CON_POLAR(n)		(((n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))
+/**< Control the dead-time feature for channel n */
+#define MCPWM_CON_DTE(n)		(((n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))
+/**< Enable/Disable update of functional register for channel n */
+#define MCPWM_CON_DISUP(n)		(((n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))
+/**< Control the polarity for all 3 channels */
+#define MCPWM_CON_INVBDC		((uint32_t)(1<<29))
+/**< 3-phase AC mode select */
+#define MCPWM_CON_ACMODE		((uint32_t)(1<<30))
+/**< 3-phase DC mode select */
+#define MCPWM_CON_DCMODE		(((uint32_t)1<<31))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture Control register
+ **********************************************************************/
+/* Capture Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Capture Control read address
+ * - MCPWM Capture Control set address
+ * - MCPWM Capture control clear address
+ */
+/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_RE(cap,mci)	(((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
+/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_FE(cap,mci)	(((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
+/** TC(n) is reset by channel (n) capture event */
+#define MCPWM_CAPCON_RT(n)				(((n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
+/** Hardware noise filter: channel (n) capture events are delayed */
+#define MCPWM_CAPCON_HNFCAP(n)			(((n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Interrupt register
+ **********************************************************************/
+/* Interrupt registers, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Interrupt Enable read address
+ * - MCPWM Interrupt Enable set address
+ * - MCPWM Interrupt Enable clear address
+ * - MCPWM Interrupt Flags read address
+ * - MCPWM Interrupt Flags set address
+ * - MCPWM Interrupt Flags clear address
+ */
+/** Limit interrupt for channel (n) */
+#define MCPWM_INT_ILIM(n)	(((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
+/** Match interrupt for channel (n) */
+#define MCPWM_INT_IMAT(n)	(((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
+/** Capture interrupt for channel (n) */
+#define MCPWM_INT_ICAP(n)	(((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
+/** Fast abort interrupt */
+#define MCPWM_INT_ABORT		((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Count Control register
+ **********************************************************************/
+/* MCPWM Count Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Count Control read address
+ * - MCPWM Count Control set address
+ * - MCPWM Count Control clear address
+ */
+/** Counter(tc) advances on a rising edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_RE(tc,mci)	(((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
+/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_FE(tc,mci)	(((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
+/** Channel (n) is in counter mode */
+#define MCPWM_CNTCON_CNTR(n)			(((n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Dead-time register
+ **********************************************************************/
+/** Dead time value x for channel n */
+#define MCPWM_DT(n,x)		(((n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Communication Pattern register
+ **********************************************************************/
+#define MCPWM_CP_A0		((uint32_t)(1<<0))	/**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_CP_B0		((uint32_t)(1<<1))	/**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_CP_A1		((uint32_t)(1<<2))	/**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_CP_B1		((uint32_t)(1<<3))	/**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_CP_A2		((uint32_t)(1<<4))	/**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_CP_B2		((uint32_t)(1<<5))	/**< MCOB2 tracks internal MCOA0 */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture clear address register
+ **********************************************************************/
+/** Clear the MCCAP (n) register */
+#define MCPWM_CAPCLR_CAP(n)		(((n<=2)) ? ((uint32_t)(1<<n)) : (0))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Types MCPWM Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief MCPWM enumeration
+ **********************************************************************/
+/**
+ * @brief	MCPWM channel identifier definition
+ */
+typedef enum
+{
+	MCPWM_CHANNEL_0 = 0,		/**< MCPWM channel 0 */
+	MCPWM_CHANNEL_1,			/**< MCPWM channel 1 */
+	MCPWM_CHANNEL_2				/**< MCPWM channel 2 */
+} en_MCPWM_Channel_Id;
+
+
+/*********************************************************************//**
+ * @brief MCPWM structure definitions
+ **********************************************************************/
+/**
+ * @brief Motor Control PWM Channel Configuration structure type definition
+ */
+typedef struct {
+	uint32_t channelType;					/**< Edge/center aligned mode for this channel,
+												should be:
+												- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
+												- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
+												*/
+	uint32_t channelPolarity;				/**< Polarity of the MCOA and MCOB pins, should be:
+												- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
+												- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
+												*/
+	uint32_t channelDeadtimeEnable;			/**< Enable/Disable DeadTime function for channel, should be:
+												- ENABLE.
+												- DISABLE.
+												*/
+	uint32_t channelDeadtimeValue;			/**< DeadTime value, should be less than 0x3FF */
+	uint32_t channelUpdateEnable;			/**< Enable/Disable updates of functional registers,
+												 should be:
+												- ENABLE.
+												- DISABLE.
+												*/
+	uint32_t channelTimercounterValue;		/**< MCPWM Timer Counter value */
+	uint32_t channelPeriodValue;			/**< MCPWM Period value */
+	uint32_t channelPulsewidthValue;		/**< MCPWM Pulse Width value */
+} MCPWM_CHANNEL_CFG_Type;
+
+/**
+ * @brief MCPWM Capture Configuration type definition
+ */
+typedef struct {
+	uint32_t captureChannel;		/**< Capture Channel Number, should be in range from 0 to 2 */
+	uint32_t captureRising;			/**< Enable/Disable Capture on Rising Edge event, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+	uint32_t captureFalling;		/**< Enable/Disable Capture on Falling Edge event, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+	uint32_t timerReset;			/**< Enable/Disable Timer reset function an capture, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+	uint32_t hnfEnable;				/**< Enable/Disable Hardware noise filter function, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+} MCPWM_CAPTURE_CFG_Type;
+
+
+/**
+ * @brief MCPWM Count Control Configuration type definition
+ */
+typedef struct {
+	uint32_t counterChannel;		/**< Counter Channel Number, should be in range from 0 to 2 */
+	uint32_t countRising;			/**< Enable/Disable Capture on Rising Edge event, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+	uint32_t countFalling;		/**< Enable/Disable Capture on Falling Edge event, should be:
+										- ENABLE.
+										- DISABLE.
+										*/
+} MCPWM_COUNT_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
+ * @{
+ */
+
+void MCPWM_Init(LPC_MCPWM_Type *MCPWMx);
+void MCPWM_ConfigChannel(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
+						MCPWM_CHANNEL_CFG_Type * channelSetup);
+void MCPWM_WriteToShadow(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
+						MCPWM_CHANNEL_CFG_Type *channelSetup);
+void MCPWM_ConfigCapture(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
+						MCPWM_CAPTURE_CFG_Type *captureConfig);
+void MCPWM_ClearCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
+uint32_t MCPWM_GetCapture(LPC_MCPWM_Type *MCPWMx, uint32_t captureChannel);
+void MCPWM_CountConfig(LPC_MCPWM_Type *MCPWMx, uint32_t channelNum,
+					uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
+void MCPWM_Start(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_Stop(LPC_MCPWM_Type *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_ACMode(LPC_MCPWM_Type *MCPWMx,uint32_t acMode);
+void MCPWM_DCMode(LPC_MCPWM_Type *MCPWMx, uint32_t dcMode,
+					uint32_t outputInvered, uint32_t outputPattern);
+void MCPWM_IntConfig(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
+void MCPWM_IntSet(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
+void MCPWM_IntClear(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
+FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_Type *MCPWMx, uint32_t ulIntType);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_MCPWM_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_nvic.h

@@ -0,0 +1,68 @@
+/**********************************************************************
+* $Id$		lpc18xx_nvic.h		2011-06-02
+*//**
+* @file		lpc18xx_nvic.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for Nesting Vectored Interrupt firmware library
+* 			on LPC18XX
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup NVIC NVIC (Nested Vector Interrupt Controller)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_NVIC_H_
+#define LPC18XX_NVIC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup NVIC_Public_Functions NVIC Public Functions
+ * @{
+ */
+
+void NVIC_SetVTOR(uint32_t offset);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_NVIC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_pwr.h

@@ -0,0 +1,83 @@
+/**********************************************************************
+* $Id$		lpc18xx_pwr.h		2011-06-02
+*//**
+* @file		lpc18xx_pwr.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for Power Control firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PWR PWR (Power Control)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_PWR_H_
+#define LPC18XX_PWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PWR_Private_Macros PWR Private Macros
+ * @{
+ */
+#define PWR_SLEEP_MODE_DEEP_SLEEP	0x3F00AA
+#define PWR_SLEEP_MODE_POWER_DOWN	0x30FCBA
+#define PWR_SLEEP_MODE_DEEP_POWER_DOWN	0x3FFF7F
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PWR_Public_Functions PWR Public Functions
+ * @{
+ */
+/* Clock Generator */
+void PWR_Sleep(void);
+void PWR_DeepSleep(void);
+void PWR_PowerDown(void);
+void PWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_PWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_qei.h

@@ -0,0 +1,426 @@
+/**********************************************************************
+* $Id$		lpc18xx_qei.h		2011-06-02
+*//**
+* @file		lpc18xx_qei.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for QEI firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup QEI QEI (Quadrature Encoder Interface)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_QEI_H_
+#define LPC18XX_QEI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup QEI_Private_Macros QEI Private Macros
+ * @{
+ */
+
+/** QEI peripheral numver definition */
+#define QEI_0					(0)					/** Always 0 - because we just have only one QEI peripheral */
+
+/** QEI Reset types */
+#define QEI_RESET_POS			QEI_CON_RESP		/**< Reset position counter */
+#define QEI_RESET_POSOnIDX		QEI_CON_RESPI		/**< Reset Posistion Counter on Index */
+#define QEI_RESET_VEL			QEI_CON_RESV		/**< Reset Velocity */
+#define QEI_RESET_IDX			QEI_CON_RESI		/**< Reset Index Counter */
+
+/** QEI Direction Invert Type Option */
+#define QEI_DIRINV_NONE		((uint32_t)(0))			/**< Direction is not inverted */
+#define QEI_DIRINV_CMPL		((uint32_t)(1))			/**< Direction is complemented */
+
+/** QEI Signal Mode Option */
+#define QEI_SIGNALMODE_QUAD		((uint32_t)(0))		/**< Signal operation: Quadrature phase mode */
+#define QEI_SIGNALMODE_CLKDIR	((uint32_t)(1))		/**< Signal operation: Clock/Direction mode */
+
+/** QEI Capture Mode Option */
+#define QEI_CAPMODE_2X			((uint32_t)(0))		/**< Capture mode: Only Phase-A edges are counted (2X) */
+#define QEI_CAPMODE_4X			((uint32_t)(1))		/**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
+
+/** QEI Invert Index Signal Option */
+#define QEI_INVINX_NONE			((uint32_t)(0))		/**< Invert Index signal option: None */
+#define QEI_INVINX_EN			((uint32_t)(1))		/**< Invert Index signal option: Enable */
+
+/** QEI timer reload option */
+#define QEI_TIMERRELOAD_TICKVAL	((uint8_t)(0))		/**< Reload value in absolute value */
+#define QEI_TIMERRELOAD_USVAL	((uint8_t)(1))		/**< Reload value in microsecond value */
+
+/** QEI Flag Status type */
+#define QEI_STATUS_DIR			((uint32_t)(1<<0))	/**< Direction status */
+
+/** QEI Compare Position channel option */
+#define QEI_COMPPOS_CH_0			((uint8_t)(0))		/**< QEI compare position channel 0 */
+#define QEI_COMPPOS_CH_1			((uint8_t)(1))		/**< QEI compare position channel 1 */
+#define QEI_COMPPOS_CH_2			((uint8_t)(2))		/**< QEI compare position channel 2 */
+
+/** QEI interrupt flag type */
+#define QEI_INTFLAG_INX_Int			((uint32_t)(1<<0))	/**< index pulse was detected interrupt */
+#define QEI_INTFLAG_TIM_Int			((uint32_t)(1<<1))	/**< Velocity timer over flow interrupt */
+#define QEI_INTFLAG_VELC_Int		((uint32_t)(1<<2))	/**< Capture velocity is less than compare interrupt */
+#define QEI_INTFLAG_DIR_Int			((uint32_t)(1<<3))	/**< Change of direction interrupt */
+#define QEI_INTFLAG_ERR_Int			((uint32_t)(1<<4))	/**< An encoder phase error interrupt */
+#define QEI_INTFLAG_ENCLK_Int		((uint32_t)(1<<5))	/**< An encoder clock pulse was detected interrupt */
+#define QEI_INTFLAG_POS0_Int		((uint32_t)(1<<6))	/**< position 0 compare value is equal to the
+														current position interrupt */
+#define QEI_INTFLAG_POS1_Int		((uint32_t)(1<<7))	/**< position 1 compare value is equal to the
+														current position interrupt */
+#define QEI_INTFLAG_POS2_Int		((uint32_t)(1<<8))	/**< position 2 compare value is equal to the
+														current position interrupt */
+#define QEI_INTFLAG_REV_Int			((uint32_t)(1<<9))	/**< Index compare value is equal to the current
+														index count interrupt */
+#define QEI_INTFLAG_POS0REV_Int		((uint32_t)(1<<10))	/**< Combined position 0 and revolution count interrupt */
+#define QEI_INTFLAG_POS1REV_Int		((uint32_t)(1<<11))	/**< Combined position 1 and revolution count interrupt */
+#define QEI_INTFLAG_POS2REV_Int		((uint32_t)(1<<12))	/**< Combined position 2 and revolution count interrupt */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/* Quadrature Encoder Interface Control Register Definition --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Control register
+ **********************************************************************/
+#define QEI_CON_RESP		((uint32_t)(1<<0))		/**< Reset position counter */
+#define QEI_CON_RESPI		((uint32_t)(1<<1))		/**< Reset Posistion Counter on Index */
+#define QEI_CON_RESV		((uint32_t)(1<<2))		/**< Reset Velocity */
+#define QEI_CON_RESI		((uint32_t)(1<<3))		/**< Reset Index Counter */
+#define QEI_CON_BITMASK		((uint32_t)(0x0F))		/**< QEI Control register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Configuration register
+ **********************************************************************/
+#define QEI_CONF_DIRINV		((uint32_t)(1<<0))		/**< Direction Invert */
+#define QEI_CONF_SIGMODE	((uint32_t)(1<<1))		/**< Signal mode */
+#define QEI_CONF_CAPMODE	((uint32_t)(1<<2))		/**< Capture mode */
+#define QEI_CONF_INVINX		((uint32_t)(1<<3))		/**< Invert index */
+#define QEI_CONF_BITMASK	((uint32_t)(0x0F))		/**< QEI Configuration register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Status register
+ **********************************************************************/
+#define QEI_STAT_DIR		((uint32_t)(1<<0))		/**< Direction bit */
+#define QEI_STAT_BITMASK	((uint32_t)(1<<0))		/**< QEI status register bit-mask */
+
+/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Status register
+ **********************************************************************/
+#define QEI_INTSTAT_INX_Int			((uint32_t)(1<<0))	/**< Indicates that an index pulse was detected */
+#define QEI_INTSTAT_TIM_Int			((uint32_t)(1<<1))	/**< Indicates that a velocity timer overflow occurred */
+#define QEI_INTSTAT_VELC_Int		((uint32_t)(1<<2))	/**< Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSTAT_DIR_Int			((uint32_t)(1<<3))	/**< Indicates that a change of direction was detected */
+#define QEI_INTSTAT_ERR_Int			((uint32_t)(1<<4))	/**< Indicates that an encoder phase error was detected */
+#define QEI_INTSTAT_ENCLK_Int		((uint32_t)(1<<5))	/**< Indicates that and encoder clock pulse was detected */
+#define QEI_INTSTAT_POS0_Int		((uint32_t)(1<<6))	/**< Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_INTSTAT_POS1_Int		((uint32_t)(1<<7))	/**< Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_INTSTAT_POS2_Int		((uint32_t)(1<<8))	/**< Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_INTSTAT_REV_Int			((uint32_t)(1<<9))	/**< Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_INTSTAT_POS0REV_Int		((uint32_t)(1<<10))	/**< Combined position 0 and revolution count interrupt. Set when
+														both the POS0_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS1REV_Int		((uint32_t)(1<<11))	/**< Combined position 1 and revolution count interrupt. Set when
+														both the POS1_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS2REV_Int		((uint32_t)(1<<12))	/**< Combined position 2 and revolution count interrupt. Set when
+														both the POS2_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_BITMASK			((uint32_t)(0x1FFF))	/**< QEI Interrupt Status register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Set register
+ **********************************************************************/
+#define QEI_INTSET_INX_Int			((uint32_t)(1<<0))	/**< Set Bit Indicates that an index pulse was detected */
+#define QEI_INTSET_TIM_Int			((uint32_t)(1<<1))	/**< Set Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTSET_VELC_Int			((uint32_t)(1<<2))	/**< Set Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSET_DIR_Int			((uint32_t)(1<<3))	/**< Set Bit Indicates that a change of direction was detected */
+#define QEI_INTSET_ERR_Int			((uint32_t)(1<<4))	/**< Set Bit Indicates that an encoder phase error was detected */
+#define QEI_INTSET_ENCLK_Int		((uint32_t)(1<<5))	/**< Set Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTSET_POS0_Int			((uint32_t)(1<<6))	/**< Set Bit Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_INTSET_POS1_Int			((uint32_t)(1<<7))	/**< Set Bit Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_INTSET_POS2_Int			((uint32_t)(1<<8))	/**< Set Bit Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_INTSET_REV_Int			((uint32_t)(1<<9))	/**< Set Bit Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_INTSET_POS0REV_Int		((uint32_t)(1<<10))	/**< Set Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTSET_POS1REV_Int		((uint32_t)(1<<11))	/**< Set Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTSET_POS2REV_Int		((uint32_t)(1<<12))	/**< Set Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTSET_BITMASK			((uint32_t)(0x1FFF))	/**< QEI Interrupt Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Clear register
+ **********************************************************************/
+#define QEI_INTCLR_INX_Int			((uint32_t)(1<<0))	/**< Clear Bit Indicates that an index pulse was detected */
+#define QEI_INTCLR_TIM_Int			((uint32_t)(1<<1))	/**< Clear Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTCLR_VELC_Int			((uint32_t)(1<<2))	/**< Clear Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTCLR_DIR_Int			((uint32_t)(1<<3))	/**< Clear Bit Indicates that a change of direction was detected */
+#define QEI_INTCLR_ERR_Int			((uint32_t)(1<<4))	/**< Clear Bit Indicates that an encoder phase error was detected */
+#define QEI_INTCLR_ENCLK_Int		((uint32_t)(1<<5))	/**< Clear Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTCLR_POS0_Int			((uint32_t)(1<<6))	/**< Clear Bit Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_INTCLR_POS1_Int			((uint32_t)(1<<7))	/**< Clear Bit Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_INTCLR_POS2_Int			((uint32_t)(1<<8))	/**< Clear Bit Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_INTCLR_REV_Int			((uint32_t)(1<<9))	/**< Clear Bit Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_INTCLR_POS0REV_Int		((uint32_t)(1<<10))	/**< Clear Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTCLR_POS1REV_Int		((uint32_t)(1<<11))	/**< Clear Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTCLR_POS2REV_Int		((uint32_t)(1<<12))	/**< Clear Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTCLR_BITMASK			((uint32_t)(0xFFFF))	/**< QEI Interrupt Clear register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable register
+ **********************************************************************/
+#define QEI_INTEN_INX_Int			((uint32_t)(1<<0))	/**< Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_INTEN_TIM_Int			((uint32_t)(1<<1))	/**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTEN_VELC_Int			((uint32_t)(1<<2))	/**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTEN_DIR_Int			((uint32_t)(1<<3))	/**< Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_INTEN_ERR_Int			((uint32_t)(1<<4))	/**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_INTEN_ENCLK_Int			((uint32_t)(1<<5))	/**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTEN_POS0_Int			((uint32_t)(1<<6))	/**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_INTEN_POS1_Int			((uint32_t)(1<<7))	/**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_INTEN_POS2_Int			((uint32_t)(1<<8))	/**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_INTEN_REV_Int			((uint32_t)(1<<9))	/**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_INTEN_POS0REV_Int		((uint32_t)(1<<10))	/**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTEN_POS1REV_Int		((uint32_t)(1<<11))	/**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTEN_POS2REV_Int		((uint32_t)(1<<12))	/**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTEN_BITMASK			((uint32_t)(0x1FFF))	/**< QEI Interrupt Enable register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Set register
+ **********************************************************************/
+#define QEI_IESET_INX_Int			((uint32_t)(1<<0))	/**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IESET_TIM_Int			((uint32_t)(1<<1))	/**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IESET_VELC_Int			((uint32_t)(1<<2))	/**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IESET_DIR_Int			((uint32_t)(1<<3))	/**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IESET_ERR_Int			((uint32_t)(1<<4))	/**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IESET_ENCLK_Int			((uint32_t)(1<<5))	/**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IESET_POS0_Int			((uint32_t)(1<<6))	/**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_IESET_POS1_Int			((uint32_t)(1<<7))	/**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_IESET_POS2_Int			((uint32_t)(1<<8))	/**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_IESET_REV_Int			((uint32_t)(1<<9))	/**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_IESET_POS0REV_Int		((uint32_t)(1<<10))	/**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IESET_POS1REV_Int		((uint32_t)(1<<11))	/**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IESET_POS2REV_Int		((uint32_t)(1<<12))	/**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IESET_BITMASK			((uint32_t)(0x1FFF))	/**< QEI Interrupt Enable Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Clear register
+ **********************************************************************/
+#define QEI_IECLR_INX_Int			((uint32_t)(1<<0))	/**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IECLR_TIM_Int			((uint32_t)(1<<1))	/**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IECLR_VELC_Int			((uint32_t)(1<<2))	/**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IECLR_DIR_Int			((uint32_t)(1<<3))	/**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IECLR_ERR_Int			((uint32_t)(1<<4))	/**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IECLR_ENCLK_Int			((uint32_t)(1<<5))	/**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IECLR_POS0_Int			((uint32_t)(1<<6))	/**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+														current position */
+#define QEI_IECLR_POS1_Int			((uint32_t)(1<<7))	/**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+														current position */
+#define QEI_IECLR_POS2_Int			((uint32_t)(1<<8))	/**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+														current position */
+#define QEI_IECLR_REV_Int			((uint32_t)(1<<9))	/**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+														index count */
+#define QEI_IECLR_POS0REV_Int		((uint32_t)(1<<10))	/**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IECLR_POS1REV_Int		((uint32_t)(1<<11))	/**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IECLR_POS2REV_Int		((uint32_t)(1<<12))	/**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IECLR_BITMASK			((uint32_t)(0xFFFF))	/**< QEI Interrupt Enable Clear register bit-mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macro check QEI peripheral */
+#define PARAM_QEIx(n)	((n==LPC_QEI))
+
+/* Macro check QEI reset type */
+#define PARAM_QEI_RESET(n)	((n==QEI_CON_RESP) \
+|| (n==QEI_RESET_POSOnIDX) \
+|| (n==QEI_RESET_VEL) \
+|| (n==QEI_RESET_IDX))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_DIRINV(n)	((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
+
+/* Macro check QEI signal mode */
+#define PARAM_QEI_SIGNALMODE(n)	((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
+
+/* Macro check QEI Capture mode */
+#define PARAM_QEI_CAPMODE(n)	((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
+
+/* Macro check QEI Invert index mode */
+#define PARAM_QEI_INVINX(n)		((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_TIMERRELOAD(n)	((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
+
+/* Macro check QEI status type */
+#define PARAM_QEI_STATUS(n)		((n==QEI_STATUS_DIR))
+
+/* Macro check QEI combine position type */
+#define PARAM_QEI_COMPPOS_CH(n)		((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
+
+/* Macro check QEI interrupt flag type */
+#define PARAM_QEI_INTFLAG(n)	((n==QEI_INTFLAG_INX_Int) \
+|| (n==QEI_INTFLAG_TIM_Int) \
+|| (n==QEI_INTFLAG_VELC_Int) \
+|| (n==QEI_INTFLAG_DIR_Int) \
+|| (n==QEI_INTFLAG_ERR_Int) \
+|| (n==QEI_INTFLAG_ENCLK_Int) \
+|| (n==QEI_INTFLAG_POS0_Int) \
+|| (n==QEI_INTFLAG_POS1_Int) \
+|| (n==QEI_INTFLAG_POS2_Int) \
+|| (n==QEI_INTFLAG_REV_Int) \
+|| (n==QEI_INTFLAG_POS0REV_Int) \
+|| (n==QEI_INTFLAG_POS1REV_Int) \
+|| (n==QEI_INTFLAG_POS2REV_Int))
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup QEI_Public_Types QEI Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief QEI structure definitions
+ **********************************************************************/
+/**
+ * @brief QEI Configuration structure type definition
+ */
+typedef struct {
+	uint32_t DirectionInvert	:1; 	/**< Direction invert option:
+										- QEI_DIRINV_NONE: QEI Direction is normal
+										- QEI_DIRINV_CMPL: QEI Direction is complemented
+										*/
+	uint32_t SignalMode			:1; 	/**< Signal mode Option:
+										- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
+										- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
+										*/
+	uint32_t CaptureMode		:1;		/**< Capture Mode Option:
+										- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
+										- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
+										*/
+	uint32_t InvertIndex		:1; 	/**< Invert Index Option:
+										- QEI_INVINX_NONE: the sense of the index input is normal
+										- QEI_INVINX_EN: inverts the sense of the index input
+										*/
+} QEI_CFG_Type;
+
+/**
+ * @brief Timer Reload Configuration structure type definition
+ */
+typedef struct {
+
+	uint8_t ReloadOption;		/**< Velocity Timer Reload Option, should be:
+								- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
+								- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
+								*/
+	uint8_t Reserved[3];
+	uint32_t ReloadValue;		/**< Velocity Timer Reload Value, 32-bit long, should be matched
+								with Velocity Timer Reload Option
+								*/
+} QEI_RELOADCFG_Type;
+
+typedef struct
+{
+	uint32_t PHA_FilterVal;		/**< FILTERPHA register input */
+	uint32_t PHB_FilterVal;		/**< FILTERPHB register input */
+	uint32_t INX_FilterVal;		/**< FILTERINX register input */
+} st_Qei_FilterCfg;
+
+
+/**
+ * @}
+ */
+
+
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup QEI_Public_Functions QEI Public Functions
+ * @{
+ */
+
+void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
+void QEI_DeInit(uint8_t qeiId);
+
+void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
+void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
+FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
+uint32_t QEI_GetPosition(uint8_t qeiId);
+void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
+void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
+uint32_t QEI_GetIndex(uint8_t qeiId);
+void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
+void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
+uint32_t QEI_GetTimer(uint8_t qeiId);
+uint32_t QEI_GetVelocity(uint8_t qeiId);
+uint32_t QEI_GetVelocityCap(uint8_t qeiId);
+void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
+void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
+uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
+
+FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
+void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
+void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
+void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
+
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_QEI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rgu.h

@@ -0,0 +1,139 @@
+/**********************************************************************
+* $Id$		lpc18xx_rgu.h		2011-06-02
+*//**
+* @file		lpc18xx_rgu.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for RGU firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RGU RGU (Reset Generation Unit)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_RGU_H_
+#define LPC18XX_RGU_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup RGU_Public_Types RGU Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief RGU enumeration
+ **********************************************************************/
+/** @brief Out Reset Signal Generated by RGU */
+typedef enum
+{
+	RGU_SIG_CORE  = 0,					/**< Core reset signal 			*/
+	RGU_SIG_PERIPH,						/**< Peripheral reset signal	*/
+	RGU_SIG_MASTER,						/**< Master reset signal		*/
+	RGU_SIG_WWDT = 4,					/**< WWDT reset signal			*/
+	RGU_SIG_CREG,						/**< CREG reset signal			*/
+	RGU_SIG_BUS = 8,					/**< Bus reset signal			*/
+	RGU_SIG_SCU,						/**< SCU reset signal			*/
+	RGU_SIG_PINMUX,						/**< Pin mux reset signal		*/
+	RGU_SIG_M3 = 13,					/**< Cortex-M3 reset signal		*/
+	RGU_SIG_LCD = 16,					/**< LCD reset signal			*/
+	RGU_SIG_USB0,						/**< USB0 reset signal			*/
+	RGU_SIG_USB1,						/**< USB1 reset signal			*/
+	RGU_SIG_DMA,						/**< DMA reset signal			*/
+	RGU_SIG_SDIO,						/**< SDIO reset signal			*/
+	RGU_SIG_EMC,						/**< EMC reset signal			*/
+	RGU_SIG_ETHERNET,					/**< Ethernet reset signal		*/
+	RGU_SIG_AES,						/**< AES reset signal			*/
+	RGU_SIG_GPIO = 28,					/**< GPIO reset signal			*/
+	RGU_SIG_TIMER0 = 32,				/**< TIMER 0 reset signal		*/
+	RGU_SIG_TIMER1,						/**< TIMER 1 reset signal		*/
+	RGU_SIG_TIMER2,						/**< TIMER 2 reset signal		*/
+	RGU_SIG_TIMER3,						/**< TIMER 3 reset signal		*/
+	RGU_SIG_RITIMER,					/**< RIT timer reset signal		*/
+	RGU_SIG_SCT,						/**< SCT reset signal			*/
+	RGU_SIG_MOTOCONPWM,					/**< Motor control reset signal	*/
+	RGU_SIG_QEI,						/**< QEI reset signal			*/
+	RGU_SIG_ADC0,						/**< ADC0 reset signal			*/
+	RGU_SIG_ADC1,						/**< ADC1 reset signal			*/
+	RGU_SIG_DAC,						/**< DAC reset signal			*/
+	RGU_SIG_UART0 = 44,					/**< UART0 reset signal			*/
+	RGU_SIG_UART1,						/**< UART1 reset signal			*/
+	RGU_SIG_UART2,						/**< UART2 reset signal			*/
+	RGU_SIG_UART3,						/**< UART3 reset signal			*/
+	RGU_SIG_I2C0,						/**< I2C0 reset signal			*/
+	RGU_SIG_I2C1,						/**< I2C1 reset signal			*/
+	RGU_SIG_SSP0,						/**< SSP0 reset signal			*/
+	RGU_SIG_SSP1,						/**< SSP1 reset signal			*/
+	RGU_SIG_I2S,						/**< I2S reset signal			*/
+	RGU_SIG_SPIFI,						/**< SPIFI reset signal			*/
+	RGU_SIG_CAN = 55					/**< CAN reset signal			*/
+}RGU_SIG;
+
+/** @brief Reset Cause Source */
+typedef enum {
+	RGU_SRC_NONE,						/**< No source				*/
+	RGU_SRC_SOFT,						/**< Software reset source	*/
+	RGU_SRC_EXT,						/**< External reset source	*/
+	RGU_SRC_CORE,						/**< Core reset source		*/
+	RGU_SRC_PERIPH,						/**< Peripheral reset source*/
+	RGU_SRC_MASTER,						/**< Master reset source	*/
+	RGU_SRC_BOD,						/**< BOD reset source		*/
+	RGU_SRC_WWDT						/**< WWDT reset source		*/
+}RGU_SRC;
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RGU_Public_Functions RGU Public Functions
+ * @{
+ */
+/* RGU peripheral control function ----------------*/
+void RGU_SoftReset(RGU_SIG ResetSignal);
+RGU_SRC RGU_GetSource(RGU_SIG ResetSignal);
+Bool RGU_GetSignalStatus(RGU_SIG ResetSignal);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC18XX_RGU_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rit.h

@@ -0,0 +1,106 @@
+/**********************************************************************
+* $Id$		lpc18xx_rit.h		2011-06-02
+*//**
+* @file		lpc18xx_rit.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for RIT firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RIT RIT (Repetitive Interrupt Timer)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_RIT_H_
+#define LPC18XX_RIT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RIT_Private_Macros RIT Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RIT control register
+ **********************************************************************/
+/**	Set interrupt flag when the counter value equals the masked compare value */
+#define RIT_CTRL_INTEN	((uint32_t) (1))
+/** Set timer enable clear to 0 when the counter value equals the masked compare value  */
+#define RIT_CTRL_ENCLR 	((uint32_t) _BIT(1))
+/** Set timer enable on debug */
+#define RIT_CTRL_ENBR	((uint32_t) _BIT(2))
+/** Set timer enable */
+#define RIT_CTRL_TEN	((uint32_t) _BIT(3))
+
+/** Macro to determine if it is valid RIT peripheral */
+#define PARAM_RITx(n)	(((uint32_t *)n)==((uint32_t *)LPC_RITIMER))
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RIT_Public_Functions RIT Public Functions
+ * @{
+ */
+/* RIT Init/DeInit functions */
+void RIT_Init(LPC_RITIMER_Type *RITx);
+void RIT_DeInit(LPC_RITIMER_Type *RITx);
+
+/* RIT config timer functions */
+void RIT_TimerConfig(LPC_RITIMER_Type *RITx, uint32_t time_interval);
+
+/* Enable/Disable RIT functions */
+void RIT_TimerClearCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
+void RIT_Cmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
+void RIT_TimerDebugCmd(LPC_RITIMER_Type *RITx, FunctionalState NewState);
+
+/* RIT Interrupt functions */
+IntStatus RIT_GetIntStatus(LPC_RITIMER_Type *RITx);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_RIT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_rtc.h

@@ -0,0 +1,322 @@
+/**********************************************************************
+* $Id$		lpc18xx_rtc.h		2011-06-02
+*//**
+* @file		lpc18xx_rtc.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for RTC firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RTC RTC (Real-Time Clock)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_RTC_H_
+#define LPC18XX_RTC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/* ----------------------- BIT DEFINITIONS ----------------------------------- */
+/* Miscellaneous register group --------------------------------------------- */
+/**********************************************************************
+* ILR register definitions
+**********************************************************************/
+/** ILR register mask */
+#define RTC_ILR_BITMASK			((0x00000003))
+/** Bit inform the source interrupt is counter increment*/
+#define RTC_IRL_RTCCIF			((1<<0))
+/** Bit inform the source interrupt is alarm match*/
+#define RTC_IRL_RTCALF			((1<<1))
+
+/**********************************************************************
+* CCR register definitions
+**********************************************************************/
+/** CCR register mask */
+#define RTC_CCR_BITMASK			((0x00000013))
+/** Clock enable */
+#define RTC_CCR_CLKEN			((1<<0))
+/** Clock reset */
+#define RTC_CCR_CTCRST			((1<<1))
+/** Calibration counter enable */
+#define RTC_CCR_CCALEN			((1<<4))
+
+/**********************************************************************
+* CIIR register definitions
+**********************************************************************/
+/** Counter Increment Interrupt bit for second */
+#define RTC_CIIR_IMSEC			((1<<0))
+/** Counter Increment Interrupt bit for minute */
+#define RTC_CIIR_IMMIN			((1<<1))
+/** Counter Increment Interrupt bit for hour */
+#define RTC_CIIR_IMHOUR			((1<<2))
+/** Counter Increment Interrupt bit for day of month */
+#define RTC_CIIR_IMDOM			((1<<3))
+/** Counter Increment Interrupt bit for day of week */
+#define RTC_CIIR_IMDOW			((1<<4))
+/** Counter Increment Interrupt bit for day of year */
+#define RTC_CIIR_IMDOY			((1<<5))
+/** Counter Increment Interrupt bit for month */
+#define RTC_CIIR_IMMON			((1<<6))
+/** Counter Increment Interrupt bit for year */
+#define RTC_CIIR_IMYEAR			((1<<7))
+/** CIIR bit mask */
+#define RTC_CIIR_BITMASK		((0xFF))
+
+/**********************************************************************
+* AMR register definitions
+**********************************************************************/
+/** Counter Increment Select Mask bit for second */
+#define RTC_AMR_AMRSEC			((1<<0))
+/** Counter Increment Select Mask bit for minute */
+#define RTC_AMR_AMRMIN			((1<<1))
+/** Counter Increment Select Mask bit for hour */
+#define RTC_AMR_AMRHOUR			((1<<2))
+/** Counter Increment Select Mask bit for day of month */
+#define RTC_AMR_AMRDOM			((1<<3))
+/** Counter Increment Select Mask bit for day of week */
+#define RTC_AMR_AMRDOW			((1<<4))
+/** Counter Increment Select Mask bit for day of year */
+#define RTC_AMR_AMRDOY			((1<<5))
+/** Counter Increment Select Mask bit for month */
+#define RTC_AMR_AMRMON			((1<<6))
+/** Counter Increment Select Mask bit for year */
+#define RTC_AMR_AMRYEAR			((1<<7))
+/** AMR bit mask */
+#define RTC_AMR_BITMASK			((0xFF))
+
+/**********************************************************************
+* RTC_AUX register definitions
+**********************************************************************/
+/** RTC Oscillator Fail detect flag */
+#define RTC_AUX_RTC_OSCF		((1<<4))
+
+/**********************************************************************
+* RTC_AUXEN register definitions
+**********************************************************************/
+/** Oscillator Fail Detect interrupt enable*/
+#define RTC_AUXEN_RTC_OSCFEN	((1<<4))
+
+/* Consolidated time register group ----------------------------------- */
+/**********************************************************************
+* Consolidated Time Register 0 definitions
+**********************************************************************/
+#define RTC_CTIME0_SECONDS_MASK		((0x3F))
+#define RTC_CTIME0_MINUTES_MASK		((0x3F00))
+#define RTC_CTIME0_HOURS_MASK		((0x1F0000))
+#define RTC_CTIME0_DOW_MASK			((0x7000000))
+
+/**********************************************************************
+* Consolidated Time Register 1 definitions
+**********************************************************************/
+#define RTC_CTIME1_DOM_MASK			((0x1F))
+#define RTC_CTIME1_MONTH_MASK		((0xF00))
+#define RTC_CTIME1_YEAR_MASK		((0xFFF0000))
+
+/**********************************************************************
+* Consolidated Time Register 2 definitions
+**********************************************************************/
+#define RTC_CTIME2_DOY_MASK			((0xFFF))
+
+/**********************************************************************
+* Time Counter Group and Alarm register group
+**********************************************************************/
+/** SEC register mask */
+#define RTC_SEC_MASK			(0x0000003F)
+/** MIN register mask */
+#define RTC_MIN_MASK			(0x0000003F)
+/** HOUR register mask */
+#define RTC_HOUR_MASK			(0x0000001F)
+/** DOM register mask */
+#define RTC_DOM_MASK			(0x0000001F)
+/** DOW register mask */
+#define RTC_DOW_MASK			(0x00000007)
+/** DOY register mask */
+#define RTC_DOY_MASK			(0x000001FF)
+/** MONTH register mask */
+#define RTC_MONTH_MASK			(0x0000000F)
+/** YEAR register mask */
+#define RTC_YEAR_MASK			(0x00000FFF)
+
+#define RTC_SECOND_MAX		59 /*!< Maximum value of second */
+#define RTC_MINUTE_MAX		59 /*!< Maximum value of minute*/
+#define RTC_HOUR_MAX		23 /*!< Maximum value of hour*/
+#define RTC_MONTH_MIN		1 /*!< Minimum value of month*/
+#define RTC_MONTH_MAX		12 /*!< Maximum value of month*/
+#define RTC_DAYOFMONTH_MIN 	1 /*!< Minimum value of day of month*/
+#define RTC_DAYOFMONTH_MAX 	31 /*!< Maximum value of day of month*/
+#define RTC_DAYOFWEEK_MAX	6 /*!< Maximum value of day of week*/
+#define RTC_DAYOFYEAR_MIN	1 /*!< Minimum value of day of year*/
+#define RTC_DAYOFYEAR_MAX	366 /*!< Maximum value of day of year*/
+#define RTC_YEAR_MAX		4095 /*!< Maximum value of year*/
+
+/**********************************************************************
+* Calibration register
+**********************************************************************/
+/* Calibration register */
+/** Calibration value */
+#define RTC_CALIBRATION_CALVAL_MASK		((0x1FFFF))
+/** Calibration direction */
+#define RTC_CALIBRATION_LIBDIR			((1<<17))
+/** Calibration max value */
+#define RTC_CALIBRATION_MAX				((0x20000))
+/** Calibration definitions */
+#define RTC_CALIB_DIR_FORWARD			((uint8_t)(0))
+#define RTC_CALIB_DIR_BACKWARD			((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid RTC peripheral */
+#define PARAM_RTCx(x)	(((uint32_t *)x)==((uint32_t *)LPC_RTC))
+
+/* Macro check RTC interrupt type */
+#define PARAM_RTC_INT(n)	((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
+
+/* Macro check RTC time type */
+#define PARAM_RTC_TIMETYPE(n)	((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
+|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
+|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
+|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
+
+/* Macro check RTC calibration type */
+#define PARAM_RTC_CALIB_DIR(n)	((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
+
+/* Macro check RTC GPREG type */
+#define PARAM_RTC_GPREG_CH(n)	((n<=63))
+
+/* RTC GPREG base address*/
+#define RTC_GPREG_BASE		0x40041000
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup RTC_Public_Types RTC Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief RTC enumeration
+ **********************************************************************/
+/** @brief RTC interrupt source */
+typedef enum {
+	RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, 	/*!<  Counter Increment Interrupt */
+	RTC_INT_ALARM = RTC_IRL_RTCALF 				/*!< The alarm interrupt */
+} RTC_INT_OPT;
+
+
+/** @brief RTC time type option */
+typedef enum {
+	RTC_TIMETYPE_SECOND = 0, 		/*!< Second */
+	RTC_TIMETYPE_MINUTE = 1, 		/*!< Month */
+	RTC_TIMETYPE_HOUR = 2, 			/*!< Hour */
+	RTC_TIMETYPE_DAYOFWEEK = 3, 	/*!< Day of week */
+	RTC_TIMETYPE_DAYOFMONTH = 4, 	/*!< Day of month */
+	RTC_TIMETYPE_DAYOFYEAR = 5, 	/*!< Day of year */
+	RTC_TIMETYPE_MONTH = 6, 		/*!< Month */
+	RTC_TIMETYPE_YEAR = 7 			/*!< Year */
+} RTC_TIMETYPE_Num;
+
+
+/*********************************************************************//**
+ * @brief RTC structure definitions
+ **********************************************************************/
+/** @brief Time structure definitions for easy manipulate the data */
+typedef struct {
+	uint32_t SEC; 		/*!< Seconds Register */
+	uint32_t MIN; 		/*!< Minutes Register */
+	uint32_t HOUR; 		/*!< Hours Register */
+	uint32_t DOM;		/*!< Day of Month Register */
+	uint32_t DOW; 		/*!< Day of Week Register */
+	uint32_t DOY; 		/*!< Day of Year Register */
+	uint32_t MONTH; 	/*!< Months Register */
+	uint32_t YEAR; 		/*!< Years Register */
+} RTC_TIME_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RTC_Public_Functions RTC Public Functions
+ * @{
+ */
+
+void RTC_Init (LPC_RTC_Type *RTCx);
+void RTC_DeInit(LPC_RTC_Type *RTCx);
+
+void RTC_ResetClockTickCounter(LPC_RTC_Type *RTCx);
+void RTC_Cmd (LPC_RTC_Type *RTCx, FunctionalState NewState);
+
+void RTC_SetTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t TimeValue);
+uint32_t RTC_GetTime(LPC_RTC_Type *RTCx, uint32_t Timetype);
+
+void RTC_SetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
+
+void RTC_AlarmIntConfig (LPC_RTC_Type *RTCx, uint32_t AlarmTimeType, FunctionalState NewState);
+void RTC_SetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype, uint32_t ALValue);
+uint32_t RTC_GetAlarmTime (LPC_RTC_Type *RTCx, uint32_t Timetype);
+void RTC_SetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullAlarmTime (LPC_RTC_Type *RTCx, RTC_TIME_Type *pFullTime);
+
+void RTC_CntIncrIntConfig (LPC_RTC_Type *RTCx, uint32_t CntIncrIntType, FunctionalState NewState);
+IntStatus RTC_GetIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
+void RTC_ClearIntPending (LPC_RTC_Type *RTCx, uint32_t IntType);
+
+void RTC_CalibCounterCmd(LPC_RTC_Type *RTCx, FunctionalState NewState);
+void RTC_CalibConfig(LPC_RTC_Type *RTCx, uint32_t CalibValue, uint8_t CalibDir);
+
+void RTC_WriteGPREG (LPC_RTC_Type *RTCx, uint8_t Channel, uint32_t Value);
+uint32_t RTC_ReadGPREG (LPC_RTC_Type *RTCx, uint8_t Channel);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_RTC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_sct.h

@@ -0,0 +1,142 @@
+/**********************************************************************
+* $Id$		lpc18xx_sct.h		2011-06-02
+*//**
+* @file		lpc18xx_sct.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for SCT firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SCT SCT (State Configurable Timer)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_SCT_H_
+#define LPC18XX_SCT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup SCT_Private_Macros SCT Private Macros
+ * @{
+ */
+
+/* -------------------------- BIT DEFINITIONS ----------------------------------- */
+/*********************************************************************//**
+ * Macro defines for SCT  configuration register
+ **********************************************************************/
+/**  Selects 16/32 bit counter */
+#define SCT_CONFIG_16BIT_COUNTER		0x00000000
+#define SCT_CONFIG_32BIT_COUNTER		0x00000001
+
+/*********************************************************************//**
+ * Macro defines for SCT control register
+ **********************************************************************/
+/**  Stop low counter */
+#define SCT_CTRL_STOP_L					(1<<1)
+/**  Halt low counter */
+#define SCT_CTRL_HALT_L					(1<<2)
+/**  Clear low or unified counter */
+#define SCT_CTRL_CLRCTR_L				(1<<3)
+/**  Direction for low or unified counter */
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO		0
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO	1
+#define SCT_CTRL_BIDIR_L(x)				(((x)&0x01)<<4)
+/**  Prescale clock for low or unified counter */
+#define SCT_CTRL_PRE_L(x)				(((x)&0xFF)<<5)
+
+/**  Stop high counter */
+#define SCT_CTRL_STOP_H					(1<<17)
+/**  Halt high counter */
+#define SCT_CTRL_HALT_H					(1<<18)
+/**  Clear high counter */
+#define SCT_CTRL_CLRCTR_H				(1<<19)
+/**  Direction for high counter */
+#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO		0
+#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO	1
+#define SCT_CTRL_BIDIR_H(x)				(((x)&0x01)<<20)
+/**  Prescale clock for high counter */
+#define SCT_CTRL_PRE_H(x)				(((x)&0xFF)<<21)
+/*********************************************************************//**
+ * Macro defines for SCT Conflict resolution register
+**********************************************************************/
+/**  Define conflict solution */
+#define SCT_RES_NOCHANGE				(0)
+#define SCT_RES_SET_OUTPUT				(1)
+#define SCT_RES_CLEAR_OUTPUT			(2)
+#define SCT_RES_TOGGLE_OUTPUT			(3)
+
+/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
+/** Check SCT output number */
+#define PARAM_SCT_OUTPUT_NUM(n)    ((n)<= CONFIG_SCT_nOU )
+
+/** Check SCT counter type */
+#define PARAM_SCT_CONFIG_COUNTER_TYPE(n)    ((n==SCT_CONFIG_16BIT_COUNTER)||(n==SCT_CONFIG_32BIT_COUNTER))
+
+/** Check SCT conflict solution */
+#define PARAM_SCT_RES(n)    ((n==SCT_RES_NOCHANGE)||(n==SCT_RES_SET_OUTPUT)\
+								||(n==SCT_RES_CLEAR_OUTPUT)||(n==SCT_RES_TOGGLE_OUTPUT))
+
+/** Check SCT event number */
+#define PARAM_SCT_EVENT(n)	((n) <= 15)
+
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SCT_Public_Functions SCT Public Functions
+ * @{
+ */
+
+void SCT_Config(uint32_t value);
+void SCT_ControlSet(uint32_t value, FunctionalState ena);
+void SCT_ConflictResolutionSet(uint8_t outnum, uint8_t value);
+void SCT_EventFlagClear(uint8_t even_num);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC18XX_SCT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_scu.h

@@ -0,0 +1,101 @@
+/**********************************************************************
+* $Id$		lpc18xx_scu.h		2011-06-02
+*//**
+* @file		lpc18xx_scu.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for SCU firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SCU	SCU (System Control Unit)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __SCU_H
+#define __SCU_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup SCT_Private_Macros SCT Private Macros
+ * @{
+ */
+
+/** Port offset definition */
+#define PORT_OFFSET 	0x80
+/** Pin offset definition */
+#define PIN_OFFSET  	0x04
+
+/* Pin modes */
+#define MD_PUP  (0x0<<3)
+#define MD_BUK  (0x1<<3)
+#define MD_PLN  (0x2<<3)
+#define MD_PDN  (0x3<<3)
+#define MD_EHS  (0x1<<5)
+#define MD_EZI  (0x1<<6)
+#define MD_ZI   (0x1<<7)
+#define MD_EHD0 (0x1<<8)
+#define MD_EHD1 (0x1<<8)
+#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
+// 0xF0
+
+/* Pin function */
+#define FUNC0 			0x0				/** Function 0 	*/
+#define FUNC1 			0x1				/** Function 1 	*/
+#define FUNC2 			0x2				/** Function 2	*/
+#define FUNC3 			0x3				/** Function 3	*/
+#define FUNC4			0x4
+#define FUNC5			0x5
+#define FUNC6			0x6
+#define FUNC7			0x7
+/**
+ * @}
+ */
+
+#define LPC_SCU_PIN(po, pi)   (*(volatile int         *) (LPC_SCU_BASE + ((po) * 0x80) + ((pi) * 0x4))    )
+#define LPC_SCU_CLK(c)        (*(volatile int         *) (LPC_SCU_BASE + 0xC00 + ((c) * 0x4))    )
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SCU_Public_Functions SCU Public Functions
+ * @{
+ */
+
+void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end __SCU_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_ssp.h

@@ -0,0 +1,446 @@
+/**********************************************************************
+* $Id$		lpc18xx_ssp.h		2011-06-02
+*//**
+* @file		lpc18xx_ssp.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for SSP firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SSP SSP (Synchronous Serial Port)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC18XX_SSP_H_
+#define LPC18XX_SSP_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup SSP_Private_Macros SSP Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * SSP configuration parameter defines
+ **********************************************************************/
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST			((uint32_t)(0))
+#define SSP_CPHA_SECOND			SSP_CR0_CPHA_SECOND
+
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI				((uint32_t)(0))
+#define SSP_CPOL_LO				SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE			SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE			((uint32_t)(0))
+
+/** SSP data bit number defines */
+#define SSP_DATABIT_4		SSP_CR0_DSS(4) 			/*!< Databit number = 4 */
+#define SSP_DATABIT_5		SSP_CR0_DSS(5) 			/*!< Databit number = 5 */
+#define SSP_DATABIT_6		SSP_CR0_DSS(6) 			/*!< Databit number = 6 */
+#define SSP_DATABIT_7		SSP_CR0_DSS(7) 			/*!< Databit number = 7 */
+#define SSP_DATABIT_8		SSP_CR0_DSS(8) 			/*!< Databit number = 8 */
+#define SSP_DATABIT_9		SSP_CR0_DSS(9) 			/*!< Databit number = 9 */
+#define SSP_DATABIT_10		SSP_CR0_DSS(10) 		/*!< Databit number = 10 */
+#define SSP_DATABIT_11		SSP_CR0_DSS(11) 		/*!< Databit number = 11 */
+#define SSP_DATABIT_12		SSP_CR0_DSS(12) 		/*!< Databit number = 12 */
+#define SSP_DATABIT_13		SSP_CR0_DSS(13) 		/*!< Databit number = 13 */
+#define SSP_DATABIT_14		SSP_CR0_DSS(14) 		/*!< Databit number = 14 */
+#define SSP_DATABIT_15		SSP_CR0_DSS(15) 		/*!< Databit number = 15 */
+#define SSP_DATABIT_16		SSP_CR0_DSS(16) 		/*!< Databit number = 16 */
+
+/** SSP Frame Format definition */
+/** Motorola SPI mode */
+#define SSP_FRAME_SPI		SSP_CR0_FRF_SPI
+/** TI synchronous serial mode */
+#define SSP_FRAME_TI		SSP_CR0_FRF_TI
+/** National Micro-wire mode */
+#define SSP_FRAME_MICROWIRE	SSP_CR0_FRF_MICROWIRE
+
+/*********************************************************************//**
+ * SSP Status defines
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_STAT_TXFIFO_EMPTY		SSP_SR_TFE
+/** SSP status TX FIFO not full bit */
+#define SSP_STAT_TXFIFO_NOTFULL		SSP_SR_TNF
+/** SSP status RX FIFO not empty bit */
+#define SSP_STAT_RXFIFO_NOTEMPTY	SSP_SR_RNE
+/** SSP status RX FIFO full bit */
+#define SSP_STAT_RXFIFO_FULL		SSP_SR_RFF
+/** SSP status SSP Busy bit */
+#define SSP_STAT_BUSY				SSP_SR_BSY
+
+/*********************************************************************//**
+ * SSP Interrupt Configuration defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTCFG_ROR		SSP_IMSC_ROR
+/** Receive TimeOut */
+#define SSP_INTCFG_RT		SSP_IMSC_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTCFG_RX		SSP_IMSC_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTCFG_TX		SSP_IMSC_TX
+
+/*********************************************************************//**
+ * SSP Configured Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_ROR		SSP_MIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RT		SSP_MIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RX		SSP_MIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_TX		SSP_MIS_TX
+
+/*********************************************************************//**
+ * SSP Raw Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_RAW_ROR		SSP_RIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RAW_RT		SSP_RIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RAW_RX		SSP_RIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_RAW_TX		SSP_RIS_TX
+
+/*********************************************************************//**
+ * SSP Interrupt Clear defines
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_INTCLR_ROR		SSP_ICR_ROR
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_INTCLR_RT		SSP_ICR_RT
+
+/*********************************************************************//**
+ * SSP DMA defines
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_TX		SSP_DMA_RXDMA_EN
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_RX		SSP_DMA_TXDMA_EN
+
+/* SSP Status Implementation definitions */
+#define SSP_STAT_DONE		(1UL<<8)		/**< Done */
+#define SSP_STAT_ERROR		(1UL<<9)		/**< Error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for CR0 register
+ **********************************************************************/
+/** SSP data size select, must be 4 bits to 16 bits */
+#define SSP_CR0_DSS(n)   		((uint32_t)((n-1)&0xF))
+/** SSP control 0 Motorola SPI mode */
+#define SSP_CR0_FRF_SPI  		((uint32_t)(0<<4))
+/** SSP control 0 TI synchronous serial mode */
+#define SSP_CR0_FRF_TI   		((uint32_t)(1<<4))
+/** SSP control 0 National Micro-wire mode */
+#define SSP_CR0_FRF_MICROWIRE  	((uint32_t)(2<<4))
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
+   bus clock high between frames, (0) = low */
+#define SSP_CR0_CPOL_HI		((uint32_t)(1<<6))
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
+   on the second clock transition of the frame, (0) = first */
+#define SSP_CR0_CPHA_SECOND	((uint32_t)(1<<7))
+/** SSP serial clock rate value load macro, divider rate is
+   PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n)   	((uint32_t)((n&0xFF)<<8))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK		((uint32_t)(0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CR1 register
+ **********************************************************************/
+/** SSP control 1 loopback mode enable bit */
+#define SSP_CR1_LBM_EN		((uint32_t)(1<<0))
+/** SSP control 1 enable bit */
+#define SSP_CR1_SSP_EN		((uint32_t)(1<<1))
+/** SSP control 1 slave enable */
+#define SSP_CR1_SLAVE_EN	((uint32_t)(1<<2))
+/** SSP control 1 slave out disable bit, disables transmit line in slave
+   mode */
+#define SSP_CR1_SO_DISABLE	((uint32_t)(1<<3))
+/** SSP CR1 bit mask */
+#define SSP_CR1_BITMASK		((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for DR register
+ **********************************************************************/
+/** SSP data bit mask */
+#define SSP_DR_BITMASK(n)   ((n)&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for SR register
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_SR_TFE      ((uint32_t)(1<<0))
+/** SSP status TX FIFO not full bit */
+#define SSP_SR_TNF      ((uint32_t)(1<<1))
+/** SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE      ((uint32_t)(1<<2))
+/** SSP status RX FIFO full bit */
+#define SSP_SR_RFF      ((uint32_t)(1<<3))
+/** SSP status SSP Busy bit */
+#define SSP_SR_BSY      ((uint32_t)(1<<4))
+/** SSP SR bit mask */
+#define SSP_SR_BITMASK	((uint32_t)(0x1F))
+
+/*********************************************************************//**
+ * Macro defines for CPSR register
+ **********************************************************************/
+/** SSP clock prescaler */
+#define SSP_CPSR_CPDVSR(n) 	((uint32_t)(n&0xFF))
+/** SSP CPSR bit mask */
+#define SSP_CPSR_BITMASK	((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro define for (IMSC) Interrupt Mask Set/Clear registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_IMSC_ROR	((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_IMSC_RT		((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_IMSC_RX		((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_IMSC_TX		((uint32_t)(1<<3))
+/** IMSC bit mask */
+#define SSP_IMSC_BITMASK	((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (RIS) Raw Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_RIS_ROR		((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_RIS_RT		((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_RIS_RX		((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_RIS_TX		((uint32_t)(1<<3))
+/** RIS bit mask */
+#define SSP_RIS_BITMASK	((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (MIS) Masked Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_MIS_ROR		((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_MIS_RT		((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_MIS_RX		((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_MIS_TX		((uint32_t)(1<<3))
+/** MIS bit mask */
+#define SSP_MIS_BITMASK	((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (ICR) Interrupt Clear registers
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_ICR_ROR		((uint32_t)(1<<0))
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_ICR_RT		((uint32_t)(1<<1))
+/** ICR bit mask */
+#define SSP_ICR_BITMASK	((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMACR register
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_RXDMA_EN  	((uint32_t)(1<<0))
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_TXDMA_EN  	((uint32_t)(1<<1))
+/** DMACR	bit mask */
+#define SSP_DMA_BITMASK		((uint32_t)(0x03))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_SSPx(n)	((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
+
+/** Macro check clock phase control mode */
+#define PARAM_SSP_CPHA(n) 		((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
+
+/** Macro check clock polarity mode */
+#define PARAM_SSP_CPOL(n)		((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
+
+/* Macro check master/slave mode */
+#define PARAM_SSP_MODE(n)		((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
+
+/* Macro check databit value */
+#define PARAM_SSP_DATABIT(n) 	((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
+|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
+|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
+|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
+|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
+|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
+|| (n==SSP_DATABIT_15))
+
+/* Macro check frame type */
+#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
+|| (n==SSP_FRAME_MICROWIRE))
+
+/* Macro check SSP status */
+#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
+|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
+|| (n==SSP_STAT_BUSY))
+
+/* Macro check interrupt configuration */
+#define PARAM_SSP_INTCFG(n)	((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
+|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
+
+/* Macro check interrupt status value */
+#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
+|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
+
+/* Macro check interrupt status raw value */
+#define PARAM_SSP_INTSTAT_RAW(n)	((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
+|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
+
+/* Macro check interrupt clear mode */
+#define PARAM_SSP_INTCLR(n)	((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
+
+/* Macro check DMA mode */
+#define PARAM_SSP_DMA(n)	((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup SSP_Public_Types SSP Public Types
+ * @{
+ */
+
+/** @brief SSP configuration structure */
+typedef struct {
+	uint32_t Databit; 		/** Databit number, should be SSP_DATABIT_x,
+							where x is in range from 4 - 16 */
+	uint32_t CPHA;			/** Clock phase, should be:
+								- SSP_CPHA_FIRST: first clock edge
+								- SSP_CPHA_SECOND: second clock edge */
+	uint32_t CPOL;			/** Clock polarity, should be:
+								- SSP_CPOL_HI: high level
+								- SSP_CPOL_LO: low level */
+	uint32_t Mode;			/** SSP mode, should be:
+								- SSP_MASTER_MODE: Master mode
+								- SSP_SLAVE_MODE: Slave mode */
+	uint32_t FrameFormat;	/** Frame Format:
+								- SSP_FRAME_SPI: Motorola SPI frame format
+								- SSP_FRAME_TI: TI frame format
+								- SSP_FRAME_MICROWIRE: National Microwire frame format */
+	uint32_t ClockRate;		/** Clock rate,in Hz */
+} SSP_CFG_Type;
+
+/**
+ * @brief SSP Transfer Type definitions
+ */
+typedef enum {
+	SSP_TRANSFER_POLLING = 0,	/**< Polling transfer */
+	SSP_TRANSFER_INTERRUPT		/**< Interrupt transfer */
+} SSP_TRANSFER_Type;
+
+/**
+ * @brief SPI Data configuration structure definitions
+ */
+typedef struct {
+	void *tx_data;				/**< Pointer to transmit data */
+	uint32_t tx_cnt;			/**< Transmit counter */
+	void *rx_data;				/**< Pointer to transmit data */
+	uint32_t rx_cnt;			/**< Receive counter */
+	uint32_t length;			/**< Length of transfer data */
+	uint32_t status;			/**< Current status of SSP activity */
+} SSP_DATA_SETUP_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SSP_Public_Functions SSP Public Functions
+ * @{
+ */
+
+void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
+void SSP_DeInit(LPC_SSPn_Type* SSPx);
+
+void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
+void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
+void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
+void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
+void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);
+uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);
+int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
+						SSP_TRANSFER_Type xfType);
+FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);
+uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);
+void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);
+IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);
+IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);
+void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);
+void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_timer.h

@@ -0,0 +1,352 @@
+/**********************************************************************
+* $Id$		lpc18xx_timer.h		2011-06-02
+*//**
+* @file		lpc18xx_timer.h
+* @brief	Contains all functions support for Timer firmware library
+* 			on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup TIMER TIMER
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC18XX_TIMER_H_
+#define __LPC18XX_TIMER_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup TIMER_Private_Macros TIMER Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/**********************************************************************
+** Interrupt information
+**********************************************************************/
+/** Macro to clean interrupt pending */
+#define TIM_IR_CLR(n) _BIT(n)
+
+/**********************************************************************
+** Timer interrupt register definitions
+**********************************************************************/
+/** Macro for getting a timer match interrupt bit */
+#define TIM_MATCH_INT(n)		(_BIT(n & 0x0F))
+/** Macro for getting a capture event interrupt bit */
+#define TIM_CAP_INT(n)     (_BIT(((n & 0x0F) + 4)))
+
+/**********************************************************************
+* Timer control register definitions
+**********************************************************************/
+/** Timer/counter enable bit */
+#define TIM_ENABLE			((uint32_t)(1<<0))
+/** Timer/counter reset bit */
+#define TIM_RESET			((uint32_t)(1<<1))
+/** Timer control bit mask */
+#define TIM_TCR_MASKBIT		((uint32_t)(3))
+
+/**********************************************************************
+* Timer match control register definitions
+**********************************************************************/
+/** Bit location for interrupt on MRx match, n = 0 to 3 */
+#define TIM_INT_ON_MATCH(n)      	(_BIT((n * 3)))
+/** Bit location for reset on MRx match, n = 0 to 3 */
+#define TIM_RESET_ON_MATCH(n)    	(_BIT(((n * 3) + 1)))
+/** Bit location for stop on MRx match, n = 0 to 3 */
+#define TIM_STOP_ON_MATCH(n)     	(_BIT(((n * 3) + 2)))
+/** Timer Match control bit mask */
+#define TIM_MCR_MASKBIT			   ((uint32_t)(0x0FFF))
+/** Timer Match control bit mask for specific channel*/
+#define	TIM_MCR_CHANNEL_MASKBIT(n)		((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer capture control register definitions
+**********************************************************************/
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
+#define TIM_CAP_RISING(n)   	(_BIT((n * 3)))
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
+#define TIM_CAP_FALLING(n)   	(_BIT(((n * 3) + 1)))
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
+#define TIM_INT_ON_CAP(n)    	(_BIT(((n * 3) + 2)))
+/** Mask bit for rising and falling edge bit */
+#define TIM_EDGE_MASK(n)		(_SBF((n * 3), 0x03))
+/** Timer capture control bit mask */
+#define TIM_CCR_MASKBIT			((uint32_t)(0x3F))
+/** Timer Capture control bit mask for specific channel*/
+#define	TIM_CCR_CHANNEL_MASKBIT(n)		((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer external match register definitions
+**********************************************************************/
+/** Bit location for output state change of MAT.n when external match
+   happens, n = 0 to 3 */
+#define TIM_EM(n)    			_BIT(n)
+/** Output state change of MAT.n when external match happens: no change */
+#define TIM_EM_NOTHING    	((uint8_t)(0x0))
+/** Output state change of MAT.n when external match happens: low */
+#define TIM_EM_LOW         	((uint8_t)(0x1))
+/** Output state change of MAT.n when external match happens: high */
+#define TIM_EM_HIGH        	((uint8_t)(0x2))
+/** Output state change of MAT.n when external match happens: toggle */
+#define TIM_EM_TOGGLE      	((uint8_t)(0x3))
+/** Macro for setting for the MAT.n change state bits */
+#define TIM_EM_SET(n,s) 	(_SBF(((n << 1) + 4), (s & 0x03)))
+/** Mask for the MAT.n change state bits */
+#define TIM_EM_MASK(n) 		(_SBF(((n << 1) + 4), 0x03))
+/** Timer external match bit mask */
+#define TIM_EMR_MASKBIT	0x0FFF
+
+/**********************************************************************
+* Timer Count Control Register definitions
+**********************************************************************/
+/** Mask to get the Counter/timer mode bits */
+#define TIM_CTCR_MODE_MASK  0x3
+/** Mask to get the count input select bits */
+#define TIM_CTCR_INPUT_MASK 0xC
+/** Timer Count control bit mask */
+#define TIM_CTCR_MASKBIT	0xF
+#define TIM_COUNTER_MODE ((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid TIMER peripheral */
+#define PARAM_TIMx(n)	((((uint32_t *)n)==((uint32_t *)LPC_TIMER0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER1)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_TIMER2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIMER3)))
+
+/* Macro check interrupt type */
+#define PARAM_TIM_INT_TYPE(TYPE)	((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\
+||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\
+||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT)\
+||(TYPE ==TIM_CR2_INT)||(TYPE ==TIM_CR3_INT))
+
+/* Macro check TIMER mode */
+#define PARAM_TIM_MODE_OPT(MODE)	((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\
+|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))
+
+/* Macro check TIMER prescale value */
+#define PARAM_TIM_PRESCALE_OPT(OPT)	((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))
+
+/* Macro check TIMER counter intput mode */
+#define PARAM_TIM_COUNTER_INPUT_OPT(OPT)	((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1)\
+											||(OPT == TIM_COUNTER_INCAP2)||(OPT == TIM_COUNTER_INCAP3))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_EXTMATCH_OPT(OPT)	((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\
+||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_CAP_MODE_OPT(OPT)	((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \
+||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup TIMER_Public_Types TIMER Public Types
+ * @{
+ */
+
+/***********************************************************************
+ * @brief Timer device enumeration
+**********************************************************************/
+/** @brief interrupt type */
+typedef enum
+{
+	TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
+	TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
+	TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
+	TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
+	TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
+	TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
+	TIM_CR2_INT =6, /*!< interrupt for Capture channel 1*/
+	TIM_CR3_INT =7 /*!< interrupt for Capture channel 1*/
+}TIM_INT_TYPE;
+
+/** @brief Timer/counter operating mode */
+typedef enum
+{
+	TIM_TIMER_MODE = 0,				/*!< Timer mode */
+	TIM_COUNTER_RISING_MODE,		/*!< Counter rising mode */
+	TIM_COUNTER_FALLING_MODE,		/*!< Counter falling mode */
+	TIM_COUNTER_ANY_MODE			/*!< Counter on both edges */
+} TIM_MODE_OPT;
+
+/** @brief Timer/Counter prescale option */
+typedef enum
+{
+	TIM_PRESCALE_TICKVAL = 0,		/*!< Prescale in absolute value */
+	TIM_PRESCALE_USVAL				/*!< Prescale in microsecond value */
+} TIM_PRESCALE_OPT;
+
+/** @brief Counter input option */
+typedef enum
+{
+	TIM_COUNTER_INCAP0 = 0,			/*!< CAPn.0 input pin for TIMERn */
+	TIM_COUNTER_INCAP1,				/*!< CAPn.1 input pin for TIMERn */
+	TIM_COUNTER_INCAP2,				/*!< CAPn.2 input pin for TIMERn */
+	TIM_COUNTER_INCAP3				/*!< CAPn.3 input pin for TIMERn */
+} TIM_COUNTER_INPUT_OPT;
+
+/** @brief Timer/Counter external match option */
+typedef enum
+{
+	TIM_EXTMATCH_NOTHING = 0,		/*!< Do nothing for external output pin if match */
+	TIM_EXTMATCH_LOW,				/*!< Force external output pin to low if match */
+	TIM_EXTMATCH_HIGH,				/*!< Force external output pin to high if match */
+	TIM_EXTMATCH_TOGGLE				/*!< Toggle external output pin if match */
+}TIM_EXTMATCH_OPT;
+
+/** @brief Timer/counter capture mode options */
+typedef enum {
+	TIM_CAPTURE_NONE = 0,	/*!< No Capture */
+	TIM_CAPTURE_RISING,		/*!< Rising capture mode */
+	TIM_CAPTURE_FALLING,	/*!< Falling capture mode */
+	TIM_CAPTURE_ANY			/*!< On both edges */
+} TIM_CAP_MODE_OPT;
+
+/***********************************************************************
+ * @brief Timer structure definitions
+**********************************************************************/
+/** @brief Configuration structure in TIMER mode */
+typedef struct
+{
+
+	uint8_t PrescaleOption;		/**< Timer Prescale option, should be:
+									- TIM_PRESCALE_TICKVAL: Prescale in absolute value
+									- TIM_PRESCALE_USVAL: Prescale in microsecond value
+									*/
+	uint8_t Reserved[3];		/**< Reserved */
+	uint32_t PrescaleValue;		/**< Prescale value */
+} TIM_TIMERCFG_Type;
+
+/** @brief Configuration structure in COUNTER mode */
+typedef struct {
+
+	uint8_t CounterOption;		/**< Counter Option, should be:
+									- TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
+									- TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
+								*/
+	uint8_t CountInputSelect;
+	uint8_t Reserved[2];
+} TIM_COUNTERCFG_Type;
+
+/** @brief Match channel configuration structure */
+typedef struct {
+	uint8_t MatchChannel;	/**< Match channel, should be in range
+							from 0..3 */
+	uint8_t IntOnMatch;		/**< Interrupt On match, should be:
+								- ENABLE: Enable this function.
+								- DISABLE: Disable this function.
+							*/
+	uint8_t StopOnMatch;	/**< Stop On match, should be:
+								- ENABLE: Enable this function.
+								- DISABLE: Disable this function.
+							*/
+	uint8_t ResetOnMatch;	/**< Reset On match, should be:
+								- ENABLE: Enable this function.
+								- DISABLE: Disable this function.
+							*/
+
+	uint8_t ExtMatchOutputType;	/**< External Match Output type, should be:
+							 	-	 TIM_EXTMATCH_NOTHING:	Do nothing for external output pin if match
+							 	-   TIM_EXTMATCH_LOW:	Force external output pin to low if match
+							 	- 	 TIM_EXTMATCH_HIGH: Force external output pin to high if match
+							 	-   TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
+							*/
+	uint8_t Reserved[3];	/** Reserved */
+	uint32_t MatchValue;	/** Match value */
+} TIM_MATCHCFG_Type;
+
+/** @brief Capture Input configuration structure */
+typedef struct {
+	uint8_t CaptureChannel;	/**< Capture channel, should be in range
+							from 0..1 */
+	uint8_t RisingEdge;		/**< caption rising edge, should be:
+								- ENABLE: Enable rising edge.
+								- DISABLE: Disable this function.
+							*/
+	uint8_t FallingEdge;	/**< caption falling edge, should be:
+								- ENABLE: Enable falling edge.
+								- DISABLE: Disable this function.
+								*/
+	uint8_t IntOnCaption;	/**< Interrupt On caption, should be:
+								- ENABLE: Enable interrupt function.
+								- DISABLE: Disable this function.
+							*/
+
+} TIM_CAPTURECFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup TIMER_Public_Functions TIMER Public Functions
+ * @{
+ */
+/* Init/DeInit TIM functions -----------*/
+void TIM_Init(LPC_TIMERn_Type *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_DeInit(LPC_TIMERn_Type *TIMx);
+
+/* TIM interrupt functions -------------*/
+void TIM_ClearIntPending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
+void TIM_ClearIntCapturePending(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntCaptureStatus(LPC_TIMERn_Type *TIMx, TIM_INT_TYPE IntFlag);
+
+/* TIM configuration functions --------*/
+void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_ConfigMatch(LPC_TIMERn_Type *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
+void TIM_UpdateMatchValue(LPC_TIMERn_Type *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
+void TIM_SetMatchExt(LPC_TIMERn_Type *TIMx,TIM_EXTMATCH_OPT ext_match );
+void TIM_ConfigCapture(LPC_TIMERn_Type *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
+void TIM_Cmd(LPC_TIMERn_Type *TIMx, FunctionalState NewState);
+
+uint32_t TIM_GetCaptureValue(LPC_TIMERn_Type *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
+void TIM_ResetCounter(LPC_TIMERn_Type *TIMx);
+void TIM_Waitus(uint32_t time);
+void TIM_Waitms(uint32_t time);
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC18XX_TIMER_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_uart.h

@@ -0,0 +1,677 @@
+/**********************************************************************
+* $Id$		lpc18xx_uart.h		2011-06-02
+*//**
+* @file		lpc18xx_uart.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for UART firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART UART
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC18XX_UART_H
+#define __LPC18XX_UART_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros  UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT			(0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR	(3)			/*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT   	((uint8_t)0xFF) 		/*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT   	((uint8_t)0xFF) 		/*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div)	((div) & 0xFF)	/**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT	((uint8_t)0xFF)	/*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT	((uint8_t)0xFF)			/*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)	/**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN		((uint32_t)(1<<0)) 	/*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN		((uint32_t)(1<<1)) 	/*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN		((uint32_t)(1<<2)) 	/*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN		((uint32_t)(1<<3))	/*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN		((uint32_t)(1<<7))	/*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN		((uint32_t)(1<<8)) 	/*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN		((uint32_t)(1<<9)) 	/*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK		((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK		((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND	((uint32_t)(1<<0))	/*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS		((uint32_t)(3<<1)) 	/*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA		((uint32_t)(2<<1)) 	/*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI		((uint32_t)(6<<1)) 	/*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE		((uint32_t)(1<<1)) 	/*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM	((uint32_t)(0<<1)) 	/*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK		((uint32_t)(7<<1))	/*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN		((uint32_t)(3<<6)) 	/*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT		((uint32_t)(1<<8)) 	/*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT		((uint32_t)(1<<9)) 	/*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK		((uint32_t)(0x3CF))	/*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN		((uint8_t)(1<<0)) 	/*!< UART FIFO enable */
+#define UART_FCR_RX_RS			((uint8_t)(1<<1)) 	/*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS			((uint8_t)(1<<2)) 	/*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL 	((uint8_t)(1<<3)) 	/*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0		((uint8_t)(0)) 		/*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1		((uint8_t)(1<<6)) 	/*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2		((uint8_t)(2<<6)) 	/*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3		((uint8_t)(3<<6)) 	/*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK		((uint8_t)(0xCF))	/*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE		(16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5     		((uint8_t)(0))   		/*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6     		((uint8_t)(1<<0))   	/*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7     		((uint8_t)(2<<0))   	/*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8     		((uint8_t)(3<<0))   	/*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL	((uint8_t)(1<<2))   	/*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN		((uint8_t)(1<<3))		/*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD		((uint8_t)(0))         	/*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN	((uint8_t)(1<<4))		/*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1		((uint8_t)(2<<4))		/*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0		((uint8_t)(3<<4))		/*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN		((uint8_t)(1<<6))		/*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN		((uint8_t)(1<<7))    	/*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK		((uint8_t)(0xFF))		/*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL		((uint8_t)(1<<0))		/*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL		((uint8_t)(1<<1))		/*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN		((uint8_t)(1<<4))		/*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN	((uint8_t)(1<<6))		/*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN	((uint8_t)(1<<7))		/*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK		((uint8_t)(0x0F3))		/*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR		((uint8_t)(1<<0)) 	/*!<Line status register: Receive data ready*/
+#define UART_LSR_OE			((uint8_t)(1<<1)) 	/*!<Line status register: Overrun error*/
+#define UART_LSR_PE			((uint8_t)(1<<2)) 	/*!<Line status register: Parity error*/
+#define UART_LSR_FE			((uint8_t)(1<<3)) 	/*!<Line status register: Framing error*/
+#define UART_LSR_BI			((uint8_t)(1<<4)) 	/*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE		((uint8_t)(1<<5)) 	/*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT		((uint8_t)(1<<6)) 	/*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE		((uint8_t)(1<<7)) 	/*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK	((uint8_t)(0xFF)) 	/*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS		((uint8_t)(1<<0))	/*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR		((uint8_t)(1<<1))	/*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI		((uint8_t)(1<<2))	/*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD		((uint8_t)(1<<3))	/*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS			((uint8_t)(1<<4))	/*!< Clear To Send State */
+#define UART1_MSR_DSR			((uint8_t)(1<<5))	/*!< Data Set Ready State */
+#define UART1_MSR_RI			((uint8_t)(1<<6))	/*!< Ring Indicator State */
+#define UART1_MSR_DCD			((uint8_t)(1<<7))	/*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK		((uint8_t)(0xFF))	/*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK		((uint8_t)(0xFF))	/*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START				((uint32_t)(1<<0))	/**< UART Auto-baud start */
+#define UART_ACR_MODE				((uint32_t)(1<<1))	/**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART		((uint32_t)(1<<2))	/**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR		((uint32_t)(1<<8))	/**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR		((uint32_t)(1<<9))	/**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK			((uint32_t)(0x307))	/**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN			((uint32_t)(1<<0))			/**< IrDA mode enable */
+#define UART_ICR_IRDAINV		((uint32_t)(1<<1))			/**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN	((uint32_t)(1<<2))			/**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n)	((uint32_t)((n&0x07)<<3))	/**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK		((uint32_t)(0x3F))			/*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART half duplex register
+ **********************************************************************/
+#define UART_HDEN_HDEN			((uint32_t)(1<<0))			/**< enable half-duplex mode*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART smart card interface control register
+ **********************************************************************/
+#define UART_SCICTRL_SCIEN		((uint32_t)(1<<0))			/**< enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_NACKDIS	((uint32_t)(1<<1))			/**< NACK response is inhibited*/
+#define UART_SCICTRL_PROTSEL_T1	((uint32_t)(1<<2))			/**< ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_TXRETRY(n)	((uint32_t)((n&0x07)<<5))	/**< number of retransmission*/
+#define UART_SCICTRL_GUARDTIME(n)	((uint32_t)((n&0xFF)<<8))	/**< Extra guard time*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART synchronous control register
+ **********************************************************************/
+#define UART_SYNCCTRL_SYNC		((uint32_t)(1<<0))			/**< enable synchronous mode*/
+#define UART_SYNCCTRL_CSRC_MASTER	((uint32_t)(1<<1))		/**< synchronous master mode*/
+#define UART_SYNCCTRL_FES		((uint32_t)(1<<2))			/**< sample on falling edge*/
+#define UART_SYNCCTRL_TSBYPASS	((uint32_t)(1<<3))			/**< to be defined*/
+#define UART_SYNCCTRL_CSCEN		((uint32_t)(1<<4))			/**< continuous running clock enable (master mode only)*/
+#define UART_SYNCCTRL_STARTSTOPDISABLE	((uint32_t)(1<<5))	/**< do not send start/stop bit*/
+#define UART_SYNCCTRL_CCCLR		((uint32_t)(1<<6))			/**< stop continuous clock*/
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n)	((uint32_t)(n&0x0F))		/**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n)		((uint32_t)((n<<4)&0xF0))	/**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK		((uint32_t)(0xFF))			/**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART1_TER_TXEN			((uint8_t)(1<<7)) 		/*!< Transmit enable bit */
+#define UART1_TER_BITMASK		((uint8_t)(0x80))		/**< UART Transmit Enable Register bit mask */
+#define UART0_2_3_TER_TXEN		((uint8_t)(1<<0)) 		/*!< Transmit enable bit */
+#define UART0_2_3_TER_BITMASK	((uint8_t)(0x01))		/**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART_RS485CTRL_NMM_EN		((uint32_t)(1<<0))	/*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+														is disabled */
+#define UART_RS485CTRL_RX_DIS		((uint32_t)(1<<1))	/*!< The receiver is disabled */
+#define UART_RS485CTRL_AADEN		((uint32_t)(1<<2))	/*!< Auto Address Detect (AAD) is enabled */
+#define UART_RS485CTRL_SEL_DTR		((uint32_t)(1<<3))	/*!< If direction control is enabled
+														(bit DCTRL = 1), pin DTR is used for direction control */
+#define UART_RS485CTRL_DCTRL_EN	((uint32_t)(1<<4))	/*!< Enable Auto Direction Control */
+#define UART_RS485CTRL_OINV_1		((uint32_t)(1<<5))	/*!< This bit reverses the polarity of the direction
+														control signal on the RTS (or DTR) pin. The direction control pin
+														will be driven to logic "1" when the transmitter has data to be sent */
+#define UART_RS485CTRL_BITMASK		((uint32_t)(0x3F))	/**< RS485 control bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) 	/**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART_RS485DLY_BITMASK		((uint8_t)(0xFF)) 	/** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n)	((uint32_t)(n&0x0F))		/**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n)	((uint32_t)((n>>8)&0x0F))	/**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK		((uint32_t)(0x0F0F))		/**< UART FIFO Level Register bit mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+
+/** Macro to check the input UART_DATABIT parameters */
+#define PARAM_UART_DATABIT(databit)	((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
+|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
+
+/** Macro to check the input UART_STOPBIT parameters */
+#define PARAM_UART_STOPBIT(stopbit)	((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
+
+/** Macro to check the input UART_PARITY parameters */
+#define PARAM_UART_PARITY(parity)	((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
+|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
+|| (parity==UART_PARITY_SP_0))
+
+/** Macro to check the input UART_FIFO parameters */
+#define PARAM_UART_FIFO_LEVEL(fifo)	((fifo==UART_FIFO_TRGLEV0) \
+|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
+|| (fifo==UART_FIFO_TRGLEV3))
+
+/** Macro to check the input UART_INTCFG parameters */
+#define PARAM_UART_INTCFG(IntCfg)	((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
+|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
+|| (IntCfg==UART_INTCFG_ABTO))
+
+/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
+#define PARAM_UART1_INTCFG(IntCfg)	((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
+
+/** Macro to check the input UART_AUTOBAUD_MODE parameters */
+#define PARAM_UART_AUTOBAUD_MODE(ABmode)	((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
+
+/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
+#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat)	((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
+		(ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
+
+/** Macro to check the input UART_IrDA_PULSEDIV parameters */
+#define PARAM_UART_IrDA_PULSEDIV(PulseDiv)	((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
+|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
+|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
+|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
+
+/* Macro to check the input UART1_SignalState parameters */
+#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
+
+/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
+#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
+
+/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
+#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
+|| (x==UART1_MODEM_MODE_AUTO_CTS))
+
+/** Macro to check the direction control pin type */
+#define PARAM_UART_RS485_DIRCTRL_PIN(x)	((x==UART_RS485_DIRCTRL_RTS) || (x==UART_RS485_DIRCTRL_DTR)|| (x==UART_RS485_DIRCTRL_DIR))
+
+/* Macro to determine if it is valid UART port number */
+#define PARAM_UARTx(x)	((((uint32_t *)x)==((uint32_t *)LPC_USART0)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_USART2)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_USART3)))
+#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_USART3))
+#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
+
+/** Macro to check the input value for UART_RS485_CFG_MATCHADDRVALUE parameter */
+#define PARAM_UART_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
+
+/** Macro to check the input value for UART_RS485_CFG_DELAYVALUE parameter */
+#define PARAM_UART_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/***********************************************************************
+ * @brief UART enumeration
+**********************************************************************/
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+	UART_DATABIT_5		= 0,     		/*!< UART 5 bit data mode */
+	UART_DATABIT_6,		     			/*!< UART 6 bit data mode */
+	UART_DATABIT_7,		     			/*!< UART 7 bit data mode */
+	UART_DATABIT_8		     			/*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+	UART_STOPBIT_1		= (0),   					/*!< UART 1 Stop Bits Select */
+	UART_STOPBIT_2		 							/*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+	UART_PARITY_NONE 	= 0,					/*!< No parity */
+	UART_PARITY_ODD,	 						/*!< Odd parity */
+	UART_PARITY_EVEN, 							/*!< Even parity */
+	UART_PARITY_SP_1, 							/*!< Forced "1" stick parity */
+	UART_PARITY_SP_0 							/*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+	UART_FIFO_TRGLEV0 = 0,	/*!< UART FIFO trigger level 0: 1 character */
+	UART_FIFO_TRGLEV1, 		/*!< UART FIFO trigger level 1: 4 character */
+	UART_FIFO_TRGLEV2,		/*!< UART FIFO trigger level 2: 8 character */
+	UART_FIFO_TRGLEV3		/*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+	UART_INTCFG_RBR = 0,	/*!< RBR Interrupt enable*/
+	UART_INTCFG_THRE,		/*!< THR Interrupt enable*/
+	UART_INTCFG_RLS,		/*!< RX line status interrupt enable*/
+	UART1_INTCFG_MS,		/*!< Modem status interrupt enable (UART1 only) */
+	UART1_INTCFG_CTS,		/*!< CTS1 signal transition interrupt enable (UART1 only) */
+	UART_INTCFG_ABEO,		/*!< Enables the end of auto-baud interrupt */
+	UART_INTCFG_ABTO		/*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+	UART_LINESTAT_RDR	= UART_LSR_RDR,			/*!<Line status register: Receive data ready*/
+	UART_LINESTAT_OE	= UART_LSR_OE,			/*!<Line status register: Overrun error*/
+	UART_LINESTAT_PE	= UART_LSR_PE,			/*!<Line status register: Parity error*/
+	UART_LINESTAT_FE	= UART_LSR_FE,			/*!<Line status register: Framing error*/
+	UART_LINESTAT_BI	= UART_LSR_BI,			/*!<Line status register: Break interrupt*/
+	UART_LINESTAT_THRE	= UART_LSR_THRE,		/*!<Line status register: Transmit holding register empty*/
+	UART_LINESTAT_TEMT	= UART_LSR_TEMT,		/*!<Line status register: Transmitter empty*/
+	UART_LINESTAT_RXFE	= UART_LSR_RXFE			/*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_MODE0				= 0,			/**< UART Auto baudrate Mode 0 */
+	UART_AUTOBAUD_MODE1							/**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+	UART_AB_MODE_Type	ABMode;			/**< Autobaudrate mode */
+	FunctionalState		AutoRestart;	/**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+	UART_AUTOBAUD_INTSTAT_ABEO		= UART_IIR_ABEO_INT,		/**< UART End of auto-baud interrupt  */
+	UART_AUTOBAUD_INTSTAT_ABTO		= UART_IIR_ABTO_INT			/**< UART Auto-baud time-out interrupt  */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum {
+	UART_IrDA_PULSEDIV2		= 0,		/**< Pulse width = 2 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV4,				/**< Pulse width = 4 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV8,				/**< Pulse width = 8 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV16,				/**< Pulse width = 16 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV32,				/**< Pulse width = 32 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV64,				/**< Pulse width = 64 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV128,				/**< Pulse width = 128 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+	UART_IrDA_PULSEDIV256				/**< Pulse width = 256 * Tpclk
+										- Configures the pulse when FixPulseEn = 1 */
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  Signal states definition
+**********************************************************************/
+typedef enum {
+	INACTIVE = 0,			/* In-active state */
+	ACTIVE = !INACTIVE 		/* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+	UART1_MODEM_STAT_DELTA_CTS	= UART1_MSR_DELTA_CTS,		/*!< Set upon state change of input CTS */
+	UART1_MODEM_STAT_DELTA_DSR	= UART1_MSR_DELTA_DSR,		/*!< Set upon state change of input DSR */
+	UART1_MODEM_STAT_LO2HI_RI	= UART1_MSR_LO2HI_RI,		/*!< Set upon low to high transition of input RI */
+	UART1_MODEM_STAT_DELTA_DCD	= UART1_MSR_DELTA_DCD,		/*!< Set upon state change of input DCD */
+	UART1_MODEM_STAT_CTS		= UART1_MSR_CTS,			/*!< Clear To Send State */
+	UART1_MODEM_STAT_DSR		= UART1_MSR_DSR,			/*!< Data Set Ready State */
+	UART1_MODEM_STAT_RI			= UART1_MSR_RI,				/*!< Ring Indicator State */
+	UART1_MODEM_STAT_DCD		= UART1_MSR_DCD				/*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+	UART1_MODEM_PIN_DTR			= 0,		/*!< Source for modem output pin DTR */
+	UART1_MODEM_PIN_RTS						/*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+	UART1_MODEM_MODE_LOOPBACK	= 0,		/*!< Loop back mode select */
+	UART1_MODEM_MODE_AUTO_RTS,				/*!< Enable Auto RTS flow-control */
+	UART1_MODEM_MODE_AUTO_CTS 				/*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+	UART_RS485_DIRCTRL_RTS = 0,	/**< Pin RTS is used for direction control */
+	UART_RS485_DIRCTRL_DTR,		/**< Pin DTR is used for direction control */
+	UART_RS485_DIRCTRL_DIR		/**< Pin DIR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+  uint32_t Baud_rate;   		/**< UART baud rate */
+  UART_PARITY_Type Parity;    	/**< Parity selection, should be:
+							   - UART_PARITY_NONE: No parity
+							   - UART_PARITY_ODD: Odd parity
+							   - UART_PARITY_EVEN: Even parity
+							   - UART_PARITY_SP_1: Forced "1" stick parity
+							   - UART_PARITY_SP_0: Forced "0" stick parity
+							   */
+  UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
+							   - UART_DATABIT_5: UART 5 bit data mode
+							   - UART_DATABIT_6: UART 6 bit data mode
+							   - UART_DATABIT_7: UART 7 bit data mode
+							   - UART_DATABIT_8: UART 8 bit data mode
+							   */
+  UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
+							   - UART_STOPBIT_1: UART 1 Stop Bits Select
+							   - UART_STOPBIT_2: UART 2 Stop Bits Select
+							   */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+	FunctionalState FIFO_ResetRxBuf;	/**< Reset Rx FIFO command state , should be:
+										 - ENABLE: Reset Rx FIFO in UART
+										 - DISABLE: Do not reset Rx FIFO  in UART
+										 */
+	FunctionalState FIFO_ResetTxBuf;	/**< Reset Tx FIFO command state , should be:
+										 - ENABLE: Reset Tx FIFO in UART
+										 - DISABLE: Do not reset Tx FIFO  in UART
+										 */
+	FunctionalState FIFO_DMAMode;		/**< DMA mode, should be:
+										 - ENABLE: Enable DMA mode in UART
+										 - DISABLE: Disable DMA mode in UART
+										 */
+	UART_FITO_LEVEL_Type FIFO_Level;	/**< Rx FIFO trigger level, should be:
+										- UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+										- UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+										- UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+										- UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+										*/
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem -  RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+	FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+													- ENABLE: Enable this function.
+													- DISABLE: Disable this function. */
+	FunctionalState Rx_State;					/*!< Receiver State:
+													- ENABLE: Enable Receiver.
+													- DISABLE: Disable Receiver. */
+	FunctionalState AutoAddrDetect_State;		/*!< Auto Address Detect mode state:
+												- ENABLE: ENABLE this function.
+												- DISABLE: Disable this function. */
+	FunctionalState AutoDirCtrl_State;			/*!< Auto Direction Control State:
+												- ENABLE: Enable this function.
+												- DISABLE: Disable this function. */
+	UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;		/*!< If direction control is enabled, state:
+												- UART1_RS485_DIRCTRL_RTS:
+												pin RTS is used for direction control.
+												- UART1_RS485_DIRCTRL_DTR:
+												pin DTR is used for direction control. */
+	 SetState DirCtrlPol_Level;					/*!< Polarity of the direction control signal on
+												the RTS (or DTR) pin:
+												- RESET: The direction control pin will be driven
+												to logic "0" when the transmitter has data to be sent.
+												- SET: The direction control pin will be driven
+												to logic "1" when the transmitter has data to be sent. */
+	uint8_t MatchAddrValue;					/*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+	uint8_t DelayValue;						/*!< delay time is in periods of the baud clock, 8-bit long */
+} UART_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_USARTn_Type *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_USARTn_Type* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_USARTn_Type* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_USARTn_Type* UARTx);
+uint32_t UART_Send(LPC_USARTn_Type *UARTx, uint8_t *txbuf,
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_USARTn_Type *UARTx, uint8_t *rxbuf, \
+		uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_USARTn_Type *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_USARTn_Type *UARTx, UART_INT_Type UARTIntCfg, \
+				FunctionalState NewState);
+void UART_ABCmd(LPC_USARTn_Type *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+				FunctionalState NewState);
+void UART_TxCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
+uint8_t UART_GetLineStatus(LPC_USARTn_Type* UARTx);
+FlagStatus UART_CheckBusy(LPC_USARTn_Type *UARTx);
+void UART_ForceBreak(LPC_USARTn_Type* UARTx);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_Type *UARTx, UART_MODEM_PIN_Type Pin, \
+							UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_Type *UARTx, UART_MODEM_MODE_Type Mode, \
+							FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_Type *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_USARTn_Type *UARTx, \
+		UART_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_USARTn_Type *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_USARTn_Type *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_USARTn_Type *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_USARTn_Type* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_USARTn_Type *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC18XX_UART_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_utils.h

@@ -0,0 +1,10 @@
+#ifndef _LPC18XX_UTILS_H
+#define _LPC18XX_UTILS_H
+
+#include "lpc_types.h"
+extern uint32_t msec;
+extern volatile uint32_t u32Milliseconds;
+void SysTick_Handler (void);
+int timer_delay_us( int cnt);
+int timer_delay_ms( int cnt);
+#endif

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_wwdt.h

@@ -0,0 +1,177 @@
+/**********************************************************************
+* $Id$		lpc18xx_wwdt.h		2011-06-02
+*//**
+* @file		lpc18xx_wwdt.h
+* @brief	Contains all macro definitions and function prototypes
+* 			support for WWDT firmware library on LPC18xx
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup WWDT	WWDT (Windowed WatchDog Timer)
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+
+#ifndef LPC18XX_WWDT_H_
+#define LPC18XX_WWDT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC18xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup WWDT_Public_Macros  WWDT Public Macros
+ * @{
+ */
+/** WDT oscillator frequency value */
+#define WDT_OSC		(12000000UL)		/* WWDT uses IRC clock */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup WWDT_Private_Macros WWDT Private Macros
+ * @{
+ */
+// time is calculated by usec
+#define WDT_GET_FROM_USEC(time)		((time*10)/((WWDT_US_INDEX *10 * 4)/WDT_OSC))
+#define WDT_GET_USEC(counter)		((counter * ((WWDT_US_INDEX *10 * 4)/WDT_OSC))/10)
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDEN			    ((uint32_t)(1<<0))
+/** WWDT interrupt enable bit */
+#define WWDT_WDMOD_WDRESET			((uint32_t)(1<<1))
+/** WWDT time out flag bit */
+#define WWDT_WDMOD_WDTOF			((uint32_t)(1<<2))
+/** WDT Time Out flag bit */
+#define WWDT_WDMOD_WDINT			((uint32_t)(1<<3))
+/** WWDT Protect flag bit */
+#define WWDT_WDMOD_WDPROTECT		((uint32_t)(1<<4))
+
+/** Define divider index for microsecond ( us ) */
+#define WWDT_US_INDEX		((uint32_t)(1000000))
+
+/** WWDT Time out minimum value */
+#define WWDT_TIMEOUT_MIN	((uint32_t)(0xFF))
+/** WWDT Time out maximum value */
+#define WWDT_TIMEOUT_MAX	((uint32_t)(0x00FFFFFF))
+
+/** WWDT Warning minimum value */
+#define WWDT_WARNINT_MIN	((uint32_t)(0xFF))
+/** WWDT Warning maximum value */
+#define WWDT_WARNINT_MAX	((uint32_t)(0x000003FF))
+
+/** WWDT Windowed minimum value */
+#define WWDT_WINDOW_MIN		((uint32_t)(0xFF))
+/** WWDT Windowed minimum value */
+#define WWDT_WINDOW_MAX		((uint32_t)(0x00FFFFFF))
+
+/** WWDT timer constant register mask */
+#define WWDT_WDTC_MASK			((uint32_t)(0x00FFFFFF))
+/** WWDT warning value register mask */
+#define WWDT_WDWARNINT_MASK		((uint32_t)(0x000003FF))
+/** WWDT feed sequence register mask */
+#define WWDT_WDFEED_MASK 		((uint32_t)(0x000000FF))
+
+/** WWDT flag */
+#define WWDT_WARNINT_FLAG		((uint8_t)(0))
+#define WWDT_TIMEOUT_FLAG		((uint8_t)(1))
+
+/** WWDT mode definitions */
+#define WWDT_PROTECT_MODE		((uint8_t)(0))
+#define WWDT_RESET_MODE			((uint8_t)(1))
+
+
+/* WWDT Timer value definition (us) */
+#define WWDT_TIMEOUT_USEC_MIN			((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds
+#define WWDT_TIMEOUT_USEC_MAX			((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))
+
+#define WWDT_TIMEWARN_USEC_MIN			((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))
+#define WWDT_TIMEWARN_USEC_MAX			((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))
+
+#define WWDT_TIMEWINDOWED_USEC_MIN		((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))
+#define WWDT_TIMEWINDOWED_USEC_MAX		((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))
+
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup WWDT_Public_Types WWDT Public Types
+ * @{
+ */
+/********************************************************************//**
+ * @brief WWDT structure definitions
+ **********************************************************************/
+typedef struct Wdt_Config
+{
+	uint8_t wdtReset;			/**< if ENABLE -> the Reset bit is enabled				*/
+	uint8_t wdtProtect;			/**< if ENABLE -> the Protect bit is enabled			*/
+	uint32_t wdtTmrConst;		/**< Set the constant value to timeout the WDT (us)		*/
+	uint32_t wdtWarningVal;		/**< Set the value to warn the WDT with interrupt (us)	*/
+	uint32_t wdtWindowVal;		/**< Set a window vaule for WDT (us)					*/
+}st_Wdt_Config;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup WWDT_Public_Functions WWDT Public Functions
+ * @{
+ */
+
+void WWDT_Init(void);
+void WWDT_UpdateTimeOut(uint32_t TimeOut);
+void WWDT_Feed (void);
+void WWDT_SetWarning(uint32_t WarnTime);
+void WWDT_SetWindow(uint32_t WindowedTime);
+void WWDT_Configure(st_Wdt_Config wdtCfg);
+void WWDT_Start(void);
+FlagStatus WWDT_GetStatus (uint8_t Status);
+void WWDT_ClearStatusFlag (uint8_t flag);
+uint32_t WWDT_GetCurrentCount(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC18XX_WWDT_H_ */
+
+/**
+ * @}
+ */
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc_types.h

@@ -0,0 +1,211 @@
+/**********************************************************************
+* $Id$		lpc_types.h			2011-06-02
+*//**
+* @file		lpc_types.h
+* @brief	Contains the NXP ABL typedefs for C standard types.
+*     		It is intended to be used in ISO C conforming development
+*     		environments and checks for this insofar as it is possible
+*     		to do so.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1800CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+	NONE_BLOCKING = 0,		/**< None Blocking type */
+	BLOCKING,				/**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros  LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n)	(1<<(n))
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) ((v)<<(f))
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array)  (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef	uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef	int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef	uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef	int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+#ifdef __CC_ARM
+#define INLINE  __inline
+#else
+#define INLINE inline
+#endif
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/spifi_rom_api.h

@@ -0,0 +1,248 @@
+/***********************************************************************
+*   Copyright(C) 2011, NXP Semiconductor
+*   All rights reserved.
+*
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef SPIFI_ROM_API_H
+#define SPIFI_ROM_API_H
+
+#include <stdint.h>
+/* define the symbol TESTING in the environment	if test output desired */
+
+/* maintain LONGEST_PROT >= the length (in bytes) of the largest
+	protection block of any serial flash that this driver handles */
+#define LONGEST_PROT 68
+
+typedef uint8_t uc;
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+/* protection/sector descriptors */
+typedef struct {
+	uint32_t base;
+	uc flags;
+	int8_t log2;
+	uint16_t rept;
+} protEnt;
+/* bits in the flags byte */
+enum {RWPROT=1};
+
+/* overall data structure includes # sectors, length of protection reg, 
+   array of descriptors 
+typedef struct {
+	uint16_t sectors;
+	uint16_t protBytes;
+	protEnt *entries;
+} protDesc;	*/
+
+typedef union {
+	uint16_t hw;
+	uc byte[2];
+}stat_t;
+/* the object that init returns, and other routines use as an operand */
+typedef struct {
+	uint32_t base, regbase, devSize, memSize;
+	uc mfger, devType, devID, busy;
+	stat_t stat;
+	uint16_t reserved;
+	uint16_t set_prot, write_prot;
+	uint32_t mem_cmd, prog_cmd;
+	uint16_t sectors, protBytes;
+	uint32_t opts, errCheck;
+	uc erase_shifts[4], erase_ops[4];
+	protEnt *protEnts;
+	char prot[LONGEST_PROT];
+} SPIFIobj;
+
+/* operands of program and erase */
+typedef struct {
+	char *dest;
+	uint32_t length;
+    char *scratch;
+	int32_t protect;
+	uint32_t options;
+} SPIFIopers;
+
+/* instruction classes for wait_busy */
+typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
+
+/* bits in options operands (MODE3, RCVCLK, and FULLCLK 
+	have the same relationship as in the Control register) */
+#define S_MODE3 1
+#define S_MODE0 0
+#define S_MINIMAL 2
+#define S_MAXIMAL 0
+#define S_FORCE_ERASE 4
+#define S_ERASE_NOT_REQD 8
+#define S_CALLER_ERASE 8
+#define S_ERASE_AS_REQD 0
+#define S_VERIFY_PROG 0x10
+#define S_VERIFY_ERASE 0x20
+#define S_NO_VERIFY 0
+#define S_RCVCLK 0x80
+#define S_INTCLK 0
+#define S_FULLCLK 0x40
+#define S_HALFCLK 0
+#define S_DUAL 0x100
+#define S_CALLER_PROT 0x200
+#define S_DRIVER_PROT 0
+
+/* the following values in the first post-address memory command byte work
+   for all known quad devices that support "no opcode" operation */
+#define NO_OPCODE_FOLLOWS 0xA5
+#define    OPCODE_FOLLOWS 0xFF
+
+/* basic SPI commands for serial flash */
+#define BASE_READ_CMD        (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
+#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
+#define BASE_PROG_CMD      (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
+
+/* the length of a standard	program command is 256 on all devices */
+#define PROG_SIZE 256
+
+/* options in obj->opts (mostly for setMulti) */
+/* used by Winbond: send 0xA3 command so hardware can read faster */
+#define OPT_SEND_A3        1
+/* used by SST: send 0x38 command to enable quad and allow full command set */
+#define OPT_SEND_38        2
+/* used by Winbond and others: read status reg 2, check it, 
+	if necessary write it back with Quad Enable set */
+#define OPT_35_OR02_01     4
+/* used by Atmel: read Configuration register, if necessary set Quad Enable */
+#define OPT_3F_OR80_3E     8
+/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
+#define OPT_65_CLR_C0_61   0x10
+/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
+   to set # dummy bytes and allow XIP mode */
+#define OPT_81          0x20
+/* set for devices without full device erase command (Numonyx type 0x40) */
+#define OPT_NO_DEV_ERASE 0x40
+/* used by Macronix: status reg 2 includes selection between write-protect 
+	in status reg and command-based */
+#define OPT_WPSEL       0x80
+/* set when protection data has been read into the SPIFI object */
+#define OPT_PROT_READ  0x100
+/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
+#define OPT_4BAD       0x200
+/* set if setMulti should set the Dual bit in Control reg */
+#define OPT_DUAL	   0x400
+/* send "# dummy bits" in C0 command to Winbond */
+#define OPT_C0         0x800
+/* set QE for Chingis */
+#define OPT_05_OR40_01 0x1000
+/* write status does not go busy */
+#define OPT_01_NO_BUSY 0x2000
+/* protection mode bits moved from protMode byte to opts  Fri May 13 2011 */
+#define OPT_PROT_STAT 0x4000
+#define OPT_PROT_REG  0x8000
+#define OPT_PROT_CMD3 0x10000
+#define OPT_PROT_CMDE 0x20000
+#define OPT_PROT_MASK 0x3C000
+
+#define OPT_ALL_QUAD  0x40000
+
+#ifndef OMIT_ROM_TABLE
+/* interface to ROM API */
+typedef struct {
+  int32_t (*spifi_init)      (SPIFIobj *obj, uint32_t csHigh, uint32_t options, 
+                          uint32_t mhz);
+  int32_t (*spifi_program)   (SPIFIobj *obj, char *source, SPIFIopers *opers);
+  int32_t (*spifi_erase)     (SPIFIobj *obj, SPIFIopers *opers);
+  /* mode switching */
+  void (*cancel_mem_mode)(SPIFIobj *obj);
+  void (*set_mem_mode)   (SPIFIobj *obj);
+
+  /* mid level functions */
+  int32_t (*checkAd)         (SPIFIobj *obj, SPIFIopers *opers);
+  int32_t (*setProt)         (SPIFIobj *obj, SPIFIopers *opers, char *change, 
+                          char *saveProt);
+  int32_t (*check_block)     (SPIFIobj *obj, char *source, SPIFIopers *opers, 
+                          uint32_t check_program);
+  int32_t (*send_erase_cmd)  (SPIFIobj *obj, uint8_t op, uint32_t addr);
+  uint32_t (*ck_erase)   (SPIFIobj *obj, uint32_t *addr, uint32_t length);
+  int32_t (*prog_block)      (SPIFIobj *obj, char *source, SPIFIopers *opers, 
+                          uint32_t *left_in_page);
+  uint32_t (*ck_prog)    (SPIFIobj *obj, char *source, char *dest, uint32_t length);
+
+  /* low level functions */
+  void(*setSize)         (SPIFIobj *obj, int32_t value);
+  int32_t (*setDev)          (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, 
+                          uint32_t prog_cmd);
+  uint32_t (*cmd)        (uc op, uc addrLen, uc intLen, uint16_t len);
+  uint32_t (*readAd)     (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
+  void (*send04)         (SPIFIobj *obj, uc op, uc len, uint32_t value);
+  void (*wren_sendAd)    (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
+  int32_t (*write_stat)      (SPIFIobj *obj, uc len, uint16_t value);
+  int32_t (*wait_busy)       (SPIFIobj *obj, uc prog_or_erase);
+} SPIFI_RTNS;
+
+#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
+#endif /* OMIT_ROM_TABLE */
+
+#ifdef USE_SPIFI_LIB
+extern SPIFI_RTNS spifi_table;
+#endif	/* USE_SPIFI_LIB */
+ 
+/* example of using this interface:
+#include "spifi_rom_api.h"
+#define CSHIGH 4
+#define SPIFI_MHZ 80
+#define source_data_ad (char *)1234
+
+	int32_t rc;
+	SPIFIopers opers;
+
+	define_spifi_romPtr(spifi);
+	SPIFIobj *obj = malloc(sizeof(SPIFIobj));
+	if (!obj) { can't allocate memory }
+
+	rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
+	if (rc) { investigate init error rc }
+	printf ("the serial flash contains %d bytes\n", obj->devSize);
+
+	opers.dest = where_to_program;
+	opers.length = how_many_bytes;
+	opers.scratch = NULL;			// unprogrammed data is not saved/restored
+	opers.protect = -1;				// save & restore protection
+	opers.options = S_VERIFY_PROG;
+
+	rc = spifi->spifi_program (obj, source_data_ad, &opers);
+	if (rc) { investigate program error rc }
+*/
+
+/* these are for normal users, including boot code */
+int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
+int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
+int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
+
+/* these are used by the manufacturer-specific init functions */
+void setSize (SPIFIobj *obj, int32_t value);
+int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
+uint32_t read04(SPIFIobj *obj, uc op, uc len);
+int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
+void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
+
+/* needs to be defined for each platform */
+void pullMISO(int high);
+
+#ifdef TESTING
+/* used by testing code */
+unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
+/* predeclare a debug routine */
+void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
+#endif
+
+#endif /* SPIFI_ROM_API_H */

FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/system_LPC18xx.h

@@ -0,0 +1,50 @@
+/**********************************************************************
+* $Id$		system_LPC18xx.h			2011-06-02
+*//**
+* @file		system_LPC18xx.h
+* @brief	Cortex-M3 Device System Header File for NXP LPC18xx Series.
+* @version	1.0
+* @date		02. June. 2011
+* @author	NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+**********************************************************************/
+
+#ifndef __SYSTEM_LPC18xx_H
+#define __SYSTEM_LPC18xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdint.h>
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC18xx_H */