[AUTO][RELEASE]: Bump file header version to "10.5.0"

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

.github/CODEOWNERS

@@ -0,0 +1,39 @@
+# Each line is a file pattern followed by one or more owners.
+
+# These owners will be the default owners for everything in
+# the repo. Unless a later match takes precedence,
+# @global-owner1 and @global-owner2 will be requested for
+# review when someone opens a pull request.
+*      @FreeRTOS/pr-bar-raiser
+
+# Order is important; the last matching pattern takes the most
+# precedence. When someone opens a pull request that only
+# modifies JS files, only @js-owner and not the global
+# owner(s) will be requested for a review.
+# *.c FreeRTOS/pr-bar-raiser
+
+# You can also use email addresses if you prefer. They'll be
+# used to look up users just like we do for commit author
+# emails.
+# *.go docs@example.com
+
+# In this example, @doctocat owns any files in the build/logs
+# directory at the root of the repository and any of its
+# subdirectories.
+# /build/logs/ @doctocat
+
+# The `docs/*` pattern will match files like
+# `docs/getting-started.md` but not further nested files like
+# `docs/build-app/troubleshooting.md`.
+# docs/*  docs@example.com
+
+# In this example, @octocat owns any file in an apps directory
+# anywhere in your repository.
+# apps/ @octocat
+
+# In this example, @doctocat owns any file in the `/docs`
+# directory in the root of your repository and any of its
+# subdirectories.
+# /docs/ @doctocat
+
+

.github/CONTRIBUTING.md

@@ -0,0 +1,70 @@
+# Contribution guidelines
+
+Thank you for your interest in contributing to our project. Whether it's a bug report, new feature, code, or
+documentation, we welcome our community to be involved in this project.
+
+Please read through this document before submitting any issues or pull requests to ensure we are able to help you and all members of the community as effectively as possible.
+
+## Code of conduct
+This project has adopted the [Amazon Open Source Code of Conduct](https://aws.github.io/code-of-conduct).
+For more information see the [Code of Conduct FAQ](https://aws.github.io/code-of-conduct-faq) or contact
+opensource-codeofconduct@amazon.com with any additional questions or comments.
+
+
+## Security issue notifications
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/). Please do **not** create a public github issue.
+
+
+## Submitting a bugs/feature request
+Have a bug to report or feature to request? Follow these steps:
+1. Search on the [FreeRTOS Community Support Forums](https://forums.freertos.org/) and [GitHub issue tracker](https://github.com/FreeRTOS/FreeRTOS/issues?utf8=%E2%9C%93&q=is%3Aissue) to be sure this hasn't been already reported or discussed.
+2. If your search turns up empty, create a new topic in the [forums](https://forums.freertos.org/) and work with the community to help clarify issues or refine the idea. Include as many of the details listed below.
+3. Once the community has had time to discuss and digest, we welcome you to create an [issue](https://github.com/FreeRTOS/FreeRTOS/issues) to report bugs or suggest features.
+
+When creating a new topic on the forums or filing an issue, please include as many relevant details as possible. Examples include:
+
+* A clear description of the situation - what you observe, what you expect, and your view on how the two differ.
+* A reproducible test case or sequence of steps.
+* The version of our code being used.
+* Any modifications you've made relevant to the bug.
+* Details of your environment or deployment. Highlight anything unusual.
+
+
+## Contributing via pull request
+Contributions via pull requests are much appreciated. Before sending us a pull request, please ensure that:
+
+1. You are working against the latest source on the *main* branch.
+2. You check existing open, and recently merged, pull requests to make sure someone else hasn't addressed the problem already.
+3. You open an issue to discuss any significant work - we would hate for your time to be wasted.
+
+To send us a pull request, please:
+
+1. Fork the repository.
+2. Modify the source; focus on the specific change you are contributing. If you also reformat all the code, it will be hard for us to focus on your change.
+3. Follow the [coding style guide](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+4. Commit to your fork using clear commit messages.
+5. Send us a pull request, answering any default questions in the pull request interface.
+   NOTE: Please make sure the default option (Allow edits from maintainers) is left checked.
+6. Pay attention to any automated CI failures reported in the pull request, and stay involved in the conversation.
+
+GitHub provides additional document on [forking a repository](https://help.github.com/articles/fork-a-repo/) and
+[creating a pull request](https://help.github.com/articles/creating-a-pull-request/).
+
+## Coding style
+* Please ensure that your code complies to the [FreeRTOS coding style guidelines](https://www.FreeRTOS.org/FreeRTOS-Coding-Standard-and-Style-Guide.html).
+
+
+## Getting your pull request merged
+All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
+
+
+## Finding contributions to work on
+Looking at the existing issues is a great way to find something to contribute on. As our projects, by default, use the default GitHub issue labels (enhancement/bug/duplicate/help wanted/invalid/question/wontfix), tackling open 'help wanted' issues is a great place to start.
+
+
+## Licensing
+The FreeRTOS kernel is released under the MIT open source license, the text of which can be found [here](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/License/license.txt)
+
+Additional license files can be found in the folders containing any supplementary libraries licensed by their respective copyright owners where applicable.
+
+We may ask you to sign a [Contributor License Agreement (CLA)](https://en.wikipedia.org/wiki/Contributor_License_Agreement) for larger changes.

.github/ISSUE_TEMPLATE/bug-report.md

@@ -0,0 +1,40 @@
+---
+name: Bug report
+about: Create a report to help us improve FreeRTOS. This should only be used for confirmed
+  bugs. If you suspect something it is best to first discuss it on the FreeRTOS community
+  support forums linked below.
+title: "[BUG]"
+labels: bug
+assignees: ''
+
+---
+
+**Describe the bug**
+A concise description of what the bug is.
+
+**Target**
+- Development board: [e.g. HiFive11 RevB]
+- Instruction Set Architecture: [e.g. RV32IMAC]
+- IDE and version: [e.g. Freedom Studio 4.12.0.2019-08-2]
+- Toolchain and version: [e.g. riscv64-unknown-elf-gcc-8.3.0-2019.08.0]
+
+**Host**
+- Host OS: [e.g. MacOS]
+- Version: [e.g. Mojave 10.14.6]
+
+**To Reproduce**
+- Use project ... and configure with ...
+- Run on ... and could observe ...
+
+**Expected behavior**
+A concise description of what you expected to happen.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
+
+**Additional context**
+Add any other context about the problem here.
+e.g. code snippet to reproduce the issue.
+e.g. stack trace, memory dump, debugger log, and many etc.
+
+<!-- For general inquiries, please post in [FreeRTOS forum](https://forums.FreeRTOS.org) for community support. -->

.github/ISSUE_TEMPLATE/config.yml

@@ -0,0 +1,6 @@
+blank_issues_enabled: false
+contact_links:
+  - name: FreeRTOS Community Support Forum
+    url: https://forums.freertos.org/
+    about: Please ask and answer questions about FreeRTOS here.
+

.github/ISSUE_TEMPLATE/documentation-issue.md

@@ -0,0 +1,23 @@
+---
+name: Documentation issue
+about: Create a report to help us improve our documentation.
+title: "[DOC]"
+labels: documentation
+assignees: ''
+
+---
+
+**Describe the issue**
+Please describe the issue and expected clarification in concise language.
+
+**Reference**
+Please attach the URL at which you are experiencing the issue.
+
+**Screenshot**
+If applicable, please attach screenshot.
+
+**Browser**
+- Browser: [e.g. Chrome]
+- Version: [e.g. 80.0.3987.132]
+
+<!-- For general inquiries, please post in [FreeRTOS forum](https://forums.FreeRTOS.org) for community support. -->

.github/ISSUE_TEMPLATE/feature_request.md

@@ -0,0 +1,30 @@
+---
+name: Feature request
+about: Suggest a new feature for this project
+title: "[Feature Request] <replace with your title>"
+labels: enhancement
+assignees: ''
+
+---
+
+**Is your feature request related to a problem? Please describe.**
+A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
+
+**Describe the solution you'd like**
+A clear and concise description of what you want to happen.
+
+**Describe alternatives you've considered**
+A clear and concise description of any alternative solutions or features you've considered.
+
+**How many devices will this feature impact?**
+Expected volume for your product.
+
+**What are your project timelines?**
+Timeline for milestones such as design completion, testing and validation, and production.
+
+**Additional context**
+Add any other context or screenshots about the feature request here.
+
+
+If you have the same (or similar) feature request, please upvote this issue with thumbs up 👍
+and use the comments section to provide answers to the questions above.

.github/SECURITY.md

@@ -0,0 +1,5 @@
+## Reporting a Vulnerability
+
+If you discover a potential security issue in this project we ask that you notify AWS/Amazon Security 
+via our [vulnerability reporting page](https://aws.amazon.com/security/vulnerability-reporting/) or directly via email to aws-security@amazon.com. 
+Please do **not** create a public github issue.

.github/actions/url_verifier.sh

@@ -0,0 +1,63 @@
+#!/bin/bash -
+
+PROJECT=$1
+echo "Verifying url links of: ${PROJECT}"
+if [ ! -d "$PROJECT" ]
+then
+    echo "Directory passed does not exist"
+    exit 2
+fi
+
+USER_AGENT="Mozilla/5.0 (Macintosh; Intel Mac OS X 10_14_6) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/88.0.4324.146 Safari/537.36"
+SCRIPT_RET=0
+
+set -o nounset        # Treat unset variables as an error
+
+declare -A dict
+
+function test {
+    while IFS= read -r LINE; do
+        FILE=$(echo $LINE | cut -f 1 -d ':')
+        URL=$(echo $LINE | grep -IoE '\b(https?|ftp|file)://[-A-Za-z0-9+&@#/%?=~_|!:,.;]*[-A-Za-z0-9+&@#/%=~_|]')
+
+        # remove trailing / if it exists curl diferenciate between links with
+        # and without / at the end
+        # URL=`echo "$URL" | sed 's,/$,,'`
+        dict+=(["$URL"]="$FILE ")
+    done < <(grep -e 'https\?://' ${PROJECT} -RIa --exclude='*.exe' --exclude-dir=.git | tr '*' ' ')
+
+    for UNIQ_URL in ${!dict[@]} # loop urls
+    do
+     CURL_RES=$(curl -si --user-agent "$(USER_AGENT)" ${UNIQ_URL} 2>/dev/null| head -n 1 | cut -f 2 -d ' ')
+     RES=$?
+
+        if [ "${CURL_RES}" == '' -o "${CURL_RES}" != '200' ]
+        then
+            echo "URL is: ${UNIQ_URL}"
+            echo "File names: ${dict[$UNIQ_URL]}"
+            if [ "${CURL_RES}" == '' ]  # curl returned an error
+            then
+                CURL_RES=$RES
+                SCRIPT_RET=1
+                echo ERROR: Result is: "${CURL_RES}"
+            elif [ "${CURL_RES}" == '403' ]
+            then
+                SCRIPT_RET=1
+                echo ERROR: Result is: "${CURL_RES}"
+            else
+                echo WARNING: Result is: "${CURL_RES}"
+            fi
+            echo "================================="
+        fi
+    done
+
+    if [ "${SCRIPT_RET}" -eq 0 ]
+    then
+        exit 0
+    else
+        exit 1
+    fi
+}
+
+test
+

.github/pull_request_template.md

@@ -0,0 +1,16 @@
+<!--- Title -->
+
+Description
+-----------
+<!--- Describe your changes in detail. -->
+
+Test Steps
+-----------
+<!-- Describe the steps to reproduce. -->
+
+Related Issue
+-----------
+<!-- If any, please provide issue ID. -->
+
+
+By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

.github/scripts/find_replace.sh

@@ -0,0 +1,7 @@
+#!/bin/bash
+old_text=$1
+new_text=$2
+echo "Old text: ${old_text}"
+echo "New text: ${new_text}"
+grep -rl "${old_text}" . | xargs gsed -i -e '1h;2,$H;$!d;g' -e "s/${old_text}/${new_text}/g"
+

.github/scripts/kernel_checker.py

@@ -0,0 +1,152 @@
+#!/usr/bin/env python3
+#/*
+# * FreeRTOS Kernel V10.5.0
+# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# *
+# * SPDX-License-Identifier: MIT
+# *
+# * Permission is hereby granted, free of charge, to any person obtaining a copy of
+# * this software and associated documentation files (the "Software"), to deal in
+# * the Software without restriction, including without limitation the rights to
+# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+# * the Software, and to permit persons to whom the Software is furnished to do so,
+# * subject to the following conditions:
+# *
+# * The above copyright notice and this permission notice shall be included in all
+# * copies or substantial portions of the Software.
+# *
+# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# *
+# * https://www.FreeRTOS.org
+# * https://github.com/FreeRTOS
+# *
+# */
+
+import os
+from common.header_checker import HeaderChecker
+
+#--------------------------------------------------------------------------------------------------
+#                                            CONFIG
+#--------------------------------------------------------------------------------------------------
+KERNEL_IGNORED_FILES = [
+    'FreeRTOS-openocd.c',
+    'Makefile',
+    '.DS_Store'
+]
+
+KERNEL_IGNORED_EXTENSIONS = [
+    '.yml',
+    '.css',
+    '.idx',
+    '.md',
+    '.url',
+    '.sty',
+    '.0-rc2',
+    '.s82',
+    '.js',
+    '.out',
+    '.pack',
+    '.2',
+    '.1-kernel-only',
+    '.0-kernel-only',
+    '.0-rc1',
+    '.readme',
+    '.tex',
+    '.png',
+    '.bat',
+    '.sh',
+    '.txt',
+    '.cmake'
+]
+
+KERNEL_ASM_EXTENSIONS = [
+    '.s',
+    '.S',
+    '.src',
+    '.inc',
+    '.s26',
+    '.s43',
+    '.s79',
+    '.s85',
+    '.s87',
+    '.s90',
+    '.asm',
+    '.h'
+]
+
+KERNEL_PY_EXTENSIONS = [
+    '.py'
+]
+
+KERNEL_IGNORED_PATTERNS = [
+    r'.*\.git.*',
+    r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
+    r'.*portable/GCC/ARM7_AT91SAM7S/.*',
+    r'.*portable/MPLAB/PIC18F/stdio.h'
+]
+
+KERNEL_THIRD_PARTY_PATTERNS = [
+    r'.*portable/ThirdParty/GCC/Posix/port*',
+    r'.*portable/ThirdParty/*',
+    r'.*portable/IAR/AVR32_UC3/.*',
+    r'.*portable/GCC/AVR32_UC3/.*',
+]
+
+KERNEL_HEADER = [
+    '/*\n',
+    ' * FreeRTOS Kernel V10.5.0\n',
+    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n',
+    ' *\n',
+    ' * SPDX-License-Identifier: MIT\n',
+    ' *\n',
+    ' * Permission is hereby granted, free of charge, to any person obtaining a copy of\n',
+    ' * this software and associated documentation files (the "Software"), to deal in\n',
+    ' * the Software without restriction, including without limitation the rights to\n',
+    ' * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n',
+    ' * the Software, and to permit persons to whom the Software is furnished to do so,\n',
+    ' * subject to the following conditions:\n',
+    ' *\n',
+    ' * The above copyright notice and this permission notice shall be included in all\n',
+    ' * copies or substantial portions of the Software.\n',
+    ' *\n',
+    ' * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n',
+    ' * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n',
+    ' * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n',
+    ' * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n',
+    ' * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n',
+    ' * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n',
+    ' *\n',
+    ' * https://www.FreeRTOS.org\n',
+    ' * https://github.com/FreeRTOS\n',
+    ' *\n',
+    ' */\n',
+]
+
+def main():
+    parser = HeaderChecker.configArgParser()
+    args   = parser.parse_args()
+
+    # Configure the checks then run
+    checker = HeaderChecker(KERNEL_HEADER,
+                            ignored_files=KERNEL_IGNORED_FILES,
+                            ignored_ext=KERNEL_IGNORED_EXTENSIONS,
+                            ignored_patterns=KERNEL_IGNORED_PATTERNS,
+                            third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
+                            py_ext=KERNEL_PY_EXTENSIONS,
+                            asm_ext=KERNEL_ASM_EXTENSIONS)
+    checker.ignoreFile(os.path.split(__file__)[-1])
+
+    rc = checker.processArgs(args)
+    if rc:
+        checker.showHelp(__file__)
+
+    return rc
+
+if __name__ == '__main__':
+    exit(main())
+

.github/uncrustify.cfg

@@ -0,0 +1,673 @@
+# Uncrustify-0.69.0
+
+newlines                        = auto     # lf/crlf/cr/auto
+input_tab_size                  = 4        # unsigned number
+output_tab_size                 = 4        # unsigned number
+string_escape_char              = 92       # unsigned number
+string_escape_char2             = 0        # unsigned number
+string_replace_tab_chars        = false    # true/false
+tok_split_gte                   = false    # true/false
+disable_processing_cmt          = " *INDENT-OFF*"      # string
+enable_processing_cmt           = " *INDENT-ON*"     # string
+enable_digraphs                 = false    # true/false
+utf8_bom                        = ignore   # ignore/add/remove/force
+utf8_byte                       = false    # true/false
+utf8_force                      = false    # true/false
+sp_arith                        = force    # ignore/add/remove/force
+sp_arith_additive               = ignore   # ignore/add/remove/force
+sp_assign                       = force    # ignore/add/remove/force
+sp_cpp_lambda_assign            = ignore   # ignore/add/remove/force
+sp_cpp_lambda_paren             = ignore   # ignore/add/remove/force
+sp_assign_default               = force    # ignore/add/remove/force
+sp_before_assign                = force    # ignore/add/remove/force
+sp_after_assign                 = force    # ignore/add/remove/force
+sp_enum_paren                   = ignore   # ignore/add/remove/force
+sp_enum_assign                  = force    # ignore/add/remove/force
+sp_enum_before_assign           = force    # ignore/add/remove/force
+sp_enum_after_assign            = force    # ignore/add/remove/force
+sp_enum_colon                   = ignore   # ignore/add/remove/force
+sp_pp_concat                    = add      # ignore/add/remove/force
+sp_pp_stringify                 = add      # ignore/add/remove/force
+sp_before_pp_stringify          = ignore   # ignore/add/remove/force
+sp_bool                         = force    # ignore/add/remove/force
+sp_compare                      = force    # ignore/add/remove/force
+sp_inside_paren                 = force    # ignore/add/remove/force
+sp_paren_paren                  = force    # ignore/add/remove/force
+sp_cparen_oparen                = ignore   # ignore/add/remove/force
+sp_balance_nested_parens        = false    # true/false
+sp_paren_brace                  = force    # ignore/add/remove/force
+sp_brace_brace                  = ignore   # ignore/add/remove/force
+sp_before_ptr_star              = force    # ignore/add/remove/force
+sp_before_unnamed_ptr_star      = force    # ignore/add/remove/force
+sp_between_ptr_star             = remove   # ignore/add/remove/force
+sp_after_ptr_star               = force    # ignore/add/remove/force
+sp_after_ptr_block_caret        = ignore   # ignore/add/remove/force
+sp_after_ptr_star_qualifier     = ignore   # ignore/add/remove/force
+sp_after_ptr_star_func          = ignore   # ignore/add/remove/force
+sp_ptr_star_paren               = ignore   # ignore/add/remove/force
+sp_before_ptr_star_func         = ignore   # ignore/add/remove/force
+sp_before_byref                 = force    # ignore/add/remove/force
+sp_before_unnamed_byref         = ignore   # ignore/add/remove/force
+sp_after_byref                  = remove   # ignore/add/remove/force
+sp_after_byref_func             = remove   # ignore/add/remove/force
+sp_before_byref_func            = ignore   # ignore/add/remove/force
+sp_after_type                   = force    # ignore/add/remove/force
+sp_after_decltype               = ignore   # ignore/add/remove/force
+sp_before_template_paren        = ignore   # ignore/add/remove/force
+sp_template_angle               = ignore   # ignore/add/remove/force
+sp_before_angle                 = remove   # ignore/add/remove/force
+sp_inside_angle                 = remove   # ignore/add/remove/force
+sp_inside_angle_empty           = ignore   # ignore/add/remove/force
+sp_angle_colon                  = ignore   # ignore/add/remove/force
+sp_after_angle                  = force    # ignore/add/remove/force
+sp_angle_paren                  = ignore   # ignore/add/remove/force
+sp_angle_paren_empty            = ignore   # ignore/add/remove/force
+sp_angle_word                   = ignore   # ignore/add/remove/force
+sp_angle_shift                  = add      # ignore/add/remove/force
+sp_permit_cpp11_shift           = false    # true/false
+sp_before_sparen                = remove   # ignore/add/remove/force
+sp_inside_sparen                = force    # ignore/add/remove/force
+sp_inside_sparen_open           = ignore   # ignore/add/remove/force
+sp_inside_sparen_close          = ignore   # ignore/add/remove/force
+sp_after_sparen                 = force    # ignore/add/remove/force
+sp_sparen_brace                 = force    # ignore/add/remove/force
+sp_invariant_paren              = ignore   # ignore/add/remove/force
+sp_after_invariant_paren        = ignore   # ignore/add/remove/force
+sp_special_semi                 = ignore   # ignore/add/remove/force
+sp_before_semi                  = remove   # ignore/add/remove/force
+sp_before_semi_for              = remove   # ignore/add/remove/force
+sp_before_semi_for_empty        = add      # ignore/add/remove/force
+sp_after_semi                   = add      # ignore/add/remove/force
+sp_after_semi_for               = force    # ignore/add/remove/force
+sp_after_semi_for_empty         = force    # ignore/add/remove/force
+sp_before_square                = remove   # ignore/add/remove/force
+sp_before_squares               = remove   # ignore/add/remove/force
+sp_cpp_before_struct_binding    = ignore   # ignore/add/remove/force
+sp_inside_square                = force    # ignore/add/remove/force
+sp_inside_square_oc_array       = ignore   # ignore/add/remove/force
+sp_after_comma                  = force    # ignore/add/remove/force
+sp_before_comma                 = remove   # ignore/add/remove/force
+sp_after_mdatype_commas         = ignore   # ignore/add/remove/force
+sp_before_mdatype_commas        = ignore   # ignore/add/remove/force
+sp_between_mdatype_commas       = ignore   # ignore/add/remove/force
+sp_paren_comma                  = force    # ignore/add/remove/force
+sp_before_ellipsis              = ignore   # ignore/add/remove/force
+sp_type_ellipsis                = ignore   # ignore/add/remove/force
+sp_type_question                = ignore   # ignore/add/remove/force
+sp_paren_ellipsis               = ignore   # ignore/add/remove/force
+sp_paren_qualifier              = ignore   # ignore/add/remove/force
+sp_paren_noexcept               = ignore   # ignore/add/remove/force
+sp_after_class_colon            = ignore   # ignore/add/remove/force
+sp_before_class_colon           = ignore   # ignore/add/remove/force
+sp_after_constr_colon           = ignore   # ignore/add/remove/force
+sp_before_constr_colon          = ignore   # ignore/add/remove/force
+sp_before_case_colon            = remove   # ignore/add/remove/force
+sp_after_operator               = ignore   # ignore/add/remove/force
+sp_after_operator_sym           = ignore   # ignore/add/remove/force
+sp_after_operator_sym_empty     = ignore   # ignore/add/remove/force
+sp_after_cast                   = force    # ignore/add/remove/force
+sp_inside_paren_cast            = force    # ignore/add/remove/force
+sp_cpp_cast_paren               = ignore   # ignore/add/remove/force
+sp_sizeof_paren                 = remove   # ignore/add/remove/force
+sp_sizeof_ellipsis              = ignore   # ignore/add/remove/force
+sp_sizeof_ellipsis_paren        = ignore   # ignore/add/remove/force
+sp_decltype_paren               = ignore   # ignore/add/remove/force
+sp_after_tag                    = ignore   # ignore/add/remove/force
+sp_inside_braces_enum           = force    # ignore/add/remove/force
+sp_inside_braces_struct         = force    # ignore/add/remove/force
+sp_inside_braces_oc_dict        = ignore   # ignore/add/remove/force
+sp_after_type_brace_init_lst_open = ignore   # ignore/add/remove/force
+sp_before_type_brace_init_lst_close = ignore   # ignore/add/remove/force
+sp_inside_type_brace_init_lst   = ignore   # ignore/add/remove/force
+sp_inside_braces                = force    # ignore/add/remove/force
+sp_inside_braces_empty          = remove   # ignore/add/remove/force
+sp_type_func                    = force    # ignore/add/remove/force
+sp_type_brace_init_lst          = ignore   # ignore/add/remove/force
+sp_func_proto_paren             = remove   # ignore/add/remove/force
+sp_func_proto_paren_empty       = ignore   # ignore/add/remove/force
+sp_func_def_paren               = remove   # ignore/add/remove/force
+sp_func_def_paren_empty         = ignore   # ignore/add/remove/force
+sp_inside_fparens               = remove   # ignore/add/remove/force
+sp_inside_fparen                = force    # ignore/add/remove/force
+sp_inside_tparen                = ignore   # ignore/add/remove/force
+sp_after_tparen_close           = ignore   # ignore/add/remove/force
+sp_square_fparen                = ignore   # ignore/add/remove/force
+sp_fparen_brace                 = add      # ignore/add/remove/force
+sp_fparen_brace_initializer     = ignore   # ignore/add/remove/force
+sp_fparen_dbrace                = ignore   # ignore/add/remove/force
+sp_func_call_paren              = remove   # ignore/add/remove/force
+sp_func_call_paren_empty        = ignore   # ignore/add/remove/force
+sp_func_call_user_paren         = ignore   # ignore/add/remove/force
+sp_func_call_user_inside_fparen = ignore   # ignore/add/remove/force
+sp_func_call_user_paren_paren   = ignore   # ignore/add/remove/force
+sp_func_class_paren             = remove   # ignore/add/remove/force
+sp_func_class_paren_empty       = ignore   # ignore/add/remove/force
+sp_return_paren                 = remove   # ignore/add/remove/force
+sp_return_brace                 = ignore   # ignore/add/remove/force
+sp_attribute_paren              = remove   # ignore/add/remove/force
+sp_defined_paren                = remove   # ignore/add/remove/force
+sp_throw_paren                  = ignore   # ignore/add/remove/force
+sp_after_throw                  = ignore   # ignore/add/remove/force
+sp_catch_paren                  = ignore   # ignore/add/remove/force
+sp_oc_catch_paren               = ignore   # ignore/add/remove/force
+sp_oc_classname_paren           = ignore   # ignore/add/remove/force
+sp_version_paren                = ignore   # ignore/add/remove/force
+sp_scope_paren                  = ignore   # ignore/add/remove/force
+sp_super_paren                  = remove   # ignore/add/remove/force
+sp_this_paren                   = remove   # ignore/add/remove/force
+sp_macro                        = force    # ignore/add/remove/force
+sp_macro_func                   = force    # ignore/add/remove/force
+sp_else_brace                   = ignore   # ignore/add/remove/force
+sp_brace_else                   = ignore   # ignore/add/remove/force
+sp_brace_typedef                = force    # ignore/add/remove/force
+sp_catch_brace                  = ignore   # ignore/add/remove/force
+sp_oc_catch_brace               = ignore   # ignore/add/remove/force
+sp_brace_catch                  = ignore   # ignore/add/remove/force
+sp_oc_brace_catch               = ignore   # ignore/add/remove/force
+sp_finally_brace                = ignore   # ignore/add/remove/force
+sp_brace_finally                = ignore   # ignore/add/remove/force
+sp_try_brace                    = ignore   # ignore/add/remove/force
+sp_getset_brace                 = ignore   # ignore/add/remove/force
+sp_word_brace                   = add      # ignore/add/remove/force
+sp_word_brace_ns                = add      # ignore/add/remove/force
+sp_before_dc                    = remove   # ignore/add/remove/force
+sp_after_dc                     = remove   # ignore/add/remove/force
+sp_d_array_colon                = ignore   # ignore/add/remove/force
+sp_not                          = remove   # ignore/add/remove/force
+sp_inv                          = remove   # ignore/add/remove/force
+sp_addr                         = remove   # ignore/add/remove/force
+sp_member                       = remove   # ignore/add/remove/force
+sp_deref                        = remove   # ignore/add/remove/force
+sp_sign                         = remove   # ignore/add/remove/force
+sp_incdec                       = remove   # ignore/add/remove/force
+sp_before_nl_cont               = add      # ignore/add/remove/force
+sp_after_oc_scope               = ignore   # ignore/add/remove/force
+sp_after_oc_colon               = ignore   # ignore/add/remove/force
+sp_before_oc_colon              = ignore   # ignore/add/remove/force
+sp_after_oc_dict_colon          = ignore   # ignore/add/remove/force
+sp_before_oc_dict_colon         = ignore   # ignore/add/remove/force
+sp_after_send_oc_colon          = ignore   # ignore/add/remove/force
+sp_before_send_oc_colon         = ignore   # ignore/add/remove/force
+sp_after_oc_type                = ignore   # ignore/add/remove/force
+sp_after_oc_return_type         = ignore   # ignore/add/remove/force
+sp_after_oc_at_sel              = ignore   # ignore/add/remove/force
+sp_after_oc_at_sel_parens       = ignore   # ignore/add/remove/force
+sp_inside_oc_at_sel_parens      = ignore   # ignore/add/remove/force
+sp_before_oc_block_caret        = ignore   # ignore/add/remove/force
+sp_after_oc_block_caret         = ignore   # ignore/add/remove/force
+sp_after_oc_msg_receiver        = ignore   # ignore/add/remove/force
+sp_after_oc_property            = ignore   # ignore/add/remove/force
+sp_after_oc_synchronized        = ignore   # ignore/add/remove/force
+sp_cond_colon                   = force    # ignore/add/remove/force
+sp_cond_colon_before            = ignore   # ignore/add/remove/force
+sp_cond_colon_after             = ignore   # ignore/add/remove/force
+sp_cond_question                = force    # ignore/add/remove/force
+sp_cond_question_before         = ignore   # ignore/add/remove/force
+sp_cond_question_after          = ignore   # ignore/add/remove/force
+sp_cond_ternary_short           = ignore   # ignore/add/remove/force
+sp_case_label                   = force    # ignore/add/remove/force
+sp_range                        = ignore   # ignore/add/remove/force
+sp_after_for_colon              = ignore   # ignore/add/remove/force
+sp_before_for_colon             = ignore   # ignore/add/remove/force
+sp_extern_paren                 = ignore   # ignore/add/remove/force
+sp_cmt_cpp_start                = ignore   # ignore/add/remove/force
+sp_cmt_cpp_doxygen              = false    # true/false
+sp_cmt_cpp_qttr                 = false    # true/false
+sp_endif_cmt                    = force    # ignore/add/remove/force
+sp_after_new                    = ignore   # ignore/add/remove/force
+sp_between_new_paren            = ignore   # ignore/add/remove/force
+sp_after_newop_paren            = ignore   # ignore/add/remove/force
+sp_inside_newop_paren           = ignore   # ignore/add/remove/force
+sp_inside_newop_paren_open      = ignore   # ignore/add/remove/force
+sp_inside_newop_paren_close     = ignore   # ignore/add/remove/force
+sp_before_tr_emb_cmt            = force    # ignore/add/remove/force
+sp_num_before_tr_emb_cmt        = 1        # unsigned number
+sp_annotation_paren             = ignore   # ignore/add/remove/force
+sp_skip_vbrace_tokens           = false    # true/false
+sp_after_noexcept               = ignore   # ignore/add/remove/force
+sp_vala_after_translation       = ignore   # ignore/add/remove/force
+force_tab_after_define          = false    # true/false
+indent_columns                  = 4        # unsigned number
+indent_continue                 = 0        # number
+indent_continue_class_head      = 0        # unsigned number
+indent_single_newlines          = false    # true/false
+indent_param                    = 0        # unsigned number
+indent_with_tabs                = 0        # unsigned number
+indent_cmt_with_tabs            = false    # true/false
+indent_align_string             = true     # true/false
+indent_xml_string               = 0        # unsigned number
+indent_brace                    = 0        # unsigned number
+indent_braces                   = false    # true/false
+indent_braces_no_func           = false    # true/false
+indent_braces_no_class          = false    # true/false
+indent_braces_no_struct         = false    # true/false
+indent_brace_parent             = false    # true/false
+indent_paren_open_brace         = false    # true/false
+indent_cs_delegate_brace        = false    # true/false
+indent_cs_delegate_body         = false    # true/false
+indent_namespace                = false    # true/false
+indent_namespace_single_indent  = false    # true/false
+indent_namespace_level          = 0        # unsigned number
+indent_namespace_limit          = 0        # unsigned number
+indent_extern                   = false    # true/false
+indent_class                    = true     # true/false
+indent_class_colon              = true     # true/false
+indent_class_on_colon           = false    # true/false
+indent_constr_colon             = false    # true/false
+indent_ctor_init_leading        = 2        # unsigned number
+indent_ctor_init                = 0        # number
+indent_else_if                  = false    # true/false
+indent_var_def_blk              = 0        # number
+indent_var_def_cont             = false    # true/false
+indent_shift                    = false    # true/false
+indent_func_def_force_col1      = false    # true/false
+indent_func_call_param          = false    # true/false
+indent_func_def_param           = false    # true/false
+indent_func_proto_param         = false    # true/false
+indent_func_class_param         = false    # true/false
+indent_func_ctor_var_param      = false    # true/false
+indent_template_param           = false    # true/false
+indent_func_param_double        = false    # true/false
+indent_func_const               = 0        # unsigned number
+indent_func_throw               = 0        # unsigned number
+indent_member                   = 3        # unsigned number
+indent_member_single            = false    # true/false
+indent_sing_line_comments       = 0        # unsigned number
+indent_relative_single_line_comments = false    # true/false
+indent_switch_case              = 4        # unsigned number
+indent_switch_pp                = true     # true/false
+indent_case_shift               = 0        # unsigned number
+indent_case_brace               = 3        # number
+indent_col1_comment             = false    # true/false
+indent_col1_multi_string_literal = false    # true/false
+indent_label                    = 1        # number
+indent_access_spec              = 1        # number
+indent_access_spec_body         = false    # true/false
+indent_paren_nl                 = false    # true/false
+indent_paren_close              = 0        # unsigned number
+indent_paren_after_func_def     = false    # true/false
+indent_paren_after_func_decl    = false    # true/false
+indent_paren_after_func_call    = false    # true/false
+indent_comma_paren              = false    # true/false
+indent_bool_paren               = false    # true/false
+indent_semicolon_for_paren      = false    # true/false
+indent_first_bool_expr          = false    # true/false
+indent_first_for_expr           = false    # true/false
+indent_square_nl                = false    # true/false
+indent_preserve_sql             = false    # true/false
+indent_align_assign             = true     # true/false
+indent_align_paren              = true     # true/false
+indent_oc_block                 = false    # true/false
+indent_oc_block_msg             = 0        # unsigned number
+indent_oc_msg_colon             = 0        # unsigned number
+indent_oc_msg_prioritize_first_colon = true     # true/false
+indent_oc_block_msg_xcode_style = false    # true/false
+indent_oc_block_msg_from_keyword = false    # true/false
+indent_oc_block_msg_from_colon  = false    # true/false
+indent_oc_block_msg_from_caret  = false    # true/false
+indent_oc_block_msg_from_brace  = false    # true/false
+indent_min_vbrace_open          = 0        # unsigned number
+indent_vbrace_open_on_tabstop   = false    # true/false
+indent_token_after_brace        = true     # true/false
+indent_cpp_lambda_body          = false    # true/false
+indent_using_block              = true     # true/false
+indent_ternary_operator         = 0        # unsigned number
+indent_off_after_return_new     = false    # true/false
+indent_single_after_return      = false    # true/false
+indent_ignore_asm_block         = false    # true/false
+nl_collapse_empty_body          = false    # true/false
+nl_assign_leave_one_liners      = true     # true/false
+nl_class_leave_one_liners       = true     # true/false
+nl_enum_leave_one_liners        = false    # true/false
+nl_getset_leave_one_liners      = false    # true/false
+nl_cs_property_leave_one_liners = false    # true/false
+nl_func_leave_one_liners        = false    # true/false
+nl_cpp_lambda_leave_one_liners  = false    # true/false
+nl_if_leave_one_liners          = false    # true/false
+nl_while_leave_one_liners       = false    # true/false
+nl_for_leave_one_liners         = false    # true/false
+nl_oc_msg_leave_one_liner       = false    # true/false
+nl_oc_mdef_brace                = ignore   # ignore/add/remove/force
+nl_oc_block_brace               = ignore   # ignore/add/remove/force
+nl_oc_interface_brace           = ignore   # ignore/add/remove/force
+nl_oc_implementation_brace      = ignore   # ignore/add/remove/force
+nl_start_of_file                = remove   # ignore/add/remove/force
+nl_start_of_file_min            = 0        # unsigned number
+nl_end_of_file                  = force    # ignore/add/remove/force
+nl_end_of_file_min              = 1        # unsigned number
+nl_assign_brace                 = add      # ignore/add/remove/force
+nl_assign_square                = ignore   # ignore/add/remove/force
+nl_tsquare_brace                = ignore   # ignore/add/remove/force
+nl_after_square_assign          = ignore   # ignore/add/remove/force
+nl_fcall_brace                  = add      # ignore/add/remove/force
+nl_enum_brace                   = force    # ignore/add/remove/force
+nl_enum_class                   = ignore   # ignore/add/remove/force
+nl_enum_class_identifier        = ignore   # ignore/add/remove/force
+nl_enum_identifier_colon        = ignore   # ignore/add/remove/force
+nl_enum_colon_type              = ignore   # ignore/add/remove/force
+nl_struct_brace                 = force    # ignore/add/remove/force
+nl_union_brace                  = force    # ignore/add/remove/force
+nl_if_brace                     = add      # ignore/add/remove/force
+nl_brace_else                   = add      # ignore/add/remove/force
+nl_elseif_brace                 = ignore   # ignore/add/remove/force
+nl_else_brace                   = add      # ignore/add/remove/force
+nl_else_if                      = ignore   # ignore/add/remove/force
+nl_before_if_closing_paren      = ignore   # ignore/add/remove/force
+nl_brace_finally                = ignore   # ignore/add/remove/force
+nl_finally_brace                = ignore   # ignore/add/remove/force
+nl_try_brace                    = ignore   # ignore/add/remove/force
+nl_getset_brace                 = force    # ignore/add/remove/force
+nl_for_brace                    = add      # ignore/add/remove/force
+nl_catch_brace                  = ignore   # ignore/add/remove/force
+nl_oc_catch_brace               = ignore   # ignore/add/remove/force
+nl_brace_catch                  = ignore   # ignore/add/remove/force
+nl_oc_brace_catch               = ignore   # ignore/add/remove/force
+nl_brace_square                 = ignore   # ignore/add/remove/force
+nl_brace_fparen                 = ignore   # ignore/add/remove/force
+nl_while_brace                  = add      # ignore/add/remove/force
+nl_scope_brace                  = ignore   # ignore/add/remove/force
+nl_unittest_brace               = ignore   # ignore/add/remove/force
+nl_version_brace                = ignore   # ignore/add/remove/force
+nl_using_brace                  = ignore   # ignore/add/remove/force
+nl_brace_brace                  = ignore   # ignore/add/remove/force
+nl_do_brace                     = add      # ignore/add/remove/force
+nl_brace_while                  = ignore   # ignore/add/remove/force
+nl_switch_brace                 = add      # ignore/add/remove/force
+nl_synchronized_brace           = ignore   # ignore/add/remove/force
+nl_multi_line_cond              = false    # true/false
+nl_multi_line_define            = true     # true/false
+nl_before_case                  = true     # true/false
+nl_after_case                   = true     # true/false
+nl_case_colon_brace             = ignore   # ignore/add/remove/force
+nl_before_throw                 = ignore   # ignore/add/remove/force
+nl_namespace_brace              = ignore   # ignore/add/remove/force
+nl_template_class               = ignore   # ignore/add/remove/force
+nl_class_brace                  = ignore   # ignore/add/remove/force
+nl_class_init_args              = ignore   # ignore/add/remove/force
+nl_constr_init_args             = ignore   # ignore/add/remove/force
+nl_enum_own_lines               = ignore   # ignore/add/remove/force
+nl_func_type_name               = remove   # ignore/add/remove/force
+nl_func_type_name_class         = ignore   # ignore/add/remove/force
+nl_func_class_scope             = ignore   # ignore/add/remove/force
+nl_func_scope_name              = ignore   # ignore/add/remove/force
+nl_func_proto_type_name         = remove   # ignore/add/remove/force
+nl_func_paren                   = remove   # ignore/add/remove/force
+nl_func_paren_empty             = ignore   # ignore/add/remove/force
+nl_func_def_paren               = remove   # ignore/add/remove/force
+nl_func_def_paren_empty         = ignore   # ignore/add/remove/force
+nl_func_call_paren              = ignore   # ignore/add/remove/force
+nl_func_call_paren_empty        = ignore   # ignore/add/remove/force
+nl_func_decl_start              = remove   # ignore/add/remove/force
+nl_func_def_start               = remove   # ignore/add/remove/force
+nl_func_decl_start_single       = ignore   # ignore/add/remove/force
+nl_func_def_start_single        = ignore   # ignore/add/remove/force
+nl_func_decl_start_multi_line   = false    # true/false
+nl_func_def_start_multi_line    = false    # true/false
+nl_func_decl_args               = add      # ignore/add/remove/force
+nl_func_def_args                = add      # ignore/add/remove/force
+nl_func_decl_args_multi_line    = false    # true/false
+nl_func_def_args_multi_line     = false    # true/false
+nl_func_decl_end                = remove   # ignore/add/remove/force
+nl_func_def_end                 = remove   # ignore/add/remove/force
+nl_func_decl_end_single         = ignore   # ignore/add/remove/force
+nl_func_def_end_single          = ignore   # ignore/add/remove/force
+nl_func_decl_end_multi_line     = false    # true/false
+nl_func_def_end_multi_line      = false    # true/false
+nl_func_decl_empty              = ignore   # ignore/add/remove/force
+nl_func_def_empty               = ignore   # ignore/add/remove/force
+nl_func_call_empty              = ignore   # ignore/add/remove/force
+nl_func_call_start              = ignore   # ignore/add/remove/force
+nl_func_call_start_multi_line   = false    # true/false
+nl_func_call_args_multi_line    = false    # true/false
+nl_func_call_end_multi_line     = false    # true/false
+nl_oc_msg_args                  = false    # true/false
+nl_fdef_brace                   = add      # ignore/add/remove/force
+nl_fdef_brace_cond              = ignore   # ignore/add/remove/force
+nl_cpp_ldef_brace               = ignore   # ignore/add/remove/force
+nl_return_expr                  = ignore   # ignore/add/remove/force
+nl_after_semicolon              = true     # true/false
+nl_paren_dbrace_open            = ignore   # ignore/add/remove/force
+nl_type_brace_init_lst          = ignore   # ignore/add/remove/force
+nl_type_brace_init_lst_open     = ignore   # ignore/add/remove/force
+nl_type_brace_init_lst_close    = ignore   # ignore/add/remove/force
+nl_after_brace_open             = true     # true/false
+nl_after_brace_open_cmt         = false    # true/false
+nl_after_vbrace_open            = false    # true/false
+nl_after_vbrace_open_empty      = false    # true/false
+nl_after_brace_close            = true     # true/false
+nl_after_vbrace_close           = false    # true/false
+nl_brace_struct_var             = ignore   # ignore/add/remove/force
+nl_define_macro                 = false    # true/false
+nl_squeeze_paren_close          = false    # true/false
+nl_squeeze_ifdef                = true     # true/false
+nl_squeeze_ifdef_top_level      = false    # true/false
+nl_before_if                    = force    # ignore/add/remove/force
+nl_after_if                     = force    # ignore/add/remove/force
+nl_before_for                   = force    # ignore/add/remove/force
+nl_after_for                    = force    # ignore/add/remove/force
+nl_before_while                 = force    # ignore/add/remove/force
+nl_after_while                  = force    # ignore/add/remove/force
+nl_before_switch                = force    # ignore/add/remove/force
+nl_after_switch                 = force    # ignore/add/remove/force
+nl_before_synchronized          = ignore   # ignore/add/remove/force
+nl_after_synchronized           = ignore   # ignore/add/remove/force
+nl_before_do                    = force    # ignore/add/remove/force
+nl_after_do                     = force    # ignore/add/remove/force
+nl_before_return                = false    # true/false
+nl_after_return                 = true     # true/false
+nl_ds_struct_enum_cmt           = false    # true/false
+nl_ds_struct_enum_close_brace   = false    # true/false
+nl_class_colon                  = ignore   # ignore/add/remove/force
+nl_constr_colon                 = ignore   # ignore/add/remove/force
+nl_namespace_two_to_one_liner   = false    # true/false
+nl_create_if_one_liner          = false    # true/false
+nl_create_for_one_liner         = false    # true/false
+nl_create_while_one_liner       = false    # true/false
+nl_create_func_def_one_liner    = false    # true/false
+nl_split_if_one_liner           = false    # true/false
+nl_split_for_one_liner          = false    # true/false
+nl_split_while_one_liner        = false    # true/false
+nl_max                          = 4        # unsigned number
+nl_max_blank_in_func            = 0        # unsigned number
+nl_before_func_body_proto       = 0        # unsigned number
+nl_before_func_body_def         = 0        # unsigned number
+nl_before_func_class_proto      = 0        # unsigned number
+nl_before_func_class_def        = 0        # unsigned number
+nl_after_func_proto             = 0        # unsigned number
+nl_after_func_proto_group       = 1        # unsigned number
+nl_after_func_class_proto       = 0        # unsigned number
+nl_after_func_class_proto_group = 0        # unsigned number
+nl_class_leave_one_liner_groups = false    # true/false
+nl_after_func_body              = 0        # unsigned number
+nl_after_func_body_class        = 2        # unsigned number
+nl_after_func_body_one_liner    = 0        # unsigned number
+nl_func_var_def_blk             = 1        # unsigned number
+nl_typedef_blk_start            = 0        # unsigned number
+nl_typedef_blk_end              = 0        # unsigned number
+nl_typedef_blk_in               = 0        # unsigned number
+nl_var_def_blk_start            = 0        # unsigned number
+nl_var_def_blk_end              = 0        # unsigned number
+nl_var_def_blk_in               = 0        # unsigned number
+nl_before_block_comment         = 2        # unsigned number
+nl_before_c_comment             = 0        # unsigned number
+nl_before_cpp_comment           = 0        # unsigned number
+nl_after_multiline_comment      = false    # true/false
+nl_after_label_colon            = false    # true/false
+nl_after_struct                 = 0        # unsigned number
+nl_before_class                 = 0        # unsigned number
+nl_after_class                  = 0        # unsigned number
+nl_before_access_spec           = 0        # unsigned number
+nl_after_access_spec            = 0        # unsigned number
+nl_comment_func_def             = 0        # unsigned number
+nl_after_try_catch_finally      = 0        # unsigned number
+nl_around_cs_property           = 0        # unsigned number
+nl_between_get_set              = 0        # unsigned number
+nl_property_brace               = ignore   # ignore/add/remove/force
+nl_inside_namespace             = 0        # unsigned number
+eat_blanks_after_open_brace     = true     # true/false
+eat_blanks_before_close_brace   = true     # true/false
+nl_remove_extra_newlines        = 0        # unsigned number
+nl_after_annotation             = ignore   # ignore/add/remove/force
+nl_between_annotation           = ignore   # ignore/add/remove/force
+pos_arith                       = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_assign                      = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_bool                        = trail    # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_compare                     = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_conditional                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_comma                       = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_enum_comma                  = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_class_comma                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_constr_comma                = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_class_colon                 = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+pos_constr_colon                = ignore   # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force
+code_width                      = 0        # unsigned number
+ls_for_split_full               = false    # true/false
+ls_func_split_full              = false    # true/false
+ls_code_width                   = false    # true/false
+align_keep_tabs                 = false    # true/false
+align_with_tabs                 = false    # true/false
+align_on_tabstop                = false    # true/false
+align_number_right              = false    # true/false
+align_keep_extra_space          = false    # true/false
+align_func_params               = false    # true/false
+align_func_params_span          = 0        # unsigned number
+align_func_params_thresh        = 0        # number
+align_func_params_gap           = 0        # unsigned number
+align_constr_value_span         = 0        # unsigned number
+align_constr_value_thresh       = 0        # number
+align_constr_value_gap          = 0        # unsigned number
+align_same_func_call_params     = false    # true/false
+align_same_func_call_params_span = 0        # unsigned number
+align_same_func_call_params_thresh = 0        # number
+align_var_def_span              = 0        # unsigned number
+align_var_def_star_style        = 0        # unsigned number
+align_var_def_amp_style         = 1        # unsigned number
+align_var_def_thresh            = 16       # number
+align_var_def_gap               = 0        # unsigned number
+align_var_def_colon             = false    # true/false
+align_var_def_colon_gap         = 0        # unsigned number
+align_var_def_attribute         = false    # true/false
+align_var_def_inline            = false    # true/false
+align_assign_span               = 0        # unsigned number
+align_assign_func_proto_span    = 0        # unsigned number
+align_assign_thresh             = 12       # number
+align_assign_decl_func          = 0        # unsigned number
+align_enum_equ_span             = 0        # unsigned number
+align_enum_equ_thresh           = 0        # number
+align_var_class_span            = 0        # unsigned number
+align_var_class_thresh          = 0        # number
+align_var_class_gap             = 0        # unsigned number
+align_var_struct_span           = 0        # unsigned number
+align_var_struct_thresh         = 0        # number
+align_var_struct_gap            = 0        # unsigned number
+align_struct_init_span          = 3        # unsigned number
+align_typedef_span              = 5        # unsigned number
+align_typedef_gap               = 3        # unsigned number
+align_typedef_func              = 0        # unsigned number
+align_typedef_star_style        = 1        # unsigned number
+align_typedef_amp_style         = 1        # unsigned number
+align_right_cmt_span            = 3        # unsigned number
+align_right_cmt_gap             = 0        # unsigned number
+align_right_cmt_mix             = false    # true/false
+align_right_cmt_same_level      = false    # true/false
+align_right_cmt_at_col          = 0        # unsigned number
+align_func_proto_span           = 0        # unsigned number
+align_func_proto_thresh         = 0        # number
+align_func_proto_gap            = 0        # unsigned number
+align_on_operator               = false    # true/false
+align_mix_var_proto             = false    # true/false
+align_single_line_func          = false    # true/false
+align_single_line_brace         = false    # true/false
+align_single_line_brace_gap     = 0        # unsigned number
+align_oc_msg_spec_span          = 0        # unsigned number
+align_nl_cont                   = true     # true/false
+align_pp_define_together        = false    # true/false
+align_pp_define_span            = 3        # unsigned number
+align_pp_define_gap             = 4        # unsigned number
+align_left_shift                = true     # true/false
+align_asm_colon                 = false    # true/false
+align_oc_msg_colon_span         = 0        # unsigned number
+align_oc_msg_colon_first        = false    # true/false
+align_oc_decl_colon             = false    # true/false
+cmt_width                       = 0        # unsigned number
+cmt_reflow_mode                 = 0        # unsigned number
+cmt_convert_tab_to_spaces       = false    # true/false
+cmt_indent_multi                = true     # true/false
+cmt_c_group                     = false    # true/false
+cmt_c_nl_start                  = false    # true/false
+cmt_c_nl_end                    = false    # true/false
+cmt_cpp_to_c                    = true     # true/false
+cmt_cpp_group                   = false    # true/false
+cmt_cpp_nl_start                = false    # true/false
+cmt_cpp_nl_end                  = false    # true/false
+cmt_star_cont                   = true     # true/false
+cmt_sp_before_star_cont         = 0        # unsigned number
+cmt_sp_after_star_cont          = 0        # unsigned number
+cmt_multi_check_last            = true     # true/false
+cmt_multi_first_len_minimum     = 4        # unsigned number
+cmt_insert_file_header          = ""         # string
+cmt_insert_file_footer          = ""         # string
+cmt_insert_func_header          = ""         # string
+cmt_insert_class_header         = ""         # string
+cmt_insert_oc_msg_header        = ""         # string
+cmt_insert_before_preproc       = false    # true/false
+cmt_insert_before_inlines       = true     # true/false
+cmt_insert_before_ctor_dtor     = false    # true/false
+mod_full_brace_do               = add      # ignore/add/remove/force
+mod_full_brace_for              = add      # ignore/add/remove/force
+mod_full_brace_function         = ignore   # ignore/add/remove/force
+mod_full_brace_if               = add      # ignore/add/remove/force
+mod_full_brace_if_chain         = false    # true/false
+mod_full_brace_if_chain_only    = false    # true/false
+mod_full_brace_while            = add      # ignore/add/remove/force
+mod_full_brace_using            = ignore   # ignore/add/remove/force
+mod_full_brace_nl               = 0        # unsigned number
+mod_full_brace_nl_block_rem_mlcond = false    # true/false
+mod_paren_on_return             = ignore   # ignore/add/remove/force
+mod_pawn_semicolon              = false    # true/false
+mod_full_paren_if_bool          = true     # true/false
+mod_remove_extra_semicolon      = true     # true/false
+mod_add_long_function_closebrace_comment = 0        # unsigned number
+mod_add_long_namespace_closebrace_comment = 0        # unsigned number
+mod_add_long_class_closebrace_comment = 0        # unsigned number
+mod_add_long_switch_closebrace_comment = 0        # unsigned number
+mod_add_long_ifdef_endif_comment = 10       # unsigned number
+mod_add_long_ifdef_else_comment = 10       # unsigned number
+mod_sort_import                 = false    # true/false
+mod_sort_using                  = false    # true/false
+mod_sort_include                = false    # true/false
+mod_move_case_break             = false    # true/false
+mod_case_brace                  = remove   # ignore/add/remove/force
+mod_remove_empty_return         = true     # true/false
+mod_enum_last_comma             = ignore   # ignore/add/remove/force
+mod_sort_oc_properties          = false    # true/false
+mod_sort_oc_property_class_weight = 0        # number
+mod_sort_oc_property_thread_safe_weight = 0        # number
+mod_sort_oc_property_readwrite_weight = 0        # number
+mod_sort_oc_property_reference_weight = 0        # number
+mod_sort_oc_property_getter_weight = 0        # number
+mod_sort_oc_property_setter_weight = 0        # number
+mod_sort_oc_property_nullability_weight = 0        # number
+pp_indent                       = force    # ignore/add/remove/force
+pp_indent_at_level              = true     # true/false
+pp_indent_count                 = 4        # unsigned number
+pp_space                        = remove   # ignore/add/remove/force
+pp_space_count                  = 0        # unsigned number
+pp_indent_region                = 0        # number
+pp_region_indent_code           = false    # true/false
+pp_indent_if                    = 0        # number
+pp_if_indent_code               = true     # true/false
+pp_define_at_level              = false    # true/false
+pp_ignore_define_body           = false    # true/false
+pp_indent_case                  = true     # true/false
+pp_indent_func_def              = true     # true/false
+pp_indent_extern                = true     # true/false
+pp_indent_brace                 = false    # true/false
+include_category_0              = ""         # string
+include_category_1              = ""         # string
+include_category_2              = ""         # string
+use_indent_func_call_param      = true     # true/false
+use_indent_continue_only_once   = false    # true/false
+indent_cpp_lambda_only_once     = false    # true/false
+use_options_overriding_for_qt_macros = true     # true/false
+warn_level_tabs_found_in_verbatim_string_literals = 2        # unsigned number

.github/workflows/auto-release.yml

@@ -0,0 +1,77 @@
+name: Kernel-Auto-Release
+
+on:
+  workflow_dispatch:
+    inputs:
+      commit_id:
+        description: 'Commit ID'
+        required: true
+        default: 'HEAD'
+      version_number:
+        description: 'Version Number (Ex. 10.4.4)'
+        required: true
+        default: '10.4.4'
+      main_br_version:
+        description: "Version String for task.h on main branch (leave empty to leave as-is)."
+        required: false
+        default: ''
+
+jobs:
+  release-packager:
+    name: Release Packager
+    runs-on: ubuntu-latest
+    steps:
+      # Install python 3
+      - name: Tool Setup
+        uses: actions/setup-python@v2
+        with:
+          python-version: 3.7.10
+          architecture:   x64
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+
+      # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
+      - name: Checkout FreeRTOS Release Tools
+        uses: actions/checkout@v2
+        with:
+          repository: FreeRTOS/FreeRTOS
+          path: tools
+
+      # Simpler git auth if we use checkout action and forward the repo to release script
+      - name: Checkout FreeRTOS Kernel
+        uses: actions/checkout@v2
+        with:
+          path: local_kernel
+          fetch-depth: 0
+
+      - name: Configure git identity
+        run: |
+          git config --global user.name ${{ github.actor }}
+          git config --global user.email ${{ github.actor }}@users.noreply.github.com
+
+      - name: create a new branch that references commit id
+        working-directory: ./local_kernel
+        run: git checkout -b ${{ github.event.inputs.version_number }} ${{ github.event.inputs.commit_id }}
+
+      - name: Generate SBOM
+        uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main
+        with:
+          repo_path: ./local_kernel
+          source_path: ./
+
+      - name: commit SBOM file
+        working-directory: ./local_kernel
+        run: |
+          git add .
+          git commit -m 'Update SBOM'
+          git push -u origin ${{ github.event.inputs.version_number }}
+          echo "COMMIT_SHA=$(git rev-parse HEAD)" >> $GITHUB_ENV
+
+      - name: Release
+        run: |
+          # Install deps and run
+          pip install -r ./tools/.github/scripts/release-requirements.txt
+          ./tools/.github/scripts/release.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          exit $?
+        env:
+            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

.github/workflows/ci.yml

@@ -0,0 +1,68 @@
+name: CI Checks
+on:
+  push:
+    branches: ["**"]
+  pull_request:
+    branches: [main]
+  workflow_dispatch:
+jobs:
+  spell-check:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout Parent Repo
+        uses: actions/checkout@v2
+        with:
+          ref: main
+          repository: aws/aws-iot-device-sdk-embedded-C
+          path: main
+      - name: Clone This Repo
+        uses: actions/checkout@v2
+        with:
+            path: ./kernel
+      - name: Install spell
+        run: |
+          sudo apt-get install spell
+          sudo apt-get install util-linux
+      - name: Check spelling
+        run: |
+          PATH=$PATH:main/tools/spell
+          # Make sure that the portable directory is not included in the spellcheck.
+          sed -i 's/find $DIRNAME/find $DIRNAME -not -path '*portable*'/g' main/tools/spell/find-unknown-comment-words
+          find-unknown-comment-words --directory kernel/ --lexicon ./kernel/.github/lexicon.txt
+          if [ "$?" = "0" ]; then
+            exit 0
+          else
+            exit 1
+          fi
+  formatting:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - name: Install Uncrustify
+        run: sudo apt-get install uncrustify=0.69.0+dfsg1-1build1
+      - name: Run Uncrustify
+        run: |
+          uncrustify --version
+          find . portable/MemMang/* portable/Common/* \( -name portable \) -prune -false -o -iname "*.[hc]" -exec uncrustify --check -c .github/uncrustify.cfg {} +
+      - name: Check For Trailing Whitespace
+        run: |
+          set +e
+          grep --exclude="README.md" --exclude-dir="portable"  -rnI -e "[[:blank:]]$" .
+          if [ "$?" = "0" ]; then
+            echo "Files have trailing whitespace."
+            exit 1
+          else
+            exit 0
+          fi
+
+  url-check:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Clone This Repo
+        uses: actions/checkout@v2
+        with:
+            path: ./kernel
+      - name: URL Checker
+        run: |
+            bash kernel/.github/actions/url_verifier.sh kernel
+

.github/workflows/git-secrets.yml

@@ -0,0 +1,24 @@
+name: git-secrets Check
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+jobs:
+  git-secrets:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: recursive
+      - name: Checkout awslabs/git-secrets
+        uses: actions/checkout@v2
+        with:
+          repository: awslabs/git-secrets
+          ref: master
+          path: git-secrets
+      - name: Install git-secrets
+        run: cd git-secrets && sudo make install && cd ..
+      - name: Run git-secrets
+        run: |
+          git-secrets --register-aws
+          git-secrets --scan

.github/workflows/kernel-checks.yml

@@ -0,0 +1,72 @@
+name: Kernel-Checker
+
+on: [push, pull_request]
+
+jobs:
+  kernel-checker:
+    name: FreeRTOS Kernel Header Checks
+    runs-on: ubuntu-latest
+    steps:
+      # Install python 3
+      - name: Tool Setup
+        uses: actions/setup-python@v2
+        with:
+          python-version: 3.7.10
+          architecture:   x64
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+
+      # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
+      - name: Checkout FreeRTOS Tools
+        uses: actions/checkout@v2
+        with:
+          repository: FreeRTOS/FreeRTOS
+          ref:  main
+          path: tools
+
+      # Checkout user pull request changes
+      - name: Checkout Pull Request
+        uses: actions/checkout@v2
+        with:
+          ref:  ${{ github.event.pull_request.head.sha }}
+          path: inspect
+
+      # Collect all affected files
+      - name: Collecting changed files
+        uses: lots0logs/gh-action-get-changed-files@2.1.4
+        with:
+          token: ${{ secrets.GITHUB_TOKEN }}
+
+      # Run checks
+      - name: Check File Headers
+        run: |
+          mv tools/.github/scripts/common inspect/.github/scripts
+          pip install -r inspect/.github/scripts/common/requirements.txt
+          cd inspect
+          .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json
+          exit $?
+  build-checker:
+    name: FreeRTOS Posix Build Check
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout the parent repository
+        uses: actions/checkout@v2
+        with:
+          ref: main
+          repository: FreeRTOS/FreeRTOS
+          submodules: 'recursive'
+          fetch-depth: 1
+          path: ./workspace
+      - name: Checkout the current repository
+        uses: actions/checkout@v2
+        with:
+          path: ./workspace/FreeRTOS/Source
+      - name: Posix Build Checker
+        run: |
+              bash workspace/.github/scripts/posix_build_checker.sh workspace
+      - name: Install lib pcap dev
+        run: |
+          sudo apt-get install libpcap-dev
+      - name: Posix Network Build Checker
+        run: |
+          bash workspace/.github/scripts/posix_network_build_checker.sh workspace

.github/workflows/unit-tests.yml

@@ -0,0 +1,54 @@
+name: CMock Unit Tests
+on: [push, pull_request]
+
+jobs:
+  run:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Checkout Parent Repository
+      uses: actions/checkout@v2
+      with:
+        ref: main
+        repository: FreeRTOS/FreeRTOS
+        submodules: 'recursive'
+        fetch-depth: 1
+    - name: Clone This Repo
+      uses: actions/checkout@v2
+      with:
+        path: ./FreeRTOS/Source
+
+    - name: Setup Python
+      uses: actions/setup-python@master
+      with:
+        python-version: 3.8
+
+    - name: Install packages
+      run: |
+          sudo apt-get install lcov cflow ruby doxygen build-essential unifdef
+    - name: Run Unit Tests with ENABLE_SANITIZER=1
+      run: |
+          make -C FreeRTOS/Test/CMock clean
+          make -C FreeRTOS/Test/CMock ENABLE_SANITIZER=1 run_col_formatted
+    - name: Run Unit Tests for coverage
+      run: |
+          make -C FreeRTOS/Test/CMock clean
+          make -C FreeRTOS/Test/CMock lcovhtml
+          lcov --config-file FreeRTOS/Test/CMock/lcovrc --summary FreeRTOS/Test/CMock/build/cmock_test.info > FreeRTOS/Test/CMock/build/cmock_test_summary.txt
+    - name: Upload coverage to Codecov
+      uses: codecov/codecov-action@v3.1.0
+      with:
+        files: ${{ github.workspace }}/FreeRTOS/Test/CMock/build/cmock_test.info
+        root_dir: ${{ github.workspace }}/FreeRTOS/Source
+        flags: unittests
+        fail_ci_if_error: false
+        verbose: false
+    - name: Archive code coverage data
+      uses: actions/upload-artifact@v2
+      with:
+        name: coverage-data
+        path: FreeRTOS/Test/CMock/build/cmock_test*
+    - name: Archive code coverage html report
+      uses: actions/upload-artifact@v2
+      with:
+        name: coverage-report
+        path: FreeRTOS/Test/CMock/build/coverage

.gitmodules

@@ -0,0 +1,6 @@
+[submodule "ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports"]
+	path = portable/ThirdParty/Partner-Supported-Ports
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports
+[submodule "ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports"]
+	path = portable/ThirdParty/Community-Supported-Ports
+	url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports

CMakeLists.txt

@@ -0,0 +1,208 @@
+cmake_minimum_required(VERSION 3.15)
+
+# User is responsible to set two mandatory options:
+# FREERTOS_CONFIG_FILE_DIRECTORY
+# FREERTOS_PORT
+#
+# User can choose which heap implementation to use (either the implementations
+# included with FreeRTOS [1..5] or a custom implementation ) by providing the
+# option FREERTOS_HEAP. If the option is not set, the cmake will default to
+# using heap_4.c.
+
+# Absolute path to FreeRTOS config file directory
+set(FREERTOS_CONFIG_FILE_DIRECTORY "" CACHE STRING "Absolute path to the directory with FreeRTOSConfig.h")
+
+if(NOT FREERTOS_CONFIG_FILE_DIRECTORY)
+    message(FATAL_ERROR " FreeRTOSConfig.h file directory not specified. Please specify absolute path to it from top-level CMake file:\n"
+        "  set(FREERTOS_CONFIG_FILE_DIRECTORY <absolute path to FreeRTOSConfig.h directory> CACHE STRING \"\")\n"
+        " or from CMake command line option:\n"
+        "  -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'")
+elseif(NOT EXISTS ${FREERTOS_CONFIG_FILE_DIRECTORY}/FreeRTOSConfig.h)
+    message(FATAL_ERROR " FreeRTOSConfig.h file not found in the directory specified (${FREERTOS_CONFIG_FILE_DIRECTORY})\n"
+        " Please specify absolute path to it from top-level CMake file:\n"
+        "  set(FREERTOS_CONFIG_FILE_DIRECTORY <absolute path to FreeRTOSConfig.h directory> CACHE STRING \"\")\n"
+        " or from CMake command line option:\n"
+        "  -DFREERTOS_CONFIG_FILE_DIRECTORY='/absolute_path/to/FreeRTOSConfig.h/directory'")
+endif()
+
+# Heap number or absolute path to custom heap implementation provided by user
+set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file")
+
+# FreeRTOS port option
+set(FREERTOS_PORT "" CACHE STRING "FreeRTOS port name")
+
+if(NOT FREERTOS_PORT)
+    message(FATAL_ERROR " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n"
+        "  set(FREERTOS_PORT GCC_ARM_CM4F CACHE STRING \"\")\n"
+        " or from CMake command line option:\n"
+        "  -DFREERTOS_PORT=GCC_ARM_CM4F\n"
+        " \n"
+        " Available port options:\n"
+        " BCC_16BIT_DOS_FLSH186            - Compiller: BCC           Target: 16 bit DOS Flsh186\n"
+        " BCC_16BIT_DOS_PC                 - Compiller: BCC           Target: 16 bit DOS PC\n"
+        " CCS_ARM_CM3                      - Compiller: CCS           Target: ARM Cortex-M3\n"
+        " CCS_ARM_CM4F                     - Compiller: CCS           Target: ARM Cortex-M4 with FPU\n"
+        " CCS_ARM_CR4                      - Compiller: CCS           Target: ARM Cortex-R4\n"
+        " CCS_MSP430X                      - Compiller: CCS           Target: MSP430X\n"
+        " CODEWARRIOR_COLDFIRE_V1          - Compiller: CoreWarrior   Target: ColdFire V1\n"
+        " CODEWARRIOR_COLDFIRE_V2          - Compiller: CoreWarrior   Target: ColdFire V2\n"
+        " CODEWARRIOR_HCS12                - Compiller: CoreWarrior   Target: HCS12\n"
+        " GCC_ARM_CA9                      - Compiller: GCC           Target: ARM Cortex-A9\n"
+        " GCC_ARM_CA53_64_BIT              - Compiller: GCC           Target: ARM Cortex-A53 64 bit\n"
+        " GCC_ARM_CA53_64_BIT_SRE          - Compiller: GCC           Target: ARM Cortex-A53 64 bit SRE\n"
+        " GCC_ARM_CM0                      - Compiller: GCC           Target: ARM Cortex-M0\n"
+        " GCC_ARM_CM3                      - Compiller: GCC           Target: ARM Cortex-M3\n"
+        " GCC_ARM_CM3_MPU                  - Compiller: GCC           Target: ARM Cortex-M3 with MPU\n"
+        " GCC_ARM_CM4_MPU                  - Compiller: GCC           Target: ARM Cortex-M4 with MPU\n"
+        " GCC_ARM_CM4F                     - Compiller: GCC           Target: ARM Cortex-M4 with FPU\n"
+        " GCC_ARM_CM7                      - Compiller: GCC           Target: ARM Cortex-M7\n"
+        " GCC_ARM_CM23_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M23 non-secure\n"
+        " GCC_ARM_CM23_SECURE              - Compiller: GCC           Target: ARM Cortex-M23 secure\n"
+        " GCC_ARM_CM23_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M23 non-trustzone non-secure\n"
+        " GCC_ARM_CM33_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M33 non-secure\n"
+        " GCC_ARM_CM33_SECURE              - Compiller: GCC           Target: ARM Cortex-M33 secure\n"
+        " GCC_ARM_CM33_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M33 non-trustzone non-secure\n"
+        " GCC_ARM_CM33_TFM                 - Compiller: GCC           Target: ARM Cortex-M33 non-secure for TF-M\n"
+        " GCC_ARM_CM55_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M55 non-secure\n"
+        " GCC_ARM_CM55_SECURE              - Compiller: GCC           Target: ARM Cortex-M55 secure\n"
+        " GCC_ARM_CM55_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M55 non-trustzone non-secure\n"
+        " GCC_ARM_CM55_TFM                 - Compiller: GCC           Target: ARM Cortex-M55 non-secure for TF-M\n"
+        " GCC_ARM_CM85_NONSECURE           - Compiller: GCC           Target: ARM Cortex-M85 non-secure\n"
+        " GCC_ARM_CM85_SECURE              - Compiller: GCC           Target: ARM Cortex-M85 secure\n"
+        " GCC_ARM_CM85_NTZ_NONSECURE       - Compiller: GCC           Target: ARM Cortex-M85 non-trustzone non-secure\n"
+        " GCC_ARM_CM85_TFM                 - Compiller: GCC           Target: ARM Cortex-M85 non-secure for TF-M\n"
+        " GCC_ARM_CR5                      - Compiller: GCC           Target: ARM Cortex-R5\n"
+        " GCC_ARM_CRX_NOGIC                - Compiller: GCC           Target: ARM Cortex-Rx no GIC\n"
+        " GCC_ARM7_AT91FR40008             - Compiller: GCC           Target: ARM7 Atmel AT91R40008\n"
+        " GCC_ARM7_AT91SAM7S               - Compiller: GCC           Target: ARM7 Atmel AT91SAM7S\n"
+        " GCC_ARM7_LPC2000                 - Compiller: GCC           Target: ARM7 LPC2000\n"
+        " GCC_ARM7_LPC23XX                 - Compiller: GCC           Target: ARM7 LPC23xx\n"
+        " GCC_ATMEGA323                    - Compiller: GCC           Target: ATMega323\n"
+        " GCC_AVR32_UC3                    - Compiller: GCC           Target: AVR32 UC3\n"
+        " GCC_COLDFIRE_V2                  - Compiller: GCC           Target: ColdFire V2\n"
+        " GCC_CORTUS_APS3                  - Compiller: GCC           Target: CORTUS APS3\n"
+        " GCC_H8S2329                      - Compiller: GCC           Target: H8S2329\n"
+        " GCC_HCS12                        - Compiller: GCC           Target: HCS12\n"
+        " GCC_IA32_FLAT                    - Compiller: GCC           Target: IA32 flat\n"
+        " GCC_MICROBLAZE                   - Compiller: GCC           Target: MicroBlaze\n"
+        " GCC_MICROBLAZE_V8                - Compiller: GCC           Target: MicroBlaze V8\n"
+        " GCC_MICROBLAZE_V9                - Compiller: GCC           Target: MicroBlaze V9\n"
+        " GCC_MSP430F449                   - Compiller: GCC           Target: MSP430F449\n"
+        " GCC_NIOSII                       - Compiller: GCC           Target: NiosII\n"
+        " GCC_PPC405_XILINX                - Compiller: GCC           Target: Xilinx PPC405\n"
+        " GCC_PPC440_XILINX                - Compiller: GCC           Target: Xilinx PPC440\n"
+        " GCC_RISC_V                       - Compiller: GCC           Target: RISC-V\n"
+        " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiller: GCC           Target: RISC-V Pulpino Vega RV32M1RM\n"
+        " GCC_RL78                         - Compiller: GCC           Target: Renesas RL78\n"
+        " GCC_RX100                        - Compiller: GCC           Target: Renesas RX100\n"
+        " GCC_RX200                        - Compiller: GCC           Target: Renesas RX200\n"
+        " GCC_RX600                        - Compiller: GCC           Target: Renesas RX600\n"
+        " GCC_RX600_V2                     - Compiller: GCC           Target: Renesas RX600 v2\n"
+        " GCC_RX700_V3_DPFPU               - Compiller: GCC           Target: Renesas RX700 v3 with DPFPU\n"
+        " GCC_STR75X                       - Compiller: GCC           Target: STR75x\n"
+        " GCC_TRICORE_1782                 - Compiller: GCC           Target: TriCore 1782\n"
+        " GCC_ARC_EM_HS                    - Compiller: GCC           Target: DesignWare ARC EM HS\n"
+        " GCC_ARC_V1                       - Compiller: GCC           Target: DesignWare ARC v1\n"
+        " GCC_ATMEGA                       - Compiller: GCC           Target: ATmega\n"
+        " GCC_POSIX                        - Compiller: GCC           Target: Posix\n"
+        " GCC_RP2040                       - Compiller: GCC           Target: RP2040 ARM Cortex-M0+\n"
+        " GCC_XTENSA_ESP32                 - Compiller: GCC           Target: Xtensa ESP32\n"
+        " GCC_AVRDX                        - Compiller: GCC           Target: AVRDx\n"
+        " GCC_AVR_MEGA0                    - Compiller: GCC           Target: AVR Mega0\n"
+        " IAR_78K0K                        - Compiller: IAR           Target: Renesas 78K0K\n"
+        " IAR_ARM_CA5_NOGIC                - Compiller: IAR           Target: ARM Cortex-A5 no GIC\n"
+        " IAR_ARM_CA9                      - Compiller: IAR           Target: ARM Cortex-A9\n"
+        " IAR_ARM_CM0                      - Compiller: IAR           Target: ARM Cortex-M0\n"
+        " IAR_ARM_CM3                      - Compiller: IAR           Target: ARM Cortex-M3\n"
+        " IAR_ARM_CM4F                     - Compiller: IAR           Target: ARM Cortex-M4 with FPU\n"
+        " IAR_ARM_CM4F_MPU                 - Compiller: IAR           Target: ARM Cortex-M4 with FPU and MPU\n"
+        " IAR_ARM_CM7                      - Compiller: IAR           Target: ARM Cortex-M7\n"
+        " IAR_ARM_CM23_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M23 non-secure\n"
+        " IAR_ARM_CM23_SECURE              - Compiller: IAR           Target: ARM Cortex-M23 secure\n"
+        " IAR_ARM_CM23_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M23 non-trustzone non-secure\n"
+        " IAR_ARM_CM33_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M33 non-secure\n"
+        " IAR_ARM_CM33_SECURE              - Compiller: IAR           Target: ARM Cortex-M33 secure\n"
+        " IAR_ARM_CM33_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M33 non-trustzone non-secure\n"
+        " IAR_ARM_CM55_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M55 non-secure\n"
+        " IAR_ARM_CM55_SECURE              - Compiller: IAR           Target: ARM Cortex-M55 secure\n"
+        " IAR_ARM_CM55_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M55 non-trustzone non-secure\n"
+        " IAR_ARM_CM85_NONSECURE           - Compiller: IAR           Target: ARM Cortex-M85 non-secure\n"
+        " IAR_ARM_CM85_SECURE              - Compiller: IAR           Target: ARM Cortex-M85 secure\n"
+        " IAR_ARM_CM85_NTZ_NONSECURE       - Compiller: IAR           Target: ARM Cortex-M85 non-trustzone non-secure\n"
+        " IAR_ARM_CRX_NOGIC                - Compiller: IAR           Target: ARM Cortex-Rx no GIC\n"
+        " IAR_ATMEGA323                    - Compiller: IAR           Target: ATMega323\n"
+        " IAR_ATMEL_SAM7S64                - Compiller: IAR           Target: Atmel SAM7S64\n"
+        " IAR_ATMEL_SAM9XE                 - Compiller: IAR           Target: Atmel SAM9XE\n"
+        " IAR_AVR_AVRDX                    - Compiller: IAR           Target: AVRDx\n"
+        " IAR_AVR_MEGA0                    - Compiller: IAR           Target: AVR Mega0\n"
+        " IAR_AVR32_UC3                    - Compiller: IAR           Target: AVR32 UC3\n"
+        " IAR_LPC2000                      - Compiller: IAR           Target: LPC2000\n"
+        " IAR_MSP430                       - Compiller: IAR           Target: MSP430\n"
+        " IAR_MSP430X                      - Compiller: IAR           Target: MSP430X\n"
+        " IAR_RISC_V                       - Compiller: IAR           Target: RISC-V\n"
+        " IAR_RL78                         - Compiller: IAR           Target: Renesas RL78\n"
+        " IAR_RX100                        - Compiller: IAR           Target: Renesas RX100\n"
+        " IAR_RX600                        - Compiller: IAR           Target: Renesas RX600\n"
+        " IAR_RX700_V3_DPFPU               - Compiller: IAR           Target: Renesas RX700 v3 with DPFPU\n"
+        " IAR_RX_V2                        - Compiller: IAR           Target: Renesas RX v2\n"
+        " IAR_STR71X                       - Compiller: IAR           Target: STR71x\n"
+        " IAR_STR75X                       - Compiller: IAR           Target: STR75x\n"
+        " IAR_STR91X                       - Compiller: IAR           Target: STR91x\n"
+        " IAR_V850ES_FX3                   - Compiller: IAR           Target: Renesas V850ES/Fx3\n"
+        " IAR_V850ES_HX3                   - Compiller: IAR           Target: Renesas V850ES/Hx3\n"
+        " MIKROC_ARM_CM4F                  - Compiller: MikroC        Target: ARM Cortex-M4 with FPU\n"
+        " MPLAB_PIC18F                     - Compiller: MPLAB         Target: PIC18F\n"
+        " MPLAB_PIC24                      - Compiller: MPLAB         Target: PIC24\n"
+        " MPLAB_PIC32MEC14XX               - Compiller: MPLAB         Target: PIC32MEC14xx\n"
+        " MPLAB_PIC32MX                    - Compiller: MPLAB         Target: PIC32MX\n"
+        " MPLAB_PIC32MZ                    - Compiller: MPLAB         Target: PIC32MZ\n"
+        " MSVC_MINGW                       - Compiller: MSVC or MinGW Target: x86\n"
+        " OWATCOM_16BIT_DOS_FLSH186        - Compiller: Open Watcom   Target: 16 bit DOS Flsh186\n"
+        " OWATCOM_16BIT_DOS_PC             - Compiller: Open Watcom   Target: 16 bit DOS PC\n"
+        " PARADIGM_TERN_EE_LARGE           - Compiller: Paradigm      Target: Tern EE large\n"
+        " PARADIGM_TERN_EE_SMALL           - Compiller: Paradigm      Target: Tern EE small\n"
+        " RENESAS_RX100                    - Compiller: Renesas       Target: RX100\n"
+        " RENESAS_RX200                    - Compiller: Renesas       Target: RX200\n"
+        " RENESAS_RX600                    - Compiller: Renesas       Target: RX600\n"
+        " RENESAS_RX600_V2                 - Compiller: Renesas       Target: RX600 v2\n"
+        " RENESAS_RX700_V3_DPFPU           - Compiller: Renesas       Target: RX700 v3 with DPFPU\n"
+        " RENESAS_SH2A_FPU                 - Compiller: Renesas       Target: SH2A with FPU\n"
+        " ROWLEY_MSP430F449                - Compiller: Rowley        Target: MSP430F449\n"
+        " RVDS_ARM_CA9                     - Compiller: RVDS          Target: ARM Cortex-A9\n"
+        " RVDS_ARM_CM0                     - Compiller: RVDS          Target: ARM Cortex-M0\n"
+        " RVDS_ARM_CM3                     - Compiller: RVDS          Target: ARM Cortex-M3\n"
+        " RVDS_ARM_CM4_MPU                 - Compiller: RVDS          Target: ARM Cortex-M4 with MPU\n"
+        " RVDS_ARM_CM4F                    - Compiller: RVDS          Target: ARM Cortex-M4 with FPU\n"
+        " RVDS_ARM_CM7                     - Compiller: RVDS          Target: ARM Cortex-M7\n"
+        " RVDS_ARM7_LPC21XX                - Compiller: RVDS          Target: ARM7 LPC21xx\n"
+        " SDCC_CYGNAL                      - Compiller: SDCC          Target: Cygnal\n"
+        " SOFTUNE_MB91460                  - Compiller: Softune       Target: MB91460\n"
+        " SOFTUNE_MB96340                  - Compiller: Softune       Target: MB96340\n"
+        " TASKING_ARM_CM4F                 - Compiller: Tasking       Target: ARM Cortex-M4 with FPU\n"
+        " CDK_THEAD_CK802                  - Compiller: CDK           Target: T-head CK802\n"
+        " XCC_XTENSA                       - Compiller: XCC           Target: Xtensa\n"
+        " WIZC_PIC18                       - Compiller: WizC          Target: PIC18")
+endif()
+
+add_subdirectory(portable)
+
+add_library(freertos_kernel STATIC
+    croutine.c
+    event_groups.c
+    list.c
+    queue.c
+    stream_buffer.c
+    tasks.c
+    timers.c
+
+    # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
+    $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
+)
+
+target_include_directories(freertos_kernel
+    PUBLIC
+        include
+        ${FREERTOS_CONFIG_FILE_DIRECTORY}
+)
+
+target_link_libraries(freertos_kernel freertos_kernel_port)

GitHub-FreeRTOS-Kernel-Home.url

@@ -0,0 +1,8 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=https://github.com/FreeRTOS/FreeRTOS-Kernel
+IconIndex=0
+IDList=
+HotKey=0
+

History.txt

@@ -1,15 +1,319 @@
-Documentation and download available at http://www.FreeRTOS.org/
+Changes between FreeRTOS V10.4.6 and FreeRTOS V10.5.0 released September 16 2022
+
+Documentation and download available at https://www.FreeRTOS.org/
+
+	+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
+	  already independently gained the ability to execute injected code to
+	  read from or write to arbitrary addresses by passing a negative argument
+	  as the xIndex parameter to pvTaskGetThreadLocalStoragePointer() or
+	  vTaskSetThreadLocalStoragePointer respectively. A check has been added to
+	  ensure that passing a negative argument as the xIndex parameter does not
+	  cause arbitrary read or write.
+	  We thank Certibit Consulting, LLC for reporting this issue.
+	+ ARMv7-M and ARMv8-M MPU ports: It was possible for an unprivileged task
+	  to invoke any function with privilege by passing it as a parameter to
+	  MPU_xTaskCreate, MPU_xTaskCreateStatic, MPU_xTimerCreate,
+	  MPU_xTimerCreateStatic, or MPU_xTimerPendFunctionCall. MPU_xTaskCreate
+	  and MPU_xTaskCreateStatic have been updated to only allow creation of
+	  unprivileged tasks. MPU_xTimerCreate, MPU_xTimerCreateStatic and
+	  MPU_xTimerPendFunctionCall APIs have been removed.
+	  We thank Huazhong University of Science and Technology for reporting
+	  this issue.
+	+ ARMv7-M and ARMv8-M MPU ports: It was possible for a third party that
+	  already independently gained the ability to execute injected code to
+	  achieve further privilege escalation by branching directly inside a
+	  FreeRTOS MPU API wrapper function with a manually crafted stack frame.
+	  The local stack variable `xRunningPrivileged` has been removed so that
+	  a manually crafted stack frame cannot be used for privilege escalation
+	  by branching directly inside a FreeRTOS MPU API wrapper.
+	  We thank Certibit Consulting, LLC, Huazhong University of Science and
+	  Technology and the SecLab team at Northeastern University for reporting
+	  this issue.
+	+ ARMv7-M MPU ports: It was possible to configure overlapping memory
+	  protection unit (MPU) regions such that an unprivileged task could access
+	  privileged data. The kernel now uses highest numbered MPU regions for
+	  kernel protections to prevent such MPU configurations.
+	  We thank the SecLab team at Northeastern University for reporting this
+	  issue.
+	+ Add support for ARM Cortex-M55.
+	+ Add support for ARM Cortex-M85. Contributed by @gbrtth.
+	+ Add vectored mode interrupt support to the RISC-V port.
+	+ Add support for RV32E extension (Embedded Profile) in RISC-V GCC port.
+	  Contributed by @Limoto.
+	+ Heap improvements:
+	  - Add a check to heap_2 to track if a memory block is allocated to
+	    the application or not. The MSB of the size field is used for this
+	    purpose. The same check already exists in heap_4 and heap_5. This
+	    check prevents double free errors.
+	  - Add a new flag configHEAP_CLEAR_MEMORY_ON_FREE to heap_2, heap_4
+	    and heap_5. If the flag is set in FreeRTOSConfig.h then memory freed using
+	    vPortFree() is automatically cleared to zero.
+	  - Add a new API pvPortCalloc to heap_2, heap_4 and heap_5 which has the same
+	    signature as the standard library calloc function.
+	  - Update the pointer types to portPOINTER_SIZE_TYPE. Contributed by
+	    @Octaviarius.
+	+ Add the ability to override send and receive completed callbacks for each
+	  instance of a stream buffer or message buffer. Earlier there could be
+	  one send and one receive callback for all instances of stream and message
+	  buffers. Having separate callbacks per instance allows different message
+	  and stream buffers to be used differently - for example, some for inter core
+	  communication and others for same core communication.
+	  The feature can be controlled by setting  the configuration option
+	  configUSE_SB_COMPLETED_CALLBACK in FreeRTOSConfig.h. When the option is set to 1,
+	  APIs xStreamBufferCreateWithCallback() or xStreamBufferCreateStaticWithCallback()
+	  (and likewise APIs for message buffer) can be used to create a stream buffer 
+	  or message buffer instance with application provided callback overrides. When
+	  the option is set to 0, then the default callbacks as defined by
+	  sbSEND_COMPLETED() and sbRECEIVE_COMPLETED() macros are invoked. To maintain 
+	  backwards compatibility, configUSE_SB_COMPLETED_CALLBACK defaults to 0. The 
+	  functionality is currently not supported for MPU enabled ports.
+	+ Generalize the FreeRTOS's Thread Local Storage (TLS) support so that it
+	  is not tied to newlib and can be used with other c-runtime libraries also.
+	  The default behavior for newlib support is kept same for backward
+	  compatibility.
+	+ Add support to build and link FreeRTOS using CMake build system. Contributed
+	  by @yhsb2k.
+	+ Add support to generate Software Bill of Materials (SBOM) for every release.
+	+ Add support for 16 MPU regions to the GCC Cortex-M33 ports.
+	+ Add ARM Cortex-M7 r0p0/r0p1 Errata 837070 workaround to ARM CM4 MPU ports.
+	  The application writer needs to define configENABLE_ERRATA_837070_WORKAROUND
+	  when using CM4 MPU ports on a Cortex-M7 r0p0/r0p1 core.
+	+ Add configSYSTICK_CLOCK_HZ to Cortex-M0 ports. This is needed to support
+	  the case when the SysTick timer is not clocked from the same source as the CPU.
+	+ Add hardware stack protection support to MicroBlazeV9 port. This ensures that
+	  the CPU immediately raises Stack Protection Violation exception as soon as any
+	  task violates its stack limits. Contributed by @uecasm.
+	+ Introduce the configUSE_MINI_LIST_ITEM configuration option. When this
+	  option is set to 1, ListItem_t and MiniLitItem_t remain separate types.
+	  However, when configUSE_MINI_LIST_ITEM == 0, MiniLitItem_t and ListItem_t
+	  are both typedefs of the same struct xLIST_ITEM. This addresses some issues
+	  observed when strict-aliasing and link time optimization are enabled.
+	  To maintain backwards compatibility, configUSE_MINI_LIST_ITEM defaults to 1.
+	+ Simplify prvInitialiseNewTask to memset newly allocated TCB structures
+	  to zero, and remove code that set individual structure members to zero.
+	+ Add prototype for prvPortYieldFromISR to the POSIX port so that it builds
+	  without any warning with -Wmissing-prototypes compiler option.
+	+ Add top of stack and end of stack to the task info report obtained using
+	  vTaskGetInfo(). Contributed by @shreyasbharath.
+	+ Add a cap to the cRxLock and cTxLock members of the queue data structure.
+	  These locks count the number items received and sent to the queue while
+	  the queue was locked. These are later used to unblock tasks waiting on
+	  the queue when the queue is unlocked. This PR caps the values of the
+	  cRxLock and cTxLock to the number of tasks in the system because we cannot
+	  unblock more tasks than there are in the system. Note that the same assert
+	  could still be triggered is the application creates more than 127 tasks.
+	+ Changed uxAutoReload parameter in timer functions to xAutoReload.  The
+	  type is now BaseType_t.  This matches the type of pdTRUE and pdFALSE.
+	  The new function xTimerGetAutoReload() provides the auto-reload state as
+	  a BaseType_t.  The legacy function uxTimerGetAutoReload is retained with the
+	  original UBaseType_t return value.
+	+ Fix support for user implementations of tickless idle that call
+	  vTaskStepTick() with xExpectedIdleTime ticks to step. The new code
+	  ensures xTickCount reaches xNextTaskUnblockTime inside xTaskIncrementTick()
+	  instead of inside vTaskStepTick(). This fixes the typical case where a task
+	  wakes up one tick late and a rare case assertion failure when xTickCount\
+	  rolls over. Contributed by @jefftenney.
+	+ Fix deadlock in event groups when pvPortMalloc and vPortFree functions
+	  are protected with a mutex. Contributed by @clemenskresser.
+	+ Fix a warning in tasks.c when compiled with -Wduplicated-branches
+	  GCC option. Contributed by @pierrenoel-bouteville-act.
+	+ Fix compilation error in tasks.c when configSUPPORT_DYNAMIC_ALLOCATION
+	  is set to zero. Contributed by @rdpoor.
+	+ Fix prvWriteMessageToBuffer() function in stream_buffer.c so that it correctly
+	  copies length on big endian platforms too.
+	+ Remove the need for  INCLUDE_vTaskSuspend to be set to 1
+	  when configUSE_TICKLESS_IDLE is enabled. Contributed by @pramithkv.
+	+ Update the RL78 IAR port to the latest version of IAR which uses the
+	  industry standard ELF format as opposed to earlier UBROF object format.
+	  Contributed by @felipe-iar.
+	+ Add tick type is atomic flag when tick count is 16-bit to PIC24 port. This
+	  allows the PIC24 family of 16 bit processors to read the tick count without
+	  a critical section when the tick count is also 16 bits.
+	+ Fix offset-out-of-range errors for GCC CM3/CM4 mpu ports when
+	  Link Time Optimization is enabled. Contributed by @niniemann.
+	+ Remove #error when RISC-V port is compiled on a 64-bit RISC-V platform.
+	  Contributed by @cmdrf.
+	+ Fix ullPortInterruptNesting alignment in Cortex-A53 port so that it is
+	  8-byte aligned. This fixes the unaligned access exception. Contributed
+	  by @Atomar25.
+	+ Fix  Interrupt Handler Register Function and Exception Process in NiosII
+	  Port. Contributed by @ghost.
+	+ Change FreeRTOS IRQ Handler for Cortex-A53 SRE port to store and restore
+	  interrupt acknowledge register. This ensures that the SRE port behavior
+	  matches the Memory Mapped IO port. Contributed by @sviaunxp.
+	+ Update the uncrustify config file to match the version of the uncrustify
+	  used in the CI Action. Also, pin the version of uncrustify in CI. Contributed
+	  by @swaldhoer.
+
+Changes between FreeRTOS V10.4.5 and FreeRTOS V10.4.6 released November 12 2021
+
+	+ ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the
+	  internal functions xPortRaisePrivilege and vPortResetPrivilege by changing
+	  them to macros.
+	+ Introduce a new config configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS which
+	  enables developers to prevent critical sections from unprivileged tasks.
+	  It defaults to 1 for backward compatibility. Application should set it to
+	  0 to disable critical sections from unprivileged tasks.
+
+Changes between FreeRTOS V10.4.4 and FreeRTOS V10.4.5 released September 10 2021
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html
+
+	+ Introduce configRUN_TIME_COUNTER_TYPE which enables developers to define
+	  the type used to hold run time statistic counters. Defaults to uint32_t
+	  for backward compatibility. #define configRUN_TIME_COUNTER_TYPE to a type
+	  (for example, uint64_t) in FreeRTOSConfig.h to override the default.
+	+ Introduce ulTaskGetIdleRunTimePercent() to complement the pre-existing
+	  ulTaskGetIdleRunTimeCounter(). Whereas the pre-existing function returns
+	  the raw run time counter value, the new function returns the percentage of
+	  the entire run time consumed by the idle task. Note the amount of idle
+	  time is only a good measure of the slack time in a system if there are no
+	  other tasks executing at the idle priority, tickless idle is not used, and
+	  configIDLE_SHOULD_YIELD is set to 0.
+	+ ARMv8-M secure-side port:  Tasks that call secure functions from the
+	  non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two
+	  contexts - one on the non-secure side and one on the secure-side. Previous
+	  versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures
+	  that reference secure-side contexts at run time.  Now the structures are
+	  allocated statically at compile time.  The change necessitates the
+	  introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant,
+	  which sets the number of statically allocated secure contexts.
+	  secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined.
+	  Applications that only use FreeRTOS code on the non-secure side, such as
+	  those running third-party code on the secure side, are not affected by
+	  this change.
+
+Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021
+	+ Minor performance improvements to xTaskIncrementTick() achieved by providing
+	  macro versions of uxListRemove() and vListInsertEnd().
+	+ Minor refactor of timers.c that obsoletes the need for the
+	  tmrCOMMAND_START_DONT_TRACE macro and removes the need for timers.c to
+	  post to its own event queue.  A consequence of this change is that auto-
+	  reload timers that miss their intended next execution time will execute
+	  again immediately rather than executing again the next time the command
+	  queue is processed.  (thanks Jeff Tenney).
+	+ Fix a race condition in the message buffer implementation.  The
+	  underlying cause was that length and data bytes are written and read as
+	  two distinct operations, which both modify the size of the buffer. If a
+	  context switch occurs after adding or removing the length bytes, but
+	  before adding or removing the data bytes, then another task may observe
+	  the message buffer in an invalid state.
+	+ The xTaskCreate() and xTaskCreateStatic() functions accept a task priority
+	  as an input parameter.  The priority has always been silently capped to
+	  (configMAX_PRIORITIES - 1) should it be set to a value above that priority.
+	  Now values above that priority will also trigger a configASSERT() failure.
+	+ Replace configASSERT( pcQueueName ) in vQueueAddToRegistry with a NULL
+	  pointer check.
+	+ Introduce the configSTACK_ALLOCATION_FROM_SEPARATE_HEAP configuration
+	  constant that enables the stack allocated to tasks to come from a heap other
+	  than the heap used by other memory allocations.  This enables stacks to be
+	  placed within special regions, such as fast tightly coupled memory.
+	+ If there is an attempt to add the same queue or semaphore handle to the
+	  queue registry more than once then prior versions would create two separate
+	  entries.  Now if this is done the first entry is overwritten rather than
+	  duplicated.
+	+ Update the ESP32 port and TF-M (Trusted Firmware M)code to the latest from
+	  their respective repositories.
+	+ Correct a build error in the POSIX port.
+	+ Additional minor formatting updates, including replacing tabs with spaces
+	  in more files.
+	+ Other minor updates include adding additional configASSERT() checks and
+	  correcting and improving code comments.
+	+ Go look at the smp branch to see the progress towards the Symetric
+	  Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
+
+Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
+
+	V10.4.3 is included in the 202012.00 LTS release.  Learn more at https:/freertos.org/lts-libraries.html
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Changes to improve robustness and consistency for buffer allocation in
+	  the heap, queue and stream buffer.
+	+ The following functions can no longer be called from unprivileged code.
+	  - xTaskCreateRestricted
+	  - xTaskCreateRestrictedStatic
+	  - vTaskAllocateMPURegions
+
+
+Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked
+	  between the first task starting to execute and that task making
+	  a FreeRTOS API call.
+	+ Introduced xTaskDelayUntil(), which is functionally equivalent to
+	  vTaskDelayUntil(), with the addition of returning a value to
+	  indicating whether or not the function placed the calling task into
+	  the Blocked state or not.
+	+ Update WolfSSL to 4.5.0 and add the FIPS ready demo.
+	+ Add support for ESP IDF 4.2 to ThirdParty Xtensa port.
+	+ Re-introduce uxTopUsedPriority to support OpenOCD debugging.
+	+ Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules.
+	+ Various general maintenance and improvements to MISRA compliance.
+
+
+Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Fixed an incorrectly named parameter that prevented the
+	  ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the
+	  test code that prevented this error causing test failures.
+
+
+Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	Major enhancements:
+
+	+ Task notifications:  Prior to FreeRTOS V10.4.0 each created task had a
+	  single direct to task notification.  From FreeRTOS V10.4.0 each task has
+	  an array of notifications.  The direct to task notification API has been
+	  extended with API functions postfixed with "Indexed" to enable the API to
+	  operate on a task notification at any array index.  See
+	  https://www.freertos.org/RTOS-task-notifications.html for more information.
+	+ Kernel ports that support memory protection units (MPUs): The ARMv7-M and
+	  ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M
+	  MPU ports now support devices that have 16 MPU regions, have the ability
+	  to override default memory attributes for privileged code and data
+	  regions, and have the ability to place the FreeRTOS kernel code outside of
+	  the Flash memory. The ARMv8-M MPU ports now support tickless idle mode.
+	  See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html
+	  for more information.
+
+	Additional noteworthy updates:
+
+	+ Code formatting is now automated to facilitate the increase in
+	  collaborative development in Git.  The auto-formated code is not identical
+	  to the original formatting conventions.  Most notably spaces are now used
+	  in place of tabs.
+	+ The prototypes for callback functions (those that start with "Application",
+	  such as vApplicationStackOverflowHook()) are now in the FreeRTOS header
+	  files, removing the need for application writers to add prototypes into
+	  the C files in which they define the functions.
+	+ New Renesas RXv3 port layer.
+	+ Updates to the Synopsys ARC code, including support for EM and HS cores,
+	  and updated BSP.
+	+ Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in
+	  the same way the Windows port layer enables FreeRTOS to run on Windows
+	  hosts.
+	+ Many other minor optimisations and enhancements. For full details
+	  see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/main
+
 
 Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020
 
-	See http://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
+	See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
 
-	./FreeRTOS-Labs directory was removed from this file. The libraries it 
+	+ ./FreeRTOS-Labs directory was removed from this file. The libraries it
 	contained are now available as a separate download.
 
 Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020
 
-	See http://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
+	See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
 
 	New and updated kernel ports:
 
@@ -203,8 +507,8 @@ Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0:
 
 	New Features and components:
 
-	+ Stream Buffers - see http://www.FreeRTOS.org/RTOS-stream-buffer-example.html
-	+ Message Buffers - see http://www.FreeRTOS.org//RTOS-message-buffer-example.html
+	+ Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html
+	+ Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html
 	+ Move FreeRTOS+TCP into the main repository, along with the basic Win32
 	  TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator.
 
@@ -306,7 +610,7 @@ Changes since FreeRTOS V9.0.0:
 
 Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016:
 
-	See http://www.FreeRTOS.org/FreeRTOS-V9.html
+	See https://www.FreeRTOS.org/FreeRTOS-V9.html
 
 	RTOS kernel updates:
 
@@ -315,7 +619,7 @@ Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016:
 	  "CreateStatic()" API functions.  The stack size parameter in
 	  xTaskCreateStatic() is now uint32_t, which changes the prototype of the
 	  callback functions.  See the following URL:
-	  http://www.freertos.org/xTaskCreateStatic.html
+	  https://www.FreeRTOS.org/xTaskCreateStatic.html
 	+ GCC ARM Cortex-A port:  Introduced the configUSE_TASK_FPU_SUPPORT
 	  constant.  When configUSE_TASK_FPU_SUPPORT is set to 2 every task is
 	  automatically given a floating point (FPU) context.
@@ -364,7 +668,7 @@ Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016:
 Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2)
 released March 30 2016:
 
-	NOTE - See http://www.FreeRTOS.org/FreeRTOS-V9.html for details
+	NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details
 
 	+ The functions that create RTOS objects using static memory allocation have
 	  been simplified and will not revert to using dynamic allocation if a
@@ -577,7 +881,7 @@ Changes between V8.1.2 and V8.2.0 released 16th January 2015
 	Significant RTOS kernel updates:
 
 	+ MAJOR NEW FEATURE!  Task notifications.  Please see the following URL for
-	  details: http://www.FreeRTOS.org/RTOS-task-notifications.html
+	  details: https://www.FreeRTOS.org/RTOS-task-notifications.html
 	+ NEW HEADER FILE REQUIRED!  Obsolete definitions have been separated into
 	  a new header file called FreeRTOS/Source/include/deprecated_definitions.h.
 	  This header file must be present to build.  Note some of the obsolete
@@ -741,21 +1045,21 @@ Changes between V8.0.0 and V8.0.1 released 2nd May 2014
 
 Changes between V7.6.0 and V8.0.0 released 19th Feb 2014
 
-	http://www.freertos.org/upgrading-to-FreeRTOS-V8.html
+	https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html
 
 	FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x,
 	although a change to the type used to reference character strings may result
 	in application code generating a few (easily clearable) compiler warnings
 	after the upgrade, and an updated typedef naming convention means use of the
 	old typedef names is now discouraged.
-	See http://www.freertos.org/upgrading-to-FreeRTOS-V8.html for full
+	See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full
 	information.
 
 	New features and functionality:
 
-	+ Event groups - see http://www.freertos.org/FreeRTOS-Event-Groups.html
+	+ Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html
 	+ Centralised deferred interrupt processing - see
-	  http://www.freertos.org/xTimerPendFunctionCallFromISR.html
+	  https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html
 
 	Other updates:
 
@@ -766,7 +1070,7 @@ Changes between V7.6.0 and V8.0.0 released 19th Feb 2014
 	  priority of the Running task.
 	+ New low power tickless demonstration project that targets the ST STM32L
 	  microcontroller - see
-	  http://www.freertos.org/STM32L-discovery-low-power-tickless-RTOS-demo.html
+	  https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html
 	+ Add xPortGetMinimumEverFreeHeapSize() to heap_4.c.
 	+ Small change to the tickless low power implementation on the SAM4L to
 	  ensure the alarm value (compare match value) cannot be set to zero when a
@@ -916,8 +1220,8 @@ Changes between V7.4.2 and V7.5.0 released July 19 2013
 
 	New API functions:
 
-	+ uxTaskGetSystemState() http://www.freertos.org/uxTaskGetSystemState.html
-	+ xQueueOverwrite() http://www.freertos.org/xQueueOverwrite.html
+	+ uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html
+	+ xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html
 	+ xQueueOverwriteFromISR()
 	+ xQueuePeekFromISR()
 
@@ -930,7 +1234,7 @@ Changes between V7.4.2 and V7.5.0 released July 19 2013
 	+ Microsemi SmartFusion2
 
 	New FreeRTOSConfig.h settings
-	http://shop.freertos.org/FreeRTOS_API_and_Configuration_Reference_s/1822.htm
+	https://freertos.org/a00110.html
 
 	+ configUSE_TIME_SLICING
 	+ configUSE_NEWLIB_REENTRANT
@@ -967,7 +1271,7 @@ Changes between V7.4.1 and V7.4.2 released May 1 2013
 
 	+ Added FreeRTOS+FAT SL source code and demo project.  The demo project
 	  runs in the FreeRTOS Windows simulator for easy and hardware independent
-	  experimentation and evaluation.  See http://www.FreeRTOS.org/fat_sl
+	  experimentation and evaluation.  See https://www.FreeRTOS.org/fat_sl
 
 Changes between V7.4.0 and V7.4.1 released April 18 2013
 
@@ -996,7 +1300,7 @@ Changes between V7.4.0 and V7.4.1 released April 18 2013
 Changes between V7.3.0 and V7.4.0 released February 20 2013
 
 	+ New feature:  Queue sets.  See:
-	  http://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html
+	  https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html
 	+ Overhauled the default tickless idle mode implementation provided with the
 	  ARM Cortex-M3 port layers.
 	+ Enhanced tickless support in the core kernel code with the introduction of
@@ -1143,7 +1447,7 @@ Changes between V7.1.0 and V7.1.1 released May 1 2012
 
 	+ Introduced the portSETUP_TCB() macro to remove the requirement for the
 	  Windows simulator to use the traceTASK_CREATE() macro, leaving the trace
-	  macro available for use by FreeRTOS+Trace (http://www.FreeRTOS.org/trace).
+	  macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace).
 	+ Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future
 	  FreeRTOS+Trace versions to provide even more information to users.
 	+ Updated the FreeRTOS MPU port to be correct for changes that were
@@ -1171,7 +1475,7 @@ Changes between V7.1.0 and V7.1.1 released May 1 2012
 
 	+ The command interpreter has now been formally released as FreeRTOS+CLI,
 	  and been moved out of the main FreeRTOS download, to instead be available
-	  from the FreeRTOS+ Ecosystem site http://www.FreeRTOS.org/plus.
+	  from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus.
 	+ flash_timer.c/h has been added to the list of standard demo tasks.  This
 	  performs the same functionality as the flash.c tasks, but using software
 	  timers in place of tasks.
@@ -1453,7 +1757,7 @@ Changes between V6.0.3 and V6.0.4 released March 14 2010
 	+ All the contributed files that were located in the Demo/Unsupported_Demos
 	  directory have been removed.  These files are instead now available in the
 	  new  Community Contributions section of the FreeRTOS website.  See
-	  http://www.freertos.org/RTOS-contributed-ports.html
+	  https://www.FreeRTOS.org/RTOS-contributed-ports.html
 	+ The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory
 	  has been upgraded to use V2.x of the Rowley Crossworks STM32 support
 	  package.
@@ -1746,9 +2050,6 @@ Changes between V4.8.0 and V5.0.0 released April 15, 2008
 	compiler might not issue any type mismatch warnings!
 
 
-	See http://www.FreeRTOS.org/upgrading.html for full information.
-
-
 	Other changes:
 
 	+ Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3
@@ -2002,7 +2303,7 @@ Changes between V4.0.1 and V4.0.2 released May 28, 2006
 	  it was also called when the tick function was called during the scheduler
 	  unlocking process.
 	+ The EMAC driver in the SAM7X lwIP demo has been made more robust as per
-	  the thread: http://sourceforge.net/forum/message.php?msg_id=3714405
+	  the thread: https://sourceforge.net/forum/message.php?msg_id=3714405
 	+ In the PC ports:  Add function prvSetTickFrequencyDefault() to set the
 	  DOS tick back to its proper value when the scheduler exits.  Thanks
 	  Raynald!

LICENSE

@@ -1,18 +0,0 @@
-Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software is furnished to do so,
-subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-

LICENSE.md

@@ -0,0 +1,19 @@
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Quick_Start_Guide.url

@@ -1,5 +1,5 @@
 [InternetShortcut]
-URL=http://www.freertos.org/FreeRTOS-quick-start-guide.html
+URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html
 IDList=
 [{000214A0-0000-0000-C000-000000000046}]
 Prop3=19,2

README.md

@@ -1,9 +1,9 @@
 ## Getting started
 This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. 
 
-The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
 
-Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.freertos.org/features.html), and [API Reference](https://www.freertos.org/a00106.html).
+Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
 
 ### Getting help
 If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
@@ -29,3 +29,11 @@ is normally only used on very memory limited systems.
 See the readme file in the ```./portable``` directory for more information.
 
 - The ```./include``` directory contains the real time kernel header files.
+
+### Code Formatting
+FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/main/tools/uncrustify.cfg). 
+
+### Spelling
+*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. 
+Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
+

croutine.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #include "FreeRTOS.h"
@@ -30,32 +31,32 @@
 #include "croutine.h"
 
 /* Remove the whole file is co-routines are not being used. */
-#if( configUSE_CO_ROUTINES != 0 )
+#if ( configUSE_CO_ROUTINES != 0 )
 
 /*
  * Some kernel aware debuggers require data to be viewed to be global, rather
  * than file scope.
  */
-#ifdef portREMOVE_STATIC_QUALIFIER
-	#define static
-#endif
+    #ifdef portREMOVE_STATIC_QUALIFIER
+        #define static
+    #endif
 
 
 /* Lists for ready and blocked co-routines. --------------------*/
-static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
-static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
-static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
-static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
-static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
-static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
+    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */
+    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */
+    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
 
 /* Other file private variables. --------------------------------*/
-CRCB_t * pxCurrentCoRoutine = NULL;
-static UBaseType_t uxTopCoRoutineReadyPriority = 0;
-static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+    CRCB_t * pxCurrentCoRoutine = NULL;
+    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
 
 /* The initial state of the co-routine when it is created. */
-#define corINITIAL_STATE	( 0 )
+    #define corINITIAL_STATE    ( 0 )
 
 /*
  * Place the co-routine represented by pxCRCB into the appropriate ready queue
@@ -64,20 +65,20 @@ static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
  * This macro accesses the co-routine ready lists and therefore must not be
  * used from within an ISR.
  */
-#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
-{																													\
-	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
-	{																												\
-		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
-	}																												\
-	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
-}
+    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                               \
+    {                                                                                                                           \
+        if( ( pxCRCB )->uxPriority > uxTopCoRoutineReadyPriority )                                                              \
+        {                                                                                                                       \
+            uxTopCoRoutineReadyPriority = ( pxCRCB )->uxPriority;                                                               \
+        }                                                                                                                       \
+        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ ( pxCRCB )->uxPriority ] ), &( ( pxCRCB )->xGenericListItem ) ); \
+    }
 
 /*
  * Utility to ready all the lists used by the scheduler.  This is called
  * automatically upon the creation of the first co-routine.
  */
-static void prvInitialiseCoRoutineLists( void );
+    static void prvInitialiseCoRoutineLists( void );
 
 /*
  * Co-routines that are readied by an interrupt cannot be placed directly into
@@ -85,7 +86,7 @@ static void prvInitialiseCoRoutineLists( void );
  * in the pending ready list in order that they can later be moved to the ready
  * list by the co-routine scheduler.
  */
-static void prvCheckPendingReadyList( void );
+    static void prvCheckPendingReadyList( void );
 
 /*
  * Macro that looks at the list of co-routines that are currently delayed to
@@ -95,259 +96,268 @@ static void prvCheckPendingReadyList( void );
  * meaning once one co-routine has been found whose timer has not expired
  * we need not look any further down the list.
  */
-static void prvCheckDelayedList( void );
+    static void prvCheckDelayedList( void );
 
 /*-----------------------------------------------------------*/
 
-BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
-{
-BaseType_t xReturn;
-CRCB_t *pxCoRoutine;
+    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex )
+    {
+        BaseType_t xReturn;
+        CRCB_t * pxCoRoutine;
 
-	/* Allocate the memory that will store the co-routine control block. */
-	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
-	if( pxCoRoutine )
-	{
-		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
-		be created and the co-routine data structures need initialising. */
-		if( pxCurrentCoRoutine == NULL )
-		{
-			pxCurrentCoRoutine = pxCoRoutine;
-			prvInitialiseCoRoutineLists();
-		}
+        /* Allocate the memory that will store the co-routine control block. */
+        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
 
-		/* Check the priority is within limits. */
-		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
-		{
-			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
-		}
+        if( pxCoRoutine )
+        {
+            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+            * be created and the co-routine data structures need initialising. */
+            if( pxCurrentCoRoutine == NULL )
+            {
+                pxCurrentCoRoutine = pxCoRoutine;
+                prvInitialiseCoRoutineLists();
+            }
 
-		/* Fill out the co-routine control block from the function parameters. */
-		pxCoRoutine->uxState = corINITIAL_STATE;
-		pxCoRoutine->uxPriority = uxPriority;
-		pxCoRoutine->uxIndex = uxIndex;
-		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+            /* Check the priority is within limits. */
+            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+            {
+                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+            }
 
-		/* Initialise all the other co-routine control block parameters. */
-		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
-		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+            /* Fill out the co-routine control block from the function parameters. */
+            pxCoRoutine->uxState = corINITIAL_STATE;
+            pxCoRoutine->uxPriority = uxPriority;
+            pxCoRoutine->uxIndex = uxIndex;
+            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
 
-		/* Set the co-routine control block as a link back from the ListItem_t.
-		This is so we can get back to the containing CRCB from a generic item
-		in a list. */
-		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
-		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+            /* Initialise all the other co-routine control block parameters. */
+            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
 
-		/* Event lists are always in priority order. */
-		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+            /* Set the co-routine control block as a link back from the ListItem_t.
+             * This is so we can get back to the containing CRCB from a generic item
+             * in a list. */
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
 
-		/* Now the co-routine has been initialised it can be added to the ready
-		list at the correct priority. */
-		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+            /* Event lists are always in priority order. */
+            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
 
-		xReturn = pdPASS;
-	}
-	else
-	{
-		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-	}
+            /* Now the co-routine has been initialised it can be added to the ready
+             * list at the correct priority. */
+            prvAddCoRoutineToReadyQueue( pxCoRoutine );
 
-	return xReturn;
-}
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        return xReturn;
+    }
 /*-----------------------------------------------------------*/
 
-void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
-{
-TickType_t xTimeToWake;
+    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                     List_t * pxEventList )
+    {
+        TickType_t xTimeToWake;
 
-	/* Calculate the time to wake - this may overflow but this is
-	not a problem. */
-	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+        /* Calculate the time to wake - this may overflow but this is
+         * not a problem. */
+        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
 
-	/* We must remove ourselves from the ready list before adding
-	ourselves to the blocked list as the same list item is used for
-	both lists. */
-	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        /* We must remove ourselves from the ready list before adding
+         * ourselves to the blocked list as the same list item is used for
+         * both lists. */
+        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
 
-	/* The list item will be inserted in wake time order. */
-	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+        /* The list item will be inserted in wake time order. */
+        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
 
-	if( xTimeToWake < xCoRoutineTickCount )
-	{
-		/* Wake time has overflowed.  Place this item in the
-		overflow list. */
-		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
-	}
-	else
-	{
-		/* The wake time has not overflowed, so we can use the
-		current block list. */
-		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
-	}
+        if( xTimeToWake < xCoRoutineTickCount )
+        {
+            /* Wake time has overflowed.  Place this item in the
+             * overflow list. */
+            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
+        else
+        {
+            /* The wake time has not overflowed, so we can use the
+             * current block list. */
+            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
 
-	if( pxEventList )
-	{
-		/* Also add the co-routine to an event list.  If this is done then the
-		function must be called with interrupts disabled. */
-		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
-	}
-}
+        if( pxEventList )
+        {
+            /* Also add the co-routine to an event list.  If this is done then the
+             * function must be called with interrupts disabled. */
+            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+        }
+    }
 /*-----------------------------------------------------------*/
 
-static void prvCheckPendingReadyList( void )
-{
-	/* Are there any co-routines waiting to get moved to the ready list?  These
-	are co-routines that have been readied by an ISR.  The ISR cannot access
-	the	ready lists itself. */
-	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
-	{
-		CRCB_t *pxUnblockedCRCB;
+    static void prvCheckPendingReadyList( void )
+    {
+        /* Are there any co-routines waiting to get moved to the ready list?  These
+         * are co-routines that have been readied by an ISR.  The ISR cannot access
+         * the ready lists itself. */
+        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+        {
+            CRCB_t * pxUnblockedCRCB;
 
-		/* The pending ready list can be accessed by an ISR. */
-		portDISABLE_INTERRUPTS();
-		{
-			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
-			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
-		}
-		portENABLE_INTERRUPTS();
+            /* The pending ready list can be accessed by an ISR. */
+            portDISABLE_INTERRUPTS();
+            {
+                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
+                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+            }
+            portENABLE_INTERRUPTS();
 
-		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
-		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
-	}
-}
+            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+        }
+    }
 /*-----------------------------------------------------------*/
 
-static void prvCheckDelayedList( void )
-{
-CRCB_t *pxCRCB;
+    static void prvCheckDelayedList( void )
+    {
+        CRCB_t * pxCRCB;
 
-	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
-	while( xPassedTicks )
-	{
-		xCoRoutineTickCount++;
-		xPassedTicks--;
+        xPassedTicks = xTaskGetTickCount() - xLastTickCount;
 
-		/* If the tick count has overflowed we need to swap the ready lists. */
-		if( xCoRoutineTickCount == 0 )
-		{
-			List_t * pxTemp;
+        while( xPassedTicks )
+        {
+            xCoRoutineTickCount++;
+            xPassedTicks--;
 
-			/* Tick count has overflowed so we need to swap the delay lists.  If there are
-			any items in pxDelayedCoRoutineList here then there is an error! */
-			pxTemp = pxDelayedCoRoutineList;
-			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
-			pxOverflowDelayedCoRoutineList = pxTemp;
-		}
+            /* If the tick count has overflowed we need to swap the ready lists. */
+            if( xCoRoutineTickCount == 0 )
+            {
+                List_t * pxTemp;
 
-		/* See if this tick has made a timeout expire. */
-		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
-		{
-			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+                /* Tick count has overflowed so we need to swap the delay lists.  If there are
+                 * any items in pxDelayedCoRoutineList here then there is an error! */
+                pxTemp = pxDelayedCoRoutineList;
+                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+                pxOverflowDelayedCoRoutineList = pxTemp;
+            }
 
-			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
-			{
-				/* Timeout not yet expired. */
-				break;
-			}
+            /* See if this tick has made a timeout expire. */
+            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+            {
+                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
 
-			portDISABLE_INTERRUPTS();
-			{
-				/* The event could have occurred just before this critical
-				section.  If this is the case then the generic list item will
-				have been moved to the pending ready list and the following
-				line is still valid.  Also the pvContainer parameter will have
-				been set to NULL so the following lines are also valid. */
-				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+                {
+                    /* Timeout not yet expired. */
+                    break;
+                }
 
-				/* Is the co-routine waiting on an event also? */
-				if( pxCRCB->xEventListItem.pxContainer )
-				{
-					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
-				}
-			}
-			portENABLE_INTERRUPTS();
+                portDISABLE_INTERRUPTS();
+                {
+                    /* The event could have occurred just before this critical
+                     *  section.  If this is the case then the generic list item will
+                     *  have been moved to the pending ready list and the following
+                     *  line is still valid.  Also the pvContainer parameter will have
+                     *  been set to NULL so the following lines are also valid. */
+                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
 
-			prvAddCoRoutineToReadyQueue( pxCRCB );
-		}
-	}
+                    /* Is the co-routine waiting on an event also? */
+                    if( pxCRCB->xEventListItem.pxContainer )
+                    {
+                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+                    }
+                }
+                portENABLE_INTERRUPTS();
 
-	xLastTickCount = xCoRoutineTickCount;
-}
+                prvAddCoRoutineToReadyQueue( pxCRCB );
+            }
+        }
+
+        xLastTickCount = xCoRoutineTickCount;
+    }
 /*-----------------------------------------------------------*/
 
-void vCoRoutineSchedule( void )
-{
-	/* See if any co-routines readied by events need moving to the ready lists. */
-	prvCheckPendingReadyList();
+    void vCoRoutineSchedule( void )
+    {
+        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
+         * called.  prvInitialiseCoRoutineLists() is called automatically when a
+         * co-routine is created. */
+        if( pxDelayedCoRoutineList != NULL )
+        {
+            /* See if any co-routines readied by events need moving to the ready lists. */
+            prvCheckPendingReadyList();
 
-	/* See if any delayed co-routines have timed out. */
-	prvCheckDelayedList();
+            /* See if any delayed co-routines have timed out. */
+            prvCheckDelayedList();
 
-	/* Find the highest priority queue that contains ready co-routines. */
-	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
-	{
-		if( uxTopCoRoutineReadyPriority == 0 )
-		{
-			/* No more co-routines to check. */
-			return;
-		}
-		--uxTopCoRoutineReadyPriority;
-	}
+            /* Find the highest priority queue that contains ready co-routines. */
+            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+            {
+                if( uxTopCoRoutineReadyPriority == 0 )
+                {
+                    /* No more co-routines to check. */
+                    return;
+                }
 
-	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
-	 of the	same priority get an equal share of the processor time. */
-	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+                --uxTopCoRoutineReadyPriority;
+            }
 
-	/* Call the co-routine. */
-	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+             * of the same priority get an equal share of the processor time. */
+            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
 
-	return;
-}
+            /* Call the co-routine. */
+            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+        }
+    }
 /*-----------------------------------------------------------*/
 
-static void prvInitialiseCoRoutineLists( void )
-{
-UBaseType_t uxPriority;
+    static void prvInitialiseCoRoutineLists( void )
+    {
+        UBaseType_t uxPriority;
 
-	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
-	{
-		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
-	}
+        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+        {
+            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+        }
 
-	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
-	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
-	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
 
-	/* Start with pxDelayedCoRoutineList using list1 and the
-	pxOverflowDelayedCoRoutineList using list2. */
-	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
-	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
-}
+        /* Start with pxDelayedCoRoutineList using list1 and the
+         * pxOverflowDelayedCoRoutineList using list2. */
+        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+    }
 /*-----------------------------------------------------------*/
 
-BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
-{
-CRCB_t *pxUnblockedCRCB;
-BaseType_t xReturn;
+    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
+    {
+        CRCB_t * pxUnblockedCRCB;
+        BaseType_t xReturn;
 
-	/* This function is called from within an interrupt.  It can only access
-	event lists and the pending ready list.  This function assumes that a
-	check has already been made to ensure pxEventList is not empty. */
-	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
-	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
-	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+        /* This function is called from within an interrupt.  It can only access
+         * event lists and the pending ready list.  This function assumes that a
+         * check has already been made to ensure pxEventList is not empty. */
+        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
 
-	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
+        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
 
-	return xReturn;
-}
+        return xReturn;
+    }
 
 #endif /* configUSE_CO_ROUTINES == 0 */
-

include/StackMacros.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,115 +21,14 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
-#ifndef STACK_MACROS_H
-#define STACK_MACROS_H
 
 #ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
-	#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.
+    #warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in a future release.
 #endif
 
-/*
- * Call the stack overflow hook function if the stack of the task being swapped
- * out is currently overflowed, or looks like it might have overflowed in the
- * past.
- *
- * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
- * the current stack state only - comparing the current top of stack value to
- * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
- * will also cause the last few stack bytes to be checked to ensure the value
- * to which the bytes were set when the task was created have not been
- * overwritten.  Note this second test does not guarantee that an overflowed
- * stack will always be recognised.
- */
-
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-																										\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
-		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
-																										\
-		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
-			( pulStack[ 1 ] != ulCheckValue ) ||												\
-			( pulStack[ 2 ] != ulCheckValue ) ||												\
-			( pulStack[ 3 ] != ulCheckValue ) )												\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
-	{																																	\
-	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
-		}																																\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-/* Remove stack overflow macro if not being used. */
-#ifndef taskCHECK_FOR_STACK_OVERFLOW
-	#define taskCHECK_FOR_STACK_OVERFLOW()
-#endif
-
-
-
-#endif /* STACK_MACROS_H */
-
+#include "stack_macros.h"

include/atomic.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /**
@@ -38,15 +39,17 @@
 #define ATOMIC_H
 
 #ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include atomic.h"
+    #error "include FreeRTOS.h must appear in source files before include atomic.h"
 #endif
 
 /* Standard includes. */
 #include <stdint.h>
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
+/* *INDENT-ON* */
 
 /*
  * Port specific definitions -- entering/exiting critical section.
@@ -58,18 +61,18 @@ extern "C" {
  */
 #if defined( portSET_INTERRUPT_MASK_FROM_ISR )
 
-	/* Nested interrupt scheme is supported in this port. */
-	#define ATOMIC_ENTER_CRITICAL()	 \
-		UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
+/* Nested interrupt scheme is supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL() \
+    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
 
-	#define ATOMIC_EXIT_CRITICAL()	  \
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
+    #define ATOMIC_EXIT_CRITICAL() \
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
 
 #else
 
-	/* Nested interrupt scheme is NOT supported in this port. */
-	#define ATOMIC_ENTER_CRITICAL()	 portENTER_CRITICAL()
-	#define ATOMIC_EXIT_CRITICAL()	  portEXIT_CRITICAL()
+/* Nested interrupt scheme is NOT supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()
+    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()
 
 #endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
 
@@ -81,11 +84,11 @@ extern "C" {
  * instead of resulting error, simply define it away.
  */
 #ifndef portFORCE_INLINE
-	#define portFORCE_INLINE
+    #define portFORCE_INLINE
 #endif
 
-#define ATOMIC_COMPARE_AND_SWAP_SUCCESS	 0x1U		/**< Compare and swap succeeded, swapped. */
-#define ATOMIC_COMPARE_AND_SWAP_FAILURE	 0x0U		/**< Compare and swap failed, did not swap. */
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */
 
 /*----------------------------- Swap && CAS ------------------------------*/
 
@@ -105,26 +108,26 @@ extern "C" {
  *       *pulDestination value equals ulComparand.
  */
 static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
-															uint32_t ulExchange,
-															uint32_t ulComparand )
+                                                            uint32_t ulExchange,
+                                                            uint32_t ulComparand )
 {
-uint32_t ulReturnValue;
+    uint32_t ulReturnValue;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		if( *pulDestination == ulComparand )
-		{
-			*pulDestination = ulExchange;
-			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
-		}
-		else
-		{
-			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
-		}
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *pulDestination == ulComparand )
+        {
+            *pulDestination = ulExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+        else
+        {
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulReturnValue;
+    return ulReturnValue;
 }
 /*-----------------------------------------------------------*/
 
@@ -141,18 +144,18 @@ uint32_t ulReturnValue;
  * @return The initial value of *ppvDestination.
  */
 static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
-														void * pvExchange )
+                                                        void * pvExchange )
 {
-void * pReturnValue;
+    void * pReturnValue;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		pReturnValue = *ppvDestination;
-		*ppvDestination = pvExchange;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        pReturnValue = *ppvDestination;
+        *ppvDestination = pvExchange;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return pReturnValue;
+    return pReturnValue;
 }
 /*-----------------------------------------------------------*/
 
@@ -173,22 +176,22 @@ void * pReturnValue;
  *       *ppvDestination value equals pvComparand.
  */
 static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
-																	void * pvExchange,
-																	void * pvComparand )
+                                                                    void * pvExchange,
+                                                                    void * pvComparand )
 {
-uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		if( *ppvDestination == pvComparand )
-		{
-			*ppvDestination = pvExchange;
-			ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
-		}
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *ppvDestination == pvComparand )
+        {
+            *ppvDestination = pvExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulReturnValue;
+    return ulReturnValue;
 }
 
 
@@ -206,18 +209,18 @@ uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
  * @return previous *pulAddend value.
  */
 static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
-												 uint32_t ulCount )
+                                                 uint32_t ulCount )
 {
-	uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulAddend;
-		*pulAddend += ulCount;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -234,18 +237,18 @@ static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
  * @return previous *pulAddend value.
  */
 static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
-													  uint32_t ulCount )
+                                                      uint32_t ulCount )
 {
-	uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulAddend;
-		*pulAddend -= ulCount;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -261,16 +264,16 @@ static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAdd
  */
 static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulAddend;
-		*pulAddend += 1;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -286,16 +289,16 @@ uint32_t ulCurrent;
  */
 static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulAddend;
-		*pulAddend -= 1;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 
 /*----------------------------- Bitwise Logical ------------------------------*/
@@ -312,18 +315,18 @@ uint32_t ulCurrent;
  * @return The original value of *pulDestination.
  */
 static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
-												uint32_t ulValue )
+                                                uint32_t ulValue )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulDestination;
-		*pulDestination |= ulValue;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination |= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -339,18 +342,18 @@ uint32_t ulCurrent;
  * @return The original value of *pulDestination.
  */
 static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
-												 uint32_t ulValue )
+                                                 uint32_t ulValue )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulDestination;
-		*pulDestination &= ulValue;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination &= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -366,18 +369,18 @@ uint32_t ulCurrent;
  * @return The original value of *pulDestination.
  */
 static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
-												  uint32_t ulValue )
+                                                  uint32_t ulValue )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulDestination;
-		*pulDestination = ~( ulCurrent & ulValue );
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination = ~( ulCurrent & ulValue );
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 /*-----------------------------------------------------------*/
 
@@ -393,22 +396,24 @@ uint32_t ulCurrent;
  * @return The original value of *pulDestination.
  */
 static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
-												 uint32_t ulValue )
+                                                 uint32_t ulValue )
 {
-uint32_t ulCurrent;
+    uint32_t ulCurrent;
 
-	ATOMIC_ENTER_CRITICAL();
-	{
-		ulCurrent = *pulDestination;
-		*pulDestination ^= ulValue;
-	}
-	ATOMIC_EXIT_CRITICAL();
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination ^= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
 
-	return ulCurrent;
+    return ulCurrent;
 }
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-}
+    }
 #endif
+/* *INDENT-ON* */
 
 #endif /* ATOMIC_H */

include/croutine.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,51 +21,54 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef CO_ROUTINE_H
 #define CO_ROUTINE_H
 
 #ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+    #error "include FreeRTOS.h must appear in source files before include croutine.h"
 #endif
 
 #include "list.h"
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
+/* *INDENT-ON* */
 
 /* Used to hide the implementation of the co-routine control block.  The
-control block structure however has to be included in the header due to
-the macro implementation of the co-routine functionality. */
+ * control block structure however has to be included in the header due to
+ * the macro implementation of the co-routine functionality. */
 typedef void * CoRoutineHandle_t;
 
 /* Defines the prototype to which co-routine functions must conform. */
-typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
+                                   UBaseType_t );
 
 typedef struct corCoRoutineControlBlock
 {
-	crCOROUTINE_CODE 	pxCoRoutineFunction;
-	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
-	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
-	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
-	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
-	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
-} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+    crCOROUTINE_CODE pxCoRoutineFunction;
+    ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
+    ListItem_t xEventListItem;   /*< List item used to place the CRCB in event lists. */
+    UBaseType_t uxPriority;      /*< The priority of the co-routine in relation to other co-routines. */
+    UBaseType_t uxIndex;         /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+    uint16_t uxState;            /*< Used internally by the co-routine implementation. */
+} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
 
 /**
  * croutine. h
- *<pre>
- BaseType_t xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 UBaseType_t uxPriority,
-                                 UBaseType_t uxIndex
-                               );</pre>
+ * @code{c}
+ * BaseType_t xCoRoutineCreate(
+ *                               crCOROUTINE_CODE pxCoRoutineCode,
+ *                               UBaseType_t uxPriority,
+ *                               UBaseType_t uxIndex
+ *                             );
+ * @endcode
  *
  * Create a new co-routine and add it to the list of co-routines that are
  * ready to run.
@@ -83,58 +88,61 @@ typedef struct corCoRoutineControlBlock
  * list, otherwise an error code defined with ProjDefs.h.
  *
  * Example usage:
-   <pre>
- // Co-routine to be created.
- void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how int32_t to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- uint8_t ucParameterToPass;
- TaskHandle_t xHandle;
-
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-   </pre>
+ * @code{c}
+ * // Co-routine to be created.
+ * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * static const char cLedToFlash[ 2 ] = { 5, 6 };
+ * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // This co-routine just delays for a fixed period, then toggles
+ *       // an LED.  Two co-routines are created using this function, so
+ *       // the uxIndex parameter is used to tell the co-routine which
+ *       // LED to flash and how int32_t to delay.  This assumes xQueue has
+ *       // already been created.
+ *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * // Function that creates two co-routines.
+ * void vOtherFunction( void )
+ * {
+ * uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle;
+ *
+ *   // Create two co-routines at priority 0.  The first is given index 0
+ *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
+ *   // is given index 1 so toggles LED 6 every 400 ticks.
+ *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ *   {
+ *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ *   }
+ * }
+ * @endcode
  * \defgroup xCoRoutineCreate xCoRoutineCreate
  * \ingroup Tasks
  */
-BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                             UBaseType_t uxPriority,
+                             UBaseType_t uxIndex );
 
 
 /**
  * croutine. h
- *<pre>
- void vCoRoutineSchedule( void );</pre>
+ * @code{c}
+ * void vCoRoutineSchedule( void );
+ * @endcode
  *
  * Run a co-routine.
  *
@@ -148,25 +156,25 @@ BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPri
  * hook).
  *
  * Example usage:
-   <pre>
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineSchedule() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
- </pre>
+ * @code{c}
+ * // This idle task hook will schedule a co-routine each time it is called.
+ * // The rest of the idle task will execute between co-routine calls.
+ * void vApplicationIdleHook( void )
+ * {
+ *  vCoRoutineSchedule();
+ * }
+ *
+ * // Alternatively, if you do not require any other part of the idle task to
+ * // execute, the idle task hook can call vCoRoutineSchedule() within an
+ * // infinite loop.
+ * void vApplicationIdleHook( void )
+ * {
+ *  for( ;; )
+ *  {
+ *      vCoRoutineSchedule();
+ *  }
+ * }
+ * @endcode
  * \defgroup vCoRoutineSchedule vCoRoutineSchedule
  * \ingroup Tasks
  */
@@ -174,77 +182,88 @@ void vCoRoutineSchedule( void );
 
 /**
  * croutine. h
- * <pre>
- crSTART( CoRoutineHandle_t xHandle );</pre>
+ * @code{c}
+ * crSTART( CoRoutineHandle_t xHandle );
+ * @endcode
  *
  * This macro MUST always be called at the start of a co-routine function.
  *
  * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
  * \defgroup crSTART crSTART
  * \ingroup Tasks
  */
-#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+#define crSTART( pxCRCB )                            \
+    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
+        case 0:
 
 /**
  * croutine. h
- * <pre>
- crEND();</pre>
+ * @code{c}
+ * crEND();
+ * @endcode
  *
  * This macro MUST always be called at the end of a co-routine function.
  *
  * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static int32_t ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
  * \defgroup crSTART crSTART
  * \ingroup Tasks
  */
-#define crEND() }
+#define crEND()    }
 
 /*
  * These macros are intended for internal use by the co-routine implementation
  * only.  The macros should not be used directly by application writers.
  */
-#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
-#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+#define crSET_STATE0( xHandle )                                       \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
+    case ( __LINE__ * 2 ):
+#define crSET_STATE1( xHandle )                                               \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
+    case ( ( __LINE__ * 2 ) + 1 ):
 
 /**
  * croutine. h
- *<pre>
- crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ * @code{c}
+ * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * @endcode
  *
  * Delay a co-routine for a fixed period of time.
  *
@@ -261,48 +280,50 @@ void vCoRoutineSchedule( void );
  * can be used to convert ticks to milliseconds.
  *
  * Example usage:
-   <pre>
- // Co-routine to be created.
- void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }</pre>
+ * @code{c}
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * // We are to delay for 200ms.
+ * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *      // Delay for 200ms.
+ *      crDELAY( xHandle, xDelayTime );
+ *
+ *      // Do something here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * @endcode
  * \defgroup crDELAY crDELAY
  * \ingroup Tasks
  */
-#define crDELAY( xHandle, xTicksToDelay )												\
-	if( ( xTicksToDelay ) > 0 )															\
-	{																					\
-		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
-	}																					\
-	crSET_STATE0( ( xHandle ) );
+#define crDELAY( xHandle, xTicksToDelay )                      \
+    if( ( xTicksToDelay ) > 0 )                                \
+    {                                                          \
+        vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
+    }                                                          \
+    crSET_STATE0( ( xHandle ) );
 
 /**
- * <pre>
- crQUEUE_SEND(
-                  CoRoutineHandle_t xHandle,
-                  QueueHandle_t pxQueue,
-                  void *pvItemToQueue,
-                  TickType_t xTicksToWait,
-                  BaseType_t *pxResult
-             )</pre>
+ * @code{c}
+ * crQUEUE_SEND(
+ *                CoRoutineHandle_t xHandle,
+ *                QueueHandle_t pxQueue,
+ *                void *pvItemToQueue,
+ *                TickType_t xTicksToWait,
+ *                BaseType_t *pxResult
+ *           )
+ * @endcode
  *
  * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
  * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
@@ -342,66 +363,68 @@ void vCoRoutineSchedule( void );
  * error defined within ProjDefs.h.
  *
  * Example usage:
-   <pre>
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xNumberToPost = 0;
- static BaseType_t xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }</pre>
+ * @code{c}
+ * // Co-routine function that blocks for a fixed period then posts a number onto
+ * // a queue.
+ * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xNumberToPost = 0;
+ * static BaseType_t xResult;
+ *
+ *  // Co-routines must begin with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // This assumes the queue has already been created.
+ *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+ *
+ *      if( xResult != pdPASS )
+ *      {
+ *          // The message was not posted!
+ *      }
+ *
+ *      // Increment the number to be posted onto the queue.
+ *      xNumberToPost++;
+ *
+ *      // Delay for 100 ticks.
+ *      crDELAY( xHandle, 100 );
+ *  }
+ *
+ *  // Co-routines must end with a call to crEND().
+ *  crEND();
+ * }
+ * @endcode
  * \defgroup crQUEUE_SEND crQUEUE_SEND
  * \ingroup Tasks
  */
-#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
-{																						\
-	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
-	if( *( pxResult ) == errQUEUE_BLOCKED )												\
-	{																					\
-		crSET_STATE0( ( xHandle ) );													\
-		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
-	}																					\
-	if( *pxResult == errQUEUE_YIELD )													\
-	{																					\
-		crSET_STATE1( ( xHandle ) );													\
-		*pxResult = pdPASS;																\
-	}																					\
-}
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \
+    {                                                                                     \
+        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \
+        {                                                                                 \
+            crSET_STATE0( ( xHandle ) );                                                  \
+            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \
+        }                                                                                 \
+        if( *pxResult == errQUEUE_YIELD )                                                 \
+        {                                                                                 \
+            crSET_STATE1( ( xHandle ) );                                                  \
+            *pxResult = pdPASS;                                                           \
+        }                                                                                 \
+    }
 
 /**
  * croutine. h
- * <pre>
-  crQUEUE_RECEIVE(
-                     CoRoutineHandle_t xHandle,
-                     QueueHandle_t pxQueue,
-                     void *pvBuffer,
-                     TickType_t xTicksToWait,
-                     BaseType_t *pxResult
-                 )</pre>
+ * @code{c}
+ * crQUEUE_RECEIVE(
+ *                   CoRoutineHandle_t xHandle,
+ *                   QueueHandle_t pxQueue,
+ *                   void *pvBuffer,
+ *                   TickType_t xTicksToWait,
+ *                   BaseType_t *pxResult
+ *               )
+ * @endcode
  *
  * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
  * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
@@ -440,58 +463,60 @@ void vCoRoutineSchedule( void );
  * an error code as defined within ProjDefs.h.
  *
  * Example usage:
- <pre>
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static BaseType_t xResult;
- static UBaseType_t uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }</pre>
+ * @code{c}
+ * // A co-routine receives the number of an LED to flash from a queue.  It
+ * // blocks on the queue until the number is received.
+ * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xResult;
+ * static UBaseType_t uxLEDToFlash;
+ *
+ *  // All co-routines must start with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // Wait for data to become available on the queue.
+ *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // We received the LED to flash - flash it!
+ *          vParTestToggleLED( uxLEDToFlash );
+ *      }
+ *  }
+ *
+ *  crEND();
+ * }
+ * @endcode
  * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
  * \ingroup Tasks
  */
-#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
-{																						\
-	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
-	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
-	{																					\
-		crSET_STATE0( ( xHandle ) );													\
-		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
-	}																					\
-	if( *( pxResult ) == errQUEUE_YIELD )												\
-	{																					\
-		crSET_STATE1( ( xHandle ) );													\
-		*( pxResult ) = pdPASS;															\
-	}																					\
-}
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \
+    {                                                                                   \
+        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \
+        {                                                                               \
+            crSET_STATE0( ( xHandle ) );                                                \
+            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \
+        }                                                                               \
+        if( *( pxResult ) == errQUEUE_YIELD )                                           \
+        {                                                                               \
+            crSET_STATE1( ( xHandle ) );                                                \
+            *( pxResult ) = pdPASS;                                                     \
+        }                                                                               \
+    }
 
 /**
  * croutine. h
- * <pre>
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvItemToQueue,
-                            BaseType_t xCoRoutinePreviouslyWoken
-                       )</pre>
+ * @code{c}
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvItemToQueue,
+ *                          BaseType_t xCoRoutinePreviouslyWoken
+ *                     )
+ * @endcode
  *
  * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
  * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
@@ -526,69 +551,72 @@ void vCoRoutineSchedule( void );
  * the ISR.
  *
  * Example usage:
- <pre>
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- char cRxedChar;
- BaseType_t xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- char cRxedChar;
- BaseType_t xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }</pre>
+ * @code{c}
+ * // A co-routine that blocks on a queue waiting for characters to be received.
+ * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * char cRxedChar;
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Wait for data to become available on the queue.  This assumes the
+ *       // queue xCommsRxQueue has already been created!
+ *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *       // Was a character received?
+ *       if( xResult == pdPASS )
+ *       {
+ *           // Process the character here.
+ *       }
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to send characters received on a serial port to
+ * // a co-routine.
+ * void vUART_ISR( void )
+ * {
+ * char cRxedChar;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   // We loop around reading characters until there are none left in the UART.
+ *   while( UART_RX_REG_NOT_EMPTY() )
+ *   {
+ *       // Obtain the character from the UART.
+ *       cRxedChar = UART_RX_REG;
+ *
+ *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+ *       // the first time around the loop.  If the post causes a co-routine
+ *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ *       // In this manner we can ensure that if more than one co-routine is
+ *       // blocked on the queue only one is woken by this ISR no matter how
+ *       // many characters are posted to the queue.
+ *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ *   }
+ * }
+ * @endcode
  * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
  * \ingroup Tasks
  */
-#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
+    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
 
 
 /**
  * croutine. h
- * <pre>
-  crQUEUE_SEND_FROM_ISR(
-                            QueueHandle_t pxQueue,
-                            void *pvBuffer,
-                            BaseType_t * pxCoRoutineWoken
-                       )</pre>
+ * @code{c}
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvBuffer,
+ *                          BaseType_t * pxCoRoutineWoken
+ *                     )
+ * @endcode
  *
  * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
  * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
@@ -623,75 +651,77 @@ void vCoRoutineSchedule( void );
  * pdFALSE.
  *
  * Example usage:
- <pre>
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static char cCharToTx = 'a';
- BaseType_t xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period.
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- char cCharToTx;
- BaseType_t xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }</pre>
+ * @code{c}
+ * // A co-routine that posts a character to a queue then blocks for a fixed
+ * // period.  The character is incremented each time.
+ * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // cChar holds its value while this co-routine is blocked and must therefore
+ * // be declared static.
+ * static char cCharToTx = 'a';
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Send the next character to the queue.
+ *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+ *
+ *       if( xResult == pdPASS )
+ *       {
+ *           // The character was successfully posted to the queue.
+ *       }
+ *       else
+ *       {
+ *          // Could not post the character to the queue.
+ *       }
+ *
+ *       // Enable the UART Tx interrupt to cause an interrupt in this
+ *       // hypothetical UART.  The interrupt will obtain the character
+ *       // from the queue and send it.
+ *       ENABLE_RX_INTERRUPT();
+ *
+ *       // Increment to the next character then block for a fixed period.
+ *       // cCharToTx will maintain its value across the delay as it is
+ *       // declared static.
+ *       cCharToTx++;
+ *       if( cCharToTx > 'x' )
+ *       {
+ *          cCharToTx = 'a';
+ *       }
+ *       crDELAY( 100 );
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to receive characters to send on a UART.
+ * void vUART_ISR( void )
+ * {
+ * char cCharToTx;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   while( UART_TX_REG_EMPTY() )
+ *   {
+ *       // Are there any characters in the queue waiting to be sent?
+ *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ *       // is woken by the post - ensuring that only a single co-routine is
+ *       // woken no matter how many times we go around this loop.
+ *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ *       {
+ *           SEND_CHARACTER( cCharToTx );
+ *       }
+ *   }
+ * }
+ * @endcode
  * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
  * \ingroup Tasks
  */
-#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
+    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
 
 /*
  * This function is intended for internal use by the co-routine macros only.
@@ -702,7 +732,8 @@ void vCoRoutineSchedule( void );
  * Removes the current co-routine from its ready list and places it in the
  * appropriate delayed list.
  */
-void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                 List_t * pxEventList );
 
 /*
  * This function is intended for internal use by the queue implementation only.
@@ -711,10 +742,12 @@ void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
  * Removes the highest priority co-routine from the event list and places it in
  * the pending ready list.
  */
-BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-}
+    }
 #endif
+/* *INDENT-ON* */
 
 #endif /* CO_ROUTINE_H */

include/deprecated_definitions.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef DEPRECATED_DEFINITIONS_H
@@ -30,158 +31,158 @@
 
 
 /* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.  The
-definitions below remain in the code for backward compatibility only.  New
-projects should not use them. */
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.  The
+ * definitions below remain in the code for backward compatibility only.  New
+ * projects should not use them. */
 
 #ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
-	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
-	typedef void ( __interrupt __far *pxISR )();
+    #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
 #endif
 
 #ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
-	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
-	typedef void ( __interrupt __far *pxISR )();
+    #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
 #endif
 
 #ifdef GCC_MEGA_AVR
-	#include "../portable/GCC/ATMega323/portmacro.h"
+    #include "../portable/GCC/ATMega323/portmacro.h"
 #endif
 
 #ifdef IAR_MEGA_AVR
-	#include "../portable/IAR/ATMega323/portmacro.h"
+    #include "../portable/IAR/ATMega323/portmacro.h"
 #endif
 
 #ifdef MPLAB_PIC24_PORT
-	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
 #endif
 
 #ifdef MPLAB_DSPIC_PORT
-	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
 #endif
 
 #ifdef MPLAB_PIC18F_PORT
-	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+    #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
 #endif
 
 #ifdef MPLAB_PIC32MX_PORT
-	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+    #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
 #endif
 
 #ifdef _FEDPICC
-	#include "libFreeRTOS/Include/portmacro.h"
+    #include "libFreeRTOS/Include/portmacro.h"
 #endif
 
 #ifdef SDCC_CYGNAL
-	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+    #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
 #endif
 
 #ifdef GCC_ARM7
-	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+    #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
 #endif
 
 #ifdef GCC_ARM7_ECLIPSE
-	#include "portmacro.h"
+    #include "portmacro.h"
 #endif
 
 #ifdef ROWLEY_LPC23xx
-	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+    #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
 #endif
 
 #ifdef IAR_MSP430
-	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+    #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
 #endif
 
 #ifdef GCC_MSP430
-	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+    #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
 #endif
 
 #ifdef ROWLEY_MSP430
-	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+    #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
 #endif
 
 #ifdef ARM7_LPC21xx_KEIL_RVDS
-	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+    #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
 #endif
 
 #ifdef SAM7_GCC
-	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+    #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
 #endif
 
 #ifdef SAM7_IAR
-	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+    #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
 #endif
 
 #ifdef SAM9XE_IAR
-	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+    #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
 #endif
 
 #ifdef LPC2000_IAR
-	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+    #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
 #endif
 
 #ifdef STR71X_IAR
-	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+    #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
 #endif
 
 #ifdef STR75X_IAR
-	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+    #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
 #endif
 
 #ifdef STR75X_GCC
-	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+    #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
 #endif
 
 #ifdef STR91X_IAR
-	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+    #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
 #endif
 
 #ifdef GCC_H8S
-	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+    #include "../../Source/portable/GCC/H8S2329/portmacro.h"
 #endif
 
 #ifdef GCC_AT91FR40008
-	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+    #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
 #endif
 
 #ifdef RVDS_ARMCM3_LM3S102
-	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+    #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
 #endif
 
 #ifdef GCC_ARMCM3_LM3S102
-	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
 #endif
 
 #ifdef GCC_ARMCM3
-	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
 #endif
 
 #ifdef IAR_ARM_CM3
-	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
 #endif
 
 #ifdef IAR_ARMCM3_LM
-	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
 #endif
 
 #ifdef HCS12_CODE_WARRIOR
-	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+    #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
 #endif
 
 #ifdef MICROBLAZE_GCC
-	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+    #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
 #endif
 
 #ifdef TERN_EE
-	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+    #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
 #endif
 
 #ifdef GCC_HCS12
-	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+    #include "../../Source/portable/GCC/HCS12/portmacro.h"
 #endif
 
 #ifdef GCC_MCF5235
@@ -189,91 +190,92 @@ projects should not use them. */
 #endif
 
 #ifdef COLDFIRE_V2_GCC
-	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+    #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
 #endif
 
 #ifdef COLDFIRE_V2_CODEWARRIOR
-	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+    #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
 #endif
 
 #ifdef GCC_PPC405
-	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+    #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
 #endif
 
 #ifdef GCC_PPC440
-	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+    #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
 #endif
 
 #ifdef _16FX_SOFTUNE
-	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+    #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
 #endif
 
 #ifdef BCC_INDUSTRIAL_PC_PORT
-	/* A short file name has to be used in place of the normal
-	FreeRTOSConfig.h when using the Borland compiler. */
-	#include "frconfig.h"
-	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
-    typedef void ( __interrupt __far *pxISR )();
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
 #endif
 
 #ifdef BCC_FLASH_LITE_186_PORT
-	/* A short file name has to be used in place of the normal
-	FreeRTOSConfig.h when using the Borland compiler. */
-	#include "frconfig.h"
-	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
-    typedef void ( __interrupt __far *pxISR )();
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
 #endif
 
 #ifdef __GNUC__
-   #ifdef __AVR32_AVR32A__
-	   #include "portmacro.h"
-   #endif
+    #ifdef __AVR32_AVR32A__
+        #include "portmacro.h"
+    #endif
 #endif
 
 #ifdef __ICCAVR32__
-   #ifdef __CORE__
-      #if __CORE__ == __AVR32A__
-	      #include "portmacro.h"
-      #endif
-   #endif
+    #ifdef __CORE__
+        #if __CORE__ == __AVR32A__
+            #include "portmacro.h"
+        #endif
+    #endif
 #endif
 
 #ifdef __91467D
-	#include "portmacro.h"
+    #include "portmacro.h"
 #endif
 
 #ifdef __96340
-	#include "portmacro.h"
+    #include "portmacro.h"
 #endif
 
 
 #ifdef __IAR_V850ES_Fx3__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
 #endif
 
 #ifdef __IAR_V850ES_Jx3__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
 #endif
 
 #ifdef __IAR_V850ES_Jx3_L__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
 #endif
 
 #ifdef __IAR_V850ES_Jx2__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
 #endif
 
 #ifdef __IAR_V850ES_Hx2__
-	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
 #endif
 
 #ifdef __IAR_78K0R_Kx3__
-	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
 #endif
 
 #ifdef __IAR_78K0R_Kx3L__
-	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
 #endif
 
 #endif /* DEPRECATED_DEFINITIONS_H */
-

include/list.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*
@@ -32,7 +33,7 @@
  *
  * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
  * numeric value (xItemValue).  Most of the time the lists are sorted in
- * descending item value order.
+ * ascending item value order.
  *
  * Lists are created already containing one list item.  The value of this
  * item is the maximum possible that can be stored, it is therefore always at
@@ -53,13 +54,14 @@
  * \ingroup FreeRTOSIntro
  */
 
-#ifndef INC_FREERTOS_H
-	#error FreeRTOS.h must be included before list.h
-#endif
 
 #ifndef LIST_H
 #define LIST_H
 
+#ifndef INC_FREERTOS_H
+    #error "FreeRTOS.h must be included before list.h"
+#endif
+
 /*
  * The list structure members are modified from within interrupts, and therefore
  * by rights should be declared volatile.  However, they are only modified in a
@@ -89,47 +91,49 @@
  * "#define configLIST_VOLATILE volatile"
  */
 #ifndef configLIST_VOLATILE
-	#define configLIST_VOLATILE
+    #define configLIST_VOLATILE
 #endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
+/* *INDENT-ON* */
 
 /* Macros that can be used to place known values within the list structures,
-then check that the known values do not get corrupted during the execution of
-the application.   These may catch the list data structures being overwritten in
-memory.  They will not catch data errors caused by incorrect configuration or
-use of FreeRTOS.*/
-#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
-	/* Define the macros to do nothing. */
-	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
-	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
-	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
-	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
-	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
-	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
-	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
-	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
-	#define listTEST_LIST_INTEGRITY( pxList )
-#else
-	/* Define macros that add new members into the list structures. */
-	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
-	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
-	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
-	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+ * then check that the known values do not get corrupted during the execution of
+ * the application.   These may catch the list data structures being overwritten in
+ * memory.  They will not catch data errors caused by incorrect configuration or
+ * use of FreeRTOS.*/
+#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+    /* Define the macros to do nothing. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+    #define listTEST_LIST_INTEGRITY( pxList )
+#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
+    /* Define macros that add new members into the list structures. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;
 
-	/* Define macros that set the new structure members to known values. */
-	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
-	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+/* Define macros that set the new structure members to known values. */
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
 
-	/* Define macros that will assert if one of the structure members does not
-	contain its expected value. */
-	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
-	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+/* Define macros that will assert if one of the structure members does not
+ * contain its expected value. */
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
 #endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
 
 
@@ -139,35 +143,39 @@ use of FreeRTOS.*/
 struct xLIST;
 struct xLIST_ITEM
 {
-	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
-	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
-	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
-	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
-	struct xLIST * configLIST_VOLATILE pxContainer;		/*< Pointer to the list in which this list item is placed (if any). */
-	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE           /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    configLIST_VOLATILE TickType_t xItemValue;          /*< The value being listed.  In most cases this is used to sort the list in ascending order. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxNext;     /*< Pointer to the next ListItem_t in the list. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
+    void * pvOwner;                                     /*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+    struct xLIST * configLIST_VOLATILE pxContainer;     /*< Pointer to the list in which this list item is placed (if any). */
+    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
 };
-typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+typedef struct xLIST_ITEM ListItem_t;                   /* For some reason lint wants this as two separate definitions. */
 
-struct xMINI_LIST_ITEM
-{
-	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	configLIST_VOLATILE TickType_t xItemValue;
-	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
-	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
-};
-typedef struct xMINI_LIST_ITEM MiniListItem_t;
+#if ( configUSE_MINI_LIST_ITEM == 1 )
+    struct xMINI_LIST_ITEM
+    {
+        listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+        configLIST_VOLATILE TickType_t xItemValue;
+        struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+        struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+    };
+    typedef struct xMINI_LIST_ITEM MiniListItem_t;
+#else
+    typedef struct xLIST_ITEM      MiniListItem_t;
+#endif
 
 /*
  * Definition of the type of queue used by the scheduler.
  */
 typedef struct xLIST
 {
-	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	volatile UBaseType_t uxNumberOfItems;
-	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
-	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
-	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listFIRST_LIST_INTEGRITY_CHECK_VALUE      /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    volatile UBaseType_t uxNumberOfItems;
+    ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+    MiniListItem_t xListEnd;                  /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+    listSECOND_LIST_INTEGRITY_CHECK_VALUE     /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
 } List_t;
 
 /*
@@ -177,7 +185,7 @@ typedef struct xLIST
  * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
  * \ingroup LinkedList
  */
-#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
 
 /*
  * Access macro to get the owner of a list item.  The owner of a list item
@@ -186,16 +194,16 @@ typedef struct xLIST
  * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
  * \ingroup LinkedList
  */
-#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )
 
 /*
  * Access macro to set the value of the list item.  In most cases the value is
- * used to sort the list in descending order.
+ * used to sort the list in ascending order.
  *
  * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
  * \ingroup LinkedList
  */
-#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )
 
 /*
  * Access macro to retrieve the value of the list item.  The value can
@@ -205,7 +213,7 @@ typedef struct xLIST
  * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
  * \ingroup LinkedList
  */
-#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )
 
 /*
  * Access macro to retrieve the value of the list item at the head of a given
@@ -214,7 +222,7 @@ typedef struct xLIST
  * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
  * \ingroup LinkedList
  */
-#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
 
 /*
  * Return the list item at the head of the list.
@@ -222,7 +230,7 @@ typedef struct xLIST
  * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
  * \ingroup LinkedList
  */
-#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )
 
 /*
  * Return the next list item.
@@ -230,7 +238,7 @@ typedef struct xLIST
  * \page listGET_NEXT listGET_NEXT
  * \ingroup LinkedList
  */
-#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )
 
 /*
  * Return the list item that marks the end of the list
@@ -238,7 +246,7 @@ typedef struct xLIST
  * \page listGET_END_MARKER listGET_END_MARKER
  * \ingroup LinkedList
  */
-#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
 
 /*
  * Access macro to determine if a list contains any items.  The macro will
@@ -247,12 +255,12 @@ typedef struct xLIST
  * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
  * \ingroup LinkedList
  */
-#define listLIST_IS_EMPTY( pxList )	( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
 
 /*
  * Access macro to return the number of items in the list.
  */
-#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )
 
 /*
  * Access function to obtain the owner of the next entry in a list.
@@ -274,19 +282,99 @@ typedef struct xLIST
  * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
  * \ingroup LinkedList
  */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
-{																							\
-List_t * const pxConstList = ( pxList );													\
-	/* Increment the index to the next item and return the item, ensuring */				\
-	/* we don't return the marker used at the end of the list.  */							\
-	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
-	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
-	{																						\
-		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
-	}																						\
-	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
-}
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
+    {                                                                                          \
+        List_t * const pxConstList = ( pxList );                                               \
+        /* Increment the index to the next item and return the item, ensuring */               \
+        /* we don't return the marker used at the end of the list.  */                         \
+        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \
+        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
+        {                                                                                      \
+            ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                       \
+        }                                                                                      \
+        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
+    }
 
+/*
+ * Version of uxListRemove() that does not return a value.  Provided as a slight
+ * optimisation for xTaskIncrementTick() by being inline.
+ *
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page listREMOVE_ITEM listREMOVE_ITEM
+ * \ingroup LinkedList
+ */
+#define listREMOVE_ITEM( pxItemToRemove ) \
+    {                                     \
+        /* The list item knows which list it is in.  Obtain the list from the list \
+         * item. */                                                              \
+        List_t * const pxList = ( pxItemToRemove )->pxContainer;                 \
+                                                                                 \
+        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
+        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;     \
+        /* Make sure the index is left pointing to a valid item. */              \
+        if( pxList->pxIndex == ( pxItemToRemove ) )                              \
+        {                                                                        \
+            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                    \
+        }                                                                        \
+                                                                                 \
+        ( pxItemToRemove )->pxContainer = NULL;                                  \
+        ( pxList->uxNumberOfItems )--;                                           \
+    }
+
+/*
+ * Inline version of vListInsertEnd() to provide slight optimisation for
+ * xTaskIncrementTick().
+ *
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page listINSERT_END listINSERT_END
+ * \ingroup LinkedList
+ */
+#define listINSERT_END( pxList, pxNewListItem )           \
+    {                                                     \
+        ListItem_t * const pxIndex = ( pxList )->pxIndex; \
+                                                          \
+        /* Only effective when configASSERT() is also defined, these tests may catch \
+         * the list data structures being overwritten in memory.  They will not catch \
+         * data errors caused by incorrect configuration or use of FreeRTOS. */ \
+        listTEST_LIST_INTEGRITY( ( pxList ) );                                  \
+        listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) );                      \
+                                                                                \
+        /* Insert a new list item into ( pxList ), but rather than sort the list, \
+         * makes the new list item the last item to be removed by a call to \
+         * listGET_OWNER_OF_NEXT_ENTRY(). */                 \
+        ( pxNewListItem )->pxNext = pxIndex;                 \
+        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
+                                                             \
+        pxIndex->pxPrevious->pxNext = ( pxNewListItem );     \
+        pxIndex->pxPrevious = ( pxNewListItem );             \
+                                                             \
+        /* Remember which list the item is in. */            \
+        ( pxNewListItem )->pxContainer = ( pxList );         \
+                                                             \
+        ( ( pxList )->uxNumberOfItems )++;                   \
+    }
 
 /*
  * Access function to obtain the owner of the first entry in a list.  Lists
@@ -304,7 +392,7 @@ List_t * const pxConstList = ( pxList );													\
  * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
  * \ingroup LinkedList
  */
-#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
 
 /*
  * Check to see if a list item is within a list.  The list item maintains a
@@ -315,7 +403,7 @@ List_t * const pxConstList = ( pxList );													\
  * @param pxListItem The list item we want to know if is in the list.
  * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
  */
-#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
 
 /*
  * Return the list a list item is contained within (referenced from).
@@ -323,14 +411,14 @@ List_t * const pxConstList = ( pxList );													\
  * @param pxListItem The list item being queried.
  * @return A pointer to the List_t object that references the pxListItem
  */
-#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
+#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )
 
 /*
  * This provides a crude means of knowing if a list has been initialised, as
  * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
  * function.
  */
-#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
 
 /*
  * Must be called before a list is used!  This initialises all the members
@@ -357,7 +445,7 @@ void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
 
 /*
  * Insert a list item into a list.  The item will be inserted into the list in
- * a position determined by its item value (descending item value order).
+ * a position determined by its item value (ascending item value order).
  *
  * @param pxList The list into which the item is to be inserted.
  *
@@ -366,7 +454,8 @@ void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
  * \page vListInsert vListInsert
  * \ingroup LinkedList
  */
-void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
 
 /*
  * Insert a list item into a list.  The item will be inserted in a position
@@ -387,7 +476,8 @@ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIV
  * \page vListInsertEnd vListInsertEnd
  * \ingroup LinkedList
  */
-void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
 
 /*
  * Remove an item from a list.  The list item has a pointer to the list that
@@ -404,9 +494,10 @@ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) P
  */
 UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-}
-#endif
-
+    }
 #endif
+/* *INDENT-ON* */
 
+#endif /* ifndef LIST_H */

include/message_buffer.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 
@@ -63,32 +64,35 @@
 #define FREERTOS_MESSAGE_BUFFER_H
 
 #ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include message_buffer.h"
+    #error "include FreeRTOS.h must appear in source files before include message_buffer.h"
 #endif
 
 /* Message buffers are built onto of stream buffers. */
 #include "stream_buffer.h"
 
+/* *INDENT-OFF* */
 #if defined( __cplusplus )
-extern "C" {
+    extern "C" {
 #endif
+/* *INDENT-ON* */
 
 /**
  * Type by which message buffers are referenced.  For example, a call to
  * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
  * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
- * etc.
+ * etc. Message buffer is essentially built as a stream buffer hence its handle
+ * is also set to same type as a stream buffer handle.
  */
-typedef void * MessageBufferHandle_t;
+typedef StreamBufferHandle_t MessageBufferHandle_t;
 
 /*-----------------------------------------------------------*/
 
 /**
  * message_buffer.h
  *
-<pre>
-MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
-</pre>
+ * @code{c}
+ * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+ * @endcode
  *
  * Creates a new message buffer using dynamically allocated memory.  See
  * xMessageBufferCreateStatic() for a version that uses statically allocated
@@ -104,6 +108,18 @@ MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
  * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
  * take up 14 bytes of message buffer space.
  *
+ * @param pxSendCompletedCallback Callback invoked when a send operation to the
+ * message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, then it will use the default implementation
+ * provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a receive operation from
+ * the message buffer is complete. If the parameter is NULL or xMessageBufferCreate()
+ * is called without the parameter, it will use the default implementation provided
+ * by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
  * @return If NULL is returned, then the message buffer cannot be created
  * because there is insufficient heap memory available for FreeRTOS to allocate
  * the message buffer data structures and storage area.  A non-NULL value being
@@ -112,43 +128,49 @@ MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
  * buffer.
  *
  * Example use:
-<pre>
-
-void vAFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-const size_t xMessageBufferSizeBytes = 100;
-
-    // Create a message buffer that can hold 100 bytes.  The memory used to hold
-    // both the message buffer structure and the messages themselves is allocated
-    // dynamically.  Each message added to the buffer consumes an additional 4
-    // bytes which are used to hold the lengh of the message.
-    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
-
-    if( xMessageBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // message buffer.
-    }
-    else
-    {
-        // The message buffer was created successfully and can now be used.
-    }
-
-</pre>
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ * const size_t xMessageBufferSizeBytes = 100;
+ *
+ *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the message buffer structure and the messages themselves is allocated
+ *  // dynamically.  Each message added to the buffer consumes an additional 4
+ *  // bytes which are used to hold the length of the message.
+ *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+ *
+ *  if( xMessageBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // message buffer.
+ *  }
+ *  else
+ *  {
+ *      // The message buffer was created successfully and can now be used.
+ *  }
+ *
+ * @endcode
  * \defgroup xMessageBufferCreate xMessageBufferCreate
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+#define xMessageBufferCreate( xBufferSizeBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
 
 /**
  * message_buffer.h
  *
-<pre>
-MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
-                                                  uint8_t *pucMessageBufferStorageArea,
-                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
-</pre>
+ * @code{c}
+ * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                uint8_t *pucMessageBufferStorageArea,
+ *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ * @endcode
  * Creates a new message buffer using statically allocated memory.  See
  * xMessageBufferCreate() for a version that uses dynamically allocated memory.
  *
@@ -161,61 +183,77 @@ MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
  * stored in the message buffer is actually (xBufferSizeBytes - 1).
  *
  * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which messages are
+ * least xBufferSizeBytes big.  This is the array to which messages are
  * copied when they are written to the message buffer.
  *
  * @param pxStaticMessageBuffer Must point to a variable of type
  * StaticMessageBuffer_t, which will be used to hold the message buffer's data
  * structure.
  *
+ * @param pxSendCompletedCallback Callback invoked when a new message is sent to the message buffer.
+ * If the parameter is NULL or xMessageBufferCreate() is called without the parameter, then it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when a message is read from a
+ * message buffer. If the parameter is NULL or xMessageBufferCreate() is called without the parameter, it will
+ * use the default implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
  * @return If the message buffer is created successfully then a handle to the
  * created message buffer is returned. If either pucMessageBufferStorageArea or
  * pxStaticmessageBuffer are NULL then NULL is returned.
  *
  * Example use:
-<pre>
-
-// Used to dimension the array used to hold the messages.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the messages within the message
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the message buffer structure.
-StaticMessageBuffer_t xMessageBufferStruct;
-
-void MyFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-
-    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
-                                                 ucBufferStorage,
-                                                 &xMessageBufferStruct );
-
-    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
-    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
-    // reference the created message buffer in other message buffer API calls.
-
-    // Other code that uses the message buffer can go here.
-}
-
-</pre>
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the messages.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the messages within the message
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the message buffer structure.
+ * StaticMessageBuffer_t xMessageBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                               ucStorageBuffer,
+ *                                               &xMessageBufferStruct );
+ *
+ *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ *  // reference the created message buffer in other message buffer API calls.
+ *
+ *  // Other code that uses the message buffer can go here.
+ * }
+ *
+ * @endcode
  * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
 
 /**
  * message_buffer.h
  *
-<pre>
-size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
-                           const void *pvTxData,
-                           size_t xDataLengthBytes,
-                           TickType_t xTicksToWait );
-<pre>
+ * @code{c}
+ * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ *                         const void *pvTxData,
+ *                         size_t xDataLengthBytes,
+ *                         TickType_t xTicksToWait );
+ * @endcode
  *
  * Sends a discrete message to the message buffer.  The message can be any
  * length that fits within the buffer's free space, and is copied into the
@@ -272,49 +310,50 @@ size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
  * time out then xDataLengthBytes is returned.
  *
  * Example use:
-<pre>
-void vAFunction( MessageBufferHandle_t xMessageBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the message buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the message buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xMessageBufferSend() times out before there was enough
-        // space in the buffer for the data to be written.
-    }
-
-    // Send the string to the message buffer.  Return immediately if there is
-    // not enough space in the buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-}
-</pre>
+ * @code{c}
+ * void vAFunction( MessageBufferHandle_t xMessageBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the message buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the message buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xMessageBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written.
+ *  }
+ *
+ *  // Send the string to the message buffer.  Return immediately if there is
+ *  // not enough space in the buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ * }
+ * @endcode
  * \defgroup xMessageBufferSend xMessageBufferSend
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
+    xStreamBufferSend( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( xTicksToWait ) )
 
 /**
  * message_buffer.h
  *
-<pre>
-size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
-                                  const void *pvTxData,
-                                  size_t xDataLengthBytes,
-                                  BaseType_t *pxHigherPriorityTaskWoken );
-<pre>
+ * @code{c}
+ * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                const void *pvTxData,
+ *                                size_t xDataLengthBytes,
+ *                                BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * Interrupt safe version of the API function that sends a discrete message to
  * the message buffer.  The message can be any length that fits within the
@@ -372,53 +411,54 @@ size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
  * then 0 is returned, otherwise xDataLengthBytes is returned.
  *
  * Example use:
-<pre>
-// A message buffer that has already been created.
-MessageBufferHandle_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the message buffer.
-    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
-                                            ( void * ) pcStringToSend,
-                                            strlen( pcStringToSend ),
-                                            &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-</pre>
+ * @code{c}
+ * // A message buffer that has already been created.
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the message buffer.
+ *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ *                                          ( void * ) pcStringToSend,
+ *                                          strlen( pcStringToSend ),
+ *                                          &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
  * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendFromISR( ( xMessageBuffer ), ( pvTxData ), ( xDataLengthBytes ), ( pxHigherPriorityTaskWoken ) )
 
 /**
  * message_buffer.h
  *
-<pre>
-size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
-                              void *pvRxData,
-                              size_t xBufferLengthBytes,
-                              TickType_t xTicksToWait );
-</pre>
+ * @code{c}
+ * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ *                            void *pvRxData,
+ *                            size_t xBufferLengthBytes,
+ *                            TickType_t xTicksToWait );
+ * @endcode
  *
  * Receives a discrete message from a message buffer.  Messages can be of
  * variable length and are copied out of the buffer.
@@ -471,43 +511,44 @@ size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
  * zero is returned.
  *
  * Example use:
-<pre>
-void vAFunction( MessageBuffer_t xMessageBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive the next message from the message buffer.  Wait in the Blocked
-    // state (so not using any CPU processing time) for a maximum of 100ms for
-    // a message to become available.
-    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
-                                            ( void * ) ucRxData,
-                                            sizeof( ucRxData ),
-                                            xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-}
-</pre>
+ * @code{c}
+ * void vAFunction( MessageBuffer_t xMessageBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive the next message from the message buffer.  Wait in the Blocked
+ *  // state (so not using any CPU processing time) for a maximum of 100ms for
+ *  // a message to become available.
+ *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ *                                          ( void * ) ucRxData,
+ *                                          sizeof( ucRxData ),
+ *                                          xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ * }
+ * @endcode
  * \defgroup xMessageBufferReceive xMessageBufferReceive
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
+    xStreamBufferReceive( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( xTicksToWait ) )
 
 
 /**
  * message_buffer.h
  *
-<pre>
-size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
-                                     void *pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                   void *pvRxData,
+ *                                   size_t xBufferLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * An interrupt safe version of the API function that receives a discrete
  * message from a message buffer.  Messages can be of variable length and are
@@ -561,50 +602,51 @@ size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
  * any.
  *
  * Example use:
-<pre>
-// A message buffer that has already been created.
-MessageBuffer_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next message from the message buffer.
-    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-</pre>
+ * @code{c}
+ * // A message buffer that has already been created.
+ * MessageBuffer_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next message from the message buffer.
+ *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
  * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveFromISR( ( xMessageBuffer ), ( pvRxData ), ( xBufferLengthBytes ), ( pxHigherPriorityTaskWoken ) )
 
 /**
  * message_buffer.h
  *
-<pre>
-void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
-</pre>
+ * @code{c}
+ * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  *
  * Deletes a message buffer that was previously created using a call to
  * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
@@ -617,13 +659,14 @@ void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
  * @param xMessageBuffer The handle of the message buffer to be deleted.
  *
  */
-#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+#define vMessageBufferDelete( xMessageBuffer ) \
+    vStreamBufferDelete( xMessageBuffer )
 
 /**
  * message_buffer.h
-<pre>
-BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
-</pre>
+ * @code{c}
+ * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  *
  * Tests to see if a message buffer is full.  A message buffer is full if it
  * cannot accept any more messages, of any size, until space is made available
@@ -634,13 +677,14 @@ BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
  * @return If the message buffer referenced by xMessageBuffer is full then
  * pdTRUE is returned.  Otherwise pdFALSE is returned.
  */
-#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferIsFull( xMessageBuffer ) \
+    xStreamBufferIsFull( xMessageBuffer )
 
 /**
  * message_buffer.h
-<pre>
-BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
-</pre>
+ * @code{c}
+ * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  *
  * Tests to see if a message buffer is empty (does not contain any messages).
  *
@@ -650,13 +694,14 @@ BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
  * pdTRUE is returned.  Otherwise pdFALSE is returned.
  *
  */
-#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferIsEmpty( xMessageBuffer ) \
+    xStreamBufferIsEmpty( xMessageBuffer )
 
 /**
  * message_buffer.h
-<pre>
-BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
-</pre>
+ * @code{c}
+ * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  *
  * Resets a message buffer to its initial empty state, discarding any message it
  * contained.
@@ -673,14 +718,15 @@ BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
  * \defgroup xMessageBufferReset xMessageBufferReset
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferReset( xMessageBuffer ) \
+    xStreamBufferReset( xMessageBuffer )
 
 
 /**
  * message_buffer.h
-<pre>
-size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
-</pre>
+ * @code{c}
+ * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  * Returns the number of bytes of free space in the message buffer.
  *
  * @param xMessageBuffer The handle of the message buffer being queried.
@@ -695,14 +741,16 @@ size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
  * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
-#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( xMessageBuffer ) /* Corrects typo in original macro name. */
 
 /**
  * message_buffer.h
- <pre>
- size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
- </pre>
+ * @code{c}
+ * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
  * Returns the length (in bytes) of the next message in a message buffer.
  * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
  * passed into xMessageBufferReceive() was too small to hold the next message.
@@ -715,14 +763,15 @@ size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
  * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
  * \ingroup MessageBufferManagement
  */
-#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
+    xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
 
 /**
  * message_buffer.h
  *
-<pre>
-BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * For advanced users only.
  *
@@ -737,7 +786,7 @@ BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuff
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
- * @param xStreamBuffer The handle of the stream buffer to which data was
+ * @param xMessageBuffer The handle of the stream buffer to which data was
  * written.
  *
  * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
@@ -754,14 +803,15 @@ BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuff
  * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
  * \ingroup StreamBufferManagement
  */
-#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
 
 /**
  * message_buffer.h
  *
-<pre>
-BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * For advanced users only.
  *
@@ -777,7 +827,7 @@ BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamB
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
- * @param xStreamBuffer The handle of the stream buffer from which data was
+ * @param xMessageBuffer The handle of the stream buffer from which data was
  * read.
  *
  * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
@@ -794,10 +844,13 @@ BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamB
  * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
  * \ingroup StreamBufferManagement
  */
-#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveCompletedFromISR( ( xMessageBuffer ), ( pxHigherPriorityTaskWoken ) )
 
+/* *INDENT-OFF* */
 #if defined( __cplusplus )
-} /* extern "C" */
+    } /* extern "C" */
 #endif
+/* *INDENT-ON* */
 
-#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
+#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */

include/mpu_prototypes.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*
@@ -37,20 +38,33 @@
 #ifndef MPU_PROTOTYPES_H
 #define MPU_PROTOTYPES_H
 
-/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+/* MPU versions of task.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,
+                            const uint16_t usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                           UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
@@ -59,90 +73,170 @@ BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
 char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
 TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                   UBaseType_t uxIndexToNotify,
+                                   uint32_t ulValue,
+                                   eNotifyAction eAction,
+                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                       uint32_t ulBitsToClearOnEntry,
+                                       uint32_t ulBitsToClearOnExit,
+                                       uint32_t * pulNotificationValue,
+                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                  const void * const pvItemToQueue,
+                                  TickType_t xTicksToWait,
+                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                              void * const pvBuffer,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                           void * const pvBuffer,
+                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcName ) FREERTOS_SYSTEM_CALL;
 void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
 QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                   BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
+                                const TickType_t xTimerPeriodInTicks,
+                                const UBaseType_t uxAutoReload,
+                                void * const pvTimerID,
+                                TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
+                                      const TickType_t xTimerPeriodInTicks,
+                                      const UBaseType_t uxAutoReload,
+                                      void * const pvTimerID,
+                                      TimerCallbackFunction_t pxCallbackFunction,
+                                      StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
 void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                       void * pvParameter1,
+                                       uint32_t ulParameter2,
+                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
+                                     const BaseType_t xCommandID,
+                                     const TickType_t xOptionalValue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of event_group.h API functions. */
 EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     const BaseType_t xClearOnExit,
+                                     const BaseType_t xWaitForAllBits,
+                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                              const void * pvTxData,
+                              size_t xDataLengthBytes,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                 void * pvRxData,
+                                 size_t xBufferLengthBytes,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
@@ -150,11 +244,21 @@ BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERT
 BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
 size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                     size_t xTriggerLevelBytes,
+                                                     BaseType_t xIsMessageBuffer,
+                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
 
 
 
 #endif /* MPU_PROTOTYPES_H */
-

include/mpu_wrappers.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,171 +21,164 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef MPU_WRAPPERS_H
 #define MPU_WRAPPERS_H
 
 /* This file redefines API functions to be called through a wrapper macro, but
-only for ports that are using the MPU. */
-#ifdef portUSING_MPU_WRAPPERS
+ * only for ports that are using the MPU. */
+#if ( portUSING_MPU_WRAPPERS == 1 )
 
-	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
-	included from queue.c or task.c to prevent it from having an effect within
-	those files. */
-	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+ * included from queue.c or task.c to prevent it from having an effect within
+ * those files. */
+    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
-		/*
-		 * Map standard (non MPU) API functions to equivalents that start
-		 * "MPU_".  This will cause the application code to call the MPU_
-		 * version, which wraps the non-MPU version with privilege promoting
-		 * then demoting code, so the kernel code always runs will full
-		 * privileges.
-		 */
+/*
+ * Map standard (non MPU) API functions to equivalents that start
+ * "MPU_".  This will cause the application code to call the MPU_
+ * version, which wraps the non-MPU version with privilege promoting
+ * then demoting code, so the kernel code always runs will full
+ * privileges.
+ */
 
-		/* Map standard tasks.h API functions to the MPU equivalents. */
-		#define xTaskCreate								MPU_xTaskCreate
-		#define xTaskCreateStatic						MPU_xTaskCreateStatic
-		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
-		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
-		#define vTaskDelete								MPU_vTaskDelete
-		#define vTaskDelay								MPU_vTaskDelay
-		#define vTaskDelayUntil							MPU_vTaskDelayUntil
-		#define xTaskAbortDelay							MPU_xTaskAbortDelay
-		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
-		#define eTaskGetState							MPU_eTaskGetState
-		#define vTaskGetInfo							MPU_vTaskGetInfo
-		#define vTaskPrioritySet						MPU_vTaskPrioritySet
-		#define vTaskSuspend							MPU_vTaskSuspend
-		#define vTaskResume								MPU_vTaskResume
-		#define vTaskSuspendAll							MPU_vTaskSuspendAll
-		#define xTaskResumeAll							MPU_xTaskResumeAll
-		#define xTaskGetTickCount						MPU_xTaskGetTickCount
-		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
-		#define pcTaskGetName							MPU_pcTaskGetName
-		#define xTaskGetHandle							MPU_xTaskGetHandle
-		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
-		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
-		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
-		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
-		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
-		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
-		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
-		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
-		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
-		#define vTaskList								MPU_vTaskList
-		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
-		#define ulTaskGetIdleRunTimeCounter				MPU_ulTaskGetIdleRunTimeCounter
-		#define xTaskGenericNotify						MPU_xTaskGenericNotify
-		#define xTaskNotifyWait							MPU_xTaskNotifyWait
-		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
-		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
-		#define ulTaskNotifyValueClear					MPU_ulTaskNotifyValueClear
-		#define xTaskCatchUpTicks						MPU_xTaskCatchUpTicks
+/* Map standard task.h API functions to the MPU equivalents. */
+        #define xTaskCreate                            MPU_xTaskCreate
+        #define xTaskCreateStatic                      MPU_xTaskCreateStatic
+        #define vTaskDelete                            MPU_vTaskDelete
+        #define vTaskDelay                             MPU_vTaskDelay
+        #define xTaskDelayUntil                        MPU_xTaskDelayUntil
+        #define xTaskAbortDelay                        MPU_xTaskAbortDelay
+        #define uxTaskPriorityGet                      MPU_uxTaskPriorityGet
+        #define eTaskGetState                          MPU_eTaskGetState
+        #define vTaskGetInfo                           MPU_vTaskGetInfo
+        #define vTaskPrioritySet                       MPU_vTaskPrioritySet
+        #define vTaskSuspend                           MPU_vTaskSuspend
+        #define vTaskResume                            MPU_vTaskResume
+        #define vTaskSuspendAll                        MPU_vTaskSuspendAll
+        #define xTaskResumeAll                         MPU_xTaskResumeAll
+        #define xTaskGetTickCount                      MPU_xTaskGetTickCount
+        #define uxTaskGetNumberOfTasks                 MPU_uxTaskGetNumberOfTasks
+        #define pcTaskGetName                          MPU_pcTaskGetName
+        #define xTaskGetHandle                         MPU_xTaskGetHandle
+        #define uxTaskGetStackHighWaterMark            MPU_uxTaskGetStackHighWaterMark
+        #define uxTaskGetStackHighWaterMark2           MPU_uxTaskGetStackHighWaterMark2
+        #define vTaskSetApplicationTaskTag             MPU_vTaskSetApplicationTaskTag
+        #define xTaskGetApplicationTaskTag             MPU_xTaskGetApplicationTaskTag
+        #define vTaskSetThreadLocalStoragePointer      MPU_vTaskSetThreadLocalStoragePointer
+        #define pvTaskGetThreadLocalStoragePointer     MPU_pvTaskGetThreadLocalStoragePointer
+        #define xTaskCallApplicationTaskHook           MPU_xTaskCallApplicationTaskHook
+        #define xTaskGetIdleTaskHandle                 MPU_xTaskGetIdleTaskHandle
+        #define uxTaskGetSystemState                   MPU_uxTaskGetSystemState
+        #define vTaskList                              MPU_vTaskList
+        #define vTaskGetRunTimeStats                   MPU_vTaskGetRunTimeStats
+        #define ulTaskGetIdleRunTimeCounter            MPU_ulTaskGetIdleRunTimeCounter
+        #define ulTaskGetIdleRunTimePercent            MPU_ulTaskGetIdleRunTimePercent
+        #define xTaskGenericNotify                     MPU_xTaskGenericNotify
+        #define xTaskGenericNotifyWait                 MPU_xTaskGenericNotifyWait
+        #define ulTaskGenericNotifyTake                MPU_ulTaskGenericNotifyTake
+        #define xTaskGenericNotifyStateClear           MPU_xTaskGenericNotifyStateClear
+        #define ulTaskGenericNotifyValueClear          MPU_ulTaskGenericNotifyValueClear
+        #define xTaskCatchUpTicks                      MPU_xTaskCatchUpTicks
 
-		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
-		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
-		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
-		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+        #define xTaskGetCurrentTaskHandle              MPU_xTaskGetCurrentTaskHandle
+        #define vTaskSetTimeOutState                   MPU_vTaskSetTimeOutState
+        #define xTaskCheckForTimeOut                   MPU_xTaskCheckForTimeOut
+        #define xTaskGetSchedulerState                 MPU_xTaskGetSchedulerState
 
-		/* Map standard queue.h API functions to the MPU equivalents. */
-		#define xQueueGenericSend						MPU_xQueueGenericSend
-		#define xQueueReceive							MPU_xQueueReceive
-		#define xQueuePeek								MPU_xQueuePeek
-		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
-		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
-		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
-		#define vQueueDelete							MPU_vQueueDelete
-		#define xQueueCreateMutex						MPU_xQueueCreateMutex
-		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
-		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
-		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
-		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
-		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
-		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
-		#define xQueueGenericCreate						MPU_xQueueGenericCreate
-		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
-		#define xQueueCreateSet							MPU_xQueueCreateSet
-		#define xQueueAddToSet							MPU_xQueueAddToSet
-		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
-		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
-		#define xQueueGenericReset						MPU_xQueueGenericReset
+/* Map standard queue.h API functions to the MPU equivalents. */
+        #define xQueueGenericSend                      MPU_xQueueGenericSend
+        #define xQueueReceive                          MPU_xQueueReceive
+        #define xQueuePeek                             MPU_xQueuePeek
+        #define xQueueSemaphoreTake                    MPU_xQueueSemaphoreTake
+        #define uxQueueMessagesWaiting                 MPU_uxQueueMessagesWaiting
+        #define uxQueueSpacesAvailable                 MPU_uxQueueSpacesAvailable
+        #define vQueueDelete                           MPU_vQueueDelete
+        #define xQueueCreateMutex                      MPU_xQueueCreateMutex
+        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic
+        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore
+        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic
+        #define xQueueGetMutexHolder                   MPU_xQueueGetMutexHolder
+        #define xQueueTakeMutexRecursive               MPU_xQueueTakeMutexRecursive
+        #define xQueueGiveMutexRecursive               MPU_xQueueGiveMutexRecursive
+        #define xQueueGenericCreate                    MPU_xQueueGenericCreate
+        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
+        #define xQueueCreateSet                        MPU_xQueueCreateSet
+        #define xQueueAddToSet                         MPU_xQueueAddToSet
+        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
+        #define xQueueSelectFromSet                    MPU_xQueueSelectFromSet
+        #define xQueueGenericReset                     MPU_xQueueGenericReset
 
-		#if( configQUEUE_REGISTRY_SIZE > 0 )
-			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
-			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
-			#define pcQueueGetName							MPU_pcQueueGetName
-		#endif
+        #if ( configQUEUE_REGISTRY_SIZE > 0 )
+            #define vQueueAddToRegistry                MPU_vQueueAddToRegistry
+            #define vQueueUnregisterQueue              MPU_vQueueUnregisterQueue
+            #define pcQueueGetName                     MPU_pcQueueGetName
+        #endif
 
-		/* Map standard timer.h API functions to the MPU equivalents. */
-		#define xTimerCreate							MPU_xTimerCreate
-		#define xTimerCreateStatic						MPU_xTimerCreateStatic
-		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
-		#define vTimerSetTimerID						MPU_vTimerSetTimerID
-		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
-		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
-		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
-		#define pcTimerGetName							MPU_pcTimerGetName
-		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
-		#define uxTimerGetReloadMode					MPU_uxTimerGetReloadMode
-		#define xTimerGetPeriod							MPU_xTimerGetPeriod
-		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
-		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+/* Map standard timer.h API functions to the MPU equivalents. */
+        #define pvTimerGetTimerID                      MPU_pvTimerGetTimerID
+        #define vTimerSetTimerID                       MPU_vTimerSetTimerID
+        #define xTimerIsTimerActive                    MPU_xTimerIsTimerActive
+        #define xTimerGetTimerDaemonTaskHandle         MPU_xTimerGetTimerDaemonTaskHandle
+        #define pcTimerGetName                         MPU_pcTimerGetName
+        #define vTimerSetReloadMode                    MPU_vTimerSetReloadMode
+        #define uxTimerGetReloadMode                   MPU_uxTimerGetReloadMode
+        #define xTimerGetPeriod                        MPU_xTimerGetPeriod
+        #define xTimerGetExpiryTime                    MPU_xTimerGetExpiryTime
+        #define xTimerGenericCommand                   MPU_xTimerGenericCommand
 
-		/* Map standard event_group.h API functions to the MPU equivalents. */
-		#define xEventGroupCreate						MPU_xEventGroupCreate
-		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
-		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
-		#define xEventGroupClearBits					MPU_xEventGroupClearBits
-		#define xEventGroupSetBits						MPU_xEventGroupSetBits
-		#define xEventGroupSync							MPU_xEventGroupSync
-		#define vEventGroupDelete						MPU_vEventGroupDelete
+/* Map standard event_group.h API functions to the MPU equivalents. */
+        #define xEventGroupCreate                      MPU_xEventGroupCreate
+        #define xEventGroupCreateStatic                MPU_xEventGroupCreateStatic
+        #define xEventGroupWaitBits                    MPU_xEventGroupWaitBits
+        #define xEventGroupClearBits                   MPU_xEventGroupClearBits
+        #define xEventGroupSetBits                     MPU_xEventGroupSetBits
+        #define xEventGroupSync                        MPU_xEventGroupSync
+        #define vEventGroupDelete                      MPU_vEventGroupDelete
 
-		/* Map standard message/stream_buffer.h API functions to the MPU
-		equivalents. */
-		#define xStreamBufferSend						MPU_xStreamBufferSend
-		#define xStreamBufferReceive					MPU_xStreamBufferReceive
-		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
-		#define vStreamBufferDelete						MPU_vStreamBufferDelete
-		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
-		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
-		#define xStreamBufferReset						MPU_xStreamBufferReset
-		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
-		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
-		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
-		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
-		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
+/* Map standard message/stream_buffer.h API functions to the MPU
+ * equivalents. */
+        #define xStreamBufferSend                      MPU_xStreamBufferSend
+        #define xStreamBufferReceive                   MPU_xStreamBufferReceive
+        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes
+        #define vStreamBufferDelete                    MPU_vStreamBufferDelete
+        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull
+        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty
+        #define xStreamBufferReset                     MPU_xStreamBufferReset
+        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable
+        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable
+        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel
+        #define xStreamBufferGenericCreate             MPU_xStreamBufferGenericCreate
+        #define xStreamBufferGenericCreateStatic       MPU_xStreamBufferGenericCreateStatic
 
 
-		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
-		macro so applications can place data in privileged access sections
-		(useful when using statically allocated objects). */
-		#define PRIVILEGED_FUNCTION
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL
+/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+ * macro so applications can place data in privileged access sections
+ * (useful when using statically allocated objects). */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL
 
-	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
-		/* Ensure API functions go in the privileged execution section. */
-		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
+/* Ensure API functions go in the privileged execution section. */
+        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
+        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
 
-	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
 #else /* portUSING_MPU_WRAPPERS */
 
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-	#define FREERTOS_SYSTEM_CALL
-	#define portUSING_MPU_WRAPPERS 0
+    #define PRIVILEGED_FUNCTION
+    #define PRIVILEGED_DATA
+    #define FREERTOS_SYSTEM_CALL
 
 #endif /* portUSING_MPU_WRAPPERS */
 
 
 #endif /* MPU_WRAPPERS_H */
-

include/portable.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,83 +21,81 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*-----------------------------------------------------------
- * Portable layer API.  Each function must be defined for each port.
- *----------------------------------------------------------*/
+* Portable layer API.  Each function must be defined for each port.
+*----------------------------------------------------------*/
 
 #ifndef PORTABLE_H
 #define PORTABLE_H
 
 /* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.
-Purely for reasons of backward compatibility the old method is still valid, but
-to make it clear that new projects should not use it, support for the port
-specific constants has been moved into the deprecated_definitions.h header
-file. */
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.
+ * Purely for reasons of backward compatibility the old method is still valid, but
+ * to make it clear that new projects should not use it, support for the port
+ * specific constants has been moved into the deprecated_definitions.h header
+ * file. */
 #include "deprecated_definitions.h"
 
 /* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
-did not result in a portmacro.h header file being included - and it should be
-included here.  In this case the path to the correct portmacro.h header file
-must be set in the compiler's include path. */
+ * did not result in a portmacro.h header file being included - and it should be
+ * included here.  In this case the path to the correct portmacro.h header file
+ * must be set in the compiler's include path. */
 #ifndef portENTER_CRITICAL
-	#include "portmacro.h"
+    #include "portmacro.h"
 #endif
 
 #if portBYTE_ALIGNMENT == 32
-	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
-#endif
+    #define portBYTE_ALIGNMENT_MASK    ( 0x001f )
+#elif portBYTE_ALIGNMENT == 16
+    #define portBYTE_ALIGNMENT_MASK    ( 0x000f )
+#elif portBYTE_ALIGNMENT == 8
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0007 )
+#elif portBYTE_ALIGNMENT == 4
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0003 )
+#elif portBYTE_ALIGNMENT == 2
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0001 )
+#elif portBYTE_ALIGNMENT == 1
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0000 )
+#else /* if portBYTE_ALIGNMENT == 32 */
+    #error "Invalid portBYTE_ALIGNMENT definition"
+#endif /* if portBYTE_ALIGNMENT == 32 */
 
-#if portBYTE_ALIGNMENT == 16
-	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
-#endif
-
-#if portBYTE_ALIGNMENT == 8
-	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
-	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
-	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
-	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
-#endif
-
-#ifndef portBYTE_ALIGNMENT_MASK
-	#error "Invalid portBYTE_ALIGNMENT definition"
+#ifndef portUSING_MPU_WRAPPERS
+    #define portUSING_MPU_WRAPPERS    0
 #endif
 
 #ifndef portNUM_CONFIGURABLE_REGIONS
-	#define portNUM_CONFIGURABLE_REGIONS 1
+    #define portNUM_CONFIGURABLE_REGIONS    1
 #endif
 
 #ifndef portHAS_STACK_OVERFLOW_CHECKING
-	#define portHAS_STACK_OVERFLOW_CHECKING 0
+    #define portHAS_STACK_OVERFLOW_CHECKING    0
 #endif
 
 #ifndef portARCH_NAME
-	#define portARCH_NAME NULL
+    #define portARCH_NAME    NULL
 #endif
 
-#ifdef __cplusplus
-extern "C" {
+#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
+    /* Defaults to 0 for backward compatibility. */
+    #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
 #endif
 
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
 #include "mpu_wrappers.h"
 
 /*
@@ -104,38 +104,50 @@ extern "C" {
  * the order that the port expects to find them.
  *
  */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#endif
-#else
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#endif
-#endif
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #endif
+#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #endif
+#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
 
 /* Used by heap_5.c to define the start address and size of each memory region
-that together comprise the total FreeRTOS heap space. */
+ * that together comprise the total FreeRTOS heap space. */
 typedef struct HeapRegion
 {
-	uint8_t *pucStartAddress;
-	size_t xSizeInBytes;
+    uint8_t * pucStartAddress;
+    size_t xSizeInBytes;
 } HeapRegion_t;
 
 /* Used to pass information about the heap out of vPortGetHeapStats(). */
 typedef struct xHeapStats
 {
-	size_t xAvailableHeapSpaceInBytes;		/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
-	size_t xSizeOfLargestFreeBlockInBytes; 	/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-	size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
-	size_t xNumberOfFreeBlocks;				/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
-	size_t xMinimumEverFreeBytesRemaining;	/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
-	size_t xNumberOfSuccessfulAllocations;	/* The number of calls to pvPortMalloc() that have returned a valid memory block. */
-	size_t xNumberOfSuccessfulFrees;		/* The number of calls to vPortFree() that has successfully freed a block of memory. */
+    size_t xAvailableHeapSpaceInBytes;      /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+    size_t xSizeOfLargestFreeBlockInBytes;  /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xNumberOfFreeBlocks;             /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xMinimumEverFreeBytesRemaining;  /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+    size_t xNumberOfSuccessfulAllocations;  /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+    size_t xNumberOfSuccessfulFrees;        /* The number of calls to vPortFree() that has successfully freed a block of memory. */
 } HeapStats_t;
 
 /*
@@ -155,17 +167,40 @@ void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEG
  * Returns a HeapStats_t structure filled with information about the current
  * heap state.
  */
-void vPortGetHeapStats( HeapStats_t *pxHeapStats );
+void vPortGetHeapStats( HeapStats_t * pxHeapStats );
 
 /*
  * Map to the memory management routines required for the port.
  */
-void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
-void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortCalloc( size_t xNum,
+                     size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
 void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 
+#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
+    void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
+    void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION;
+#else
+    #define pvPortMallocStack    pvPortMalloc
+    #define vPortFreeStack       vPortFree
+#endif
+
+#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+
+/**
+ * task.h
+ * @code{c}
+ * void vApplicationMallocFailedHook( void )
+ * @endcode
+ *
+ * This hook function is called when allocation failed.
+ */
+    void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+#endif
+
 /*
  * Setup the hardware ready for the scheduler to take control.  This generally
  * sets up a tick interrupt and sets timers for the correct tick frequency.
@@ -186,14 +221,18 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
  * Fills the xMPUSettings structure with the memory region information
  * contained in xRegions.
  */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	struct xMEMORY_REGION;
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    struct xMEMORY_REGION;
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
 #endif
 
+/* *INDENT-OFF* */
 #ifdef __cplusplus
-}
+    }
 #endif
+/* *INDENT-ON* */
 
 #endif /* PORTABLE_H */
-

include/projdefs.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PROJDEFS_H
@@ -32,93 +33,90 @@
  * Defines the prototype to which task functions must conform.  Defined in this
  * file to ensure the type is known before portable.h is included.
  */
-typedef void (*TaskFunction_t)( void * );
+typedef void (* TaskFunction_t)( void * );
 
 /* Converts a time in milliseconds to a time in ticks.  This macro can be
-overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
-definition here is not suitable for your application. */
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
 #ifndef pdMS_TO_TICKS
-	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
 #endif
 
-#define pdFALSE			( ( BaseType_t ) 0 )
-#define pdTRUE			( ( BaseType_t ) 1 )
+#define pdFALSE                                  ( ( BaseType_t ) 0 )
+#define pdTRUE                                   ( ( BaseType_t ) 1 )
 
-#define pdPASS			( pdTRUE )
-#define pdFAIL			( pdFALSE )
-#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
-#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+#define pdPASS                                   ( pdTRUE )
+#define pdFAIL                                   ( pdFALSE )
+#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )
+#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )
 
 /* FreeRTOS error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
-#define errQUEUE_BLOCKED						( -4 )
-#define errQUEUE_YIELD							( -5 )
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )
+#define errQUEUE_BLOCKED                         ( -4 )
+#define errQUEUE_YIELD                           ( -5 )
 
 /* Macros used for basic data corruption checks. */
 #ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
-	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0
 #endif
 
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#if ( configUSE_16_BIT_TICKS == 1 )
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a
 #else
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL
 #endif
 
 /* The following errno values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
-#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
-#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
-#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
-#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
-#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
-#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
-#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
-#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
-#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
-#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
-#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
-#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
-#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
-#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
-#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
-#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
-#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
-#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
-#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
-#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
-#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
-#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
-#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
-#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
-#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
-#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
-#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
-#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
-#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
-#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
-#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
-#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
-#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
-#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
-#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
-#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
-#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
-#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
-#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+ * itself. */
+#define pdFREERTOS_ERRNO_NONE             0   /* No errors */
+#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */
+#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */
+#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */
+#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */
+#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */
+#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */
+#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */
+#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */
+#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */
+#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */
+#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */
+#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */
+#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */
+#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */
+#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */
+#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */
+#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */
+#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */
+#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */
+#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */
+#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */
+#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */
+#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */
+#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */
+#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */
+#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */
+#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */
+#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */
+#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */
+#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */
+#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */
+#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */
+#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */
+#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */
+#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */
+#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */
+#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */
+#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */
+#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */
 
 /* The following endian values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_LITTLE_ENDIAN		0
-#define pdFREERTOS_BIG_ENDIAN			1
+ * itself. */
+#define pdFREERTOS_LITTLE_ENDIAN          0
+#define pdFREERTOS_BIG_ENDIAN             1
 
 /* Re-defining endian values for generic naming. */
-#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
-#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
+#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN
 
 
 #endif /* PROJDEFS_H */
-
-
-

include/stack_macros.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef STACK_MACROS_H
@@ -44,86 +45,93 @@
 
 /*-----------------------------------------------------------*/
 
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+/*
+ * portSTACK_LIMIT_PADDING is a number of extra words to consider to be in
+ * use on the stack.
+ */
+#ifndef portSTACK_LIMIT_PADDING
+    #define portSTACK_LIMIT_PADDING    0
+#endif
 
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+        /* Is the currently saved stack pointer within the stack limit? */                            \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )           \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
 
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-																										\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+                                                                                                      \
+        /* Is the currently saved stack pointer within the stack limit? */                            \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )      \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
 
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
-		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
-																										\
-		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
-			( pulStack[ 1 ] != ulCheckValue ) ||														\
-			( pulStack[ 2 ] != ulCheckValue ) ||														\
-			( pulStack[ 3 ] != ulCheckValue ) )															\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \
+                                                                                                      \
+        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
 
-	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
-	{																																	\
-	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
-		}																																\
-	}
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
+    {                                                                                                                                     \
+        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+                                                                                                                                          \
+                                                                                                                                          \
+        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
+                                                                                                                                          \
+        /* Has the extremity of the task stack ever been written over? */                                                                 \
+        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
+        {                                                                                                                                 \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \
+        }                                                                                                                                 \
+    }
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
 /* Remove stack overflow macro if not being used. */
 #ifndef taskCHECK_FOR_STACK_OVERFLOW
-	#define taskCHECK_FOR_STACK_OVERFLOW()
+    #define taskCHECK_FOR_STACK_OVERFLOW()
 #endif
 
 
 
 #endif /* STACK_MACROS_H */
-

include/stdint.readme

@@ -1,3 +1,30 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
 
 #ifndef FREERTOS_STDINT
 #define FREERTOS_STDINT
@@ -10,7 +37,7 @@
  * To use this file:
  *
  *    1) Copy this file into the directory that contains your FreeRTOSConfig.h
- *       header file, as that directory will already be in the compilers include
+ *       header file, as that directory will already be in the compiler's include
  *       path.
  *
  *    2) Rename the copied file stdint.h.
@@ -24,4 +51,8 @@ typedef unsigned short uint16_t;
 typedef long int32_t;
 typedef unsigned long uint32_t;
 
+#ifndef SIZE_MAX
+    #define SIZE_MAX    ( ( size_t ) -1 )
+#endif
+
 #endif /* FREERTOS_STDINT */

include/stream_buffer.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*
@@ -52,12 +53,14 @@
 #define STREAM_BUFFER_H
 
 #ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+    #error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
 #endif
 
+/* *INDENT-OFF* */
 #if defined( __cplusplus )
-extern "C" {
+    extern "C" {
 #endif
+/* *INDENT-ON* */
 
 /**
  * Type by which stream buffers are referenced.  For example, a call to
@@ -68,13 +71,19 @@ extern "C" {
 struct StreamBufferDef_t;
 typedef struct StreamBufferDef_t * StreamBufferHandle_t;
 
+/**
+ *  Type used as a stream buffer's optional callback.
+ */
+typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t xIsInsideISR,
+                                                 BaseType_t * const pxHigherPriorityTaskWoken );
 
 /**
- * message_buffer.h
+ * stream_buffer.h
  *
-<pre>
-StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
-</pre>
+ * @code{c}
+ * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * @endcode
  *
  * Creates a new stream buffer using dynamically allocated memory.  See
  * xStreamBufferCreateStatic() for a version that uses statically allocated
@@ -100,6 +109,16 @@ StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTrigg
  * trigger level of 1 being used.  It is not valid to specify a trigger level
  * that is greater than the buffer size.
  *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
  * @return If NULL is returned, then the stream buffer cannot be created
  * because there is insufficient heap memory available for FreeRTOS to allocate
  * the stream buffer data structures and storage area.  A non-NULL value being
@@ -108,43 +127,50 @@ StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTrigg
  * buffer.
  *
  * Example use:
-<pre>
-
-void vAFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
-
-    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
-    // both the stream buffer structure and the data in the stream buffer is
-    // allocated dynamically.
-    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
-
-    if( xStreamBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // stream buffer.
-    }
-    else
-    {
-        // The stream buffer was created successfully and can now be used.
-    }
-}
-</pre>
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the stream buffer structure and the data in the stream buffer is
+ *  // allocated dynamically.
+ *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream buffer was created successfully and can now be used.
+ *  }
+ * }
+ * @endcode
  * \defgroup xStreamBufferCreate xStreamBufferCreate
  * \ingroup StreamBufferManagement
  */
-#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
 
 /**
  * stream_buffer.h
  *
-<pre>
-StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
-                                                size_t xTriggerLevelBytes,
-                                                uint8_t *pucStreamBufferStorageArea,
-                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
-</pre>
+ * @code{c}
+ * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                              size_t xTriggerLevelBytes,
+ *                                              uint8_t *pucStreamBufferStorageArea,
+ *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * @endcode
  * Creates a new stream buffer using statically allocated memory.  See
  * xStreamBufferCreate() for a version that uses dynamically allocated memory.
  *
@@ -169,63 +195,80 @@ StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
  * that is greater than the buffer size.
  *
  * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * least xBufferSizeBytes big.  This is the array to which streams are
  * copied when they are written to the stream buffer.
  *
  * @param pxStaticStreamBuffer Must point to a variable of type
  * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
  * structure.
  *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least equal to
+ * trigger level is sent to the stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbSEND_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes are read from a
+ * stream buffer. If the parameter is NULL, it will use the default
+ * implementation provided by sbRECEIVE_COMPLETED macro. To enable the callback,
+ * configUSE_SB_COMPLETED_CALLBACK must be set to 1 in FreeRTOSConfig.h.
+ *
  * @return If the stream buffer is created successfully then a handle to the
  * created stream buffer is returned. If either pucStreamBufferStorageArea or
  * pxStaticstreamBuffer are NULL then NULL is returned.
  *
  * Example use:
-<pre>
-
-// Used to dimension the array used to hold the streams.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the streams within the stream
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the stream buffer structure.
-StaticStreamBuffer_t xStreamBufferStruct;
-
-void MyFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xTriggerLevel = 1;
-
-    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
-                                               xTriggerLevel,
-                                               ucBufferStorage,
-                                               &xStreamBufferStruct );
-
-    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
-    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
-    // reference the created stream buffer in other stream buffer API calls.
-
-    // Other code that uses the stream buffer can go here.
-}
-
-</pre>
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                             xTriggerLevel,
+ *                                             ucStorageBuffer,
+ *                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ *  // reference the created stream buffer in other stream buffer API calls.
+ *
+ *  // Other code that uses the stream buffer can go here.
+ * }
+ *
+ * @endcode
  * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
  * \ingroup StreamBufferManagement
  */
-#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
 
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                          const void *pvTxData,
-                          size_t xDataLengthBytes,
-                          TickType_t xTicksToWait );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ *                        const void *pvTxData,
+ *                        size_t xDataLengthBytes,
+ *                        TickType_t xTicksToWait );
+ * @endcode
  *
  * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
  *
@@ -275,54 +318,54 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  * write as many bytes as possible.
  *
  * Example use:
-<pre>
-void vAFunction( StreamBufferHandle_t xStreamBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the stream buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the stream buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xStreamBufferSend() times out before there was enough
-        // space in the buffer for the data to be written, but it did
-        // successfully write xBytesSent bytes.
-    }
-
-    // Send the string to the stream buffer.  Return immediately if there is not
-    // enough space in the buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The entire string could not be added to the stream buffer because
-        // there was not enough free space in the buffer, but xBytesSent bytes
-        // were sent.  Could try again to send the remaining bytes.
-    }
-}
-</pre>
+ * @code{c}
+ * void vAFunction( StreamBufferHandle_t xStreamBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the stream buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xStreamBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written, but it did
+ *      // successfully write xBytesSent bytes.
+ *  }
+ *
+ *  // Send the string to the stream buffer.  Return immediately if there is not
+ *  // enough space in the buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The entire string could not be added to the stream buffer because
+ *      // there was not enough free space in the buffer, but xBytesSent bytes
+ *      // were sent.  Could try again to send the remaining bytes.
+ *  }
+ * }
+ * @endcode
  * \defgroup xStreamBufferSend xStreamBufferSend
  * \ingroup StreamBufferManagement
  */
 size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-						  const void *pvTxData,
-						  size_t xDataLengthBytes,
-						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+                          const void * pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-                                 const void *pvTxData,
-                                 size_t xDataLengthBytes,
-                                 BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                               const void *pvTxData,
+ *                               size_t xDataLengthBytes,
+ *                               BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * Interrupt safe version of the API function that sends a stream of bytes to
  * the stream buffer.
@@ -374,56 +417,56 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  * space for all the bytes to be written.
  *
  * Example use:
-<pre>
-// A stream buffer that has already been created.
-StreamBufferHandle_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the stream buffer.
-    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
-                                           ( void * ) pcStringToSend,
-                                           strlen( pcStringToSend ),
-                                           &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // There was not enough free space in the stream buffer for the entire
-        // string to be written, ut xBytesSent bytes were written.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-</pre>
+ * @code{c}
+ * // A stream buffer that has already been created.
+ * StreamBufferHandle_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the stream buffer.
+ *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ *                                         ( void * ) pcStringToSend,
+ *                                         strlen( pcStringToSend ),
+ *                                         &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // There was not enough free space in the stream buffer for the entire
+ *      // string to be written, ut xBytesSent bytes were written.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
  * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
  * \ingroup StreamBufferManagement
  */
 size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-								 const void *pvTxData,
-								 size_t xDataLengthBytes,
-								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+                                 const void * pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                             void *pvRxData,
-                             size_t xBufferLengthBytes,
-                             TickType_t xTicksToWait );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ *                           void *pvRxData,
+ *                           size_t xBufferLengthBytes,
+ *                           TickType_t xTicksToWait );
+ * @endcode
  *
  * Receives bytes from a stream buffer.
  *
@@ -473,46 +516,46 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
  * out before xBufferLengthBytes were available.
  *
  * Example use:
-<pre>
-void vAFunction( StreamBuffer_t xStreamBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
-    // Wait in the Blocked state (so not using any CPU processing time) for a
-    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
-    // available.
-    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
-                                           ( void * ) ucRxData,
-                                           sizeof( ucRxData ),
-                                           xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains another xRecievedBytes bytes of data, which can
-        // be processed here....
-    }
-}
-</pre>
+ * @code{c}
+ * void vAFunction( StreamBuffer_t xStreamBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ *  // Wait in the Blocked state (so not using any CPU processing time) for a
+ *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ *  // available.
+ *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ *                                         ( void * ) ucRxData,
+ *                                         sizeof( ucRxData ),
+ *                                         xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains another xReceivedBytes bytes of data, which can
+ *      // be processed here....
+ *  }
+ * }
+ * @endcode
  * \defgroup xStreamBufferReceive xStreamBufferReceive
  * \ingroup StreamBufferManagement
  */
 size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-							 void *pvRxData,
-							 size_t xBufferLengthBytes,
-							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+                             void * pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-                                    void *pvRxData,
-                                    size_t xBufferLengthBytes,
-                                    BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                                  void *pvRxData,
+ *                                  size_t xBufferLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * An interrupt safe version of the API function that receives bytes from a
  * stream buffer.
@@ -549,53 +592,53 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
  * @return The number of bytes read from the stream buffer, if any.
  *
  * Example use:
-<pre>
-// A stream buffer that has already been created.
-StreamBuffer_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next stream from the stream buffer.
-    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // ucRxData contains xReceivedBytes read from the stream buffer.
-        // Process the stream here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-</pre>
+ * @code{c}
+ * // A stream buffer that has already been created.
+ * StreamBuffer_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next stream from the stream buffer.
+ *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // ucRxData contains xReceivedBytes read from the stream buffer.
+ *      // Process the stream here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * @endcode
  * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
  * \ingroup StreamBufferManagement
  */
 size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-									void *pvRxData,
-									size_t xBufferLengthBytes,
-									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+                                    void * pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Deletes a stream buffer that was previously created using a call to
  * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
@@ -615,9 +658,9 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTI
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Queries a stream buffer to see if it is full.  A stream buffer is full if it
  * does not have any free space, and therefore cannot accept any more data.
@@ -635,9 +678,9 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
  * it does not contain any data.
@@ -655,9 +698,9 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Resets a stream buffer to its initial, empty, state.  Any data that was in
  * the stream buffer is discarded.  A stream buffer can only be reset if there
@@ -678,9 +721,9 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_F
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Queries a stream buffer to see how much free space it contains, which is
  * equal to the amount of data that can be sent to the stream buffer before it
@@ -699,9 +742,9 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVIL
 /**
  * stream_buffer.h
  *
-<pre>
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
-</pre>
+ * @code{c}
+ * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
  *
  * Queries a stream buffer to see how much data it contains, which is equal to
  * the number of bytes that can be read from the stream buffer before the stream
@@ -720,9 +763,9 @@ size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILE
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+ * @endcode
  *
  * A stream buffer's trigger level is the number of bytes that must be in the
  * stream buffer before a task that is blocked on the stream buffer to
@@ -752,14 +795,15 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, siz
  * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
  * \ingroup StreamBufferManagement
  */
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * For advanced users only.
  *
@@ -791,14 +835,15 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
  * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
  * \ingroup StreamBufferManagement
  */
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
 /**
  * stream_buffer.h
  *
-<pre>
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-</pre>
+ * @code{c}
+ * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * @endcode
  *
  * For advanced users only.
  *
@@ -831,29 +876,38 @@ BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuf
  * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
  * \ingroup StreamBufferManagement
  */
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
 /* Functions below here are not part of the public API. */
 StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-												 size_t xTriggerLevelBytes,
-												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+                                                 size_t xTriggerLevelBytes,
+                                                 BaseType_t xIsMessageBuffer,
+                                                 StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                 StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+
 
 StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-													   size_t xTriggerLevelBytes,
-													   BaseType_t xIsMessageBuffer,
-													   uint8_t * const pucStreamBufferStorageArea,
-													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+                                                       size_t xTriggerLevelBytes,
+                                                       BaseType_t xIsMessageBuffer,
+                                                       uint8_t * const pucStreamBufferStorageArea,
+                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                       StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                       StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 
 size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
-#if( configUSE_TRACE_FACILITY == 1 )
-	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
-	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
+                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 #endif
 
+/* *INDENT-OFF* */
 #if defined( __cplusplus )
-}
+    }
 #endif
+/* *INDENT-ON* */
 
-#endif	/* !defined( STREAM_BUFFER_H ) */
+#endif /* !defined( STREAM_BUFFER_H ) */

list.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,180 +21,206 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 
 #include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
 #include "FreeRTOS.h"
 #include "list.h"
 
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+ * defined for the header files above, but not in this file, in order to
+ * generate the correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
 /*-----------------------------------------------------------
- * PUBLIC LIST API documented in list.h
- *----------------------------------------------------------*/
+* PUBLIC LIST API documented in list.h
+*----------------------------------------------------------*/
 
 void vListInitialise( List_t * const pxList )
 {
-	/* The list structure contains a list item which is used to mark the
-	end of the list.  To initialise the list the list end is inserted
-	as the only list entry. */
-	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    /* The list structure contains a list item which is used to mark the
+     * end of the list.  To initialise the list the list end is inserted
+     * as the only list entry. */
+    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
-	/* The list end value is the highest possible value in the list to
-	ensure it remains at the end of the list. */
-	pxList->xListEnd.xItemValue = portMAX_DELAY;
+    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
 
-	/* The list end next and previous pointers point to itself so we know
-	when the list is empty. */
-	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    /* The list end value is the highest possible value in the list to
+     * ensure it remains at the end of the list. */
+    pxList->xListEnd.xItemValue = portMAX_DELAY;
 
-	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+    /* The list end next and previous pointers point to itself so we know
+     * when the list is empty. */
+    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 
-	/* Write known values into the list if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
-	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+    /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
+    #if ( configUSE_MINI_LIST_ITEM == 0 )
+    {
+        pxList->xListEnd.pvOwner = NULL;
+        pxList->xListEnd.pxContainer = NULL;
+        listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
+    }
+    #endif
+
+    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+    /* Write known values into the list if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
 }
 /*-----------------------------------------------------------*/
 
 void vListInitialiseItem( ListItem_t * const pxItem )
 {
-	/* Make sure the list item is not recorded as being on a list. */
-	pxItem->pxContainer = NULL;
+    /* Make sure the list item is not recorded as being on a list. */
+    pxItem->pxContainer = NULL;
 
-	/* Write known values into the list item if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+    /* Write known values into the list item if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
 }
 /*-----------------------------------------------------------*/
 
-void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem )
 {
-ListItem_t * const pxIndex = pxList->pxIndex;
+    ListItem_t * const pxIndex = pxList->pxIndex;
 
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
 
-	/* Insert a new list item into pxList, but rather than sort the list,
-	makes the new list item the last item to be removed by a call to
-	listGET_OWNER_OF_NEXT_ENTRY(). */
-	pxNewListItem->pxNext = pxIndex;
-	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+    /* Insert a new list item into pxList, but rather than sort the list,
+     * makes the new list item the last item to be removed by a call to
+     * listGET_OWNER_OF_NEXT_ENTRY(). */
+    pxNewListItem->pxNext = pxIndex;
+    pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
 
-	pxIndex->pxPrevious->pxNext = pxNewListItem;
-	pxIndex->pxPrevious = pxNewListItem;
+    pxIndex->pxPrevious->pxNext = pxNewListItem;
+    pxIndex->pxPrevious = pxNewListItem;
 
-	/* Remember which list the item is in. */
-	pxNewListItem->pxContainer = pxList;
+    /* Remember which list the item is in. */
+    pxNewListItem->pxContainer = pxList;
 
-	( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems )++;
 }
 /*-----------------------------------------------------------*/
 
-void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem )
 {
-ListItem_t *pxIterator;
-const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+    ListItem_t * pxIterator;
+    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
 
-	/* Insert the new list item into the list, sorted in xItemValue order.
+    /* Insert the new list item into the list, sorted in xItemValue order.
+     *
+     * If the list already contains a list item with the same item value then the
+     * new list item should be placed after it.  This ensures that TCBs which are
+     * stored in ready lists (all of which have the same xItemValue value) get a
+     * share of the CPU.  However, if the xItemValue is the same as the back marker
+     * the iteration loop below will not end.  Therefore the value is checked
+     * first, and the algorithm slightly modified if necessary. */
+    if( xValueOfInsertion == portMAX_DELAY )
+    {
+        pxIterator = pxList->xListEnd.pxPrevious;
+    }
+    else
+    {
+        /* *** NOTE ***********************************************************
+        *  If you find your application is crashing here then likely causes are
+        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
+        *  more tips, and ensure configASSERT() is defined!
+        *  https://www.FreeRTOS.org/a00110.html#configASSERT
+        *
+        *   1) Stack overflow -
+        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
+        *   2) Incorrect interrupt priority assignment, especially on Cortex-M
+        *      parts where numerically high priority values denote low actual
+        *      interrupt priorities, which can seem counter intuitive.  See
+        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
+        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+        *      https://www.FreeRTOS.org/a00110.html
+        *   3) Calling an API function from within a critical section or when
+        *      the scheduler is suspended, or calling an API function that does
+        *      not end in "FromISR" from an interrupt.
+        *   4) Using a queue or semaphore before it has been initialised or
+        *      before the scheduler has been started (are interrupts firing
+        *      before vTaskStartScheduler() has been called?).
+        *   5) If the FreeRTOS port supports interrupt nesting then ensure that
+        *      the priority of the tick interrupt is at or below
+        *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
+        **********************************************************************/
 
-	If the list already contains a list item with the same item value then the
-	new list item should be placed after it.  This ensures that TCBs which are
-	stored in ready lists (all of which have the same xItemValue value) get a
-	share of the CPU.  However, if the xItemValue is the same as the back marker
-	the iteration loop below will not end.  Therefore the value is checked
-	first, and the algorithm slightly modified if necessary. */
-	if( xValueOfInsertion == portMAX_DELAY )
-	{
-		pxIterator = pxList->xListEnd.pxPrevious;
-	}
-	else
-	{
-		/* *** NOTE ***********************************************************
-		If you find your application is crashing here then likely causes are
-		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
-		more tips, and ensure configASSERT() is defined!
-		https://www.freertos.org/a00110.html#configASSERT
+        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+        {
+            /* There is nothing to do here, just iterating to the wanted
+             * insertion position. */
+        }
+    }
 
-			1) Stack overflow -
-			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
-			2) Incorrect interrupt priority assignment, especially on Cortex-M
-			   parts where numerically high priority values denote low actual
-			   interrupt priorities, which can seem counter intuitive.  See
-			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
-			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-			   https://www.freertos.org/a00110.html
-			3) Calling an API function from within a critical section or when
-			   the scheduler is suspended, or calling an API function that does
-			   not end in "FromISR" from an interrupt.
-			4) Using a queue or semaphore before it has been initialised or
-			   before the scheduler has been started (are interrupts firing
-			   before vTaskStartScheduler() has been called?).
-		**********************************************************************/
+    pxNewListItem->pxNext = pxIterator->pxNext;
+    pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+    pxNewListItem->pxPrevious = pxIterator;
+    pxIterator->pxNext = pxNewListItem;
 
-		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
-		{
-			/* There is nothing to do here, just iterating to the wanted
-			insertion position. */
-		}
-	}
+    /* Remember which list the item is in.  This allows fast removal of the
+     * item later. */
+    pxNewListItem->pxContainer = pxList;
 
-	pxNewListItem->pxNext = pxIterator->pxNext;
-	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
-	pxNewListItem->pxPrevious = pxIterator;
-	pxIterator->pxNext = pxNewListItem;
-
-	/* Remember which list the item is in.  This allows fast removal of the
-	item later. */
-	pxNewListItem->pxContainer = pxList;
-
-	( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems )++;
 }
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
 /* The list item knows which list it is in.  Obtain the list from the list
-item. */
-List_t * const pxList = pxItemToRemove->pxContainer;
+ * item. */
+    List_t * const pxList = pxItemToRemove->pxContainer;
 
-	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
-	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
 
-	/* Make sure the index is left pointing to a valid item. */
-	if( pxList->pxIndex == pxItemToRemove )
-	{
-		pxList->pxIndex = pxItemToRemove->pxPrevious;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
+    /* Make sure the index is left pointing to a valid item. */
+    if( pxList->pxIndex == pxItemToRemove )
+    {
+        pxList->pxIndex = pxItemToRemove->pxPrevious;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
-	pxItemToRemove->pxContainer = NULL;
-	( pxList->uxNumberOfItems )--;
+    pxItemToRemove->pxContainer = NULL;
+    ( pxList->uxNumberOfItems )--;
 
-	return pxList->uxNumberOfItems;
+    return pxList->uxNumberOfItems;
 }
 /*-----------------------------------------------------------*/
-

manifest.yml

@@ -0,0 +1,4 @@
+name : "FreeRTOS-Kernel"
+version: "v10.4.6"
+description: "FreeRTOS Kernel."
+license: "MIT"

portable/ARMv8M/ReadMe.txt

@@ -1,10 +1,11 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+This directory tree contains the master copy of the FreeeRTOS Armv8-M and
+Armv8.1-M ports.
 Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each
 FreeRTOS release.
 
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+If your Armv8-M and Armv8.1-M application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
 
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+If your Armv8-M and Armv8.1-M application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.

portable/ARMv8M/copy_files.py

@@ -1,6 +1,8 @@
 #/*
-# * FreeRTOS Kernel V10.3.1
-# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# * FreeRTOS Kernel V10.5.0
+# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# *
+# * SPDX-License-Identifier: MIT
 # *
 # * Permission is hereby granted, free of charge, to any person obtaining a copy of
 # * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
 # * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 # * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 # *
-# * http://www.FreeRTOS.org
-# * http://aws.amazon.com/freertos
+# * https://www.FreeRTOS.org
+# * https://github.com/FreeRTOS
 # *
-# * 1 tab == 4 spaces!
 # */
 
 import os
@@ -32,51 +33,99 @@ _THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
 _FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
 
 _COMPILERS_ = ['GCC', 'IAR']
-_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
+_ARCH_NS_ = ['ARM_CM85', 'ARM_CM85_NTZ', 'ARM_CM55', 'ARM_CM55_NTZ', 'ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+_ARCH_S_ = ['ARM_CM85', 'ARM_CM55', 'ARM_CM33', 'ARM_CM23']
 
-_SUPPORTED_CONFIGS_ =   {
-                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
-                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-                        }
-
-# Files to be complied in the Secure Project
-_SECURE_FILE_PATHS_ = [
+# Files to be compiled in the Secure Project
+_SECURE_COMMON_FILE_PATHS_ = [
     os.path.join('secure', 'context'),
-    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
     os.path.join('secure', 'heap'),
     os.path.join('secure', 'init'),
     os.path.join('secure', 'macros')
 ]
 
-# Files to be complied in the Non-Secure Project
-_NONSECURE_FILE_PATHS_ = [
-    'non_secure',
-    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
+_SECURE_PORTABLE_FILE_PATHS_ = {
+    'GCC':{
+        'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM23')],
+        'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
+        'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')],
+        'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'GCC', 'ARM_CM33')]
+    },
+    'IAR':{
+        'ARM_CM23':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM23')],
+        'ARM_CM33':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
+        'ARM_CM55':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')],
+        'ARM_CM85':[os.path.join('secure', 'context', 'portable', 'IAR', 'ARM_CM33')]
+    }
+}
+
+# Files to be compiled in the Non-Secure Project
+_NONSECURE_COMMON_FILE_PATHS_ = [
+    'non_secure'
 ]
 
-
-def is_supported_config(compiler, arch):
-    return arch in _SUPPORTED_CONFIGS_[compiler]
+_NONSECURE_PORTABLE_FILE_PATHS_ = {
+    'GCC':{
+        'ARM_CM23'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23')],
+        'ARM_CM23_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM23_NTZ')],
+        'ARM_CM33'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33')],
+        'ARM_CM33_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ')],
+        'ARM_CM55'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
+                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],
+        'ARM_CM55_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
+                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM55', 'portmacro.h')],
+        'ARM_CM85'      : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33', 'portasm.c'),
+                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')],
+        'ARM_CM85_NTZ'  : [os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM33_NTZ', 'portasm.c'),
+                           os.path.join('non_secure', 'portable', 'GCC', 'ARM_CM85', 'portmacro.h')]
+    },
+    'IAR':{
+        'ARM_CM23'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23')],
+        'ARM_CM23_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM23_NTZ')],
+        'ARM_CM33'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33')],
+        'ARM_CM33_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ')],
+        'ARM_CM55'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
+                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],
+        'ARM_CM55_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
+                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM55', 'portmacro.h')],
+        'ARM_CM85'      : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33', 'portasm.s'),
+                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')],
+        'ARM_CM85_NTZ'  : [os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM33_NTZ', 'portasm.s'),
+                           os.path.join('non_secure', 'portable', 'IAR', 'ARM_CM85', 'portmacro.h')]
+    },
+}
 
 
 def copy_files_in_dir(src_abs_path, dst_abs_path):
-    for src_file in os.listdir(src_abs_path):
-        src_file_abs_path = os.path.join(src_abs_path, src_file)
-        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
-            if not os.path.exists(dst_abs_path):
-                os.makedirs(dst_abs_path)
-            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
-            shutil.copy2(src_file_abs_path, dst_abs_path)
+    if os.path.isfile(src_abs_path):
+        print('Src: {}'.format(src_abs_path))
+        print('Dst: {}\n'.format(dst_abs_path))
+        shutil.copy2(src_abs_path, dst_abs_path)
+    else:
+        for src_file in os.listdir(src_abs_path):
+            src_file_abs_path = os.path.join(src_abs_path, src_file)
+            if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
+                if not os.path.exists(dst_abs_path):
+                    os.makedirs(dst_abs_path)
+                print('Src: {}'.format(src_file_abs_path))
+                print('Dst: {}\n'.format(dst_abs_path))
+                shutil.copy2(src_file_abs_path, dst_abs_path)
 
 
-def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
-    _COMPILER_ARCH_ = os.path.join(compiler, arch)
+def copy_common_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
     for src_path in src_paths:
-        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
 
-        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
-        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
+        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path)
+        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path)
+
+        copy_files_in_dir(src_abs_path, dst_abs_path)
+
+
+def copy_portable_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
+    for src_path in src_paths[compiler][arch]:
+
+        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path)
+        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, compiler, arch, dst_path)
 
         copy_files_in_dir(src_abs_path, dst_abs_path)
 
@@ -85,14 +134,14 @@ def copy_files():
     # Copy Secure Files
     for compiler in _COMPILERS_:
         for arch in _ARCH_S_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
+            copy_common_files_for_compiler_and_arch(compiler, arch, _SECURE_COMMON_FILE_PATHS_, 'secure')
+            copy_portable_files_for_compiler_and_arch(compiler, arch, _SECURE_PORTABLE_FILE_PATHS_, 'secure')
 
     # Copy Non-Secure Files
     for compiler in _COMPILERS_:
         for arch in _ARCH_NS_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
+            copy_common_files_for_compiler_and_arch(compiler, arch, _NONSECURE_COMMON_FILE_PATHS_, 'non_secure')
+            copy_portable_files_for_compiler_and_arch(compiler, arch, _NONSECURE_PORTABLE_FILE_PATHS_, 'non_secure')
 
 
 def main():

portable/ARMv8M/non_secure/ReadMe.txt

@@ -1,11 +1,11 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+This directory tree contains the master copy of the FreeRTOS Armv8-M and
+Armv8.1-M ports.
 Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
+each FreeRTOS release.
 
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
 
+If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -39,415 +40,439 @@
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
 #endif
 
 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1									\n"/* r5 = 1. */
+            "	bics r4, r5									\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]								\n"/* Disable MPU. */
+            "												\n"
+            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]								\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2						\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]								\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2							\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	movs r5, #4									\n"/* r5 = 4. */
+            "	str  r5, [r2]								\n"/* Program RNR = 4. */
+            "	ldmia r3!, {r6,r7}							\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2						\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}							\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5									\n"/* r5 = 5. */
+            "	str  r5, [r2]								\n"/* Program RNR = 5. */
+            "	ldmia r3!, {r6,r7}							\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2						\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}							\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6									\n"/* r5 = 6. */
+            "	str  r5, [r2]								\n"/* Program RNR = 6. */
+            "	ldmia r3!, {r6,r7}							\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2						\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}							\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7									\n"/* r5 = 7. */
+            "	str  r5, [r2]								\n"/* Program RNR = 7. */
+            "	ldmia r3!, {r6,r7}							\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2						\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}							\n"/* Write fourth set of RBAR/RLAR registers. */
+            "												\n"
+            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1									\n"/* r5 = 1. */
+            "	orrs r4, r5									\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]								\n"/* Enable MPU. */
+            "	dsb											\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2				\n"
+            "	str  r1, [r5]								\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3							\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32								\n"/* Discard everything up to r0. */
+            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
+            "	isb											\n"
+            "	bx   r4										\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2				\n"
+            "	str  r1, [r4]								\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2									\n"/* r1 = 2. */
+            "	msr  CONTROL, r1							\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32								\n"/* Discard everything up to r0. */
+            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
+            "	isb											\n"
+            "	bx   r3										\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94				\n"
+            "xMAIR0Const2: .word 0xe000edc0					\n"
+            "xRNRConst2: .word 0xe000ed98					\n"
+            "xRBARConst2: .word 0xe000ed9c					\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	adds r1, r1, #16								\n" /* Move to the high registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	ldr r3, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r3]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+        "	mrs r2, psp										\n"/* Read PSP in r2. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r1, r3, #25								\n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r2, r2, #16							\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mrs r3, control								\n"/* r3 = CONTROL. */
+            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r2, r2, #12							\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r2, r2, #48							\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	adds r2, r2, #16							\n"/* r2 = r2 + 16. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the low registers that are not saved automatically. */
+            "	mov r4, r8									\n"/* r4 = r8. */
+            "	mov r5, r9									\n"/* r5 = r9. */
+            "	mov r6, r10									\n"/* r6 = r10. */
+            "	mov r7, r11									\n"/* r7 = r11. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the high registers that are not saved automatically. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mrs r3, control								\n"/* r3 = CONTROL. */
+            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r2, r2, #48							\n"/* r2 = r2 - 48. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r2, r2, #44							\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r2!, {r0, r1, r3-r7}					\n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "	mov r4, r8									\n"/* r4 = r8. */
+            "	mov r5, r9									\n"/* r5 = r9. */
+            "	mov r6, r10									\n"/* r6 = r10. */
+            "	mov r7, r11									\n"/* r7 = r11. */
+            "	stmia r2!, {r4-r7}							\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r2, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1									\n"/* r5 = 1. */
+            "	bics r4, r5									\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r3]								\n"/* Disable MPU. */
+            "												\n"
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr r4, [r1]								\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr r3, xMAIR0Const							\n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r3]								\n"/* Program MAIR0. */
+            "	ldr r4, xRNRConst							\n"/* r4 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r5, #4									\n"/* r5 = 4. */
+            "	str  r5, [r4]								\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r6,r7}							\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5									\n"/* r5 = 5. */
+            "	str  r5, [r4]								\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r6,r7}							\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6									\n"/* r5 = 6. */
+            "	str  r5, [r4]								\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r6,r7}							\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7									\n"/* r5 = 7. */
+            "	str  r5, [r4]								\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r6,r7}							\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r6,r7}							\n"/* Write fourth set of RBAR/RLAR registers. */
+            "												\n"
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1									\n"/* r5 = 1. */
+            "	orrs r4, r5									\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r3]								\n"/* Enable MPU. */
+            "	dsb											\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r2!, {r0, r1, r3, r4}					\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3								\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
+             "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
+            "	push {r2, r4}								\n"
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "	pop {r2, r4}								\n"
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
+            "	bx lr										\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r2!, {r0, r1, r4}						\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
+            "	push {r2, r4}								\n"
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "	pop {r2, r4}								\n"
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
+            "	bx lr										\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	adds r2, r2, #16								\n"/* Move to the high registers. */
+        "	ldmia r2!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+        "	mov r8, r4										\n"/* r8 = r4. */
+        "	mov r9, r5										\n"/* r9 = r5. */
+        "	mov r10, r6										\n"/* r10 = r6. */
+        "	mov r11, r7										\n"/* r11 = r7. */
+        "	msr psp, r2										\n"/* Remember the new top of stack for the task. */
+        "	subs r2, r2, #32								\n"/* Go back to the low registers. */
+        "	ldmia r2!, {r4-r7}								\n"/* Restore the low registers that are not automatically restored. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94				\n"
+            "xMAIR0Const: .word 0xe000edc0					\n"
+            "xRNRConst: .word 0xe000ed98					\n"
+            "xRBARConst: .word 0xe000ed9c					\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	beq free_secure_context							\n"
-	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
-	" free_secure_context:								\n"
-	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r2, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r1, [r2]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r1, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	bne free_secure_context							\n"/* Branch if r1 != 0. */
+        "	bx lr											\n"/* There is no secure context (xSecureContext is NULL). */
+        " free_secure_context:								\n"
+        "	svc %0											\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,260 +45,27 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M23"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()             __asm volatile ( " cpsie i " ::: "memory" )
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -39,328 +40,342 @@
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
 #endif
 
 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#else /* configENABLE_MPU */
-	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	adds r0, r0, #28								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	"	bx r3											\n"
-	#else /* configENABLE_MPU */
-	"	adds r0, r0, #24								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	bx r3											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r0, r0, #44								\n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r1-r7}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #else /* configENABLE_MPU */
+            "	subs r0, r0, #40								\n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r2-r7}								\n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	adds r0, r0, #28								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #44								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r1-r7}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+            "	bx r3											\n"
+        #else /* configENABLE_MPU */
+            "	adds r0, r0, #24								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #40								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r2-r7}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	bx r3											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,260 +45,27 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M23"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()             __asm volatile ( " cpsie i " ::: "memory" )
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -41,370 +42,429 @@
 
 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1									\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]								\n"/* Disable MPU. */
+            "												\n"
+            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]								\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2						\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]								\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2							\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4									\n"/* r4 = 4. */
+            "	str  r4, [r2]								\n"/* Program RNR = 4. */
+            "	adds r3, #4									\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2						\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}							\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "												\n"
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "	ldr  r2, xRNRConst2							\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #8									\n"/* r4 = 8. */
+            "	str  r4, [r2]								\n"/* Program RNR = 8. */
+            "	ldr  r2, xRBARConst2						\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}							\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "	ldr  r2, xRNRConst2							\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #12								\n"/* r4 = 12. */
+            "	str  r4, [r2]								\n"/* Program RNR = 12. */
+            "	ldr  r2, xRBARConst2						\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}							\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "												\n"
+            "	ldr r2, xMPUCTRLConst2						\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]								\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1									\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]								\n"/* Enable MPU. */
+            "	dsb											\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2				\n"
+            "	str  r1, [r5]								\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3							\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32								\n"/* Discard everything up to r0. */
+            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
+            "	isb											\n"
+            "	mov  r0, #0									\n"
+            "	msr  basepri, r0							\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r4										\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}							\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2				\n"
+            "	str  r1, [r4]								\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2								\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2									\n"/* r1 = 2. */
+            "	msr  CONTROL, r1							\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32								\n"/* Discard everything up to r0. */
+            "	msr  psp, r0								\n"/* This is now the new top of stack to use in the task. */
+            "	isb											\n"
+            "	mov  r0, #0									\n"
+            "	msr  basepri, r0							\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3										\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94				\n"
+            "xMAIR0Const2: .word 0xe000edc0					\n"
+            "xRNRConst2: .word 0xe000ed98					\n"
+            "xRBARConst2: .word 0xe000ed9c					\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	mrs r0, basepri									\n" /* r0 = basepri. Return original basepri value. */
-	"	mov r1, %0										\n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	msr basepri, r1									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	:: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	msr basepri, r0									\n" /* basepri = ulMask. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	mov r0, %0										\n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-	"	msr basepri, r0									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bl vTaskSwitchContext							\n"
-	"	mov r0, #0										\n" /* r0 = 0. */
-	"	msr basepri, r0									\n" /* Enable interrupts. */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	:: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	ldr r3, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r3]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+        "	mrs r2, psp										\n"/* Read PSP in r2. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r1, r3, #25								\n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "													\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB.*/
+        #if ( configENABLE_MPU == 1 )
+            "	subs r2, r2, #16							\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mrs r3, control								\n"/* r3 = CONTROL. */
+            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r2, r2, #12							\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "	it eq										\n"
+            "	vstmdbeq r2!, {s16-s31}						\n"/* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r2, r2, #48							\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	adds r2, r2, #16							\n"/* r2 = r2 + 16. */
+            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mrs r3, control								\n"/* r3 = CONTROL. */
+            "	mov r4, lr									\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r2, r2, #16							\n"/* r2 = r2 - 16. */
+            "	stmia r2!, {r0, r1, r3, r4}					\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r2, r2, #44							\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r2, [r1]								\n"/* Save the new top of stack in TCB. */
+            "	adds r2, r2, #12							\n"/* r2 = r2 + 12. */
+            "	stm r2, {r4-r11}							\n"/* Store the registers that are not saved automatically. */
+            "	mrs r1, psplim								\n"/* r1 = PSPLIM. */
+            "	mov r3, lr									\n"/* r3 = LR/EXC_RETURN. */
+            "	subs r2, r2, #12							\n"/* r2 = r2 - 12. */
+            "	stmia r2!, {r0, r1, r3}						\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r3]									\n"/* Read pxCurrentTCB. */
+        "	ldr r2, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb											\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1									\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r3]								\n"/* Disable MPU. */
+            "												\n"
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr r4, [r1]								\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr r3, xMAIR0Const							\n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r3]								\n"/* Program MAIR0. */
+            "	ldr r3, xRNRConst							\n"/* r3 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4									\n"/* r4 = 4. */
+            "	str r4, [r3]								\n"/* Program RNR = 4. */
+            "	adds r1, #4									\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}							\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r3!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "												\n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+            "	ldr r3, xRNRConst							\n"/* r3 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #8									\n"/* r4 = 8. */
+            "	str r4, [r3]								\n"/* Program RNR = 8. */
+            "	ldr r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}							\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r3!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "	ldr r3, xRNRConst							\n"/* r3 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #12								\n"/* r4 = 12. */
+            "	str r4, [r3]								\n"/* Program RNR = 12. */
+            "	ldr r3, xRBARConst							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}							\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r3!, {r4-r11}							\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "												\n"
+            "	ldr r3, xMPUCTRLConst						\n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r3]								\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1									\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r3]								\n"/* Enable MPU. */
+            "	dsb											\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r2!, {r0, r1, r3, r4}					\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3								\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
+            "	push {r2, r4}								\n"
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "	pop {r2, r4}								\n"
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
+            "	bx lr										\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r2!, {r0, r1, r4}						\n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "	msr psplim, r1								\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	ldr r3, xSecureContextConst					\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r3]								\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context					\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	ldr r3, pxCurrentTCBConst					\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "	ldr r1, [r3]								\n"/* Read pxCurrentTCB. */
+            "	push {r2, r4}								\n"
+            "	bl SecureContext_LoadContext				\n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "	pop {r2, r4}								\n"
+            "	mov lr, r4									\n"/* LR = r4. */
+            "	lsls r1, r4, #25							\n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context						\n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r2									\n"/* Remember the new top of stack for the task. */
+            "	bx lr										\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	ldmia r2!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "	tst lr, #0x10								\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "	it eq										\n"
+            "	vldmiaeq r2!, {s16-s31}						\n"/* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+        "	msr psp, r2										\n"/* Remember the new top of stack for the task. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94				\n"
+            "xMAIR0Const: .word 0xe000edc0					\n"
+            "xRNRConst: .word 0xe000ed98					\n"
+            "xRBARConst: .word 0xe000ed9c					\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
 }
 /*-----------------------------------------------------------*/
 
 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r2, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r1, [r2]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r1, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	it ne											\n"
+        "	svcne %0										\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,260 +45,22 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+#define portARCH_NAME                       "Cortex-M33"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -41,276 +42,324 @@
 
 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str  r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #8										\n"/* r3 = 8. */
+            "	str  r3, [r2]									\n"/* Program RNR = 8. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #12									\n"/* r3 = 12. */
+            "	str  r3, [r2]									\n"/* Program RNR = 12. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
 }
 /*-----------------------------------------------------------*/
 
 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 {
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	mrs r0, basepri									\n" /* r0 = basepri. Return original basepri value. */
-	"	mov r1, %0										\n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	msr basepri, r1									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	:: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	msr basepri, r0									\n" /* basepri = ulMask. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bx lr											\n" /* Return. */
-	::: "memory"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 
 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	mov r0, %0										\n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-	"	msr basepri, r0									\n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	bl vTaskSwitchContext							\n"
-	"	mov r0, #0										\n" /* r0 = 0. */
-	"	msr basepri, r0									\n" /* Enable interrupts. */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	:: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "	it eq											\n"
+            "	vstmdbeq r0!, {s16-s31}							\n"/* Store the additional FP context registers which are not saved automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r1-r11}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+        #else /* configENABLE_MPU */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r2-r11}								\n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+        "													\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            #if ( configTOTAL_MPU_REGIONS == 16 )
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #8										\n"/* r3 = 8. */
+            "	str r3, [r2]									\n"/* Program RNR = 8. */
+            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #12									\n"/* r3 = 12. */
+            "	str r3, [r2]									\n"/* Program RNR = 12. */
+            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r0!, {r1-r11}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+        #else /* configENABLE_MPU */
+            "	ldmia r0!, {r2-r11}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "	tst r3, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "	it eq											\n"
+            "	vldmiaeq r0!, {s16-s31}							\n"/* Restore the additional FP context registers which are not restored automatically. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+        #else /* configENABLE_MPU */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+        #endif /* configENABLE_MPU */
+        "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+        "	bx r3											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
 }
 /*-----------------------------------------------------------*/
 
 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 {
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,260 +45,22 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
+#define portARCH_NAME                       "Cortex-M33"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h

@@ -0,0 +1,71 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                       "Cortex-M55"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h

@@ -0,0 +1,71 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                       "Cortex-M85"
+#define portDONT_DISCARD                    __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,12 +21,18 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
 	EXTERN pxCurrentTCB
 	EXTERN xSecureContext
 	EXTERN vTaskSwitchContext
@@ -193,64 +201,66 @@ vClearInterruptMask:
 /*-----------------------------------------------------------*/
 
 PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r3]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r3]							/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+	mrs r2, psp								/* Read PSP in r2. */
 
 	cbz r0, save_ns_context					/* No secure context to save. */
 	push {r0-r2, r14}
-	bl SecureContext_SaveContext
+	bl SecureContext_SaveContext			/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 	pop {r0-r3}								/* LR is now in r3. */
 	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	lsls r1, r3, #25						/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
+	ldr r1, [r3]							/* Read pxCurrentTCB. */
 #if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	subs r2, r2, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mrs r3, control							/* r3 = CONTROL. */
 	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	stmia r2!, {r0, r1, r3, r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 #else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	subs r2, r2, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+	stmia r2!, {r0, r1, r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
 #endif /* configENABLE_MPU */
 	b select_next_task
 
 	save_ns_context:
 		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
 	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		subs r2, r2, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
+		adds r2, r2, #16					/* r2 = r2 + 16. */
+		stmia r2!, {r4-r7}					/* Store the low registers that are not saved automatically. */
 		mov r4, r8							/* r4 = r8. */
 		mov r5, r9							/* r5 = r9. */
 		mov r6, r10							/* r6 = r10. */
 		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		stmia r2!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mrs r3, control						/* r3 = CONTROL. */
 		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #48					/* r1 = r1 - 48. */
-		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+		subs r2, r2, #48					/* r2 = r2 - 48. */
+		stmia r2!, {r0, r1, r3, r4}			/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		subs r2, r2, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		stmia r2!, {r0, r1, r3-r7}			/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
 		mov r4, r8							/* r4 = r8. */
 		mov r5, r9							/* r5 = r9. */
 		mov r6, r10							/* r6 = r10. */
 		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		stmia r2!, {r4-r7}					/* Store the high registers that are not saved automatically. */
 	#endif /* configENABLE_MPU */
 
 	select_next_task:
@@ -258,96 +268,100 @@ PendSV_Handler:
 		bl vTaskSwitchContext
 		cpsie i
 
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		ldr r2, [r1]						/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
 	#if ( configENABLE_MPU == 1 )
 		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		movs r5, #1							/* r5 = 1. */
 		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
+		str r4, [r3]						/* Disable MPU. */
 
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+		ldr r4, [r1]						/* r4 = *r1 i.e. r4 = MAIR0. */
+		ldr r3, =0xe000edc0					/* r3 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r3]						/* Program MAIR0. */
+		ldr r4, =0xe000ed98					/* r4 = 0xe000ed98 [Location of RNR]. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
 		movs r5, #4							/* r5 = 4. */
-		str  r5, [r2]						/* Program RNR = 4. */
-		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		str  r5, [r4]						/* Program RNR = 4. */
+		ldmia r1!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
+		stmia r3!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
 		movs r5, #5							/* r5 = 5. */
-		str  r5, [r2]						/* Program RNR = 5. */
-		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		str  r5, [r4]						/* Program RNR = 5. */
+		ldmia r1!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
+		stmia r3!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
 		movs r5, #6							/* r5 = 6. */
-		str  r5, [r2]						/* Program RNR = 6. */
-		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		str  r5, [r4]						/* Program RNR = 6. */
+		ldmia r1!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
+		stmia r3!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
 		movs r5, #7							/* r5 = 7. */
-		str  r5, [r2]						/* Program RNR = 7. */
-		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+		str  r5, [r4]						/* Program RNR = 7. */
+		ldmia r1!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
+		stmia r3!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
 
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		movs r5, #1							/* r5 = 1. */
 		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
+		str r4, [r3]						/* Enable MPU. */
 		dsb									/* Force memory writes before continuing. */
 	#endif /* configENABLE_MPU */
 
 	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		ldmia r2!, {r0, r1, r3, r4}			/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
 		msr control, r3						/* Restore the CONTROL register value for the task. */
 		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		push {r2, r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+		pop {r2, r4}
 		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		ldmia r2!, {r0, r1, r4}				/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		push {r2, r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+		pop {r2, r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#endif /* configENABLE_MPU */
 
 	restore_ns_context:
-		adds r1, r1, #16					/* Move to the high registers. */
-		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		adds r2, r2, #16					/* Move to the high registers. */
+		ldmia r2!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
 		mov r8, r4							/* r8 = r4. */
 		mov r9, r5							/* r9 = r5. */
 		mov r10, r6							/* r10 = r6. */
 		mov r11, r7							/* r11 = r7. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		subs r1, r1, #32					/* Go back to the low registers. */
-		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
+		subs r2, r2, #32					/* Go back to the low registers. */
+		ldmia r2!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
 		bx lr
 /*-----------------------------------------------------------*/
 
@@ -364,10 +378,10 @@ SVC_Handler:
 /*-----------------------------------------------------------*/
 
 vPortFreeSecureContext:
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	beq free_secure_context
+	ldr r2, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r1, [r2]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r1, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	bne free_secure_context					/* Branch if r1 != 0. */
 	bx lr									/* There is no secure context (xSecureContext is NULL). */
 	free_secure_context:
 		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,256 +45,23 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M23"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()             __asm volatile ( " cpsie i " ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
@@ -302,7 +72,7 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,11 +21,16 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
 
 	EXTERN pxCurrentTCB
 	EXTERN vTaskSwitchContext

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,256 +45,23 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M23"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()             __asm volatile ( " cpsie i " ::: "memory" )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
@@ -302,7 +72,7 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
@@ -128,6 +129,8 @@ vRestoreContextOfFirstTask:
 	adds r0, #32							/* Discard everything up to r0. */
 	msr  psp, r0							/* This is now the new top of stack to use in the task. */
 	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
 	bx   r4									/* Finally, branch to EXC_RETURN. */
 #else /* configENABLE_MPU */
 	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
@@ -139,6 +142,8 @@ vRestoreContextOfFirstTask:
 	adds r0, #32							/* Discard everything up to r0. */
 	msr  psp, r0							/* This is now the new top of stack to use in the task. */
 	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
 	bx   r3									/* Finally, branch to EXC_RETURN. */
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -179,62 +184,65 @@ vClearInterruptMask:
 /*-----------------------------------------------------------*/
 
 PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r3]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r3]							/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+	mrs r2, psp								/* Read PSP in r2. */
 
 	cbz r0, save_ns_context					/* No secure context to save. */
 	push {r0-r2, r14}
-	bl SecureContext_SaveContext
+	bl SecureContext_SaveContext			/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 	pop {r0-r3}								/* LR is now in r3. */
 	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	lsls r1, r3, #25						/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+
 	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
+	ldr r1, [r3]							/* Read pxCurrentTCB. */
 #if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	subs r2, r2, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mrs r3, control							/* r3 = CONTROL. */
 	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	stmia r2!, {r0, r1, r3, r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 #else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
+	subs r2, r2, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r2, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
 	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+	stmia r2!, {r0, r1, r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
 #endif /* configENABLE_MPU */
 	b select_next_task
 
 	save_ns_context:
 		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+	#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
+		vstmdbeq r2!, {s16-s31}				/* Store the additional FP context registers which are not saved automatically. */
+	#endif /* configENABLE_FPU || configENABLE_MVE */
 	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		subs r2, r2, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
+		adds r2, r2, #16					/* r2 = r2 + 16. */
+		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mrs r3, control						/* r3 = CONTROL. */
 		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+		subs r2, r2, #16					/* r2 = r2 - 16. */
+		stmia r2!, {r0, r1, r3, r4}			/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
 	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
+		subs r2, r2, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r2, [r1]						/* Save the new top of stack in TCB. */
+		adds r2, r2, #12					/* r2 = r2 + 12. */
+		stm r2, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r1, psplim						/* r1 = PSPLIM. */
 		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+		subs r2, r2, #12					/* r2 = r2 - 12. */
+		stmia r2!, {r0, r1, r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
 	#endif /* configENABLE_MPU */
 
 	select_next_task:
@@ -246,77 +254,81 @@ PendSV_Handler:
 		mov r0, #0							/* r0 = 0. */
 		msr basepri, r0						/* Enable interrupts. */
 
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		ldr r2, [r1]						/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
 	#if ( configENABLE_MPU == 1 )
 		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
+		str r4, [r3]						/* Disable MPU. */
 
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+		ldr r4, [r1]						/* r4 = *r1 i.e. r4 = MAIR0. */
+		ldr r3, =0xe000edc0					/* r3 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r3]						/* Program MAIR0. */
+		ldr r3, =0xe000ed98					/* r3 = 0xe000ed98 [Location of RNR]. */
 		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+		str r4, [r3]						/* Program RNR = 4. */
+		adds r1, #4							/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+		ldr  r3, =0xe000ed9c				/* r3 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r1!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r3!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
 
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		ldr r3, =0xe000ed94					/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r3]						/* Read the value of MPU_CTRL. */
 		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
+		str r4, [r3]						/* Enable MPU. */
 		dsb									/* Force memory writes before continuing. */
 	#endif /* configENABLE_MPU */
 
 	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		ldmia r2!, {r0, r1, r3, r4}			/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
 		msr control, r3						/* Restore the CONTROL register value for the task. */
 		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		push {r2, r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+		pop {r2, r4}
 		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
+		ldmia r2!, {r0, r1, r4}				/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+		msr psplim, r1						/* Restore the PSPLIM register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r3, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r3]						/* Restore the task's xSecureContext. */
 		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r1, [r3]						/* Read pxCurrentTCB. */
+		push {r2, r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+		pop {r2, r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r1, r4, #25					/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 	#endif /* configENABLE_MPU */
 
 	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		ldmia r2!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
+		vldmiaeq r2!, {s16-s31}				/* Restore the additional FP context registers which are not restored automatically. */
+	#endif /* configENABLE_FPU || configENABLE_MVE */
+		msr psp, r2							/* Remember the new top of stack for the task. */
 		bx lr
 /*-----------------------------------------------------------*/
 
@@ -330,9 +342,9 @@ SVC_Handler:
 
 vPortFreeSecureContext:
 	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	ldr r2, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r1, [r2]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r1, #0								/* Raise svc if task's xSecureContext is not NULL. */
 	it ne
 	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
 	bx lr									/* Return. */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,256 +45,23 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M33"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
@@ -302,7 +72,7 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 /* Including FreeRTOSConfig.h here will cause build errors if the header file
 contains code not understood by the assembler - for example the 'extern' keyword.
@@ -116,6 +117,8 @@ vRestoreContextOfFirstTask:
 	adds r0, #32							/* Discard everything up to r0. */
 	msr  psp, r0							/* This is now the new top of stack to use in the task. */
 	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
 	bx   r3									/* Finally, branch to EXC_RETURN. */
 #else /* configENABLE_MPU */
 	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
@@ -125,6 +128,8 @@ vRestoreContextOfFirstTask:
 	adds r0, #32							/* Discard everything up to r0. */
 	msr  psp, r0							/* This is now the new top of stack to use in the task. */
 	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
 	bx   r2									/* Finally, branch to EXC_RETURN. */
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -166,11 +171,11 @@ vClearInterruptMask:
 
 PendSV_Handler:
 	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
+	vstmdbeq r0!, {s16-s31}					/* Store the additional FP context registers which are not saved automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
 #if ( configENABLE_MPU == 1 )
 	mrs r1, psplim							/* r1 = PSPLIM. */
 	mrs r2, control							/* r2 = CONTROL. */
@@ -230,11 +235,11 @@ PendSV_Handler:
 	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 #endif /* configENABLE_MPU */
 
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
 	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
+	vldmiaeq r0!, {s16-s31}					/* Restore the additional FP context registers which are not restored automatically. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
 
  #if ( configENABLE_MPU == 1 )
 	msr psplim, r1							/* Restore the PSPLIM register value for the task. */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,20 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H
 #define PORTMACRO_H
 
 #ifdef __cplusplus
-extern "C" {
+    extern "C" {
 #endif
 
+#include "portmacrocommon.h"
+
 /*------------------------------------------------------------------------------
  * Port specific definitions.
  *
@@ -42,256 +45,23 @@ extern "C" {
  *------------------------------------------------------------------------------
  */
 
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
+#define portARCH_NAME                       "Cortex-M33"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
 #endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern BaseType_t xPortIsInsideInterrupt( void );
-
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMask( x )
-#define portDISABLE_INTERRUPTS()							ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()								vClearInterruptMask( 0 )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
@@ -302,7 +72,7 @@ typedef struct MPU_SETTINGS
 /*-----------------------------------------------------------*/
 
 #ifdef __cplusplus
-}
+    }
 #endif
 
 #endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h

@@ -0,0 +1,83 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                       "Cortex-M55"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h

@@ -0,0 +1,83 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#include "portmacrocommon.h"
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_MVE
+    #error configENABLE_MVE must be defined in FreeRTOSConfig.h. Set configENABLE_MVE to 1 to enable the MVE or 0 to disable the MVE.
+#endif /* configENABLE_MVE */
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portARCH_NAME                       "Cortex-M85"
+#define portDONT_DISCARD                    __root
+/*-----------------------------------------------------------*/
+
+#if( configTOTAL_MPU_REGIONS == 16 )
+    #error 16 MPU regions are not yet supported for this port.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Be006
+#pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif /* PORTMACRO_H */

portable/ARMv8M/non_secure/portasm.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef __PORT_ASM_H__
@@ -38,14 +39,14 @@
  * @brief Restore the context of the first task so that the first task starts
  * executing.
  */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief Checks whether or not the processor is privileged.
  *
  * @return 1 if the processor is already privileged, 0 otherwise.
  */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
 
 /**
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
@@ -58,7 +59,7 @@ BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
  *  Bit[0] = 0 --> The processor is running privileged
  *  Bit[0] = 1 --> The processor is running unprivileged.
  */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
@@ -68,32 +69,32 @@ void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
  *  Bit[0] = 0 --> The processor is running privileged
  *  Bit[0] = 1 --> The processor is running unprivileged.
  */
-void vResetPrivilege( void ) __attribute__ (( naked ));
+void vResetPrivilege( void ) __attribute__( ( naked ) );
 
 /**
  * @brief Starts the first task.
  */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief Disables interrupts.
  */
-uint32_t ulSetInterruptMask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief Enables interrupts.
  */
-void vClearInterruptMask( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief PendSV Exception handler.
  */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief SVC Handler.
  */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 /**
  * @brief Allocate a Secure context for the calling task.
@@ -101,13 +102,13 @@ void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
  * @param[in] ulSecureStackSize The size of the stack to be allocated on the
  * secure side for the calling task.
  */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
 
 /**
  * @brief Free the task's secure context.
  *
  * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
  */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
 
 #endif /* __PORT_ASM_H__ */

portable/ARMv8M/non_secure/portmacrocommon.h

@@ -0,0 +1,311 @@
+/*
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACROCOMMON_H
+    #define PORTMACROCOMMON_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS       ( 8UL )
+#endif
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( configTOTAL_MPU_REGIONS - 1UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } while( 0 )
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACROCOMMON_H */

portable/ARMv8M/secure/ReadMe.txt

@@ -1,10 +1,11 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+This directory tree contains the master copy of the FreeRTOS Armv8-M and
+Armv8.1-M ports.
 Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to
+each FreeRTOS release.
 
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+If your Armv8-M/Armv8.1-M application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85] directories.
 
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+If your Armv8-M/Armv8.1-M application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NTZ directories.

portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Secure context includes. */
@@ -31,61 +32,68 @@
 /* Secure port macros. */
 #include "secure_port_macros.h"
 
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
 #endif
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
 {
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
+    /* pxSecureContext value is in r0. */
+    __asm volatile
+    (
+        " .syntax unified                   \n"
+        "                                   \n"
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
+        " cbz r1, load_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
+        " ldmia r0!, {r1, r2}               \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+        "                                   \n"
+        #if ( configENABLE_MPU == 1 )
+            " ldmia r1!, {r3}               \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            " msr control, r3               \n" /* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "                                   \n"
+        " msr psplim, r2                    \n" /* PSPLIM = r2. */
+        " msr psp, r1                       \n" /* PSP = r1. */
+        "                                   \n"
+        " load_ctx_therad_mode:             \n"
+        "    bx lr                          \n"
+        "                                   \n"
+        ::: "r0", "r1", "r2"
+    );
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
 {
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#else /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	#endif /* configENABLE_MPU */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
+    /* pxSecureContext value is in r0. */
+    __asm volatile
+    (
+        " .syntax unified                   \n"
+        "                                   \n"
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
+        " cbz r1, save_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
+        " mrs r1, psp                       \n" /* r1 = PSP. */
+        "                                   \n"
+        #if ( configENABLE_MPU == 1 )
+            " mrs r2, control               \n" /* r2 = CONTROL. */
+            " subs r1, r1, #4               \n" /* Make space for the CONTROL value on the stack. */
+            " str r1, [r0]                  \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+            " stmia r1!, {r2}               \n" /* Store CONTROL value on the stack. */
+        #else /* configENABLE_MPU */
+            " str r1, [r0]                  \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+        #endif /* configENABLE_MPU */
+        "                                   \n"
+        " movs r1, %0                       \n" /* r1 = securecontextNO_STACK. */
+        " msr psplim, r1                    \n" /* PSPLIM = securecontextNO_STACK. */
+        " msr psp, r1                       \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "                                   \n"
+        " save_ctx_therad_mode:             \n"
+        "   bx lr                           \n"
+        "                                   \n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Secure context includes. */
@@ -31,58 +32,66 @@
 /* Secure port macros. */
 #include "secure_port_macros.h"
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
+
+void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
 {
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
+    /* pxSecureContext value is in r0. */
+    __asm volatile
+    (
+        " .syntax unified                   \n"
+        "                                   \n"
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
+        " cbz r1, load_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
+        " ldmia r0!, {r1, r2}               \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
+        "                                   \n"
+        #if ( configENABLE_MPU == 1 )
+            " ldmia r1!, {r3}               \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            " msr control, r3               \n" /* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "                                   \n"
+        " msr psplim, r2                    \n" /* PSPLIM = r2. */
+        " msr psp, r1                       \n" /* PSP = r1. */
+        "                                   \n"
+        " load_ctx_therad_mode:             \n"
+        "    bx lr                          \n"
+        "                                   \n"
+        ::: "r0", "r1", "r2"
+    );
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
 {
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
+    /* pxSecureContext value is in r0. */
+    __asm volatile
+    (
+        " .syntax unified                   \n"
+        "                                   \n"
+        " mrs r1, ipsr                      \n" /* r1 = IPSR. */
+        " cbz r1, save_ctx_therad_mode      \n" /* Do nothing if the processor is running in the Thread Mode. */
+        " mrs r1, psp                       \n" /* r1 = PSP. */
+        "                                   \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            " vstmdb r1!, {s0}              \n" /* Trigger the deferred stacking of FPU registers. */
+            " vldmia r1!, {s0}              \n" /* Nullify the effect of the previous statement. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+        "                                   \n"
+        #if ( configENABLE_MPU == 1 )
+            " mrs r2, control               \n" /* r2 = CONTROL. */
+            " stmdb r1!, {r2}               \n" /* Store CONTROL value on the stack. */
+        #endif /* configENABLE_MPU */
+        "                                   \n"
+        " str r1, [r0]                      \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+        " movs r1, %0                       \n" /* r1 = securecontextNO_STACK. */
+        " msr psplim, r1                    \n" /* PSPLIM = securecontextNO_STACK. */
+        " msr psp, r1                       \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "                                   \n"
+        " save_ctx_therad_mode:             \n"
+        "    bx lr                          \n"
+        "                                   \n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,58 +21,68 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
+    SECTION .text:CODE:NOROOT(2)
+    THUMB
 
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+    PUBLIC SecureContext_LoadContextAsm
+    PUBLIC SecureContext_SaveContextAsm
 
 #if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
 #endif
 /*-----------------------------------------------------------*/
 
 SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
+    /* pxSecureContext value is in r0. */
+    mrs r1, ipsr                    /* r1 = IPSR. */
+    cbz r1, load_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */
+    ldmia r0!, {r1, r2}             /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
 
-	load_ctx_therad_mode:
-		bx lr
+#if ( configENABLE_MPU == 1 )
+    ldmia r1!, {r3}                 /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+    msr control, r3                 /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+
+    msr psplim, r2                  /* PSPLIM = r2. */
+    msr psp, r1                     /* PSP = r1. */
+
+    load_ctx_therad_mode:
+        bx lr
 /*-----------------------------------------------------------*/
 
 SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
-#else /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-#endif /* configENABLE_MPU */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+    /* pxSecureContext value is in r0. */
+    mrs r1, ipsr                    /* r1 = IPSR. */
+    cbz r1, save_ctx_therad_mode    /* Do nothing if the processor is running in the Thread Mode. */
+    mrs r1, psp                     /* r1 = PSP. */
 
-	save_ctx_therad_mode:
-		bx lr
+#if ( configENABLE_MPU == 1 )
+    mrs r2, control                 /* r2 = CONTROL. */
+    subs r1, r1, #4                 /* Make space for the CONTROL value on the stack. */
+    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+    stmia r1!, {r2}                 /* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+    str r1, [r0]                    /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+
+    movs r1, #0                     /* r1 = securecontextNO_STACK. */
+    msr psplim, r1                  /* PSPLIM = securecontextNO_STACK. */
+    msr psp, r1                     /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+    save_ctx_therad_mode:
+        bx lr
 /*-----------------------------------------------------------*/
 
-	END
+    END

portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,55 +21,66 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
+    SECTION .text:CODE:NOROOT(2)
+    THUMB
 
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+    PUBLIC SecureContext_LoadContextAsm
+    PUBLIC SecureContext_SaveContextAsm
 /*-----------------------------------------------------------*/
 
 SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
+    /* pxSecureContext value is in r0. */
+    mrs r1, ipsr                        /* r1 = IPSR. */
+    cbz r1, load_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
+    ldmia r0!, {r1, r2}                 /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
 
-	load_ctx_therad_mode:
-		bx lr
+#if ( configENABLE_MPU == 1 )
+    ldmia r1!, {r3}                     /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+    msr control, r3                     /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+
+    msr psplim, r2                      /* PSPLIM = r2. */
+    msr psp, r1                         /* PSP = r1. */
+
+    load_ctx_therad_mode:
+        bx lr
 /*-----------------------------------------------------------*/
 
 SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
-	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
-	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+    /* pxSecureContext value is in r0. */
+    mrs r1, ipsr                        /* r1 = IPSR. */
+    cbz r1, save_ctx_therad_mode        /* Do nothing if the processor is running in the Thread Mode. */
+    mrs r1, psp                         /* r1 = PSP. */
 
-	save_ctx_therad_mode:
-		bx lr
+#if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+    vstmdb r1!, {s0}                    /* Trigger the deferred stacking of FPU registers. */
+    vldmia r1!, {s0}                    /* Nullify the effect of the previous statement. */
+#endif /* configENABLE_FPU || configENABLE_MVE */
+
+#if ( configENABLE_MPU == 1 )
+    mrs r2, control                     /* r2 = CONTROL. */
+    stmdb r1!, {r2}                     /* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+
+    str r1, [r0]                        /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
+    movs r1, #0                         /* r1 = securecontextNO_STACK. */
+    msr psplim, r1                      /* PSPLIM = securecontextNO_STACK. */
+    msr psp, r1                         /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+    save_ctx_therad_mode:
+        bx lr
 /*-----------------------------------------------------------*/
 
-	END
+    END

portable/ARMv8M/secure/context/secure_context.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Secure context includes. */
@@ -40,7 +41,7 @@
  * Bit[0] - 0 --> Thread mode is privileged.
  * Bit[1] - 1 --> Thread mode uses PSP.
  */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
 
 /**
  * @brief CONTROL value for un-privileged tasks.
@@ -48,157 +49,303 @@
  * Bit[0] - 1 --> Thread mode is un-privileged.
  * Bit[1] - 1 --> Thread mode uses PSP.
  */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+
+/**
+ * @brief Size of stack seal values in bytes.
+ */
+#define securecontextSTACK_SEAL_SIZE               8
+
+/**
+ * @brief Stack seal value as recommended by ARM.
+ */
+#define securecontextSTACK_SEAL_VALUE              0xFEF5EDA5
+
+/**
+ * @brief Maximum number of secure contexts.
+ */
+#ifndef secureconfigMAX_SECURE_CONTEXTS
+    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+#endif
 /*-----------------------------------------------------------*/
 
 /**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
+ * @brief Pre-allocated array of secure contexts.
  */
-typedef struct SecureContext
+SecureContext_t xSecureContexts[ secureconfigMAX_SECURE_CONTEXTS ];
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Get a free secure context for a task from the secure context pool (xSecureContexts).
+ *
+ * This function ensures that only one secure context is allocated for a task.
+ *
+ * @param[in] pvTaskHandle The task handle for which the secure context is allocated.
+ *
+ * @return Index of a free secure context in the xSecureContexts array.
+ */
+static uint32_t ulGetSecureContext( void * pvTaskHandle );
+
+/**
+ * @brief Return the secure context to the secure context pool (xSecureContexts).
+ *
+ * @param[in] ulSecureContextIndex Index of the context in the xSecureContexts array.
+ */
+static void vReturnSecureContext( uint32_t ulSecureContextIndex );
+
+/* These are implemented in assembly. */
+extern void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext );
+extern void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext );
+/*-----------------------------------------------------------*/
+
+static uint32_t ulGetSecureContext( void * pvTaskHandle )
 {
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
+    /* Start with invalid index. */
+    uint32_t i, ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+
+    for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+    {
+        if( ( xSecureContexts[ i ].pucCurrentStackPointer == NULL ) &&
+            ( xSecureContexts[ i ].pucStackLimit == NULL ) &&
+            ( xSecureContexts[ i ].pucStackStart == NULL ) &&
+            ( xSecureContexts[ i ].pvTaskHandle == NULL ) &&
+            ( ulSecureContextIndex == secureconfigMAX_SECURE_CONTEXTS ) )
+        {
+            ulSecureContextIndex = i;
+        }
+        else if( xSecureContexts[ i ].pvTaskHandle == pvTaskHandle )
+        {
+            /* A task can only have one secure context. Do not allocate a second
+             * context for the same task. */
+            ulSecureContextIndex = secureconfigMAX_SECURE_CONTEXTS;
+            break;
+        }
+    }
+
+    return ulSecureContextIndex;
+}
+/*-----------------------------------------------------------*/
+
+static void vReturnSecureContext( uint32_t ulSecureContextIndex )
+{
+    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = NULL;
+    xSecureContexts[ ulSecureContextIndex ].pucStackLimit = NULL;
+    xSecureContexts[ ulSecureContextIndex ].pucStackStart = NULL;
+    xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = NULL;
+}
 /*-----------------------------------------------------------*/
 
 secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 {
-	uint32_t ulIPSR;
+    uint32_t ulIPSR, i;
+    static uint32_t ulSecureContextsInitialized = 0;
 
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
 
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ( ulIPSR != 0 ) && ( ulSecureContextsInitialized == 0 ) )
+    {
+        /* Ensure to initialize secure contexts only once. */
+        ulSecureContextsInitialized = 1;
 
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        /* Initialize all secure contexts. */
+        for( i = 0; i < secureconfigMAX_SECURE_CONTEXTS; i++ )
+        {
+            xSecureContexts[ i ].pucCurrentStackPointer = NULL;
+            xSecureContexts[ i ].pucStackLimit = NULL;
+            xSecureContexts[ i ].pucStackStart = NULL;
+            xSecureContexts[ i ].pvTaskHandle = NULL;
+        }
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
 }
 /*-----------------------------------------------------------*/
 
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged,
+                                                                                       void * pvTaskHandle )
 #else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       void * pvTaskHandle )
 #endif /* configENABLE_MPU */
 {
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
+    uint8_t * pucStackMemory = NULL;
+    uint8_t * pucStackLimit;
+    uint32_t ulIPSR, ulSecureContextIndex;
+    SecureContextHandle_t xSecureContextHandle = securecontextINVALID_CONTEXT_ID;
 
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
 
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+    /* Read the Interrupt Program Status Register (IPSR) and Process Stack Limit
+     * Register (PSPLIM) value. */
+    secureportREAD_IPSR( ulIPSR );
+    secureportREAD_PSPLIM( pucStackLimit );
 
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode.
+     * Also do nothing, if a secure context us already loaded. PSPLIM is set to
+     * securecontextNO_STACK when no secure context is loaded. */
+    if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
+    {
+        /* Ontain a free secure context. */
+        ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+        /* Were we able to get a free context? */
+        if( ulSecureContextIndex < secureconfigMAX_SECURE_CONTEXTS )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize + securecontextSTACK_SEAL_SIZE );
 
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte for stack (excluding the space for seal values)
+                 * because the hardware decrements the stack pointer before
+                 * writing i.e. if stack pointer is 0x2, a push operation will
+                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
+                /* Seal the created secure process stack. */
+                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContexts[ ulSecureContextIndex ].pucStackLimit = pucStackMemory;
 
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
+                xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
-	return xSecureContextHandle;
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+
+                /* Ensure to never return 0 as a valid context handle. */
+                xSecureContextHandle = ulSecureContextIndex + 1UL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
 {
-	uint32_t ulIPSR;
+    uint32_t ulIPSR, ulSecureContextIndex;
 
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
 
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Only free if a valid context handle is passed. */
+        if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+        {
+            ulSecureContextIndex = xSecureContextHandle - 1UL;
 
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
+            /* Ensure that the secure context being deleted is associated with
+             * the task. */
+            if( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle )
+            {
+                /* Free the stack space. */
+                vPortFree( xSecureContexts[ ulSecureContextIndex ].pucStackLimit );
 
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
+                /* Return the secure context back to the free secure contexts pool. */
+                vReturnSecureContext( ulSecureContextIndex );
+            }
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+    uint8_t * pucStackLimit;
+    uint32_t ulSecureContextIndex;
+
+    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+    {
+        ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+        secureportREAD_PSPLIM( pucStackLimit );
+
+        /* Ensure that no secure context is loaded and the task is loading it's
+         * own context. */
+        if( ( pucStackLimit == securecontextNO_STACK ) &&
+            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+        {
+            SecureContext_LoadContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+{
+    uint8_t * pucStackLimit;
+    uint32_t ulSecureContextIndex;
+
+    if( ( xSecureContextHandle > 0UL ) && ( xSecureContextHandle <= secureconfigMAX_SECURE_CONTEXTS ) )
+    {
+        ulSecureContextIndex = xSecureContextHandle - 1UL;
+
+        secureportREAD_PSPLIM( pucStackLimit );
+
+        /* Ensure that task's context is loaded and the task is saving it's own
+         * context. */
+        if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
+            ( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )
+        {
+            SecureContext_SaveContextAsm( &( xSecureContexts[ ulSecureContextIndex ] ) );
+        }
+    }
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/secure/context/secure_context.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef __SECURE_CONTEXT_H__
@@ -35,15 +36,35 @@
 #include "FreeRTOSConfig.h"
 
 /**
- * @brief PSP value when no task's context is loaded.
+ * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK	0x0
+#define securecontextNO_STACK               0x0
 
 /**
- * @brief Opaque handle.
+ * @brief Invalid context ID.
  */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
+#define securecontextINVALID_CONTEXT_ID     0UL
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent a secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first address of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+    void * pvTaskHandle;              /**< Task handle of the task this context is associated with. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Opaque handle for a secure context.
+ */
+typedef uint32_t SecureContextHandle_t;
 /*-----------------------------------------------------------*/
 
 /**
@@ -69,10 +90,13 @@ void SecureContext_Init( void );
  * @return Opaque context handle if context is successfully allocated, NULL
  * otherwise.
  */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged,
+                                                         void * pvTaskHandle );
 #else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         void * pvTaskHandle );
 #endif /* configENABLE_MPU */
 
 /**
@@ -84,7 +108,7 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -95,7 +119,7 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -106,6 +130,6 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */

portable/ARMv8M/secure/heap/secure_heap.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -37,37 +38,40 @@
 /**
  * @brief Total heap size.
  */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
+#ifndef secureconfigTOTAL_HEAP_SIZE
+    #define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+#endif
 
 /* No test marker by default. */
 #ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
+    #define mtCOVERAGE_TEST_MARKER()
 #endif
 
 /* No tracing by default. */
 #ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
+    #define traceMALLOC( pvReturn, xWantedSize )
 #endif
 
 /* No tracing by default. */
 #ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
+    #define traceFREE( pv, xBlockSize )
 #endif
 
 /* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
 
 /* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
 /*-----------------------------------------------------------*/
 
 /* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
 #else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
 #endif /* configAPPLICATION_ALLOCATED_HEAP */
 
 /**
@@ -77,8 +81,8 @@
  */
 typedef struct A_BLOCK_LINK
 {
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
 } BlockLink_t;
 /*-----------------------------------------------------------*/
 
@@ -97,7 +101,7 @@ static void prvHeapInit( void );
  *
  * @param[in] pxBlockToInsert The block being freed.
  */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
 /*-----------------------------------------------------------*/
 
 /**
@@ -109,7 +113,7 @@ static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( s
 /**
  * @brief Create a couple of list links to mark the start and end of the list.
  */
-static BlockLink_t xStart, *pxEnd = NULL;
+static BlockLink_t xStart, * pxEnd = NULL;
 
 /**
  * @brief Keeps track of the number of free bytes remaining, but says nothing
@@ -130,321 +134,318 @@ static size_t xBlockAllocatedBit = 0;
 
 static void prvHeapInit( void )
 {
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
 
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
 
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
 
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
 
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
 
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
 
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
 }
 /*-----------------------------------------------------------*/
 
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
 {
-BlockLink_t *pxIterator;
-uint8_t *puc;
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
 
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
 
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
 
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 }
 /*-----------------------------------------------------------*/
 
-void *pvPortMalloc( size_t xWantedSize )
+void * pvPortMalloc( size_t xWantedSize )
 {
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
 
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
 
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
 
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
 
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
 
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
 
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
 
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
 
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
 
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
 
-	traceMALLOC( pvReturn, xWantedSize );
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
 
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
+    traceMALLOC( pvReturn, xWantedSize );
 
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
 }
 /*-----------------------------------------------------------*/
 
-void vPortFree( void *pv )
+void vPortFree( void * pv )
 {
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
 
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
 
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
 
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
 
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
 
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
 }
 /*-----------------------------------------------------------*/
 
 size_t xPortGetFreeHeapSize( void )
 {
-	return xFreeBytesRemaining;
+    return xFreeBytesRemaining;
 }
 /*-----------------------------------------------------------*/
 
 size_t xPortGetMinimumEverFreeHeapSize( void )
 {
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
+    return xMinimumEverFreeBytesRemaining;
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/secure/heap/secure_heap.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef __SECURE_HEAP_H__
@@ -39,13 +40,27 @@
  * @return Pointer to the memory region if the allocation is successful, NULL
  * otherwise.
  */
-void *pvPortMalloc( size_t xWantedSize );
+void * pvPortMalloc( size_t xWantedSize );
 
 /**
  * @brief Frees the previously allocated memory.
  *
  * @param[in] pv Pointer to the memory to be freed.
  */
-void vPortFree( void *pv );
+void vPortFree( void * pv );
+
+/**
+ * @brief Get the free heap size.
+ *
+ * @return Free heap size.
+ */
+size_t xPortGetFreeHeapSize( void );
+
+/**
+ * @brief Get the minimum ever free heap size.
+ *
+ * @return Minimum ever free heap size.
+ */
+size_t xPortGetMinimumEverFreeHeapSize( void );
 
 #endif /* __SECURE_HEAP_H__ */

portable/ARMv8M/secure/init/secure_init.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* Standard includes. */
@@ -37,69 +38,69 @@
 /**
  * @brief Constants required to manipulate the SCB.
  */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
 
 /**
  * @brief Constants required to manipulate the FPU.
  */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
 
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
 /*-----------------------------------------------------------*/
 
 secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
 {
-	uint32_t ulIPSR;
+    uint32_t ulIPSR;
 
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
 
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
 }
 /*-----------------------------------------------------------*/
 
 secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
 {
-	uint32_t ulIPSR;
+    uint32_t ulIPSR;
 
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
 
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
 
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
 
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
 }
 /*-----------------------------------------------------------*/

portable/ARMv8M/secure/init/secure_init.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef __SECURE_INIT_H__

portable/ARMv8M/secure/macros/secure_port_macros.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef __SECURE_PORT_MACROS_H__
@@ -31,103 +32,109 @@
 /**
  * @brief Byte alignment requirements.
  */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
 
 /**
  * @brief Macro to declare a function as non-secure callable.
  */
 #if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
 #else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
 #endif
 
 /**
  * @brief Set the secure PRIMASK value.
  */
 #define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
 
 /**
  * @brief Set the non-secure PRIMASK value.
  */
 #define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
 
 /**
  * @brief Read the PSP value in the given variable.
  */
 #define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
 
 /**
  * @brief Set the PSP to the given value.
  */
 #define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Read the PSPLIM value in the given variable.
+ */
+#define secureportREAD_PSPLIM( pucOutStackLimit ) \
+    __asm volatile ( "mrs %0, psplim"  : "=r" ( pucOutStackLimit ) )
 
 /**
  * @brief Set the PSPLIM to the given value.
  */
 #define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
 
 /**
  * @brief Set the NonSecure MSP to the given value.
  */
 #define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
 
 /**
  * @brief Set the CONTROL register to the given value.
  */
 #define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
 
 /**
  * @brief Read the Interrupt Program Status Register (IPSR) value in the given
  * variable.
  */
 #define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
 
 /**
  * @brief PRIMASK value to enable interrupts.
  */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
 
 /**
  * @brief PRIMASK value to disable interrupts.
  */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
 
 /**
  * @brief Disable secure interrupts.
  */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
 
 /**
  * @brief Disable non-secure interrupts.
  *
  * This effectively disables context switches.
  */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
 
 /**
  * @brief Enable non-secure interrupts.
  */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
 
 /**
  * @brief Assert definition.
  */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
 
 #endif /* __SECURE_PORT_MACROS_H__ */

portable/BCC/16BitDOS/Flsh186/port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*

portable/BCC/16BitDOS/Flsh186/prtmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H

portable/BCC/16BitDOS/PC/port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*

portable/BCC/16BitDOS/PC/prtmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORTMACRO_H

portable/BCC/16BitDOS/common/portasm.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 #ifndef PORT_ASM_H

portable/BCC/16BitDOS/common/portcomn.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*

portable/CCS/ARM_CM3/port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,76 +21,76 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
 
 /* Scheduler includes. */
 #include "FreeRTOS.h"
 #include "task.h"
 
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
 #endif
 
 #ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
 #else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
 #endif
 
 /* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
 /* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
 
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
 
 /* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
 
 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
 
 /* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
+#define portINITIAL_XPSR                      ( 0x01000000 )
 
 /* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
 
 /* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
 
 /* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
 
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
@@ -115,34 +117,34 @@ static void prvTaskExitError( void );
 /*-----------------------------------------------------------*/
 
 /* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
-setting. */
+ * setting. */
 const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
 
 /* Each task maintains its own interrupt status in the critical nesting
-variable. */
+ * variable. */
 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
 
 /*
  * The number of SysTick increments that make up one tick period.
  */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 
 /*
  * The maximum number of tick periods that can be suppressed is limited by the
  * 24 bit resolution of the SysTick timer.
  */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 
 /*
  * Compensate for the CPU cycles that pass while the SysTick is stopped (low
  * power functionality only.
  */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
 #endif /* configUSE_TICKLESS_IDLE */
 
 /*
@@ -151,9 +153,9 @@ static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
  */
 #if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
 #endif /* configASSERT_DEFINED */
 
 /*-----------------------------------------------------------*/
@@ -165,40 +167,43 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
                                      TaskFunction_t pxCode,
                                      void * pvParameters )
 {
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
 
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
 
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
 
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
 
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+    pxTopOfStack -= 8;                            /* R11, R10, R9, R8, R7, R6, R5 and R4. */
 
-	return pxTopOfStack;
+    return pxTopOfStack;
 }
 /*-----------------------------------------------------------*/
 
 static void prvTaskExitError( void )
 {
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
 
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
+    for( ; ; )
+    {
+    }
 }
 /*-----------------------------------------------------------*/
 
@@ -207,308 +212,312 @@ static void prvTaskExitError( void )
  */
 BaseType_t xPortStartScheduler( void )
 {
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
 
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
 
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
 
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
 
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
 
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* configASSERT_DEFINED */
 
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
 
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
 
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
 
-	/* Start the first task. */
-	vPortStartFirstTask();
+    /* Start the first task. */
+    vPortStartFirstTask();
 
-	/* Should not get here! */
-	return 0;
+    /* Should not get here! */
+    return 0;
 }
 /*-----------------------------------------------------------*/
 
 void vPortEndScheduler( void )
 {
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
 }
 /*-----------------------------------------------------------*/
 
 void vPortEnterCritical( void )
 {
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
 
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
 }
 /*-----------------------------------------------------------*/
 
 void vPortExitCritical( void )
 {
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
 }
 /*-----------------------------------------------------------*/
 
 void xPortSysTickHandler( void )
 {
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	( void ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
 }
 /*-----------------------------------------------------------*/
 
-#if( configUSE_TICKLESS_IDLE == 1 )
+#if ( configUSE_TICKLESS_IDLE == 1 )
 
-	#pragma WEAK( vPortSuppressTicksAndSleep )
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
+    #pragma WEAK( vPortSuppressTicksAndSleep )
+    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
 
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
 
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
 
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
 
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm( "	cpsid i" );
-		__asm( "	dsb" );
-		__asm( "	isb" );
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
 
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm( "	cpsid i");
+        __asm( "	dsb");
+        __asm( "	isb");
 
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
 
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
 
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
 
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__asm( "	cpsie i" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __asm( "	cpsie i");
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
 
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
 
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm( "	dsb" );
-				__asm( "	wfi" );
-				__asm( "	isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
 
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm( "	cpsie i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm( "	dsb");
+                __asm( "	wfi");
+                __asm( "	isb");
+            }
 
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm( "	cpsid i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
 
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm( "	cpsie i");
+            __asm( "	dsb");
+            __asm( "	isb");
 
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm( "	cpsid i");
+            __asm( "	dsb");
+            __asm( "	isb");
 
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
 
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
 
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
 
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
 
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
 
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
 
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
 
-			/* Exit with interrupts enabled. */
-			__asm( "	cpsie i" );
-		}
-	}
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm( "	cpsie i");
+        }
+    }
 
 #endif /* configUSE_TICKLESS_IDLE */
 /*-----------------------------------------------------------*/
@@ -520,102 +529,81 @@ void xPortSysTickHandler( void )
 #pragma WEAK( vPortSetupTimerInterrupt )
 void vPortSetupTimerInterrupt( void )
 {
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
 
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 }
 /*-----------------------------------------------------------*/
 
-#if( configASSERT_DEFINED == 1 )
+#if ( configASSERT_DEFINED == 1 )
 
-	void vPortValidateInterruptPriority( void )
-	{
-	extern uint32_t ulPortGetIPSR( void );
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
+    void vPortValidateInterruptPriority( void )
+    {
+        extern uint32_t ulPortGetIPSR( void );
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
 
-		ulCurrentInterrupt = ulPortGetIPSR();
+        ulCurrentInterrupt = ulPortGetIPSR();
 
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
 
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
 
 #endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

portable/CCS/ARM_CM3/portasm.asm

@@ -1,6 +1,8 @@
 ;/*
-; * FreeRTOS Kernel V10.3.1
-; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.5.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
 ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
 ; *
-; * 1 tab == 4 spaces!
 ; */
 
 	.thumb

portable/CCS/ARM_CM3/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,18 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -44,128 +45,127 @@ extern "C" {
  */
 
 /* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 
 /*-----------------------------------------------------------*/
 
 /* Compiler directives. */
-#define portWEAK_SYMBOL				__attribute__((weak))
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
 
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__asm( "	dsb" );										\
-	__asm( "	isb" );										\
-}
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __asm( "	dsb");                                \
+        __asm( "	isb");                                \
+    }
 
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
 
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
 
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-	/*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
 
-#define portDISABLE_INTERRUPTS()										\
-{																		\
-	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__asm( "	dsb" );													\
-	__asm( "	isb" );													\
-}
+    #define portDISABLE_INTERRUPTS()                                     \
+    {                                                                    \
+        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __asm( "	dsb");                                                 \
+        __asm( "	isb");                                                 \
+    }
 
-#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
 
 /* portNOP() is not required by this port. */
-#define portNOP()
+    #define portNOP()
 
 /*-----------------------------------------------------------*/
 
-#ifdef __cplusplus
-}
-#endif
+    #ifdef __cplusplus
+        }
+    #endif
 
 #endif /* PORTMACRO_H */
-

portable/CCS/ARM_CM4F/portasm.asm

@@ -1,6 +1,8 @@
 ;/*
-; * FreeRTOS Kernel V10.3.1
-; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.5.0
+; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * SPDX-License-Identifier: MIT
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
 ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
 ; *
-; * 1 tab == 4 spaces!
 ; */
 
 	.thumb

portable/CCS/ARM_CM4F/portmacro.h

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,19 +21,18 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 
 #ifndef PORTMACRO_H
-#define PORTMACRO_H
+    #define PORTMACRO_H
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
 
 /*-----------------------------------------------------------
  * Port specific definitions.
@@ -44,122 +45,121 @@ extern "C" {
  */
 
 /* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
 
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
 
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
 
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
 /*-----------------------------------------------------------*/
 
 /* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
 /*-----------------------------------------------------------*/
 
 /* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__asm( "	dsb" );										\
-	__asm( "	isb" );										\
-}
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __asm( "	dsb");                                \
+        __asm( "	isb");                                \
+    }
 
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    do { if( xSwitchRequired != pdFALSE ) portYIELD(); } while( 0 )
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
 
 /*-----------------------------------------------------------*/
 
 /* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
 
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
 
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 
-	/*-----------------------------------------------------------*/
+/*-----------------------------------------------------------*/
 
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
 
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 /*-----------------------------------------------------------*/
 
 /* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
 
-#define portDISABLE_INTERRUPTS()										\
-{																		\
-	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__asm( "	dsb" );													\
-	__asm( "	isb" );													\
-}
+    #define portDISABLE_INTERRUPTS()                                     \
+    {                                                                    \
+        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __asm( "	dsb");                                                 \
+        __asm( "	isb");                                                 \
+    }
 
-#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
 /*-----------------------------------------------------------*/
 
 /* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
 
 /*-----------------------------------------------------------*/
 
 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
 /*-----------------------------------------------------------*/
 
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
 
 /* portNOP() is not required by this port. */
-#define portNOP()
+    #define portNOP()
 
 /*-----------------------------------------------------------*/
 
-#ifdef __cplusplus
-}
-#endif
+    #ifdef __cplusplus
+        }
+    #endif
 
 #endif /* PORTMACRO_H */
-

portable/CCS/ARM_Cortex-R4/port.c

@@ -1,6 +1,8 @@
 /*
- * FreeRTOS Kernel V10.3.1
- * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.5.0
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -19,10 +21,9 @@
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
  *
- * 1 tab == 4 spaces!
  */
 
 /* FreeRTOS includes. */