Jim Wilson ec2260af61 RISC-V: PR30449, Add lga assembler macro support. ...

Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539

Added new load address pseudo instruction which is always expanded to GOT
access, no matter the .option rvc is set or not.

gas/
	PR 30449
	* config/tc-riscv.c (macro): Add M_LGA support.
	* testsuite/gas/riscv/la-variants.d: New.
	* testsuite/gas/riscv/la-variants.s: New.
include/
	PR 30449
	* opcode/riscv.h (M_LGA): New.
opcodes/
	PR 30449
	* riscv-opc.c (riscv_opcodes): Add lga support.

2023-06-01 12:25:08 +08:00

..

aarch64.h

aarch64: Remove stray reglist variable

2023-03-30 17:01:30 +01:00

alpha.h

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

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avr.h

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bfin.h

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cgen.h

bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]

2023-02-03 11:18:50 -06:00

ChangeLog-0415

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ChangeLog-9103

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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loongarch.h

LoongArch: include: Add support for linker relaxation.

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m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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nios2.h

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nios2r1.h

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nios2r2.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

RISC-V: Support XVentanaCondOps extension

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riscv.h

RISC-V: PR30449, Add lga assembler macro support.

2023-06-01 12:25:08 +08:00

rl78.h

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rx.h

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s12z.h

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s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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xgate.h

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