Tamar Christina e1e1528448 AArch64: Enable FP16 by default for Armv9-A. ...

In Armv9-A SVE is mandatory, and for SVE FP16 is mandatory.  This fixes a disconnect
between GCC and binutils where GCC has FP16 on by default and gas doesn't.

include/ChangeLog:

2022-05-16  Tamar Christina  <tamar.christina@arm.com>

	* opcode/aarch64.h (AARCH64_ARCH_V9_FEATURES): Add AARCH64_FEATURE_F16.

2022-05-18 10:37:10 +01:00

..

aarch64.h

AArch64: Enable FP16 by default for Armv9-A.

2022-05-18 10:37:10 +01:00

alpha.h

Update year range in copyright notice of binutils files

2022-01-02 12:04:28 +10:30

arc-attrs.h

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arc-func.h

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arc.h

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arm.h

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avr.h

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bfin.h

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cgen.h

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ChangeLog-0415

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ChangeLog-9103

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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2022-01-02 12:04:28 +10:30

loongarch.h

gas:LoongArch: Fix segment error in compilation due to too long symbol name.

2022-03-20 09:37:12 +08:00

m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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nios2.h

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nios2r1.h

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nios2r2.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

Delete PowerPC macro insn support

2022-03-16 10:08:46 +10:30

pru.h

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pyr.h

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riscv-opc.h

RISC-V: Added half-precision floating-point v1.0 instructions.

2022-05-17 13:31:38 +08:00

riscv.h

RISC-V: Added half-precision floating-point v1.0 instructions.

2022-05-17 13:31:38 +08:00

rl78.h

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2022-01-02 12:04:28 +10:30

rx.h

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2022-01-02 12:04:28 +10:30

s12z.h

Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.

2020-01-02 12:04:40 +00:00

s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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