forked from Imagelibrary/binutils-gdb
d81352b8b8
(v850_callback): Declare.
(do_format_5): Fix extraction of OP[0].
(sim_size): Remove debugging printf.
(sim_set_callbacks): Do something useful.
(sim_stop_reason): Gross hacks to get c-torture running.
* simops.c: Simplify code for computing targets of bCC
insns. Invert 's' bit if 'ov' bit is set for some
instructions. Fix 'cy' bit handling for numerous
instructions. Make the simulator stop when a halt
instruction is encountered. Very crude support for
emulated syscalls (trap 0).
* v850_sim.h: Include "callback.h" and declare
v850_callback. Items in the operand array are 32bits.
Fixes & syscall stuff.
1595 lines
31 KiB
C
1595 lines
31 KiB
C
#include <signal.h>
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#include "v850_sim.h"
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#include "simops.h"
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/* sld.b */
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void
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OP_300 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op2 = temp;
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result = get_byte (State.mem + State.regs[30] + op2);
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result = (result << 24) >> 24;
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State.regs[OP[0]] = result;
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}
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/* sld.h */
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void
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OP_400 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op2 = temp << 1;
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result = get_half (State.mem + State.regs[30] + op2);
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result = (result << 16) >> 16;
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State.regs[OP[0]] = result;
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}
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/* sld.w */
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void
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OP_500 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op2 = temp << 2;
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result = get_word (State.mem + State.regs[30] + op2);
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State.regs[OP[0]] = result;
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}
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/* sst.b */
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void
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OP_380 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op1 = temp;
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put_byte (State.mem + State.regs[30] + op1, op0);
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}
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/* sst.h */
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void
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OP_480 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op1 = temp << 1;
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put_half (State.mem + State.regs[30] + op1, op0);
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}
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/* sst.w */
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void
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OP_501 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[1];
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temp = (temp << 25) >> 25;
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op1 = temp << 2;
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put_word (State.mem + State.regs[30] + op1, op0);
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}
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/* ld.b */
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void
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OP_700 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[2];
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temp = (temp << 16) >> 16;
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op2 = temp;
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result = get_byte (State.mem + op0 + op2);
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result = (result << 24) >> 24;
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State.regs[OP[1]] = result;
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}
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/* ld.h */
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void
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OP_720 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[2];
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temp = (temp << 16) >> 16;
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temp &= ~0x1;
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op2 = temp;
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result = get_half (State.mem + op0 + op2);
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result = (result << 16) >> 16;
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State.regs[OP[1]] = result;
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}
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/* ld.w */
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void
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OP_10720 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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temp = OP[2];
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temp = (temp << 16) >> 16;
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temp &= ~0x1;
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op2 = temp;
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result = get_word (State.mem + op0 + op2);
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State.regs[OP[1]] = result;
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}
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/* st.b */
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void
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OP_740 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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temp = OP[2];
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temp = (temp << 16) >> 16;
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op2 = temp;
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put_byte (State.mem + op0 + op2, op1);
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}
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/* st.h */
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void
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OP_760 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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temp = OP[2];
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temp &= ~0x1;
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temp = (temp << 16) >> 16;
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op2 = temp;
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put_half (State.mem + op0 + op2, op1);
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}
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/* st.w */
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void
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OP_10760 ()
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{
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unsigned int op0, op1, op2;
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int result, temp;
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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temp = OP[2];
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temp &= ~0x1;
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temp = (temp << 16) >> 16;
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op2 = temp;
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put_word (State.mem + op0 + op2, op1);
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}
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/* bv disp9 */
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void
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OP_580 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_OV) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bl disp9 */
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void
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OP_581 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_CY) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* be disp9 */
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void
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OP_582 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_Z) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnh disp 9*/
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void
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OP_583 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bn disp9 */
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void
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OP_584 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_S) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* br disp9 */
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void
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OP_585 ()
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{
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unsigned int op0;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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State.pc += op0;
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}
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/* blt disp9 */
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void
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OP_586 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* ble disp9 */
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void
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OP_587 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_Z) != 0)
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|| (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnv disp9 */
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void
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OP_588 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_OV) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bnl disp9 */
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void
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OP_589 ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_CY) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bne disp9 */
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void
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OP_58A ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_Z) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bh disp9 */
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void
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OP_58B ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bp disp9 */
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void
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OP_58C ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_S) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bsa disp9 */
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void
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OP_58D ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((psw & PSW_SAT) != 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bge disp9 */
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void
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OP_58E ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* bgt disp9 */
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void
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OP_58F ()
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{
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unsigned int op0, psw;
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int temp;
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op0 = ((signed)OP[0] << 23) >> 23;
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psw = State.sregs[5];
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if ((((psw & PSW_Z) != 0)
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|| (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
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State.pc += op0;
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else
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State.pc += 2;
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}
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/* jmp [reg1] */
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void
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OP_60 ()
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{
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/* interp.c will bump this by +2, so correct for it here. */
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State.pc = State.regs[OP[0]] - 2;
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}
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/* jarl disp22, reg */
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void
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OP_780 ()
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{
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unsigned int op0, opc;
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int temp;
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temp = OP[0];
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temp = (temp << 10) >> 10;
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op0 = temp;
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opc = State.pc;
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State.pc += temp;
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/* Gross. jarl X,r0 is really jr and doesn't save its result. */
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if (OP[1] != 0)
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State.regs[OP[1]] = opc + 4;
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}
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/* add reg, reg */
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void
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OP_1C0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* add sign_extend(imm5), reg */
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void
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OP_240 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0x1f);
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temp = (temp << 27) >> 27;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* addi sign_extend(imm16), reg, reg */
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void
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OP_600 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0xffff);
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temp = (temp << 16) >> 16;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* According to the manual, 's' is inverted if 'ov'
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is set. */
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s = ov ? !s : s;
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* sub reg1, reg2 */
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void
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OP_1A0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op1 - op0;
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/* Compute the condition codes. */
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|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
|
|
/* According to the manual, 's' is inverted if 'ov'
|
|
is set. */
|
|
s = ov ? !s : s;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* subr reg1, reg2 */
|
|
void
|
|
OP_180 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 - op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op0 < op1);
|
|
ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
|
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
|
|
|
/* According to the manual, 's' is inverted if 'ov'
|
|
is set. */
|
|
s = ov ? !s : s;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* mulh reg1, reg2 */
|
|
void
|
|
OP_E0 ()
|
|
{
|
|
State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
|
|
* (State.regs[OP[0]] & 0xffff));
|
|
}
|
|
|
|
/* mulh sign_extend(imm5), reg2
|
|
|
|
Condition codes */
|
|
void
|
|
OP_2E0 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value << 27) >> 27;
|
|
|
|
State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
|
|
}
|
|
|
|
/* mulhi imm16, reg1, reg2 */
|
|
void
|
|
OP_6E0 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = value & 0xffff;
|
|
|
|
State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
|
|
}
|
|
|
|
/* divh reg1, reg2 */
|
|
void
|
|
OP_40 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = State.regs[OP[0]] & 0xffff;
|
|
temp = (temp << 16) >> 16;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
|
|
if (op0 == 0xffffffff && op1 == 0x80000000)
|
|
{
|
|
result = 0x80000000;
|
|
ov = 1;
|
|
}
|
|
else if (op0 != 0)
|
|
{
|
|
result = op1 / op0;
|
|
ov = 0;
|
|
}
|
|
else
|
|
ov = 1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* cmp reg, reg */
|
|
void
|
|
OP_1E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
|
|
/* Set condition codes. */
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* cmp sign_extend(imm5), reg */
|
|
void
|
|
OP_260 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = OP[0];
|
|
temp = (temp << 27) >> 27;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
|
|
/* Set condition codes. */
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* setf cccc,reg2 */
|
|
void
|
|
OP_7E0 ()
|
|
{
|
|
/* Hack alert. We turn off a bit in op0 since we really only
|
|
wanted 4 bits. */
|
|
unsigned int op0, psw, result;
|
|
|
|
op0 = OP[0] & 0xf;
|
|
psw = State.sregs[5];
|
|
|
|
switch (op0)
|
|
{
|
|
case 0x0:
|
|
result = ((psw & PSW_OV) != 0);
|
|
break;
|
|
case 0x1:
|
|
result = ((psw & PSW_CY) != 0);
|
|
break;
|
|
case 0x2:
|
|
result = ((psw & PSW_Z) != 0);
|
|
break;
|
|
case 0x3:
|
|
result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
|
|
break;
|
|
case 0x4:
|
|
result = ((psw & PSW_S) != 0);
|
|
break;
|
|
case 0x5:
|
|
result = 1;
|
|
break;
|
|
case 0x6:
|
|
result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
|
|
break;
|
|
case 0x7:
|
|
result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
|
|
|| ((psw & PSW_Z) != 0)) != 0);
|
|
break;
|
|
case 0x8:
|
|
result = ((psw & PSW_OV) == 0);
|
|
break;
|
|
case 0x9:
|
|
result = ((psw & PSW_CY) == 0);
|
|
break;
|
|
case 0xa:
|
|
result = ((psw & PSW_Z) == 0);
|
|
break;
|
|
case 0xb:
|
|
result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
|
|
break;
|
|
case 0xc:
|
|
result = ((psw & PSW_S) == 0);
|
|
break;
|
|
case 0xd:
|
|
result = ((psw & PSW_SAT) != 0);
|
|
break;
|
|
case 0xe:
|
|
result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
|
|
break;
|
|
case 0xf:
|
|
result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
|
|
|| ((psw & PSW_Z) != 0)) == 0);
|
|
break;
|
|
}
|
|
|
|
State.regs[OP[1]] = result;
|
|
}
|
|
|
|
/* satadd reg,reg */
|
|
void
|
|
OP_C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 + op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < op0 || result < op1);
|
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && s)
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satadd sign_extend(imm5), reg */
|
|
void
|
|
OP_220 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = (OP[0] & 0x1f);
|
|
temp = (temp << 27) >> 27;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 + op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < op0 || result < op1);
|
|
ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
|
|
&& (op0 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && s)
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satsub reg1, reg2 */
|
|
void
|
|
OP_A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && s)
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* satsubi sign_extend(imm16), reg */
|
|
void
|
|
OP_660 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
int temp;
|
|
|
|
/* Compute the result. */
|
|
temp = (OP[0] & 0xffff);
|
|
temp = (temp << 16) >> 16;
|
|
op0 = temp;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 - op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && s)
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
void
|
|
OP_80 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov, sat;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 - op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (result < op0);
|
|
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
|
|
&& (op1 & 0x80000000) != (result & 0x80000000));
|
|
sat = ov;
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
|
|
| (sat ? PSW_SAT : 0));
|
|
|
|
/* Handle saturated results. */
|
|
if (sat && s)
|
|
State.regs[OP[1]] = 0x80000000;
|
|
else if (sat)
|
|
State.regs[OP[1]] = 0x7fffffff;
|
|
}
|
|
|
|
/* tst reg,reg */
|
|
void
|
|
OP_160 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the condition codes. */
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* mov reg, reg */
|
|
void
|
|
OP_0 ()
|
|
{
|
|
State.regs[OP[1]] = State.regs[OP[0]];
|
|
}
|
|
|
|
/* mov sign_extend(imm5), reg */
|
|
void
|
|
OP_200 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value << 27) >> 27;
|
|
State.regs[OP[1]] = value;
|
|
}
|
|
|
|
/* movea sign_extend(imm16), reg, reg */
|
|
|
|
void
|
|
OP_620 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value << 16) >> 16;
|
|
|
|
State.regs[OP[2]] = State.regs[OP[1]] + value;
|
|
}
|
|
|
|
/* movhi imm16, reg, reg */
|
|
void
|
|
OP_640 ()
|
|
{
|
|
int value = OP[0];
|
|
|
|
value = (value & 0xffff) << 16;
|
|
|
|
State.regs[OP[2]] = State.regs[OP[1]] + value;
|
|
}
|
|
|
|
/* sar zero_extend(imm5),reg1 */
|
|
void
|
|
OP_2A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = (signed)op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
|
|
}
|
|
|
|
/* sar reg1, reg2 */
|
|
void
|
|
OP_A007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = (signed)op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shl zero_extend(imm5),reg1 */
|
|
void
|
|
OP_2C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 << op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (32 - op0)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shl reg1, reg2 */
|
|
void
|
|
OP_C007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 << op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (32 - op0)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shr zero_extend(imm5),reg1 */
|
|
void
|
|
OP_280 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* shr reg1, reg2 */
|
|
void
|
|
OP_8007E0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = State.regs[OP[0]] & 0x1f;
|
|
op1 = State.regs[OP[1]];
|
|
result = op1 >> op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
cy = (op1 & (1 << (op0 - 1)));
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
|
|
| (cy ? PSW_CY : 0));
|
|
}
|
|
|
|
/* or reg, reg */
|
|
void
|
|
OP_100 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 | op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* ori zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_680 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 | op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* and reg, reg */
|
|
void
|
|
OP_140 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* andi zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_6C0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 & op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= (z ? PSW_Z : 0);
|
|
}
|
|
|
|
/* xor reg, reg */
|
|
void
|
|
OP_120 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 ^ op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* xori zero_extend(imm16), reg, reg */
|
|
void
|
|
OP_6A0 ()
|
|
{
|
|
unsigned int op0, op1, result, z, s, cy, ov;
|
|
|
|
op0 = OP[0] & 0xffff;
|
|
op1 = State.regs[OP[1]];
|
|
result = op0 ^ op1;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[2]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* not reg1, reg2 */
|
|
void
|
|
OP_20 ()
|
|
{
|
|
unsigned int op0, result, z, s, cy, ov;
|
|
|
|
/* Compute the result. */
|
|
op0 = State.regs[OP[0]];
|
|
result = ~op0;
|
|
|
|
/* Compute the condition codes. */
|
|
z = (result == 0);
|
|
s = (result & 0x80000000);
|
|
|
|
/* Store the result and condition codes. */
|
|
State.regs[OP[1]] = result;
|
|
State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
|
|
State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
|
|
}
|
|
|
|
/* set1 */
|
|
void
|
|
OP_7C0 ()
|
|
{
|
|
unsigned int op0, op1, op2;
|
|
int result, temp;
|
|
|
|
op0 = State.regs[OP[0]];
|
|
op1 = OP[1] & 0x7;
|
|
temp = OP[2];
|
|
temp = (temp << 16) >> 16;
|
|
op2 = temp;
|
|
temp = get_byte (State.mem + op0 + op2);
|
|
State.sregs[5] &= ~PSW_Z;
|
|
if ((temp & (1 << op1)) == 0)
|
|
State.sregs[5] |= PSW_Z;
|
|
temp |= (1 << op1);
|
|
put_byte (State.mem + op0 + op2, temp);
|
|
}
|
|
|
|
/* not1 */
|
|
void
|
|
OP_47C0 ()
|
|
{
|
|
unsigned int op0, op1, op2;
|
|
int result, temp;
|
|
|
|
op0 = State.regs[OP[0]];
|
|
op1 = OP[1] & 0x7;
|
|
temp = OP[2];
|
|
temp = (temp << 16) >> 16;
|
|
op2 = temp;
|
|
temp = get_byte (State.mem + op0 + op2);
|
|
State.sregs[5] &= ~PSW_Z;
|
|
if ((temp & (1 << op1)) == 0)
|
|
State.sregs[5] |= PSW_Z;
|
|
temp ^= (1 << op1);
|
|
put_byte (State.mem + op0 + op2, temp);
|
|
}
|
|
|
|
/* clr1 */
|
|
void
|
|
OP_87C0 ()
|
|
{
|
|
unsigned int op0, op1, op2;
|
|
int result, temp;
|
|
|
|
op0 = State.regs[OP[0]];
|
|
op1 = OP[1] & 0x7;
|
|
temp = OP[2];
|
|
temp = (temp << 16) >> 16;
|
|
op2 = temp;
|
|
temp = get_byte (State.mem + op0 + op2);
|
|
State.sregs[5] &= ~PSW_Z;
|
|
if ((temp & (1 << op1)) == 0)
|
|
State.sregs[5] |= PSW_Z;
|
|
temp &= ~(1 << op1);
|
|
put_byte (State.mem + op0 + op2, temp);
|
|
}
|
|
|
|
/* tst1 */
|
|
void
|
|
OP_C7C0 ()
|
|
{
|
|
unsigned int op0, op1, op2;
|
|
int result, temp;
|
|
|
|
op0 = State.regs[OP[0]];
|
|
op1 = OP[1] & 0x7;
|
|
temp = OP[2];
|
|
temp = (temp << 16) >> 16;
|
|
op2 = temp;
|
|
temp = get_byte (State.mem + op0 + op2);
|
|
State.sregs[5] &= ~PSW_Z;
|
|
if ((temp & (1 << op1)) == 0)
|
|
State.sregs[5] |= PSW_Z;
|
|
}
|
|
|
|
/* di */
|
|
void
|
|
OP_16007E0 ()
|
|
{
|
|
State.sregs[5] |= PSW_ID;
|
|
}
|
|
|
|
/* ei */
|
|
void
|
|
OP_16087E0 ()
|
|
{
|
|
State.sregs[5] &= ~PSW_ID;
|
|
}
|
|
|
|
/* halt, not supported */
|
|
void
|
|
OP_12007E0 ()
|
|
{
|
|
State.exception = SIGQUIT;
|
|
}
|
|
|
|
/* reti, not supported */
|
|
void
|
|
OP_14007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* trap, not supportd */
|
|
void
|
|
OP_10007E0 ()
|
|
{
|
|
extern int errno;
|
|
|
|
/* Trap 0 is used for simulating low-level I/O */
|
|
|
|
if (OP[0] == 0)
|
|
{
|
|
#if 0
|
|
char *fstr = State.regs[2] + State.imem;
|
|
printf (fstr,State.regs[3],State.regs[4],State.regs[5]);
|
|
#else
|
|
int save_errno = errno;
|
|
errno = 0;
|
|
|
|
/* Registers passed to trap 0 */
|
|
|
|
#define FUNC State.regs[6] /* function number, return value */
|
|
#define PARM1 State.regs[7] /* optional parm 1 */
|
|
#define PARM2 State.regs[8] /* optional parm 2 */
|
|
#define PARM3 State.regs[9] /* optional parm 3 */
|
|
|
|
/* Registers set by trap 0 */
|
|
|
|
#define RETVAL State.regs[10] /* return value */
|
|
#define RETERR State.regs[11] /* return error code */
|
|
|
|
/* Turn a pointer in a register into a pointer into real memory. */
|
|
|
|
#define MEMPTR(x) ((char *)((x) + State.mem))
|
|
|
|
|
|
switch (FUNC)
|
|
{
|
|
#if 0
|
|
#if !defined(__GO32__) && !defined(_WIN32)
|
|
case SYS_fork:
|
|
RETVAL = fork ();
|
|
break;
|
|
case SYS_execve:
|
|
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
|
|
(char **)MEMPTR (PARM3));
|
|
break;
|
|
case SYS_execv:
|
|
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
|
|
break;
|
|
case SYS_pipe:
|
|
{
|
|
reg_t buf;
|
|
int host_fd[2];
|
|
|
|
buf = PARM1;
|
|
RETVAL = pipe (host_fd);
|
|
SW (buf, host_fd[0]);
|
|
buf += sizeof(uint16);
|
|
SW (buf, host_fd[1]);
|
|
}
|
|
break;
|
|
|
|
case SYS_wait:
|
|
{
|
|
int status;
|
|
|
|
RETVAL = wait (&status);
|
|
SW (PARM1, status);
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
case SYS_read:
|
|
RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
|
|
PARM3);
|
|
break;
|
|
#endif
|
|
case SYS_write:
|
|
if (PARM1 == 1)
|
|
RETVAL = (int)v850_callback->write_stdout (v850_callback,
|
|
MEMPTR (PARM2), PARM3);
|
|
else
|
|
RETVAL = (int)v850_callback->write (v850_callback, PARM1,
|
|
MEMPTR (PARM2), PARM3);
|
|
break;
|
|
#if 0
|
|
case SYS_lseek:
|
|
RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
|
|
break;
|
|
case SYS_close:
|
|
RETVAL = v850_callback->close (v850_callback, PARM1);
|
|
break;
|
|
case SYS_open:
|
|
RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
|
|
break;
|
|
#endif
|
|
case SYS_exit:
|
|
/* EXIT - caller can look in PARM1 to work out the
|
|
reason */
|
|
if (PARM1 == 0xdead || PARM1 == 0x1)
|
|
State.exception = SIGABRT;
|
|
else
|
|
State.exception = SIGQUIT;
|
|
break;
|
|
|
|
#if 0
|
|
case SYS_stat: /* added at hmsi */
|
|
/* stat system call */
|
|
{
|
|
struct stat host_stat;
|
|
reg_t buf;
|
|
|
|
RETVAL = stat (MEMPTR (PARM1), &host_stat);
|
|
|
|
buf = PARM2;
|
|
|
|
/* The hard-coded offsets and sizes were determined by using
|
|
* the D10V compiler on a test program that used struct stat.
|
|
*/
|
|
SW (buf, host_stat.st_dev);
|
|
SW (buf+2, host_stat.st_ino);
|
|
SW (buf+4, host_stat.st_mode);
|
|
SW (buf+6, host_stat.st_nlink);
|
|
SW (buf+8, host_stat.st_uid);
|
|
SW (buf+10, host_stat.st_gid);
|
|
SW (buf+12, host_stat.st_rdev);
|
|
SLW (buf+16, host_stat.st_size);
|
|
SLW (buf+20, host_stat.st_atime);
|
|
SLW (buf+28, host_stat.st_mtime);
|
|
SLW (buf+36, host_stat.st_ctime);
|
|
}
|
|
break;
|
|
|
|
case SYS_chown:
|
|
RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
|
|
break;
|
|
case SYS_chmod:
|
|
RETVAL = chmod (MEMPTR (PARM1), PARM2);
|
|
break;
|
|
case SYS_utime:
|
|
/* Cast the second argument to void *, to avoid type mismatch
|
|
if a prototype is present. */
|
|
RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
|
|
break;
|
|
#endif
|
|
default:
|
|
abort ();
|
|
}
|
|
RETERR = errno;
|
|
errno = save_errno;
|
|
#endif
|
|
}
|
|
else if (OP[0] == 1 )
|
|
{
|
|
char *fstr = State.regs[2] + State.mem;
|
|
puts (fstr);
|
|
}
|
|
}
|
|
|
|
/* ldsr, reg,reg */
|
|
void
|
|
OP_2007E0 ()
|
|
{
|
|
unsigned int op0;
|
|
|
|
op0 = State.regs[OP[0]];
|
|
State.sregs[OP[1]] = op0;
|
|
}
|
|
|
|
/* stsr, not supported */
|
|
void
|
|
OP_4007E0 ()
|
|
{
|
|
unsigned int op0;
|
|
|
|
op0 = State.sregs[OP[1]];
|
|
State.regs[OP[0]] = op0;
|
|
}
|
|
|