Andrew Cagney bc6df23d14 For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping ...

through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.

1997-12-08 03:22:58 +00:00

..

.Sanitize

Add DM (bit 4) to PSW. See 7-1 for more info.

1997-12-04 07:01:30 +00:00

ChangeLog

For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping

1997-12-08 03:22:58 +00:00

configure

Enable d10v simulator testsuite - two tests: Hello World and exit47.

1997-10-15 00:00:41 +00:00

configure.in

Enable d10v simulator testsuite - two tests: Hello World and exit47.

1997-10-15 00:00:41 +00:00

exit47.s

…

hello.s

Enable d10v simulator testsuite - two tests: Hello World and exit47.

1997-10-15 00:00:41 +00:00

loop.s

…

Makefile.in

Add DM (bit 4) to PSW. See 7-1 for more info.

1997-12-04 07:01:30 +00:00

t-mac.s

For MACU add unsigned multiply to accumulator.

1997-12-02 05:18:27 +00:00

t-macros.i

* d10v_sim.h (SEXT56): Define.

1997-12-03 08:03:33 +00:00

t-msbu.s

For "msbu", subtract unsigned product from ACC,

1997-12-02 07:18:53 +00:00

t-mulxu.s

For "mulxu", store unsigned product in ACC.

1997-12-02 06:37:09 +00:00

t-mvtac.s

Test mv[tf]ac instructions.

1997-12-02 05:31:33 +00:00

t-mvtc.s

Add DM (bit 4) to PSW. See 7-1 for more info.

1997-12-04 07:01:30 +00:00

t-rac.s

* d10v_sim.h (SEXT56): Define.

1997-12-03 08:03:33 +00:00

t-rachi.s

Test rachi instruction.

1997-11-10 08:27:15 +00:00

t-rep.s

* d10v_sim.h (SEXT56): Define.

1997-12-03 08:03:33 +00:00

t-sub2w.s

For sub2w, compute carry according to negated addition rules.

1997-12-02 00:27:27 +00:00

t-sub.s

For "sub", compute carry by comparing inputs.

1997-12-02 07:59:52 +00:00

t-subi.s

Test SUBI omsn

1997-11-17 22:36:19 +00:00