Files
binutils-gdb/sim/example-synacor
Mike Frysinger bc56166f66 sim: unify toolchain dependency logic
The common dir is already probing this info since it's using automake,
so pass it down to the subdirs so they don't have to probe it at all.
2021-06-19 16:07:31 -04:00
..
2021-06-18 00:50:14 -04:00

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.