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b625eff8a2346fe1107aa4ab7bbf4302f2c2136e
binutils-gdb/include/opcode
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Philipp Tomsich b625eff8a2 RISC-V: Support Zicond extension 
This implements the Zicond (conditional integer operations) extension,
    as of version 1.0-rc2.

    The Zicond extension acts as a building block for branchless sequences
    including conditional-arithmetic, conditional-logic and
    conditional-select/move.
    The following instructions constitute Zicond:
      - czero.eqz rd, rs1, rs2  =>  rd = (rs2 == 0) ? 0 : rs1
      - czero.nez rd, rs1, rs2  =>  rd = (rs2 != 0) ? 0 : rs1

    See
      https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf
    for the proposed specification and usage details.

    bfd/ChangeLog:

            * elfxx-riscv.c (riscv_multi_subset_supports): Recognize
            INSN_CLASS_ZICOND.
            (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND.

    gas/ChangeLog:

            * testsuite/gas/riscv/zicond.d: New test.
            * testsuite/gas/riscv/zicond.s: New test.

    include/ChangeLog:

            * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define.
            (MASK_CZERO_EQZ): Define.
            (MATCH_CZERO_NEZ): Define,
            (MASK_CZERO_NEZ): Define.
            (DECLARE_INSN): Add czero.eqz and czero.nez.
            * opcode/riscv.h (enum riscv_insn_class): Add
            INSN_CLASS_ZICOND.

    opcodes/ChangeLog:

            * riscv-opc.c: Add czero.eqz and czero.nez.

    Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-06-27 07:24:43 -06:00
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aarch64.h
aarch64: Remove stray reglist variable
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alpha.h
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arc-attrs.h
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arc-func.h
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arc.h
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arm.h
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avr.h
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bfin.h
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cgen.h
bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]
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ChangeLog-0415
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ChangeLog-9103
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convex.h
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cr16.h
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cris.h
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dlx.h
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ft32.h
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h8300.h
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hppa.h
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i386.h
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ia64.h
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loongarch.h
LoongArch: Support referring to FCSRs as $fcsrX
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m68hc11.h
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m68k.h
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metag.h
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mips.h
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mmix.h
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mn10200.h
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msp430.h
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np1.h
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pyr.h
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riscv-opc.h
RISC-V: Support Zicond extension
2023-06-27 07:24:43 -06:00
riscv.h
RISC-V: Support Zicond extension
2023-06-27 07:24:43 -06:00
rl78.h
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rx.h
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s12z.h
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s390.h
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score-datadep.h
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score-inst.h
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sparc.h
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spu-insns.h
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spu.h
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tic4x.h
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tic6x-control-registers.h
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tic6x-insn-formats.h
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tic6x-opcode-table.h
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tic6x.h
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