Srinath Parvathaneni b33f1bcd15 aarch64: Add SVE2.1 Contiguous load/store instructions. ...

Hi,

This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.

2024-01-15 11:45:42 +00:00

..

aarch64.h

aarch64: Add SVE2.1 Contiguous load/store instructions.

2024-01-15 11:45:42 +00:00

alpha.h

Update year range in copyright notice of binutils files

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arc-attrs.h

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arc-func.h

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arc.h

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arm.h

arm: Add support for Armv8.9-A and Armv9.4-A

2024-01-08 14:13:40 +00:00

avr.h

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2024-01-04 22:58:12 +10:30

bfin.h

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bpf.h

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cgen.h

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ChangeLog-0415

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ChangeLog-9103

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convex.h

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cr16.h

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cris.h

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crx.h

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csky.h

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d10v.h

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d30v.h

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dlx.h

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ft32.h

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h8300.h

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hppa.h

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i386.h

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ia64.h

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kvx.h

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loongarch.h

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m68hc11.h

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m68k.h

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metag.h

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mips.h

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mmix.h

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mn10200.h

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mn10300.h

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moxie.h

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msp430-decode.h

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msp430.h

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nds32.h

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nfp.h

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nios2.h

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nios2r1.h

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nios2r2.h

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np1.h

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ns32k.h

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pdp11.h

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pj.h

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pn.h

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ppc.h

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pru.h

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pyr.h

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riscv-opc.h

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riscv.h

RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli

2024-01-05 09:59:48 +08:00

rl78.h

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rx.h

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s12z.h

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s390.h

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score-datadep.h

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score-inst.h

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sparc.h

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spu-insns.h

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spu.h

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tic4x.h

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tic6x-control-registers.h

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tic6x-insn-formats.h

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tic6x-opcode-table.h

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tic6x.h

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tic30.h

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tic54x.h

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tilegx.h

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tilepro.h

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v850.h

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vax.h

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visium.h

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wasm.h

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xgate.h

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