Mike Frysinger aea0b94653 sim: cgen: regenerate decode tables ...

Integrate some changes from upstream cgen that tightened up the
generated output.  Shouldn't be any functional changes here.

2023-12-24 04:07:32 -05:00

..

arch.c

sim regen

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arch.h

sim regen

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ChangeLog-2021

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cpu.c

sim regen

2023-08-19 12:41:32 +09:30

cpu.h

sim regen

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cpuall.h

sim regen

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decode.c

sim: cgen: regenerate decode tables

2023-12-24 04:07:32 -05:00

decode.h

sim regen

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dv-lm32cpu.c

sim: lm32: fix -Wunused-variable warnings

2023-12-19 05:51:10 -05:00

dv-lm32timer.c

sim: lm32: fix -Wunused-variable warnings

2023-12-19 05:51:10 -05:00

dv-lm32uart.c

sim: lm32: fix -Wunused-variable warnings

2023-12-19 05:51:10 -05:00

lm32-sim.h

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lm32.c

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local.mk

sim: cgen: unify the genmloop logic a bit

2023-12-20 21:24:40 -05:00

mloop.in

sim: mloop: add #line pragmas everywhere

2023-12-21 20:16:26 -05:00

model.c

sim regen

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sem-switch.c

sim regen

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sem.c

sim regen

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sim-if.c

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sim-main.h

sim: signal: mark signal callback funcs as noreturn since they don't return

2023-12-21 01:59:22 -05:00

traps.c

sim: lm32: fix -Wunused-variable warnings

2023-12-19 05:51:10 -05:00

user.c

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