forked from Imagelibrary/binutils-gdb
3224e32fb8
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>
96 lines
1.2 KiB
ArmAsm
96 lines
1.2 KiB
ArmAsm
# Basic Tests for C extension.
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# mach: riscv32 riscv64
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# sim(riscv32): --model RV32IC
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# sim(riscv64): --model RV64IC
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# ld(riscv32): -m elf32lriscv
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# ld(riscv64): -m elf64lriscv
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# as(riscv32): -march=rv32ic
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# as(riscv64): -march=rv64ic
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.include "testutils.inc"
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.data
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.align 4
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_data:
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.word 1234
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.word 0
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start
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la a0, _data
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# Test load-store instructions.
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c.lw a1,0(a0)
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c.sw a1,4(a0)
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c.lw a2,4(a0)
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li a5,1234
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bne a1,a5,test_fail
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bne a2,a5,test_fail
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# Test basic arithmetic.
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c.li a0,0
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c.li a1,1
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c.addi a0,1
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c.addi a0,-1
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c.add a0,a1
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c.sub a0,a1
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li a5,1
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bne a0,x0,test_fail
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bne a1,a5,test_fail
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# Test logical operations.
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c.li a0,7
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c.li a1,7
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c.li a2,4
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c.li a3,3
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c.li a4,3
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c.andi a0,3
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c.and a1,a0
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c.or a2,a3
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c.xor a4,a4
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li a5,3
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bne a0,a5,test_fail
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bne a1,a5,test_fail
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bne a4,x0,test_fail
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li a5,7
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bne a2,a5,test_fail
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# Test shift operations.
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c.li a0,4
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c.li a1,4
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c.slli a0,1
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c.srli a1,1
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li a5,8
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bne a0,a5,test_fail
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li a5,2
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bne a1,a5,test_fail
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# Test jump instruction.
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c.j 1f
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j test_fail
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1:
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la a0,2f
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# Test jump register instruction.
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c.jr a0
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j test_fail
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2:
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# Test branch instruction.
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c.li a0,1
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c.beqz a0,test_fail
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c.li a0,0
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c.bnez a0,test_fail
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test_pass:
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pass
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fail
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test_fail:
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fail
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