forked from Imagelibrary/binutils-gdb
9c87d6c7e4
parameters. Added support for new opcode-list format. General error message fixups. (c4x_inst_add): Reject insn not for our CPU (md_begin): Added matrix for setting the proper opcode-level & device-flags according to cpu type and revision. Rewrite the opcode hasher. (c4x_operand_parse): Fix opcode bug (c4x_operands_match): New function argument. Added dry-run mechanism, that is optional error generation. Added constraint 'i' and 'j'. (c4x_insn_check): Added new function for post-verification of the generated insn. (md_assemble): Check all opcodes before croaking because of an argument mismatch. Need this to be able to fully support ortogonally arguments. (md_parse_options): Revised commandprompt swicthes and added new ones. (md_show_usage): Complete rewrite of printout. * gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn * gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter * gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter * gas/testsuite/gas/tic4x/allopcodes.S: Add support for new opclass.h changes * gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for the new enhanced opcodes. * gas/testsuite/gas/tic4x/opcodes.s: Regenerate * gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above * gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for the enhanced and special insns. * gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite * include/opcode/tic4x.h: File reordering. Added enhanced opcodes. * opcodes/tic4x-dis.c: Added support for enhanced and special insn. (c4x_print_op): Added insn class 'i' and 'j' (c4x_hash_opcode_special): Add to support special insn (c4x_hash_opcode): Update to support the new opcode-list format. Add support for the new special insns. (c4x_disassemble): New opcode-list support.
372 lines
12 KiB
ArmAsm
372 lines
12 KiB
ArmAsm
;;
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;; test all addressing modes and register constraints
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;; (types/classes is read from include/opcodes/tic4x.h)
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;;
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.text
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start:
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;;
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;; Type B - infix condition branch
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;;
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Type_BI:bu Type_BI ; Unconditional branch (00000)
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bc Type_BI ; Carry branch (00001)
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blo Type_BI ; Lower than branch (00001)
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bls Type_BI ; Lower than or same branch (00010)
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bhi Type_BI ; Higher than branch (00011)
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bhs Type_BI ; Higher than or same branch (00100)
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bnc Type_BI ; No carry branch (00100)
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beq Type_BI ; Equal to branch (00101)
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bz Type_BI ; Zero branch (00101)
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bne Type_BI ; Not equal to branch (00110)
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bnz Type_BI ; Not zero branch (00110)
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blt Type_BI ; Less than branch (00111)
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bn Type_BI ; Negative branch (00111)
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ble Type_BI ; Less than or equal to branch (01000)
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bgt Type_BI ; Greater than branch (01001)
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bp Type_BI ; Positive branch (01001)
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bge Type_BI ; Greater than or equal branch (01010)
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bnn Type_BI ; Nonnegative branch (01010)
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bnv Type_BI ; No overflow branch (01000)
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bv Type_BI ; Overflow branch (01101)
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bnuf Type_BI ; No underflow branch (01110)
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buf Type_BI ; Underflow branch (01111)
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bnlv Type_BI ; No latched overflow branch (10000)
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blv Type_BI ; Latched overflow branch (10001)
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bnluf Type_BI ; No latched FP underflow branch (10010)
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bluf Type_BI ; Latched FP underflow branch (10011)
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bzuf Type_BI ; Zero or FP underflow branch (10100)
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b Type_BI ; Unconditional branch (00000)
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;;
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;; Type C - infix condition load
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;;
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Type_CI:ldiu R0,R0 ; Unconditional load (00000)
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ldic R0,R0 ; Carry load (00001)
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ldilo R0,R0 ; Lower than load (00001)
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ldils R0,R0 ; Lower than or same load (00010)
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ldihi R0,R0 ; Higher than load (00011)
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ldihs R0,R0 ; Higher than or same load (00100)
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ldinc R0,R0 ; No carry load (00100)
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ldieq R0,R0 ; Equal to load (00101)
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ldiz R0,R0 ; Zero load (00101)
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ldine R0,R0 ; Not equal to load (00110)
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ldinz R0,R0 ; Not zero load (00110)
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ldil R0,R0 ; Less than load (00111)
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ldin R0,R0 ; Negative load (00111)
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ldile R0,R0 ; Less than or equal to load (01000)
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ldigt R0,R0 ; Greater than load (01001)
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ldip R0,R0 ; Positive load (01001)
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ldige R0,R0 ; Greater than or equal load (01010)
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ldinn R0,R0 ; Nonnegative load (01010)
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ldinv R0,R0 ; No overflow load (01000)
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ldiv R0,R0 ; Overflow load (01101)
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ldinuf R0,R0 ; No underflow load (01110)
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ldiuf R0,R0 ; Underflow load (01111)
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ldinlv R0,R0 ; No latched overflow load (10000)
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ldilv R0,R0 ; Latched overflow load (10001)
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ldinluf R0,R0 ; No latched FP underflow load (10010)
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ldiluf R0,R0 ; Latched FP underflow load (10011)
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ldizuf R0,R0 ; Zero or FP underflow load (10100)
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;;
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;; Type * - Indirect (full)
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;;
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Type_ind:
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ldi *AR0,R0 ; Indirect addressing (G=10)
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ldi *+AR0(5),R0 ; with predisplacement add
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ldi *-AR0(5),R0 ; with predisplacement subtract
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ldi *++AR0(5),R0 ; with predisplacement add and modify
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ldi *--AR0(5),R0 ; with predisplacement subtract and modify
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ldi *AR0++(5),R0 ; with postdisplacement add and modify
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ldi *AR0--(5),R0 ; with postdisplacement subtract and modify
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ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify
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ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify
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ldi *+AR0(IR0),R0 ; with predisplacement add
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ldi *-AR0(IR0),R0 ; with predisplacement subtract
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ldi *++AR0(IR0),R0 ; with predisplacement add and modify
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ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify
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ldi *AR0++(IR0),R0 ; with postdisplacement add and modify
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ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify
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ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify
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ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify
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ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify
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ldi *AR0++,R0 ; Same as *AR0++(1)
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;;
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;; Type # - Direct for ldp
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;;
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Type_ldp:
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ldp 12
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ldp @start
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ldp start
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;;
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;; Type @ - Direct
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;;
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Type_dir:
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ldi @start,R0
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ldi start,R0
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ldi @16,R0
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ldi @65535,R0
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;;
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;; Type A - Address register
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;;
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Type_A: dbc AR0,R0
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dbc AR2,R0
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dbc AR7,R0
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;;
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;; Type B - Unsigned integer (PC)
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;;
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Type_B: br start
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br 0x809800
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;;
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;; Type C - Indirect
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;;
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.ifdef TEST_C4X
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Type_C: addc3 *+AR0(5),R0,R0
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.endif
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;;
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;; Type E - Register (all)
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;;
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Type_E: andn3 R0,R0,R0
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andn3 AR0,R0,R0
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addc3 DP,R0,R0
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andn3 R7,R0,R0
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;;
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;; Type e - Register (0-11)
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;;
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Type_ee:subf3 R7,R0,R0
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addf3 R0,R0,R0
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addf3 R7,R0,R0
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cmpf3 R7,R0
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.ifdef TEST_C4X
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addf3 R11,R0,R0
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.endif
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;;
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;; Type F - Short float immediate
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;;
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Type_F: ldf 0,R0
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ldf 3.5,R0
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ldf -3.5,R0
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ldf 0e-3.5e-1,R0
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;;
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;; Type G - Register (all)
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;;
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Type_G: andn3 R0,AR0,R0
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addc3 R0,DP,R0
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addc3 R0,R0,R0
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andn3 R0,R7,R0
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;;
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;; Type g - Register (0-11)
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;;
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Type_gg:subf3 R0,R7,R0
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addf3 R0,R0,R0
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addf3 R0,R7,R0
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cmpf3 R0,R7
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.ifdef TEST_C4X
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addf3 R0,R11,R0
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.endif
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;;
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;; Type H - Register (0-7)
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;;
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Type_H: stf R0,*AR0 &|| stf R0,*AR0
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stf R0,*AR0 &|| stf R2,*AR0
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stf R0,*AR0 &|| stf R7,*AR0
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;;
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;; Type I - Indirect
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;;
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Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10)
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addf3 *+AR0(1),R0,R0 ; with predisplacement add
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addf3 *-AR0(1),R0,R0 ; with predisplacement subtract
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addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify
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addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify
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addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify
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addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify
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addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify
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addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify
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addf3 *+AR0(IR0),R0,R0; with predisplacement add
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addf3 *-AR0(IR0),R0,R0; with predisplacement subtract
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addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify
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addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify
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addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify
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addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify
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addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify
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addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify
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addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify
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addf3 *AR0++,R0,R0 ; Same as *AR0++(1)
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;;
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;; Type J - Indirect
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;;
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Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
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addf3 R0,*+AR0(1),R0 ; with predisplacement add
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addf3 R0,*-AR0(1),R0 ; with predisplacement subtract
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addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify
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addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify
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addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify
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addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify
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addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify
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addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify
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addf3 R0,*+AR0(IR0),R0; with predisplacement add
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addf3 R0,*-AR0(IR0),R0; with predisplacement subtract
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addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify
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addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify
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addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify
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addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify
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addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify
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addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify
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addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify
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addf3 R0,*AR0++,R0 ; Same as *AR0++(1)
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;;
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;; Type K - Register (0-7)
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;;
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Type_K: ldf *AR0,R0 &|| ldf *AR0,R1
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ldf *AR0,R0 &|| ldf *AR0,R2
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ldf *AR0,R0 &|| ldf *AR0,R7
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;;
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;; Type L - Register (0-7)
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;;
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Type_L: stf R0,*AR0 &|| stf R0,*AR0
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stf R2,*AR0 &|| stf R0,*AR0
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stf R7,*AR0 &|| stf R0,*AR0
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;;
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;; Type M - Register (2-3)
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;;
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Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
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mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3
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;;
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;; Type N - Register (0-1)
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;;
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Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
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mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2
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;;
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;; Type O - Indirect
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;;
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.ifdef TEST_C4X
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Type_O: addc3 *+AR0(5),*+AR0(5),R0
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.endif
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;;
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;; Type P - Displacement (PC rel)
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;;
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Type_P: callc start
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callc 1
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;;
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;; Type Q - Register (all)
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;;
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Type_Q: ldi R0,R0
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ldi AR0,R0
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ldi DP,R0
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ldi SP,R0
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;;
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;; Type q - Register (0-11)
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;;
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Type_qq:fix R0,R0
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fix R7,R0
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.ifdef TEST_C4X
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fix R11,R0
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absf R11,R0
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.endif
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;;
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;; Type R - Register (all)
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;;
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Type_R: ldi R0,R0
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ldi R0,AR0
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ldi R0,DP
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ldi R0,SP
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;;
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;; Type r - Register (0-11)
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;;
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Type_rr:ldf R0,R0
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ldf R0,R7
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.ifdef TEST_C4X
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ldf R0,R11
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.endif
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;;
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;; Type S - Signed immediate
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;;
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Type_S: ldi 0,R0
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ldi -123,R0
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ldi 6543,R0
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ldi -32768, R0
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;;
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;; Type T - Integer
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;;
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.ifdef TEST_C4X
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Type_T: stik 0,*AR0
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stik 12,*AR0
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stik -5,*AR0
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.endif
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;;
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;; Type U - Unsigned integer
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;;
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Type_U: and 0,R0
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and 256,R0
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and 65535,R0
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;;
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;; Type V - Vector
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;;
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Type_V: trapu 12
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trapu 0
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trapu 31
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.ifdef TEST_C4X
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trapu 511
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.endif
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;;
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;; Type W - Short int
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;;
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.ifdef TEST_C4X
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Type_W: addc3 -3,R0,R0
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addc3 5,R0,R0
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.endif
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;;
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;; Type X - Expansion register
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;;
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.ifdef TEST_C4X
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Type_X: ldep IVTP,R0
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ldep TVTP,R0
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.endif
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;;
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;; Type Y - Address register
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;;
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.ifdef TEST_C4X
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Type_Y: lda R0,AR0
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lda R0,DP
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lda R0,SP
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lda R0,IR0
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.endif
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;;
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;; Type Z - Expansion register
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;;
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.ifdef TEST_C4X
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Type_Z: ldpe R0,IVTP
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ldpe R0,TVTP
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.endif
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