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80e61ea097e7a5c272e2d4f6f15a72a226779569
binutils-gdb/sim
History
Mike Frysinger 80e61ea097 sim: m32c: rename open symbol to avoid collisions 
If the header files define open(), make sure our local open var
doesn't shadow it.
2021-05-29 12:03:27 -04:00
..
aarch64
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
arm
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
avr
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
bfin
sim: bfin: fix the otp fix fix
2021-05-28 23:31:24 -04:00
bpf
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
common
sim: leverage gnulib
2021-05-29 11:56:43 -04:00
cr16
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
cris
opcodes: cris: move desc & opc files from sim/
2021-05-24 18:42:34 -04:00
d10v
sim/d10v: Use offsetof in a static assertion about structure layout.
2021-05-21 17:27:05 -07:00
erc32
sim: switch config.h usage to defs.h
2021-05-16 22:38:41 -04:00
example-synacor
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
frv
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
ft32
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
h8300
sim: h8300 Fixed different behavior in preinc/predec.
2021-05-28 21:14:24 +09:00
igen
sim: add support for build-time ar & ranlib
2021-05-04 08:22:07 -04:00
iq2000
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
lm32
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
m4
sim: riscv: move __int128 check to configure
2021-05-16 00:04:17 -04:00
m32c
sim: m32c: rename open symbol to avoid collisions
2021-05-29 12:03:27 -04:00
m32r
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
m68hc11
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
mcore
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
microblaze
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
mips
sim: mips: Add shadow mappings for 32-bit memory address space
2021-05-22 11:32:35 +05:30
mn10300
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
moxie
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
msp430
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
or1k
sim: cgen: invert sim_state storage for cgen ports
2021-05-17 00:46:32 -04:00
ppc
sim: leverage gnulib
2021-05-29 11:56:43 -04:00
pru
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
riscv
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
rl78
sim: rl78: rename open symbol to avoid collisions
2021-05-23 17:40:32 -04:00
rx
sim: switch config.h usage to defs.h
2021-05-16 22:38:41 -04:00
sh
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
testsuite
sim: h8300 add special case test.
2021-05-28 21:14:24 +09:00
v850
sim: fully merge sim_state_base into sim_state
2021-05-17 01:05:08 -04:00
.gitignore
…
aclocal.m4
sim: unify toolchain settings
2021-04-02 23:31:14 -04:00
ChangeLog
sim: install library header files
2021-05-16 22:42:02 -04:00
configure
sim: add support for build-time ar & ranlib
2021-05-04 08:22:07 -04:00
configure.ac
sim: example-synacor: a simple implementation for reference
2021-04-03 16:19:16 -04:00
MAINTAINERS
…
Makefile.am
sim: install library header files
2021-05-16 22:42:02 -04:00
Makefile.in
sim: install library header files
2021-05-16 22:42:02 -04:00
README-HACKING
sim: create header namespace
2021-05-14 00:41:05 -04:00