forked from Imagelibrary/binutils-gdb
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
303 lines
6.8 KiB
ArmAsm
303 lines
6.8 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp
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// Spec Reference: comp3op pregs + pregs << 1
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 p1, 0x89ab1def;
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imm32 p2, 0x56781abc;
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imm32 p3, 0xdef01234;
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imm32 p4, 0x23451899;
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imm32 p5, 0x78911345;
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imm32 sp, 0x98761432;
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imm32 fp, 0x12341678;
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P1 = P1 + ( P1 << 1 );
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P2 = P1 + ( P2 << 1 );
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P3 = P1 + ( P3 << 1 );
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P4 = P1 + ( P4 << 1 );
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P5 = P1 + ( P5 << 1 );
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SP = P1 + ( SP << 1 );
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FP = P1 + FP;
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CHECKREG p1, 0x9D0159CD;
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CHECKREG p2, 0x49F18F45;
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CHECKREG p3, 0x5AE17E35;
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CHECKREG p4, 0xE38B8AFF;
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CHECKREG p5, 0x8E238057;
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CHECKREG sp, 0xCDED8231;
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CHECKREG fp, 0xAF357045;
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imm32 p1, 0x89abcd2f;
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imm32 p2, 0x56789a2c;
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imm32 p3, 0xdef01224;
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imm32 p4, 0x23456829;
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imm32 p5, 0x78912325;
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imm32 sp, 0x98765422;
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imm32 fp, 0x12345628;
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P1 = P2 + ( P1 << 1 );
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P2 = P2 + ( P2 << 1 );
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P3 = P2 + ( P3 << 1 );
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P4 = P2 + ( P4 << 1 );
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P5 = P2 + ( P5 << 1 );
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SP = P2 + ( SP << 1 );
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FP = P2 + ( FP << 1 );
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CHECKREG p1, 0x69D0348A;
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CHECKREG p2, 0x0369CE84;
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CHECKREG p3, 0xC149F2CC;
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CHECKREG p4, 0x49F49ED6;
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CHECKREG p5, 0xF48C14CE;
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CHECKREG sp, 0x345676C8;
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CHECKREG fp, 0x27D27AD4;
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imm32 p1, 0x89abcde3;
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imm32 p2, 0x56789ab3;
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imm32 p3, 0xdef01233;
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imm32 p4, 0x23456893;
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imm32 p5, 0x78912343;
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imm32 sp, 0x98765433;
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imm32 fp, 0x12345673;
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P1 = P3 + ( P1 << 1 );
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P2 = P3 + ( P2 << 1 );
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P3 = P3 + ( P3 << 1 );
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P4 = P3 + ( P4 << 1 );
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P5 = P3 + ( P5 << 1 );
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SP = P3 + ( SP << 1 );
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FP = P3 + ( FP << 1 );
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CHECKREG p1, 0xF247ADF9;
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CHECKREG p2, 0x8BE14799;
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CHECKREG p3, 0x9CD03699;
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CHECKREG p4, 0xE35B07BF;
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CHECKREG p5, 0x8DF27D1F;
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CHECKREG sp, 0xCDBCDEFF;
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CHECKREG fp, 0xC138E37F;
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imm32 p1, 0x49abcdef;
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imm32 p2, 0x46789abc;
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imm32 p3, 0x4ef01234;
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imm32 p4, 0x43456899;
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imm32 p5, 0x48912345;
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imm32 sp, 0x48765432;
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imm32 fp, 0x42345678;
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P1 = P4 + ( P1 << 1 );
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P2 = P4 + ( P2 << 1 );
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P3 = P4 + ( P3 << 1 );
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P4 = P4 + ( P4 << 1 );
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P5 = P4 + ( P5 << 1 );
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SP = P4 + ( SP << 1 );
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FP = P4 + ( FP << 1 );
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CHECKREG p1, 0xD69D0477;
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CHECKREG p2, 0xD0369E11;
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CHECKREG p3, 0xE1258D01;
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CHECKREG p4, 0xC9D039CB;
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CHECKREG p5, 0x5AF28055;
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CHECKREG sp, 0x5ABCE22F;
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CHECKREG fp, 0x4E38E6BB;
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imm32 p1, 0x85abcdef;
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imm32 p2, 0x55789abc;
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imm32 p3, 0xd5f01234;
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imm32 p4, 0x25456899;
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imm32 p5, 0x75912345;
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imm32 sp, 0x95765432;
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imm32 fp, 0x15345678;
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P1 = P5 + ( P1 << 1 );
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P2 = P5 + ( P2 << 1 );
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P3 = P5 + ( P3 << 1 );
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P4 = P5 + ( P4 << 1 );
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P5 = P5 + ( P5 << 1 );
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SP = P5 + ( SP << 1 );
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FP = P5 + ( FP << 1 );
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CHECKREG p1, 0x80E8BF23;
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CHECKREG p2, 0x208258BD;
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CHECKREG p3, 0x217147AD;
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CHECKREG p4, 0xC01BF477;
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CHECKREG p5, 0x60B369CF;
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CHECKREG sp, 0x8BA01233;
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CHECKREG fp, 0x8B1C16BF;
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imm32 p1, 0x89a6cdef;
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imm32 p2, 0x56769abc;
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imm32 p3, 0xdef61234;
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imm32 p4, 0x23466899;
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imm32 p5, 0x78962345;
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imm32 sp, 0x98765432;
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imm32 fp, 0x12365678;
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P1 = SP + ( P1 << 1 );
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P2 = SP + ( P2 << 1 );
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P3 = SP + ( P3 << 1 );
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P4 = SP + ( P4 << 1 );
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P5 = SP + ( P5 << 1 );
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SP = SP + ( SP << 1 );
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FP = SP + ( FP << 1 );
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CHECKREG p1, 0xABC3F010;
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CHECKREG p2, 0x456389AA;
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CHECKREG p3, 0x5662789A;
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CHECKREG p4, 0xDF032564;
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CHECKREG p5, 0x89A29ABC;
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CHECKREG sp, 0xC962FC96;
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CHECKREG fp, 0xEDCFA986;
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imm32 p1, 0x89ab7def;
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imm32 p2, 0x56787abc;
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imm32 p3, 0xdef07234;
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imm32 p4, 0x23457899;
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imm32 p5, 0x78917345;
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imm32 sp, 0x98767432;
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imm32 fp, 0x12345678;
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P1 = FP + ( P1 << 1 );
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P2 = FP + ( P2 << 1 );
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P3 = FP + ( P3 << 1 );
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P4 = FP + ( P4 << 1 );
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P5 = FP + ( P5 << 1 );
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SP = FP + ( SP << 1 );
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FP = FP + ( FP << 1 );
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CHECKREG p1, 0x258B5256;
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CHECKREG p2, 0xBF254BF0;
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CHECKREG p3, 0xD0153AE0;
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CHECKREG p4, 0x58BF47AA;
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CHECKREG p5, 0x03573D02;
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CHECKREG sp, 0x43213EDC;
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CHECKREG fp, 0x369D0368;
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imm32 p1, 0x29ab1def;
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imm32 p2, 0x52781abc;
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imm32 p3, 0xde201234;
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imm32 p4, 0x23421899;
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imm32 p5, 0x78912345;
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imm32 sp, 0x98761232;
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imm32 fp, 0x12341628;
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P1 = P3 + ( P1 << 1 );
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P2 = P4 + ( P1 << 1 );
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P3 = P5 + ( P1 << 1 );
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P4 = SP + ( P1 << 1 );
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P5 = FP + ( P1 << 1 );
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FP = P1 + ( P1 << 1 );
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CHECKREG p1, 0x31764E12;
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CHECKREG p2, 0x862EB4BD;
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CHECKREG p3, 0xDB7DBF69;
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CHECKREG p4, 0xFB62AE56;
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CHECKREG p5, 0x7520B24C;
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CHECKREG fp, 0x9462EA36;
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imm32 p1, 0x893bcd2f;
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imm32 p2, 0x56739a2c;
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imm32 p3, 0x3ef03224;
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imm32 p4, 0x23456329;
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imm32 p5, 0x78312335;
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imm32 sp, 0x98735423;
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imm32 fp, 0x12343628;
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P1 = P4 + ( P2 << 1 );
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P2 = P5 + ( P2 << 1 );
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P3 = SP + ( P2 << 1 );
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P4 = FP + ( P2 << 1 );
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SP = P1 + ( P2 << 1 );
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FP = P2 + ( P2 << 1 );
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CHECKREG p1, 0xD02C9781;
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CHECKREG p2, 0x2518578D;
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CHECKREG p3, 0xE2A4033D;
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CHECKREG p4, 0x5C64E542;
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CHECKREG sp, 0x1A5D469B;
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CHECKREG fp, 0x6F4906A7;
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imm32 p1, 0x894bcde3;
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imm32 p2, 0x56749ab3;
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imm32 p3, 0x4ef04233;
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imm32 p4, 0x24456493;
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imm32 p5, 0x78412344;
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imm32 sp, 0x98745434;
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imm32 fp, 0x12344673;
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P1 = P5 + ( P3 << 1 );
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P2 = SP + ( P3 << 1 );
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P3 = FP + ( P3 << 1 );
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P5 = P1 + ( P3 << 1 );
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SP = P2 + ( P3 << 1 );
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FP = P3 + ( P3 << 1 );
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CHECKREG p1, 0x1621A7AA;
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CHECKREG p2, 0x3654D89A;
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CHECKREG p3, 0xB014CAD9;
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CHECKREG p5, 0x764B3D5C;
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CHECKREG sp, 0x967E6E4C;
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CHECKREG fp, 0x103E608B;
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imm32 p1, 0x49abc5ef;
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imm32 p2, 0x46789a5c;
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imm32 p3, 0x4ef01235;
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imm32 p4, 0x53456899;
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imm32 p5, 0x45912345;
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imm32 sp, 0x48565432;
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imm32 fp, 0x42355678;
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P1 = SP + ( P4 << 1 );
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P2 = FP + ( P4 << 1 );
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P4 = P1 + ( P4 << 1 );
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P5 = P2 + ( P4 << 1 );
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SP = P3 + ( P4 << 1 );
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FP = P4 + ( P4 << 1 );
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CHECKREG p1, 0xEEE12564;
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CHECKREG p2, 0xE8C027AA;
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CHECKREG p4, 0x956BF696;
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CHECKREG p5, 0x139814D6;
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CHECKREG sp, 0x79C7FF61;
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CHECKREG fp, 0xC043E3C2;
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imm32 p1, 0x85ab6def;
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imm32 p2, 0x657896bc;
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imm32 p3, 0xd6f01264;
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imm32 p4, 0x25656896;
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imm32 p5, 0x75962345;
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imm32 sp, 0x95766432;
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imm32 fp, 0x15345678;
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P1 = FP + ( P5 << 1 );
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P3 = P1 + ( P5 << 1 );
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P4 = P2 + ( P5 << 1 );
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P5 = P3 + ( P5 << 1 );
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SP = P4 + ( P5 << 1 );
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FP = P5 + ( P5 << 1 );
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CHECKREG p1, 0x00609D02;
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CHECKREG p3, 0xEB8CE38C;
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CHECKREG p4, 0x50A4DD46;
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CHECKREG p5, 0xD6B92A16;
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CHECKREG sp, 0xFE173172;
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CHECKREG fp, 0x842B7E42;
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imm32 p1, 0x89a7cdef;
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imm32 p2, 0x56767abc;
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imm32 p3, 0xdef61734;
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imm32 p4, 0x73466879;
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imm32 p5, 0x77962347;
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imm32 sp, 0x98765432;
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imm32 fp, 0x12375678;
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P2 = P1 + ( SP << 1 );
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P3 = P2 + ( SP << 1 );
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P4 = P3 + ( SP << 1 );
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P5 = P4 + ( SP << 1 );
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SP = P5 + ( SP << 1 );
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FP = SP + ( SP << 1 );
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CHECKREG p2, 0xBA947653;
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CHECKREG p3, 0xEB811EB7;
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CHECKREG p4, 0x1C6DC71B;
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CHECKREG p5, 0x4D5A6F7F;
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CHECKREG sp, 0x7E4717E3;
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CHECKREG fp, 0x7AD547A9;
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imm32 p1, 0x88ab78ef;
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imm32 p2, 0x56887a8c;
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imm32 p3, 0x8ef87238;
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imm32 p4, 0x28458899;
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imm32 p5, 0x78817845;
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imm32 sp, 0x98787482;
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imm32 fp, 0x12348678;
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P1 = P2 + ( FP << 1 );
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P2 = P3 + ( FP << 1 );
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P3 = P4 + ( FP << 1 );
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P4 = P5 + ( FP << 1 );
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P5 = SP + ( FP << 1 );
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SP = FP + ( FP << 1 );
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CHECKREG p1, 0x7AF1877C;
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CHECKREG p2, 0xB3617F28;
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CHECKREG p3, 0x4CAE9589;
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CHECKREG p4, 0x9CEA8535;
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CHECKREG p5, 0xBCE18172;
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CHECKREG sp, 0x369D9368;
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pass
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