Maciej W. Rozycki 5575639b8d MIPS: Make the CODE10 operand code consistent between ISAs ...

This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.

2014-08-26 13:44:34 +01:00

..

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Regenerate files for openrisk -> or1k change

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.gitignore

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aarch64-asm-2.c

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aarch64-dis.c

[AArch64 disassembler] Add missing checks of undefine encodings on

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aarch64-dis.h

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aarch64-tbl.h

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aclocal.m4

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arc-ext.h

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arc-opc.c

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arm-dis.c

ARM/opcodes: Fix negative hexadecimal offset disassembly

2014-08-22 16:42:12 +01:00

avr-dis.c

Add support for the AVR Tiny series of microcontrollers.

2014-07-01 10:20:17 +01:00

bfin-dis.c

opcodes: blackfin: convert ad-hoc ints to bfd_boolean

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cgen-asm.c

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cgen.sh

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ChangeLog

MIPS: Make the CODE10 operand code consistent between ISAs

2014-08-26 13:44:34 +01:00

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config.in

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configure

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configure.ac

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configure.com

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dis-init.c

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disassemble.c

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dlx-dis.c

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h8300-dis.c

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h8500-dis.c

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h8500-opc.h

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i370-opc.c

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i386-dis-evex.h

Add AVX512DQ instructions and their AVX512VL variants.

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i386-dis.c

Add AVX512DQ instructions and their AVX512VL variants.

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i386-gen.c

Add AVX512DQ instructions and their AVX512VL variants.

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i386-init.h

Add AVX512DQ instructions and their AVX512VL variants.

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i386-opc.c

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i386-opc.h

Add AVX512DQ instructions and their AVX512VL variants.

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i386-opc.tbl

Add AVX512DQ instructions and their AVX512VL variants.

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i386-reg.tbl

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i386-tbl.h

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ia64-raw.tbl

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ia64-waw.tbl

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MAINTAINERS

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Makefile.am

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Makefile.in

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makefile.vms

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microblaze-opcm.h

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micromips-opc.c

MIPS: Make the CODE10 operand code consistent between ISAs

2014-08-26 13:44:34 +01:00

mips16-opc.c

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mips-dis.c

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mips-formats.h

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mips-opc.c

[MIPS] Rename COPROC related macros

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mmix-dis.c

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moxie-dis.c

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moxie-opc.c

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msp430-decode.c

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msp430-dis.c

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mt-asm.c

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ns32k-dis.c

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opintl.h

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or1k-asm.c

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or1k-desc.c

or1k: add missing l.msync, l.psync and l.psync instructions.

2014-07-20 20:26:09 +03:00

or1k-desc.h

or1k: add missing l.msync, l.psync and l.psync instructions.

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or1k-dis.c

Whitespace fixes for cpu/or1k.opc

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or1k-ibld.c

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or1k-opc.c

or1k: add missing l.msync, l.psync and l.psync instructions.

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or1k-opc.h

or1k: add missing l.msync, l.psync and l.psync instructions.

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or1k-opinst.c

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rx-decode.c

Fix RX gas testsuite failures by accounting for new variations in the disassembler's output.

2014-03-19 09:38:25 +00:00

rx-decode.opc

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rx-dis.c

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s390-dis.c

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sparc-dis.c

This patch adds support for the hyperprivileged registers %hstick_offset

2014-03-19 16:43:41 +00:00

sparc-opc.c

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2014-06-02 13:11:17 +02:00

spu-dis.c

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stamp-h.in

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sysdep.h

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v850-opc.c

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2014-03-05 22:16:15 +10:30

vax-dis.c

Use sigsetjmp/siglongjmp in opcodes

2014-05-02 08:27:16 -07:00

w65-dis.c

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2014-03-05 22:16:15 +10:30

w65-opc.h

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xc16x-asm.c

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xc16x-desc.c

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xc16x-desc.h

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xc16x-dis.c

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xc16x-ibld.c

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xc16x-opc.c

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xc16x-opc.h

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xgate-dis.c

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xgate-opc.c

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xstormy16-asm.c

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xstormy16-desc.c

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xstormy16-desc.h

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xstormy16-dis.c

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xstormy16-ibld.c

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xstormy16-opc.c

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xstormy16-opc.h

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2014-03-05 22:16:15 +10:30

xtensa-dis.c

Use sigsetjmp/siglongjmp in opcodes

2014-05-02 08:27:16 -07:00

z8k-dis.c

Use sigsetjmp/siglongjmp in opcodes

2014-05-02 08:27:16 -07:00

z8k-opc.h

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z8kgen.c

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z80-dis.c

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