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binutils-gdb/opcodes
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Andrew Burgess 3a337a86d9 opcodes/riscv: add disassembler options support to libopcodes 
In preparation for the next commit, which will add GDB support for
RISC-V disassembler options, this commit restructures how the
disassembler options are managed within libopcodes.

The implementation provided here is based on this mailing list patch
which was never committed:

  https://sourceware.org/pipermail/binutils/2021-January/114944.html

which in turn took inspiration from the MIPS implementation of the
same feature.

The biggest changes from the original mailing list post are:

  1. The GDB changes have been split into a separate patch, and

  2. The `riscv_option_args_privspec` variable, which held the valid
  priv-spec values is now gone, instead we use the `riscv_priv_specs`
  array from bfd/cpu-riscv.c instead.

Co-authored-by: Simon Cook <simon.cook@embecosm.com>

include/ChangeLog:

	* dis-asm.h (disassembler_options_riscv): Declare.

opcodes/ChangeLog:

	* riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
	(riscv_options): New static global.
	(disassembler_options_riscv): New function.
	(print_riscv_disassembler_options): Rewrite to use
	disassembler_options_riscv.
2021-11-26 10:18:35 +00:00
..
po
Updated French translation for the opcodes directory.
2021-11-25 11:13:32 +00:00
.gitignore
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aarch64-asm-2.c
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-asm.c
Fix building the AArch64 assembler and disassembler when assertions are disabled.
2021-11-25 13:11:25 +00:00
aarch64-asm.h
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-dis-2.c
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-dis.c
Fix building the AArch64 assembler and disassembler when assertions are disabled.
2021-11-25 13:11:25 +00:00
aarch64-dis.h
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-gen.c
opcodes: constify aarch64_opcode_tables
2021-07-01 17:51:00 -04:00
aarch64-opc-2.c
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-opc.c
Fix building the AArch64 assembler and disassembler when assertions are disabled.
2021-11-25 13:11:25 +00:00
aarch64-opc.h
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aarch64-tbl.h
aarch64: [SME] SVE2 instructions added to support SME
2021-11-17 20:27:42 +00:00
aclocal.m4
Implement a workaround for GNU mak jobserver
2021-01-12 05:45:44 -08:00
alpha-dis.c
Update year range in copyright notice of binutils files
2021-01-01 10:31:05 +10:30
alpha-opc.c
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2021-01-01 10:31:05 +10:30
arc-dis.c
arc: Construct disassembler options dynamically
2021-06-02 15:32:58 +03:00
arc-dis.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
arc-ext-tbl.h
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2021-01-01 10:31:05 +10:30
arc-ext.c
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2021-01-01 10:31:05 +10:30
arc-ext.h
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2021-01-01 10:31:05 +10:30
arc-fxi.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
arc-nps400-tbl.h
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arc-opc.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
arc-regs.h
opcodes: Fix the auxiliary register numbers for ARC HS
2021-08-17 18:33:05 +02:00
arc-tbl.h
Update year range in copyright notice of binutils files
2021-01-01 10:31:05 +10:30
arm-dis.c
arm: add armv9-a architecture to -march
2021-11-01 10:51:03 +00:00
avr-dis.c
Remove bfd_stdint.h
2021-03-31 10:49:23 +10:30
bfin-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
bpf-asm.c
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2021-01-01 10:31:05 +10:30
bpf-desc.c
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2021-01-01 10:31:05 +10:30
bpf-desc.h
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2021-01-01 10:31:05 +10:30
bpf-dis.c
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2021-01-01 10:31:05 +10:30
bpf-ibld.c
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2021-01-01 10:31:05 +10:30
bpf-opc.c
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2021-01-01 10:31:05 +10:30
bpf-opc.h
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2021-01-01 10:31:05 +10:30
cgen-asm.c
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cgen-asm.in
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2021-01-01 10:31:05 +10:30
cgen-bitset.c
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2021-01-01 10:31:05 +10:30
cgen-dis.c
opcodes: make use of __builtin_popcount when available
2021-06-22 09:53:13 +01:00
cgen-dis.in
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2021-01-01 10:31:05 +10:30
cgen-ibld.in
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2021-01-01 10:31:05 +10:30
cgen-opc.c
C99 opcodes configury
2021-04-05 15:28:04 +09:30
cgen.sh
opcodes: cris: move desc & opc files from sim/
2021-05-24 18:42:34 -04:00
ChangeLog
opcodes/riscv: add disassembler options support to libopcodes
2021-11-26 10:18:35 +00:00
ChangeLog-0001
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ChangeLog-0203
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ChangeLog-2004
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ChangeLog-2005
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ChangeLog-2010
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ChangeLog-2013
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ChangeLog-2014
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ChangeLog-2015
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ChangeLog-2016
PR27116, Spelling errors found by Debian style checker
2021-01-01 14:36:35 +10:30
ChangeLog-2017
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ChangeLog-2018
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ChangeLog-2019
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ChangeLog-2020
ChangeLog rotation
2021-01-01 10:31:02 +10:30
ChangeLog-9297
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ChangeLog-9899
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config.in
ENABLE_CHECKING in bfd, opcodes, binutils, ld
2021-04-13 00:35:44 +09:30
configure
Don't compile some opcodes files when bfd is 32-bit only
2021-11-12 19:02:12 +10:30
configure.ac
Don't compile some opcodes files when bfd is 32-bit only
2021-11-12 19:02:12 +10:30
configure.com
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2021-01-01 10:31:05 +10:30
cr16-dis.c
Remove strneq macro and use startswith.
2021-04-01 15:00:56 +02:00
cr16-opc.c
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2021-01-01 10:31:05 +10:30
cris-desc.c
Regen cris files
2021-05-25 17:17:04 +09:30
cris-desc.h
Regen cris files
2021-05-25 17:17:04 +09:30
cris-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
cris-opc.c
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2021-01-01 10:31:05 +10:30
cris-opc.h
Regen cris files
2021-05-25 17:17:04 +09:30
crx-dis.c
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2021-01-01 10:31:05 +10:30
crx-opc.c
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2021-01-01 10:31:05 +10:30
csky-dis.c
PR28168: [CSKY] Fix stack overflow in disassembler
2021-08-13 14:13:58 +08:00
csky-opc.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
d10v-dis.c
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2021-01-01 10:31:05 +10:30
d10v-opc.c
opcodes: d10v: simplify header includes
2021-11-02 22:57:52 -04:00
d30v-dis.c
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2021-01-01 10:31:05 +10:30
d30v-opc.c
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2021-01-01 10:31:05 +10:30
dep-in.sed
…
dis-buf.c
Return symbol from symbol_at_address_func
2021-04-06 23:25:09 +09:30
dis-init.c
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2021-01-01 10:31:05 +10:30
disassemble.c
Don't compile some opcodes files when bfd is 32-bit only
2021-11-12 19:02:12 +10:30
disassemble.h
LoongArch opcodes support
2021-10-24 21:36:31 +10:30
dlx-dis.c
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2021-01-01 10:31:05 +10:30
epiphany-asm.c
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2021-01-01 10:31:05 +10:30
epiphany-desc.c
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2021-01-01 10:31:05 +10:30
epiphany-desc.h
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2021-01-01 10:31:05 +10:30
epiphany-dis.c
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2021-01-01 10:31:05 +10:30
epiphany-ibld.c
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2021-01-01 10:31:05 +10:30
epiphany-opc.c
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2021-01-01 10:31:05 +10:30
epiphany-opc.h
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2021-01-01 10:31:05 +10:30
fr30-asm.c
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2021-01-01 10:31:05 +10:30
fr30-desc.c
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2021-01-01 10:31:05 +10:30
fr30-desc.h
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2021-01-01 10:31:05 +10:30
fr30-dis.c
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fr30-ibld.c
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2021-01-01 10:31:05 +10:30
fr30-opc.c
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2021-01-01 10:31:05 +10:30
fr30-opc.h
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2021-01-01 10:31:05 +10:30
frv-asm.c
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2021-01-01 10:31:05 +10:30
frv-desc.c
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2021-01-01 10:31:05 +10:30
frv-desc.h
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2021-01-01 10:31:05 +10:30
frv-dis.c
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2021-01-01 10:31:05 +10:30
frv-ibld.c
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2021-01-01 10:31:05 +10:30
frv-opc.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
frv-opc.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
ft32-dis.c
FT32: Remove recursion in ft32_opcode
2021-08-24 20:39:29 +09:30
ft32-opc.c
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2021-01-01 10:31:05 +10:30
h8300-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
hppa-dis.c
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2021-01-01 10:31:05 +10:30
i386-dis-evex-len.h
x86/Intel: correct AVX512 S/G disassembly
2021-03-10 08:20:29 +01:00
i386-dis-evex-mod.h
x86: drop xmm_m{b,w,d,q}_mode
2021-07-22 13:08:39 +02:00
i386-dis-evex-prefix.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-dis-evex-reg.h
x86/Intel: correct AVX512 S/G disassembly
2021-03-10 08:20:29 +01:00
i386-dis-evex-w.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-dis-evex.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-dis.c
x86: Print {bad} on invalid broadcast in OP_E_memory
2021-09-28 11:13:50 +08:00
i386-gen.c
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-init.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-opc.c
x86: drop seg_entry
2021-03-30 14:09:41 +02:00
i386-opc.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-opc.tbl
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
i386-reg.tbl
x86: adjust st(<N>) parsing
2021-03-30 14:08:11 +02:00
i386-tbl.h
[PATCH 1/2] Enable Intel AVX512_FP16 instructions
2021-08-05 21:03:41 +08:00
ia64-asmtab.c
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2021-01-01 10:31:05 +10:30
ia64-asmtab.h
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2021-01-01 10:31:05 +10:30
ia64-dis.c
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2021-01-01 10:31:05 +10:30
ia64-gen.c
Add startswith function and use it instead of CONST_STRNEQ.
2021-03-22 11:01:43 +01:00
ia64-ic.tbl
…
ia64-opc-a.c
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2021-01-01 10:31:05 +10:30
ia64-opc-b.c
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ia64-opc-d.c
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ia64-opc-f.c
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ia64-opc-i.c
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2021-01-01 10:31:05 +10:30
ia64-opc-m.c
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2021-01-01 10:31:05 +10:30
ia64-opc-x.c
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2021-01-01 10:31:05 +10:30
ia64-opc.c
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ia64-opc.h
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2021-01-01 10:31:05 +10:30
ia64-raw.tbl
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ia64-war.tbl
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ia64-waw.tbl
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ip2k-asm.c
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2021-01-01 10:31:05 +10:30
ip2k-desc.c
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2021-01-01 10:31:05 +10:30
ip2k-desc.h
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2021-01-01 10:31:05 +10:30
ip2k-dis.c
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2021-01-01 10:31:05 +10:30
ip2k-ibld.c
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2021-01-01 10:31:05 +10:30
ip2k-opc.c
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2021-01-01 10:31:05 +10:30
ip2k-opc.h
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2021-01-01 10:31:05 +10:30
iq2000-asm.c
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2021-01-01 10:31:05 +10:30
iq2000-desc.c
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2021-01-01 10:31:05 +10:30
iq2000-desc.h
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2021-01-01 10:31:05 +10:30
iq2000-dis.c
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2021-01-01 10:31:05 +10:30
iq2000-ibld.c
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2021-01-01 10:31:05 +10:30
iq2000-opc.c
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2021-01-01 10:31:05 +10:30
iq2000-opc.h
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2021-01-01 10:31:05 +10:30
lm32-asm.c
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2021-01-01 10:31:05 +10:30
lm32-desc.c
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2021-01-01 10:31:05 +10:30
lm32-desc.h
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2021-01-01 10:31:05 +10:30
lm32-dis.c
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lm32-ibld.c
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lm32-opc.c
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2021-01-01 10:31:05 +10:30
lm32-opc.h
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2021-01-01 10:31:05 +10:30
lm32-opinst.c
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2021-01-01 10:31:05 +10:30
loongarch-coder.c
LoongArch opcodes support
2021-10-24 21:36:31 +10:30
loongarch-dis.c
LoongArch opcodes support
2021-10-24 21:36:31 +10:30
loongarch-opc.c
LoongArch opcodes support
2021-10-24 21:36:31 +10:30
m32c-asm.c
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2021-01-01 10:31:05 +10:30
m32c-desc.c
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m32c-desc.h
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m32c-dis.c
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m32c-ibld.c
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m32c-opc.c
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m32c-opc.h
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m32r-asm.c
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m32r-desc.c
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m32r-desc.h
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m32r-dis.c
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2021-01-01 10:31:05 +10:30
m32r-ibld.c
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m32r-opc.c
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m32r-opc.h
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m32r-opinst.c
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2021-01-01 10:31:05 +10:30
m68hc11-dis.c
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2021-01-01 10:31:05 +10:30
m68hc11-opc.c
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2021-01-01 10:31:05 +10:30
m68k-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
m68k-opc.c
m68k: Require m68020up rather than m68000up for CHK.L instruction.
2021-01-07 14:45:10 +00:00
m10200-dis.c
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2021-01-01 10:31:05 +10:30
m10200-opc.c
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m10300-dis.c
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m10300-opc.c
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2021-01-01 10:31:05 +10:30
MAINTAINERS
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2021-01-01 10:31:05 +10:30
Makefile.am
Re: Don't compile some opcodes files when bfd is 32-bit only
2021-11-18 18:55:16 +10:30
Makefile.in
Re: Don't compile some opcodes files when bfd is 32-bit only
2021-11-18 18:55:16 +10:30
makefile.vms
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2021-01-01 10:31:05 +10:30
mcore-dis.c
PR1202, mcore disassembler: wrong address loopt
2021-06-03 13:05:57 +09:30
mcore-opc.h
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2021-01-01 10:31:05 +10:30
mep-asm.c
opcodes: constify & local meps macros
2021-07-01 18:04:16 -04:00
mep-desc.c
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2021-01-01 10:31:05 +10:30
mep-desc.h
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mep-dis.c
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mep-ibld.c
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mep-opc.c
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mep-opc.h
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2021-01-01 10:31:05 +10:30
metag-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
microblaze-dis.c
opcodes: constify & scope microblaze opcodes
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microblaze-dis.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
microblaze-opc.h
opcodes: constify & scope microblaze opcodes
2021-07-01 17:55:26 -04:00
microblaze-opcm.h
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2021-01-01 10:31:05 +10:30
micromips-opc.c
MIPS/opcodes: Do not use CP0 register names for control registers
2021-05-29 03:26:32 +02:00
mips16-opc.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
mips-dis.c
Correct gs264e bfd_mach in mips_arch_choices.
2021-07-27 09:18:27 +08:00
mips-formats.h
Use bool in opcodes
2021-03-31 10:49:23 +10:30
mips-opc.c
MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions
2021-05-29 03:26:33 +02:00
mmix-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
mmix-opc.c
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2021-01-01 10:31:05 +10:30
moxie-dis.c
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2021-01-01 10:31:05 +10:30
moxie-opc.c
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2021-01-01 10:31:05 +10:30
msp430-decode.c
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2021-01-01 10:31:05 +10:30
msp430-decode.opc
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2021-01-01 10:31:05 +10:30
msp430-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
mt-asm.c
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2021-01-01 10:31:05 +10:30
mt-desc.c
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2021-01-01 10:31:05 +10:30
mt-desc.h
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2021-01-01 10:31:05 +10:30
mt-dis.c
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2021-01-01 10:31:05 +10:30
mt-ibld.c
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2021-01-01 10:31:05 +10:30
mt-opc.c
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2021-01-01 10:31:05 +10:30
mt-opc.h
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2021-01-01 10:31:05 +10:30
nds32-asm.c
opcodes: cleanup nds32 variables
2021-07-01 18:03:02 -04:00
nds32-asm.h
Re: Fix minor NDS32 renaming snafu
2021-07-02 20:48:55 +09:30
nds32-dis.c
Re: Fix minor NDS32 renaming snafu
2021-07-02 20:48:55 +09:30
nds32-opc.h
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2021-01-01 10:31:05 +10:30
nfp-dis.c
Add a sanity check to the init_nfp6000_mecsr_sec() function in the NFP disassembler.
2021-09-06 10:44:29 +01:00
nios2-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
nios2-opc.c
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2021-01-01 10:31:05 +10:30
ns32k-dis.c
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2021-01-01 10:31:05 +10:30
opc2c.c
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2021-01-01 10:31:05 +10:30
opintl.h
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2021-01-01 10:31:05 +10:30
or1k-asm.c
or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()
2021-05-06 20:51:24 +09:00
or1k-desc.c
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2021-01-01 10:31:05 +10:30
or1k-desc.h
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2021-01-01 10:31:05 +10:30
or1k-dis.c
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2021-01-01 10:31:05 +10:30
or1k-ibld.c
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2021-01-01 10:31:05 +10:30
or1k-opc.c
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2021-01-01 10:31:05 +10:30
or1k-opc.h
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2021-01-01 10:31:05 +10:30
or1k-opinst.c
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2021-01-01 10:31:05 +10:30
pdp11-dis.c
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2021-01-01 10:31:05 +10:30
pdp11-opc.c
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2021-01-01 10:31:05 +10:30
pj-dis.c
pj: asan: out of bounds, ubsan: left shift of negative
2021-09-03 11:45:58 +09:30
pj-opc.c
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2021-01-01 10:31:05 +10:30
ppc-dis.c
PowerPC table driven -Mraw disassembly
2021-05-29 21:06:06 +09:30
ppc-opc.c
PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5
2021-09-25 18:21:17 -05:00
pru-dis.c
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2021-01-01 10:31:05 +10:30
pru-opc.c
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2021-01-01 10:31:05 +10:30
riscv-dis.c
opcodes/riscv: add disassembler options support to libopcodes
2021-11-26 10:18:35 +00:00
riscv-opc.c
RISC-V: Add instructions and operand set for z[fdq]inx
2021-11-18 14:43:23 +08:00
rl78-decode.c
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2021-01-01 10:31:05 +10:30
rl78-decode.opc
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2021-01-01 10:31:05 +10:30
rl78-dis.c
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2021-01-01 10:31:05 +10:30
rx-decode.c
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2021-01-01 10:31:05 +10:30
rx-decode.opc
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2021-01-01 10:31:05 +10:30
rx-dis.c
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2021-01-01 10:31:05 +10:30
s12z-dis.c
s12z/disassembler: call memory_error_func when appropriate
2021-10-11 14:07:03 +01:00
s12z-opc.c
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2021-01-01 10:31:05 +10:30
s12z-opc.h
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2021-01-01 10:31:05 +10:30
s390-dis.c
Add startswith function and use it instead of CONST_STRNEQ.
2021-03-22 11:01:43 +01:00
s390-mkopc.c
IBM Z: Implement instruction set extensions
2021-02-15 14:32:17 +01:00
s390-opc.c
IBM Z: Remove lpswey parameter
2021-08-04 16:51:50 +02:00
s390-opc.txt
IBM Z: Remove lpswey parameter
2021-08-04 16:51:50 +02:00
score7-dis.c
Remove strneq macro and use startswith.
2021-04-01 15:00:56 +02:00
score-dis.c
Remove strneq macro and use startswith.
2021-04-01 15:00:56 +02:00
score-opc.h
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2021-01-01 10:31:05 +10:30
sh-dis.c
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2021-01-01 10:31:05 +10:30
sh-opc.h
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2021-01-01 10:31:05 +10:30
sparc-dis.c
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2021-01-01 10:31:05 +10:30
sparc-opc.c
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2021-01-01 10:31:05 +10:30
spu-dis.c
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2021-01-01 10:31:05 +10:30
spu-opc.c
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2021-01-01 10:31:05 +10:30
stamp-h.in
…
sysdep.h
C99 opcodes configury
2021-04-05 15:28:04 +09:30
tic4x-dis.c
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2021-01-01 10:31:05 +10:30
tic6x-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
tic30-dis.c
Fix another strncpy warning
2021-06-19 11:08:55 +09:30
tic54x-dis.c
opcodes: tic54x: namespace exported variables
2021-02-08 18:26:08 -05:00
tic54x-opc.c
opcodes: tic54x: namespace exported variables
2021-02-08 18:26:08 -05:00
tilegx-dis.c
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2021-01-01 10:31:05 +10:30
tilegx-opc.c
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2021-01-01 10:31:05 +10:30
tilepro-dis.c
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2021-01-01 10:31:05 +10:30
tilepro-opc.c
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2021-01-01 10:31:05 +10:30
v850-dis.c
Use bool in opcodes
2021-03-31 10:49:23 +10:30
v850-opc.c
Fix the V850 assembler's generation of relocations for the st.b instruction.
2021-09-02 12:16:10 +01:00
vax-dis.c
ubsan: vax: pointer overflow
2021-06-19 11:08:56 +09:30
visium-dis.c
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2021-01-01 10:31:05 +10:30
visium-opc.c
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2021-01-01 10:31:05 +10:30
wasm32-dis.c
C99 opcodes configury
2021-04-05 15:28:04 +09:30
xc16x-asm.c
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2021-01-01 10:31:05 +10:30
xc16x-desc.c
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2021-01-01 10:31:05 +10:30
xc16x-desc.h
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2021-01-01 10:31:05 +10:30
xc16x-dis.c
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2021-01-01 10:31:05 +10:30
xc16x-ibld.c
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2021-01-01 10:31:05 +10:30
xc16x-opc.c
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2021-01-01 10:31:05 +10:30
xc16x-opc.h
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2021-01-01 10:31:05 +10:30
xgate-dis.c
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2021-01-01 10:31:05 +10:30
xgate-opc.c
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2021-01-01 10:31:05 +10:30
xstormy16-asm.c
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2021-01-01 10:31:05 +10:30
xstormy16-desc.c
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2021-01-01 10:31:05 +10:30
xstormy16-desc.h
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2021-01-01 10:31:05 +10:30
xstormy16-dis.c
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2021-01-01 10:31:05 +10:30
xstormy16-ibld.c
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2021-01-01 10:31:05 +10:30
xstormy16-opc.c
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2021-01-01 10:31:05 +10:30
xstormy16-opc.h
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2021-01-01 10:31:05 +10:30
xtensa-dis.c
opcodes: xtensa: support branch visualization
2021-05-01 02:47:30 -07:00
z8k-dis.c
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2021-01-01 10:31:05 +10:30
z8k-opc.h
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2021-01-01 10:31:05 +10:30
z8kgen.c
Update year range in copyright notice of binutils files
2021-01-01 10:31:05 +10:30
z80-dis.c
z80/disassembler: call memory_error_func when appropriate
2021-10-11 14:07:03 +01:00