Files
binutils-gdb/include/opcode/s390.h
Jens Remus a3f1e7c56a s390: Simplify (dis)assembly of insn operands with const bits
Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.

The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.

This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx

include/
	* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
	S390_OPERAND_OR8): Remove.

opcodes/
	* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
	(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
	as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
	(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
	respective insn fmt mask.
	(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
	Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
	mask.
	* s390-dis.c (s390_print_insn_with_opcode): Mask constant
	operand bits set in insn template of non-length unsigned
	integer operands.

gas/
	* config/tc-s390.c (s390_insert_operand): Do not OR constant
	operand value bits.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-12 15:06:06 +02:00

197 lines
6.0 KiB
C

/* s390.h -- Header file for S390 opcode table
Copyright (C) 2000-2024 Free Software Foundation, Inc.
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef S390_H
#define S390_H
/* List of instruction sets variations. */
enum s390_opcode_mode_val
{
S390_OPCODE_ESA = 0,
S390_OPCODE_ZARCH
};
enum s390_opcode_cpu_val
{
S390_OPCODE_G5 = 0,
S390_OPCODE_G6,
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
S390_OPCODE_Z9_EC,
S390_OPCODE_Z10,
S390_OPCODE_Z196,
S390_OPCODE_ZEC12,
S390_OPCODE_Z13,
S390_OPCODE_ARCH12,
S390_OPCODE_ARCH13,
S390_OPCODE_ARCH14,
S390_OPCODE_MAXCPU
};
/* Values defined for the flags field of a struct s390_opcode. */
/* Last one or two instruction operands are optional. */
#define S390_INSTR_FLAG_OPTPARM 0x1
#define S390_INSTR_FLAG_OPTPARM2 0x2
/* Instruction requires a specific facility. */
#define S390_INSTR_FLAG_HTM 0x4
#define S390_INSTR_FLAG_VX 0x8
#define S390_INSTR_FLAG_FACILITY_MASK 0xc
/* Instruction annotations for jump visualization. */
#define S390_INSTR_FLAG_CLASS_BRANCH 0x10
#define S390_INSTR_FLAG_CLASS_RELATIVE 0x20
#define S390_INSTR_FLAG_CLASS_CONDITIONAL 0x40
#define S390_INSTR_FLAG_CLASS_SUBROUTINE 0x80
#define S390_INSTR_FLAG_CLASS_MASK 0xf0
#define S390_INSTR_FLAGS_CLASS_JUMP \
(S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE)
#define S390_INSTR_FLAGS_CLASS_CONDJUMP \
(S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \
| S390_INSTR_FLAG_CLASS_CONDITIONAL)
#define S390_INSTR_FLAGS_CLASS_JUMPSR \
(S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \
| S390_INSTR_FLAG_CLASS_SUBROUTINE)
/* Instruction is an .insn pseudo-mnemonic. */
#define S390_INSTR_FLAG_PSEUDO_MNEMONIC 0x100
/* The opcode table is an array of struct s390_opcode. */
struct s390_opcode
{
/* The opcode name (mnemonic). */
const char * name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned char opcode[6];
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned char mask[6];
/* The opcode length in bytes. */
int oplen;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[6];
/* Bitmask of execution modes this opcode is available for. */
unsigned int modes;
/* First cpu this opcode is available for. */
enum s390_opcode_cpu_val min_cpu;
/* Instruction specific flags. */
unsigned int flags;
/* Instruction description. */
const char * description;
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct s390_opcode s390_opcodes[];
extern const int s390_num_opcodes;
/* A opcode format table for the .insn pseudo mnemonic. */
extern const struct s390_opcode s390_opformats[];
extern const int s390_num_opformats;
/* The operands table is an array of struct s390_operand. */
struct s390_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* One bit syntax flags. */
unsigned long flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the s390_opcodes table. */
extern const struct s390_operand s390_operands[];
/* Values defined for the flags field of a struct s390_operand. */
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define S390_OPERAND_GPR 0x1
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define S390_OPERAND_FPR 0x2
/* This operand names an access register. The disassembler
prints these with a leading 'a'. */
#define S390_OPERAND_AR 0x4
/* This operand names a control register. The disassembler
prints these with a leading 'c'. */
#define S390_OPERAND_CR 0x8
/* This operand is a displacement. */
#define S390_OPERAND_DISP 0x10
/* This operand names a base register. */
#define S390_OPERAND_BASE 0x20
/* This operand names an index register, it can be skipped. */
#define S390_OPERAND_INDEX 0x40
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define S390_OPERAND_PCREL 0x80
/* This operand takes signed values. */
#define S390_OPERAND_SIGNED 0x100
/* This operand is a length. */
#define S390_OPERAND_LENGTH 0x200
/* The operand needs to be a valid GP or FP register pair. */
#define S390_OPERAND_REG_PAIR 0x400
/* This operand names a vector register. The disassembler uses this
to print register names with a leading 'v'. */
#define S390_OPERAND_VR 0x800
#define S390_OPERAND_CP16 0x1000
#endif /* S390_H */