forked from Imagelibrary/binutils-gdb
db7858e227
The cgen code declares some macros/funcs using the trace_xxx prefix, but the code isn't generic and only works with cgen targets. This is blocking the creation of new common trace functions. Let's blindly add cgen_xxx prefixes to all these symbols. Some already use this convention to avoid conflicts, so it makes sense to align them. In the future we might want to move some to the common trace core, but one thing at a time.
438 lines
11 KiB
C
438 lines
11 KiB
C
/* Tracing support for CGEN-based simulators.
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Copyright (C) 1996-2015 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <errno.h>
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#include "dis-asm.h"
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#include "bfd.h"
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#include "sim-main.h"
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#include "sim-fpu.h"
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#ifndef SIZE_INSTRUCTION
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#define SIZE_INSTRUCTION 16
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#endif
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#ifndef SIZE_LOCATION
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#define SIZE_LOCATION 20
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#endif
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#ifndef SIZE_PC
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#define SIZE_PC 6
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#endif
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#ifndef SIZE_LINE_NUMBER
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#define SIZE_LINE_NUMBER 4
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#endif
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#ifndef SIZE_CYCLE_COUNT
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#define SIZE_CYCLE_COUNT 2
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#endif
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#ifndef SIZE_TOTAL_CYCLE_COUNT
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#define SIZE_TOTAL_CYCLE_COUNT 9
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#endif
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#ifndef SIZE_TRACE_BUF
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#define SIZE_TRACE_BUF 1024
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#endif
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/* Text is queued in TRACE_BUF because we want to output the insn's cycle
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count first but that isn't known until after the insn has executed.
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This also handles the queueing of trace results, TRACE_RESULT may be
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called multiple times for one insn. */
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static char trace_buf[SIZE_TRACE_BUF];
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/* If NULL, output to stdout directly. */
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static char *bufptr;
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/* Non-zero if this is the first insn in a set of parallel insns. */
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static int first_insn_p;
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/* For communication between cgen_trace_insn and cgen_trace_result. */
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static int printed_result_p;
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/* Insn and its extracted fields.
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Set by cgen_trace_insn, used by cgen_trace_insn_fini.
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??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
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static const struct cgen_insn *current_insn;
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static const struct argbuf *current_abuf;
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void
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cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
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{
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bufptr = trace_buf;
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*bufptr = 0;
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first_insn_p = first_p;
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/* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
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called. */
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current_insn = NULL;
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current_abuf = NULL;
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}
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void
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cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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/* Was insn traced? It might not be if trace ranges are in effect. */
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if (current_insn == NULL)
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return;
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/* The first thing printed is current and total cycle counts. */
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if (PROFILE_MODEL_P (cpu)
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&& ARGBUF_PROFILE_P (current_abuf))
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{
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unsigned long total = PROFILE_MODEL_TOTAL_CYCLES (CPU_PROFILE_DATA (cpu));
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unsigned long this_insn = PROFILE_MODEL_CUR_INSN_CYCLES (CPU_PROFILE_DATA (cpu));
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if (last_p)
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{
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trace_printf (sd, cpu, "%-*ld %-*ld ",
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SIZE_CYCLE_COUNT, this_insn,
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SIZE_TOTAL_CYCLE_COUNT, total);
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}
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else
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{
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trace_printf (sd, cpu, "%-*ld %-*s ",
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SIZE_CYCLE_COUNT, this_insn,
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SIZE_TOTAL_CYCLE_COUNT, "---");
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}
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}
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/* Print the disassembled insn. */
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trace_printf (sd, cpu, "%s", TRACE_PREFIX (CPU_TRACE_DATA (cpu)));
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#if 0
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/* Print insn results. */
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{
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const CGEN_OPINST *opinst = CGEN_INSN_OPERANDS (current_insn);
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if (opinst)
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{
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int i;
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int indices[MAX_OPERAND_INSTANCES];
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/* Fetch the operands used by the insn. */
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/* FIXME: Add fn ptr to CGEN_CPU_DESC. */
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CGEN_SYM (get_insn_operands) (CPU_CPU_DESC (cpu), current_insn,
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0, CGEN_FIELDS_BITSIZE (&insn_fields),
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indices);
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for (i = 0;
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CGEN_OPINST_TYPE (opinst) != CGEN_OPINST_END;
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++i, ++opinst)
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{
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if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
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cgen_trace_result (cpu, current_insn, opinst, indices[i]);
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}
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}
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}
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#endif
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/* Print anything else requested. */
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if (*trace_buf)
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trace_printf (sd, cpu, " %s\n", trace_buf);
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else
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trace_printf (sd, cpu, "\n");
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}
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void
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cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
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const struct argbuf *abuf, IADDR pc)
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{
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char disasm_buf[50];
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printed_result_p = 0;
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current_insn = opcode;
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current_abuf = abuf;
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if (CGEN_INSN_VIRTUAL_P (opcode))
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{
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trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, 0,
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NULL, 0, CGEN_INSN_NAME (opcode));
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return;
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}
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CPU_DISASSEMBLER (cpu) (cpu, opcode, abuf, pc, disasm_buf);
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trace_prefix (CPU_STATE (cpu), cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
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NULL, 0,
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"%s%-*s",
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first_insn_p ? " " : "|",
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SIZE_INSTRUCTION, disasm_buf);
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}
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void
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cgen_trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
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{
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va_list args;
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int printed_one_p = 0;
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char *fmt;
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va_start (args, name);
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trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
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SIZE_PC, (unsigned long) pc, name);
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do {
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int type,ival;
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fmt = va_arg (args, char *);
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if (fmt)
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{
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if (printed_one_p)
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trace_printf (CPU_STATE (cpu), cpu, ", ");
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printed_one_p = 1;
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type = va_arg (args, int);
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switch (type)
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{
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case 'x' :
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ival = va_arg (args, int);
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trace_printf (CPU_STATE (cpu), cpu, fmt, ival);
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break;
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default :
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abort ();
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}
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}
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} while (fmt);
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va_end (args);
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trace_printf (CPU_STATE (cpu), cpu, "\n");
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}
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void
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cgen_trace_result (SIM_CPU *cpu, char *name, int type, ...)
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{
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va_list args;
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va_start (args, type);
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if (printed_result_p)
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cgen_trace_printf (cpu, ", ");
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switch (type)
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{
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case 'x' :
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default :
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cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
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break;
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case 'f':
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{
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DI di;
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sim_fpu f;
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/* this is separated from previous line for sunos cc */
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di = va_arg (args, DI);
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sim_fpu_64to (&f, di);
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cgen_trace_printf (cpu, "%s <- ", name);
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sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
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break;
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}
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case 'D' :
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{
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DI di;
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/* this is separated from previous line for sunos cc */
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di = va_arg (args, DI);
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cgen_trace_printf (cpu, "%s <- 0x%x%08x", name,
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GETHIDI(di), GETLODI (di));
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break;
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}
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}
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printed_result_p = 1;
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va_end (args);
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}
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/* Print trace output to BUFPTR if active, otherwise print normally.
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This is only for tracing semantic code. */
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void
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cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...)
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{
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va_list args;
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va_start (args, fmt);
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if (bufptr == NULL)
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{
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if (TRACE_FILE (CPU_TRACE_DATA (cpu)) == NULL)
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(* STATE_CALLBACK (CPU_STATE (cpu))->evprintf_filtered)
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(STATE_CALLBACK (CPU_STATE (cpu)), fmt, args);
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else
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vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, args);
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}
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else
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{
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vsprintf (bufptr, fmt, args);
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bufptr += strlen (bufptr);
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/* ??? Need version of SIM_ASSERT that is always enabled. */
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if (bufptr - trace_buf > SIZE_TRACE_BUF)
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abort ();
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}
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va_end (args);
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}
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/* Disassembly support. */
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/* sprintf to a "stream" */
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int
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sim_disasm_sprintf (SFILE *f, const char *format, ...)
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{
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#ifndef __STDC__
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SFILE *f;
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const char *format;
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#endif
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int n;
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va_list args;
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va_start (args, format);
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#ifndef __STDC__
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f = va_arg (args, SFILE *);
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format = va_arg (args, char *);
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#endif
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vsprintf (f->current, format, args);
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f->current += n = strlen (f->current);
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va_end (args);
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return n;
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}
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/* Memory read support for an opcodes disassembler. */
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int
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sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
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struct disassemble_info *info)
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{
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SIM_CPU *cpu = (SIM_CPU *) info->application_data;
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SIM_DESC sd = CPU_STATE (cpu);
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unsigned length_read;
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length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
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length);
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if (length_read != length)
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return EIO;
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return 0;
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}
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/* Memory error support for an opcodes disassembler. */
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void
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sim_disasm_perror_memory (int status, bfd_vma memaddr,
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struct disassemble_info *info)
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{
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if (status != EIO)
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/* Can't happen. */
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info->fprintf_func (info->stream, "Unknown error %d.", status);
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else
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/* Actually, address between memaddr and memaddr + len was
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out of bounds. */
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info->fprintf_func (info->stream,
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"Address 0x%x is out of bounds.",
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(int) memaddr);
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}
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/* Disassemble using the CGEN opcode table.
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??? While executing an instruction, the insn has been decoded and all its
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fields have been extracted. It is certainly possible to do the disassembly
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with that data. This seems simpler, but maybe in the future the already
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extracted fields will be used. */
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void
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sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
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const ARGBUF *abuf, IADDR pc, char *buf)
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{
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unsigned int length;
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unsigned int base_length;
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unsigned long insn_value;
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struct disassemble_info disasm_info;
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SFILE sfile;
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union {
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unsigned8 bytes[CGEN_MAX_INSN_SIZE];
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unsigned16 shorts[8];
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unsigned32 words[4];
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} insn_buf;
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SIM_DESC sd = CPU_STATE (cpu);
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CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
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CGEN_EXTRACT_INFO ex_info;
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CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
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int insn_bit_length = CGEN_INSN_BITSIZE (insn);
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int insn_length = insn_bit_length / 8;
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sfile.buffer = sfile.current = buf;
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INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
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(fprintf_ftype) sim_disasm_sprintf);
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disasm_info.endian =
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(bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
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: bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
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: BFD_ENDIAN_UNKNOWN);
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length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
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insn_length);
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if (length != insn_length)
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{
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sim_io_error (sd, "unable to read address %x", pc);
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}
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/* If the entire insn will fit into an integer, then do it. Otherwise, just
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use the bits of the base_insn. */
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if (insn_bit_length <= 32)
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base_length = insn_bit_length;
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else
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base_length = min (cd->base_insn_bitsize, insn_bit_length);
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switch (base_length)
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{
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case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
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case 8 : insn_value = insn_buf.bytes[0]; break;
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case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
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case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
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default: abort ();
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}
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disasm_info.buffer_vma = pc;
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disasm_info.buffer = insn_buf.bytes;
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disasm_info.buffer_length = length;
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ex_info.dis_info = (PTR) &disasm_info;
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ex_info.valid = (1 << length) - 1;
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ex_info.insn_bytes = insn_buf.bytes;
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length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
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/* Result of extract fn is in bits. */
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/* ??? This assumes that each instruction has a fixed length (and thus
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for insns with multiple versions of variable lengths they would each
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have their own table entry). */
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if (length == insn_bit_length)
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{
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(*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
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}
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else
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{
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/* This shouldn't happen, but aborting is too drastic. */
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strcpy (buf, "***unknown***");
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}
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}
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