forked from Imagelibrary/binutils-gdb
11dd08e9a0
Limit MIPS16 instruction disassembly according to the ISA level and ASE set selected, as with the regular MIPS and microMIPS instruction sets. Retain the property of `objdump -m mips:16' disassembling all MIPS16 instructions however, regardless of any ISA level recorded in the binary examined. To validate the disassembler use the GAS test suite for its convenience of running tests across multiple ISAs, even though placing the tests in the binutils test suite would be more appropriate. Adjust the single binutils test which depends on 64-bit instruction disassembly to have the ISA level required actually recorded in the binary examined. opcodes/ * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. (print_insn_mips16): Check opcode entries for validity against the ISA level and ASE set selected. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module' rather than `.set' to set the ISA level. gas/ * testsuite/gas/mips/mips16-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16-sub.d: New test. * testsuite/gas/mips/mips16e-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-sub.d: New test. * testsuite/gas/mips/mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test. * testsuite/gas/mips/mips16-sub.s: New test source. * testsuite/gas/mips/mips16e-sub.s: New test source. * testsuite/gas/mips/mips16e-64-sub.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.
199 lines
3.6 KiB
ArmAsm
199 lines
3.6 KiB
ArmAsm
.text
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.module mips3
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.set mips16
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.globl foo
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.ent foo
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foo:
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# Individual major opcodes.
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addiu $2, $sp, 0x4011
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.half 0xf008, 0x0211
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.half 0xf008, 0x0231
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.half 0xf008, 0x0251
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.half 0xf008, 0x0291
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addiu $2, $pc, 0x4011
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.half 0xf008, 0x0a11
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.half 0xf008, 0x0a31
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.half 0xf008, 0x0a51
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.half 0xf008, 0x0a91
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b . + 0x8026
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.half 0xf008, 0x1011
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.half 0xf008, 0x1031
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.half 0xf008, 0x1051
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.half 0xf008, 0x1091
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.half 0xf008, 0x1111
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.half 0xf008, 0x1211
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.half 0xf008, 0x1411
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beqz $2, . + 0x8026
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.half 0xf008, 0x2211
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.half 0xf008, 0x2231
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.half 0xf008, 0x2251
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.half 0xf008, 0x2291
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bnez $2, . + 0x8026
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.half 0xf008, 0x2a11
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.half 0xf008, 0x2a31
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.half 0xf008, 0x2a51
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.half 0xf008, 0x2a91
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addiu $2, 0x4011
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.half 0xf008, 0x4a11
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.half 0xf008, 0x4a31
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.half 0xf008, 0x4a51
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.half 0xf008, 0x4a91
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slti $2, 0x4011
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.half 0xf008, 0x5211
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.half 0xf008, 0x5231
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.half 0xf008, 0x5251
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.half 0xf008, 0x5291
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sltiu $2, 0x4011
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.half 0xf008, 0x5a11
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.half 0xf008, 0x5a31
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.half 0xf008, 0x5a51
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.half 0xf008, 0x5a91
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li $2, 0x4011
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.half 0xf008, 0x6a11
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.half 0xf008, 0x6a31
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.half 0xf008, 0x6a51
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.half 0xf008, 0x6a91
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cmpi $2, 0x4011
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.half 0xf008, 0x7211
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.half 0xf008, 0x7231
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.half 0xf008, 0x7251
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.half 0xf008, 0x7291
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lw $2, 0x4011($sp)
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.half 0xf008, 0x9211
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.half 0xf008, 0x9231
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.half 0xf008, 0x9251
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.half 0xf008, 0x9291
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lw $2, 0x4011($pc)
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.half 0xf008, 0xb211
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.half 0xf008, 0xb231
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.half 0xf008, 0xb251
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.half 0xf008, 0xb291
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sw $2, 0x4011($sp)
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.half 0xf008, 0xd211
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.half 0xf008, 0xd231
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.half 0xf008, 0xd251
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.half 0xf008, 0xd291
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# I8 major opcode.
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bteqz . + 0x8026
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.half 0xf008, 0x6011
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.half 0xf008, 0x6031
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.half 0xf008, 0x6051
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.half 0xf008, 0x6091
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btnez . + 0x8026
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.half 0xf008, 0x6111
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.half 0xf008, 0x6131
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.half 0xf008, 0x6151
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.half 0xf008, 0x6191
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sw $ra, 0x4011($sp)
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.half 0xf008, 0x6211
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.half 0xf008, 0x6231
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.half 0xf008, 0x6251
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.half 0xf008, 0x6291
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addiu $sp, 0x4011
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.half 0xf008, 0x6311
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.half 0xf008, 0x6331
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.half 0xf008, 0x6351
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.half 0xf008, 0x6391
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# SHIFT major opcode
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sll $2, $3, 0x14
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.half 0xf500, 0x3260
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.half 0xf500, 0x3264
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.half 0xf500, 0x3268
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.half 0xf500, 0x3270
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.half 0xf501, 0x3260
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.half 0xf502, 0x3260
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.half 0xf504, 0x3260
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.half 0xf508, 0x3260
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.half 0xf510, 0x3260
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.half 0xf520, 0x3260
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dsll $2, $3, 0x14
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.half 0xf500, 0x3261
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.half 0xf500, 0x3265
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.half 0xf500, 0x3269
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.half 0xf500, 0x3271
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.half 0xf501, 0x3261
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.half 0xf502, 0x3261
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.half 0xf504, 0x3261
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.half 0xf508, 0x3261
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.half 0xf510, 0x3261
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.half 0xf520, 0x3261
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srl $2, $3, 0x14
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.half 0xf500, 0x3262
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.half 0xf500, 0x3266
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.half 0xf500, 0x326a
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.half 0xf500, 0x3272
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.half 0xf501, 0x3262
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.half 0xf502, 0x3262
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.half 0xf504, 0x3262
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.half 0xf508, 0x3262
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.half 0xf510, 0x3262
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.half 0xf520, 0x3262
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sra $2, $3, 0x14
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.half 0xf500, 0x3263
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.half 0xf500, 0x3267
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.half 0xf500, 0x326b
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.half 0xf500, 0x3273
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.half 0xf501, 0x3263
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.half 0xf502, 0x3263
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.half 0xf504, 0x3263
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.half 0xf508, 0x3263
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.half 0xf510, 0x3263
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.half 0xf520, 0x3263
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# RR major opcode
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dsrl $2, 0x14
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.half 0xf500, 0xe848
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.half 0xf500, 0xe948
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.half 0xf500, 0xea48
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.half 0xf500, 0xec48
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.half 0xf501, 0xe848
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.half 0xf502, 0xe848
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.half 0xf504, 0xe848
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.half 0xf508, 0xe848
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.half 0xf510, 0xe848
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.half 0xf520, 0xe848
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dsra $2, 0x14
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.half 0xf500, 0xe853
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.half 0xf500, 0xe953
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.half 0xf500, 0xea53
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.half 0xf500, 0xec53
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.half 0xf501, 0xe853
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.half 0xf502, 0xe853
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.half 0xf504, 0xe853
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.half 0xf508, 0xe853
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.half 0xf510, 0xe853
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.half 0xf520, 0xe853
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# I64 major opcode.
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daddiu $sp, 0x4011
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.half 0xf008, 0xfb11
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.half 0xf008, 0xfb31
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.half 0xf008, 0xfb51
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.half 0xf008, 0xfb91
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.end foo
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# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 4, 0
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.space 16
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