forked from Imagelibrary/binutils-gdb
0ef0eba580
(lookup_hash): Call hash rather than computing the hash
code here.
(do_format_1_2): Handle format 1 and format 2 instructions.
Get operands correctly and call the target function.
(do_format_6): Get operands correctly and call the target
function.
(do_formats_9_10): Rough cut so shift ops will work.
(sim_resume): Tweak to deal with format 1 and format 2
handling in a single funtion. Don't update the PC
for format 3 insns. Fix typos.
* simops.c: Slightly reorganize. Add condition code handling
to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
and "not" instructions.
* v850_sim.h (reg_t): Registers are 32bits.
(_state): The V850 has 32 general registers. Add a 32bit
psw and pc register too. Add accessor macros
Fixing lots of stuff. Starting to add condition code support. Basically
check pointing the work to date.
666 lines
8.6 KiB
C
666 lines
8.6 KiB
C
#include <signal.h>
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#include "v850_sim.h"
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#include "simops.h"
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void
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OP_220 ()
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{
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}
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void
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OP_10760 ()
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{
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}
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void
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OP_C7C0 ()
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{
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}
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void
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OP_760 ()
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{
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}
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void
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OP_580 ()
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{
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}
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void
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OP_700 ()
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{
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}
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void
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OP_581 ()
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{
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}
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void
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OP_582 ()
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{
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}
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void
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OP_583 ()
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{
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}
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void
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OP_584 ()
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{
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}
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void
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OP_585 ()
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{
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}
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void
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OP_586 ()
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{
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}
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void
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OP_587 ()
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{
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}
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void
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OP_588 ()
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{
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}
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void
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OP_589 ()
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{
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}
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void
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OP_58A ()
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{
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}
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void
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OP_58B ()
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{
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}
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void
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OP_58C ()
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{
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}
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void
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OP_400 ()
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{
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}
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void
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OP_160 ()
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{
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}
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void
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OP_58D ()
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{
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}
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void
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OP_58E ()
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{
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}
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void
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OP_58F ()
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{
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}
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void
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OP_660 ()
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{
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}
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/* add reg, reg */
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void
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OP_1C0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* add sign_extend(imm5), reg */
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void
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OP_240 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0x1f);
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temp = (temp << 27) >> 27;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* addi sign_extend(imm16), reg, reg */
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void
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OP_600 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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int temp;
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/* Compute the result. */
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temp = (OP[0] & 0xffff);
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temp = (temp << 16) >> 16;
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op0 = temp;
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op1 = State.regs[OP[1]];
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result = op0 + op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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cy = (result < op0 || result < op1);
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ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
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&& (op0 & 0x80000000) != (result & 0x80000000));
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
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| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
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}
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/* sub reg1, reg2
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XXX condition codes */
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void
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OP_1A0 ()
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{
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State.regs[OP[1]] -= State.regs[OP[0]];
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}
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/* subr reg1, reg2
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XXX condition codes */
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void
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OP_180 ()
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{
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State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
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}
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/* mulh reg1, reg2
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XXX condition codes */
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void
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OP_E0 ()
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{
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State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
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* (State.regs[OP[0]] & 0xffff));
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}
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/* mulh sign_extend(imm5), reg2
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Condition codes */
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void
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OP_2E0 ()
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{
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int value = OP[0];
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value = (value << 27) >> 27;
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State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
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}
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/* mulhi imm16, reg1, reg2
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XXX condition codes */
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void
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OP_6E0 ()
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{
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int value = OP[0];
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value = value & 0xffff;
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State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
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}
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/* divh reg1, reg2
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XXX condition codes.
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XXX Is this signed or unsigned? */
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void
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OP_40 ()
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{
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State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
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}
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void
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OP_10720 ()
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{
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}
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void
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OP_780 ()
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{
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}
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void
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OP_720 ()
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{
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}
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void
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OP_60 ()
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{
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}
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void
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OP_87C0 ()
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{
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}
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void
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OP_300 ()
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{
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}
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/* mov reg, reg */
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void
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OP_0 ()
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{
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State.regs[OP[1]] = State.regs[OP[0]];
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}
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/* mov sign_extend(imm5), reg */
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void
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OP_200 ()
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{
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int value = OP[0];
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value = (value << 27) >> 27;
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State.regs[OP[1]] = value;
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}
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/* movea sign_extend(imm16), reg, reg */
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void
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OP_620 ()
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{
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int value = OP[0];
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value = (value << 16) >> 16;
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State.regs[OP[2]] = State.regs[OP[1]] + value;
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}
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/* movhi imm16, reg, reg */
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void
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OP_640 ()
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{
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int value = OP[0];
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value = (value & 0xffff) << 16;
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State.regs[OP[2]] = State.regs[OP[1]] + value;
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}
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void
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OP_7C0 ()
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{
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}
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void
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OP_1687E0 ()
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{
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}
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void
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OP_1E0 ()
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{
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}
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void
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OP_A0 ()
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{
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}
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void
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OP_260 ()
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{
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}
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void
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OP_740 ()
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{
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}
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void
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OP_80 ()
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{
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}
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/* sar zero_extend(imm5),reg1
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XXX condition codes. */
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void
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OP_2A0 ()
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{
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int temp = State.regs[OP[1]];
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temp >>= (OP[0] & 0x1f);
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State.regs[OP[1]] = temp;
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}
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/* sar reg1, reg2
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XXX condition codes. */
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void
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OP_A007E0 ()
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{
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int temp = State.regs[OP[1]];
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temp >>= (State.regs[OP[0]] & 0x1f);
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State.regs[OP[1]] = temp;
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}
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/* shl zero_extend(imm5),reg1
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XXX condition codes. */
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void
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OP_2C0 ()
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{
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State.regs[OP[1]] <<= (OP[0] & 0x1f);
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}
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/* shl reg1, reg2
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XXX condition codes. */
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void
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OP_C007E0 ()
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{
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State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
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}
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/* shr zero_extend(imm5),reg1
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XXX condition codes. */
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void
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OP_280 ()
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{
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State.regs[OP[1]] >>= (OP[0] & 0x1f);
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}
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/* shr reg1, reg2
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XXX condition codes. */
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void
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OP_8007E0 ()
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{
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State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
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}
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void
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OP_500 ()
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{
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}
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void
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OP_47C0 ()
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{
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}
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void
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OP_7E0 ()
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{
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}
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/* or reg, reg */
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void
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OP_100 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 | op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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}
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/* ori zero_extend(imm16), reg, reg */
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void
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OP_680 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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op0 = OP[0] & 0xffff;
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op1 = State.regs[OP[1]];
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result = op0 | op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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State.psw |= (z ? PSW_Z : 0);
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}
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/* and reg, reg */
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void
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OP_140 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 & op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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}
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/* andi zero_extend(imm16), reg, reg */
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void
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OP_6C0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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op0 = OP[0] & 0xffff;
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op1 = State.regs[OP[1]];
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result = op0 & op1;
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/* Compute the condition codes. */
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z = (result == 0);
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= (z ? PSW_Z : 0);
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}
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/* xor reg, reg */
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void
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OP_120 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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op1 = State.regs[OP[1]];
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result = op0 ^ op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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}
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/* xori zero_extend(imm16), reg, reg */
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void
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OP_6A0 ()
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{
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unsigned int op0, op1, result, z, s, cy, ov;
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op0 = OP[0] & 0xffff;
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op1 = State.regs[OP[1]];
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result = op0 ^ op1;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[2]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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State.psw |= (z ? PSW_Z : 0);
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}
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/* not reg1, reg2 */
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void
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OP_20 ()
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{
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unsigned int op0, result, z, s, cy, ov;
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/* Compute the result. */
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op0 = State.regs[OP[0]];
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result = ~op0;
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/* Compute the condition codes. */
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z = (result == 0);
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s = (result & 0x80000000);
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/* Store the result and condition codes. */
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State.regs[OP[1]] = result;
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State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
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State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
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}
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void
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OP_C0 ()
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{
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}
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void
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OP_480 ()
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{
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}
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void
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OP_380 ()
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{
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}
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void
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OP_501 ()
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{
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}
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/* di, not supported */
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void
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OP_16007E0 ()
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{
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abort ();
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}
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/* ei, not supported */
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void
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OP_16087E0 ()
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{
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abort ();
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}
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|
|
|
/* halt, not supported */
|
|
void
|
|
OP_12007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* reti, not supported */
|
|
void
|
|
OP_14007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* trap, not supportd */
|
|
void
|
|
OP_10007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* ldsr, not supported */
|
|
void
|
|
OP_2007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|
|
/* stsr, not supported */
|
|
void
|
|
OP_4007E0 ()
|
|
{
|
|
abort ();
|
|
}
|
|
|