forked from Imagelibrary/binutils-gdb
80d61d8d61
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
147 lines
4.8 KiB
C
147 lines
4.8 KiB
C
/* opcode/i386.h -- Intel 80386 opcode macros
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Copyright (C) 1989-2023 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
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ix86 Unix assemblers, generate floating point instructions with
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reversed source and destination registers in certain cases.
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Unfortunately, gcc and possibly many other programs use this
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reversed syntax, so we're stuck with it.
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eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
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`fsub %st,%st(3)' results in st(3) = st - st(3), rather than
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the expected st(3) = st(3) - st
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This happens with all the non-commutative arithmetic floating point
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operations with two register operands, where the source register is
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%st, and destination register is %st(i).
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The affected opcode map is dceX, dcfX, deeX, defX. */
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#ifndef OPCODE_I386_H
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#define OPCODE_I386_H
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#ifndef SYSV386_COMPAT
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/* Set non-zero for broken, compatible instructions. Set to zero for
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non-broken opcodes at your peril. gcc generates SystemV/386
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compatible instructions. */
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#define SYSV386_COMPAT 1
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#endif
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#define MOV_AX_DISP32 0xa0
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#define POP_SEG_SHORT 0x07
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#define POP_SEG386_SHORT 0xfa1
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#define JUMP_PC_RELATIVE 0xeb
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#define INT_OPCODE 0xcd
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#define INT3_OPCODE 0xcc
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/* The opcode for the fwait instruction, which disassembler treats as a
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prefix when it can. */
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#define FWAIT_OPCODE 0x9b
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/* Instruction prefixes.
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NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
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part of the opcode. Other prefixes may still appear between them
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and the 0x0f part of the opcode. */
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#define ADDR_PREFIX_OPCODE 0x67
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#define DATA_PREFIX_OPCODE 0x66
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#define LOCK_PREFIX_OPCODE 0xf0
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#define CS_PREFIX_OPCODE 0x2e
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#define DS_PREFIX_OPCODE 0x3e
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#define ES_PREFIX_OPCODE 0x26
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#define FS_PREFIX_OPCODE 0x64
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#define GS_PREFIX_OPCODE 0x65
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#define SS_PREFIX_OPCODE 0x36
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#define REPNE_PREFIX_OPCODE 0xf2
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#define REPE_PREFIX_OPCODE 0xf3
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#define XACQUIRE_PREFIX_OPCODE 0xf2
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#define XRELEASE_PREFIX_OPCODE 0xf3
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#define BND_PREFIX_OPCODE 0xf2
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#define NOTRACK_PREFIX_OPCODE 0x3e
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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/* register numbers */
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#define EAX_REG_NUM 0
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#define ECX_REG_NUM 1
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#define EDX_REG_NUM 2
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#define EBX_REG_NUM 3
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#define ESP_REG_NUM 4
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#define EBP_REG_NUM 5
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#define ESI_REG_NUM 6
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#define EDI_REG_NUM 7
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/* modrm_byte.regmem for twobyte escape */
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#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
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/* index_base_byte.index for no index register addressing */
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
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/* Extract fields from the mod/rm byte. */
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#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
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#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
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#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
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/* Extract fields from the sib byte. */
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#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
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#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
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#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
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/* x86-64 extension prefix. */
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#define REX_OPCODE 0x40
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#define REX2_OPCODE 0xd5
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/* Non-zero if OPCODE is the rex prefix. */
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#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
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/* M0 in rex2 prefix represents map0 or map1. */
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#define REX2_M 0x8
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/* Indicates 64 bit operand size. */
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#define REX_W 8
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/* High extension to reg field of modrm byte. */
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#define REX_R 4
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/* High extension to SIB index field. */
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#define REX_X 2
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/* High extension to base field of modrm or SIB, or reg field of opcode. */
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#define REX_B 1
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/* max operands per insn */
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#define MAX_OPERANDS 5
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/* max immediates per insn (lcall, ljmp, insertq, extrq) */
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#define MAX_IMMEDIATE_OPERANDS 2
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/* max memory refs per insn (string ops) */
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#define MAX_MEMORY_OPERANDS 2
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/* max size of insn mnemonics. */
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#define MAX_MNEM_SIZE 20
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/* max size of register name in insn mnemonics. */
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#define MAX_REG_NAME_SIZE 8
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#endif /* OPCODE_I386_H */
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