Commit Graph

646 Commits

Author SHA1 Message Date
Jan Beulich
7d3182d6aa x86: Intel syntax implies Intel mnemonics
As noted in the context of d53e6b98a2 ("x86/Intel: correct disassembly
of fsub*/fdiv*") there's no such thing as Intel syntax without Intel
mnemonics. Enforce this on the assembler side, and disentangle command
line option handling on the disassembler side accordingly.

As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes
redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and
remove the then no longer accessible templates.
2023-12-15 12:04:39 +01:00
Cui, Lili
b70a487d59 Make const_1_mode print $1 in AT&T syntax
Make const_1_mode print $1 in AT&T syntax, otherwise
there will be correctness issues when it is extended
to support APX NDD,

gas/ChangeLog:

        * testsuite/gas/i386/intel.d: Adjust testcase.
        * testsuite/gas/i386/lfence-load.d: Ditto.
        * testsuite/gas/i386/noreg16-data32.d: Ditto.
        * testsuite/gas/i386/noreg16.d: Ditto.
        * testsuite/gas/i386/noreg32-data16.d: Ditto.
        * testsuite/gas/i386/noreg32.d: Ditto.
        * testsuite/gas/i386/noreg64-data16.d: Ditto.
        * testsuite/gas/i386/noreg64-rex64.d: Ditto.
        * testsuite/gas/i386/noreg64.d: Ditto.
        * testsuite/gas/i386/opcode-suffix.d: Ditto.
        * testsuite/gas/i386/opcode.d: Ditto.
        * testsuite/gas/i386/x86-64-lfence-load.d: Ditto.
        * testsuite/gas/i386/x86-64-opcode.d: Ditto.

opcodes/ChangeLog:

        * i386-dis.c (OP_I): Make const_1_mode print $1 in AT&T syntax.
2023-12-13 06:07:36 +00:00
Hu, Lin1
8170af78e1 Support Intel USER_MSR
This patches aims to support Intel USER_MSR. In addition to the usual
support, this patch includes encoding and decoding support for MAP7 and
immediate numbers as the last operand (ATT style).

gas/ChangeLog:

	* NEWS: Support Intel USER_MSR.
	* config/tc-i386.c (smallest_imm_type): Reject imm32 in 64bit
	mode.
	(build_vex_prefix): Add VEXMAP7.
	(md_assemble): Handling the imm32 of USER_MSR.
	(match_template): Handling the unusual immediate.
	* doc/c-i386.texi: Document .user_msr.
	* testsuite/gas/i386/i386.exp: Run USER_MSR tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/user_msr-inval.l: New test.
	* testsuite/gas/i386/user_msr-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-user_msr-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-user_msr.d: Ditto.
	* testsuite/gas/i386/x86-64-user_msr.s: Ditto.

opcodes/ChangeLog:
	* i386-dis.c (struct instr_info): Add a new attribute
	has_skipped_modrm.
	(Gq): New.
	(Rq): Ditto.
	(q_mm_mode): Ditto.
	(Nq): Change mode from q_mode to q_mm_mode.
	(VEX_LEN_TABLE):
	(get_valid_dis386): Add VEX_MAP7 in VEX prefix.
	and handle the map7_f8 for save space.
	(OP_Skip_MODRM): Set has_skipped_modrm.
	(OP_E): Skip codep++ when has skipped modrm byte.
	(OP_R): Support q_mode and q_mm_mode.
	(REG_VEX_MAP7_F8_L_0_W_0): New.
	(PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64): Ditto.
	(X86_64_VEX_MAP7_F8_L_0_W_0_R_0): Ditto.
	(VEX_LEN_MAP7_F8): Ditto.
	(VEX_W_MAP7_F8_L_0): Ditto.
	(MOD_0F38F8): Ditto.
	(PREFIX_0F38F8_M_0): Ditto.
	(PREFIX_0F38F8_M_1_X86_64): Ditto.
	(X86_64_0F38F8_M_1): Ditto.
	(PREFIX_0F38F8): Remove.
	(prefix_table): Add PREFIX_0F38F8_M_1_X86_64.
	Remove PREFIX_0F38F8.
	(reg_table): Add REG_VEX_MAP7_F8_L_0_W_0,
	PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64.
	(x86_64_table): Add X86_64_0F38F8_PREFIX_3_M_1,
	X86_64_VEX_MAP7_F8_L_0_W_0_R_0 and X86_64_0F38F8_M_1.
	(vex_table): Add VEX_MAP7.
	(vex_len_table): Add VEX_LEN_MAP7_F8,
	VEX_W_MAP7_F8_L_0.
	(mod_table): New entry for USER_MSR and
	add MOD_0F38F8.
	* i386-gen.c (cpu_flag_init): Add CPU_USER_MSR_FLAGS and
	CPU_ANY_USER_MSR_FLAGS. Add add VEXMAP7.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (SPACE_VEXMAP7): New.
	(CPU_USER_MSR_FLAGS): Ditoo.
	(CPU_ANY_USER_MSR_FLAGS): Ditto.
	(i386_cpu_flags): Add cpuuser_msr.
	* i386-opc.tbl: Add USER_MSR instructions.
	* i386-tbl.h: Regenerated.
2023-10-31 16:24:41 +08:00
Sam James
b5c37946cc Revert "2.41 Release sources"
This reverts commit 675b9d612c.

See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 12:06:23 +01:00
Nick Clifton
675b9d612c 2.41 Release sources 2023-08-02 09:23:36 +01:00
Hu, Lin1
cd2908958a Support Intel PBNDKB
gas/ChangeLog:

	* NEWS: Support Intel PBNDKB.
	* config/tc-i386.c: Add pbndkb.
	* doc/c-i386.texi: Document .pbndkb.
	* testsuite/gas/i386/i386.exp: Add PBNDKB tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/pbndkb-inval.l: New test.
	* testsuite/gas/i386/pbndkb-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New.
	(X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0.
	(rm_table): New entry for pbndkb.
	* i386-gen.c (cpu_flag): Add PBNDKB.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuPBNDKB): New.
	(i386_cpu_flags): Add cpupbndkb.
	* i386-opc.tbl: Add PBNDKB instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:52 +08:00
Haochen Jiang
2bced1684b Support Intel SM4
gas/ChangeLog:

	* NEWS: Support Intel SM4.
	* config/tc-i386.c: Add sm4.
	* doc/c-i386.texi: Document .sm4.
	* testsuite/gas/i386/i386.exp: Run SM4 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm4-intel.d: Add SM4 tests.
	* testsuite/gas/i386/sm4.d: Ditto.
	* testsuite/gas/i386/sm4.s: Ditto.
	* testsuite/gas/i386/x86-64-sm4-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (prefix_table): Add SM4 instructions.
	* i386-gen.c (isa_dependencies): Add SM4.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM4): New.
	(i386_cpu_flags): Add cpusm4.
	* i386-opc.tbl: Add SM4 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:46 +08:00
Haochen Jiang
c55ba32b7a Support Intel SM3
gas/ChangeLog:

	* NEWS: Support Intel SM3.
	* config/tc-i386.c: Add sm3.
	* doc/c-i386.texi: Document .sm3.
	* testsuite/gas/i386/i386.exp: Run sm3 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm3-intel.d: New test.
	* testsuite/gas/i386/sm3.d: Ditto.
	* testsuite/gas/i386/sm3.s: Ditto.
	* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
	(VEX_LEN_0F38DA_W_0_P_0): Ditto.
	(VEX_LEN_0F38DA_W_0_P_2): Ditto.
	(VEX_LEN_0F3ADE_W_0): Ditto.
	(VEX_W_0F38DA): Ditto.
	(VEX_W_0F3ADE): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
	(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
	VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
	(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
	* i386-gen.c (isa_dependencies): Add SM3.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM3): New.
	(i386_cpu_flags): Add cpusm3.
	* i386-opc.tbl: Add SM3 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:25 +08:00
Haochen Jiang
3ac2eb9481 Support Intel SHA512
gas/ChangeLog:

	* NEWS: Support Intel SHA512.
	* config/tc-i386.c: Add sha512.
	* doc/c-i386.texi: Document .sha512.
	* testsuite/gas/i386/disassem.d: Add SHA512 tests.
	* testsuite/gas/i386/disassem.s: Ditto.
	* testsuite/gas/i386/i386.exp: Run SHA512 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sha512-intel.d: New test.
	* testsuite/gas/i386/sha512-inval.l: Ditto.
	* testsuite/gas/i386/sha512-inval.s: Ditto.
	* testsuite/gas/i386/sha512.d: Ditto.
	* testsuite/gas/i386/sha512.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Rxmmq): New.
	(Rymm): Ditto.
	(PREFIX_VEX_0F38CB): Ditto.
	(PREFIX_VEX_0F38CC): Ditto.
	(PREFIX_VEX_0F38CD): Ditto.
	(VEX_LEN_0F38CB_P_3_W_0): Ditto.
	(VEX_LEN_0F38CC_P_3_W_0): Ditto.
	(VEX_LEN_0F38CD_P_3_W_0): Ditto.
	(VEX_W_0F38CB_P_3): Ditto.
	(VEX_W_0F38CC_P_3): Ditto.
	(VEX_W_0F38CD_P_3): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC,
	PREFIX_VEX_0F38CD.
	(vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0,
	VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0.
	(vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3.
	* i386-gen.c (isa_dependencies): Add SHA512.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSHA512): New.
	(i386_cpu_flags): Add cpusha512.
	* i386-opc.tbl: Add SHA512 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:17 +08:00
konglin1
3fde5f6e7d Support Intel AVX-VNNI-INT16
gas/ChangeLog:

	* NEWS: Support Intel AVX-VNNI-INT16.
	* config/tc-i386.c: Add avx_vnni_int16.
	* doc/c-i386.texi: Document avx_vnni_int16.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.s: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
	(PREFIX_VEX_0F38D3_W_0): Ditto.
	(VEX_W_0F38D2_P_0): Ditto.
	(VEX_W_0F38D2_P_1): Ditto.
	(VEX_W_0F38D2_P_2): Ditto.
	(VEX_W_0F38D3_P_0): Ditto.
	(VEX_W_0F38D3_P_1): Ditto.
	(VEX_W_0F38D3_P_2): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
	PREFIX_VEX_0F38D3_W_0.
	(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
	(vex_w_table): Ditto.
	* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
	(cpu_flag): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h: (CpuAVX_VNNI_INT16): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:51:20 +08:00
Jan Beulich
178e197078 x86: adjust disassembly of insns operating on selector values
Bring disassembly back in line with what the assembler accepts, thus
also making it self-consistent (with, in particular selector load/store
insns). While there further add D to all affected insns except ARPL
(where S is used, matching LAR/LSL), to also behave correctly in suffix-
always mode.

While there also hook up the Intel variant of the LKGS test.
2023-07-21 08:57:24 +02:00
Jan Beulich
c54748b2fa x86: simplify disassembly of LAR/LSL
For whatever reason in c9f5b96bda ("x86: correct handling of LAR and
LSL") I didn't realize that we can easily use Sv instead of going
through mod_table[]. Redo this aspect of that change.
2023-07-21 08:56:49 +02:00
Jan Beulich
034b6bec54 x86: simplify table-referencing macros
First of all it is entirely unclear why THREE_BYTE_TABLE_PREFIX() was
introduced by bf890a93a7. Nothing uses the .prefix_requirement values
from the two relevant entries.

And then having VEX_Cn_TABLE() and friends take arguments is misleading.
These aren't used (or pointlessly used in the case of VEX_C5_TABLE); the
respective table index is decoded from the insn (or implied in the case
of VEX_C5_TABLE).
2023-07-11 08:22:17 +02:00
Jan Beulich
1a05d24e98 x86: convert 0FXOP to just XOP in enumerator names
There's nothing 0f-ish in XOP encodings.
2023-07-11 08:21:51 +02:00
Jan Beulich
310e6b6322 x86: misc further register-only insns don't need to go through mod_table[]
Several already use OP_R(), which rejects the memory forms of insns, and
a few others can easily be converted to do so as well. Note that for it
to be able to use BadOp() without forward declaration, OP_Skip_MODRM() is
moved down.

While there add the previously missing PREFIX_OPCODE to legacy opcode
0FD7.
2023-07-11 08:21:28 +02:00
Jan Beulich
2bd8129f96 x86: various operations on mask registers can avoid going through mod_table[]
Now that we have OP_R(), use it here as well, while wiring memory-only
operands to OP_M() at the same time. To keep the number of consumed
opcode bytes similar to before, make BadOp() also account for VEX/XOP/
EVEX prefix bytes. To keep that change simple, convert need_vex to an
actual count of prefix bytes (keeping intact all prior boolean uses of
the field).

Note how this improves disassembly of such bad encodings, by at least
leaving a hint towards what a "nearby" instruction is. (For KSHIFT*
change the immediates test testcases use, such that disassembly remains
sufficiently in sync.)

While there also use Ux for VPMOV{B,W,D,Q}2M, where decoding through
mod_table[] was missing in the earlier scheme.
2023-07-11 08:21:03 +02:00
Jan Beulich
2ad525c286 x86: slightly rework handling of some register-only insns
Fold OP_MS() and OP_XS() into OP_R(), paralleling OP_M(). Use operand
names (largely) matching those in the SDM. For 128-bit-only forms use
Uxmm though, marking 256-bit forms as bad. This then allows no longer
going through vex_len_table[] for two of the insns.

Specifically _do not_ continue to mis-use v_mode.
2023-07-11 08:20:17 +02:00
Jan Beulich
5d9f7f5099 x86: SIMD shift-by-immediate don't need to go through mod_table[]
OP_MS() and OP_XS() reject memory forms of insns quite fine. This then
also eliminates mis-named enumerators (we use M_1 for register forms).
2023-07-11 08:19:53 +02:00
Jan Beulich
61ff570794 x86: misc further memory-only insns don't need to go through mod_table[]
Several already use OP_M(), which rejects the register forms of insns,
and a few others can easily be converted to do so as well. (Note that
FXSAVE_Fixup() wires through to OP_M(). Note further that OP_IndirE(),
which wasn't placed very well anyway, is moved down to avoid the need to
forward-declare BadOp().)

Also adjust formatting of and drop PREFIX_OPCODE from a few adjacent
entries.
2023-07-11 08:19:22 +02:00
Jan Beulich
7be4d0e3f0 x86: {,V}MOVNT* don't need to go through mod_table[]
Most of them use Mx already for the memory operand, which rejects the
register form of the insn. Use that operand type also for the two EVEX
forms which so far have used EXEvexXNoBcst (and thus failed to reject
the register forms), compensating by flagging broadcast as bad for all
Mx. This way several other insns which don't permit embedded broadcast
either are also covered at the same time.
2023-07-11 08:17:22 +02:00
Jan Beulich
3ef1c4468d x86: fold legacy/VEX {,V}MOV{H,L}* entries
By changing decode order to do ModR/M.mod last (rather than VEX.L), the
VEX entries (which are already reused by EVEX decoding) can be folded
with their legacy counterparts as well. Note how this change of decode
order also allows removing two auxiliary #define-s, which were
introduced during earlier folding (because of that unhelpful order of
steps).
2023-07-11 08:16:00 +02:00
Jan Beulich
c8bbc28bb8 x86: fold certain legacy/VEX table entries
Introduce macro V to expand to 'v' in the VEX/EVEX case, and replace a
couple of abort()s where legacy code can now legitimately make it. While
there for {,V}LDDQU drop hoing through mod_table[] - OP_M() rejects
register operands quite fine.
2023-07-11 08:15:39 +02:00
Jan Beulich
151da91724 x86: flag bad EVEX masking for miscellaneous insns
Masking is not permitted for certain further insns, not falling in any
of the earlier categories. Introduce the Y macro (not expanding to any
output) to flag such cases.

Note that in a few cases entries already covered otherwise are converted
as well, to continue to allow sharing of the string literals.
2023-07-04 17:02:17 +02:00
Jan Beulich
37c5374291 x86: flag EVEX masking when destination is GPR(-like)
Masking is not permitted in this case. See the code comment for how this
is being dealt with.

To avoid excess special casing of modes, have OP_M() call OP_E_memory()
directly.
2023-07-04 17:01:56 +02:00
Jan Beulich
1f83c96159 x86: flag EVEX.z set when destination is memory
Zeroing-masking is not permitted in this case. See the code comment for
how this is being dealt with.
2023-07-04 17:01:10 +02:00
Jan Beulich
ac500f1772 x86: flag EVEX.z set when destination is a mask register
While only zeroing-masking is possible in this case, this still requires
EVEX.z to be clear. Introduce a "global" flag right here, to be re-used
by checks which need to live in specific operand handlers.
2023-07-04 17:00:35 +02:00
Jan Beulich
07d618b91f x86: re-work EVEX-z-without-masking check
Rather than corrupting disassmbly altogether, flag EVEX.z set as bad
when masking isn't in effect in the first place at the time the
destination operand is actually processed.
2023-07-04 17:00:15 +02:00
Jan Beulich
fffb10b122 x86: fix expansion of %XV
Only %LV should continue on to S handling; avoid emitting a stray 'l'
(typically) in suffix-always mode.
2023-06-21 08:32:13 +02:00
Jan Beulich
93497bf9ab x86: fix disassembler build after 1a3b4f90bc
In commit 1a3b4f90bc ("x86: convert two pointers to (indexing)
integers") I neglected the fact that compilers may warn about comparing
ptrdiff_t (signed long) with size_t (unsigned long) values. Since just
before we've checked that the value is positive, simply add a cast
(despite my dislike for casts).
2023-05-26 12:44:52 +02:00
Jan Beulich
1a3b4f90bc x86: convert two pointers to (indexing) integers
This in particular reduces the number of pointers to non-const that we
have (and that could potentially be used for undue modification of
state). As a result, fetch_code()'s 2nd parameter can then also become
pointer-to-const.
2023-05-26 09:53:51 +02:00
Jan Beulich
d8acf37693 x86: disassembling over-long insns
The present way of dealing with them - misusing MAX_MNEM_SIZE, which has
nothing to do with insn length - leads to inconsistent results. Since we
allow for up to MAX_CODE_LENGTH - 1 prefix bytes (which then could be
followed by another MAX_CODE_LENGTH "normal" insn bytes until we're done
decoding), size the_buffer[] accordingly.

Move struct dis_private down to be able to use MAX_CODE_LENGTH without
moving its #define. While doing this also alter the order to have the
potentially large array last.
2023-05-26 09:53:25 +02:00
Jan Beulich
a4aa034a0a x86: use fixed-width type for codep and friends
This first of all removes a dependency on bfd_byte and unsigned char
being the same types. It further eliminates the need to mask by 0xff
when fetching values (which wasn't done fully consistently anyway),
improving code legibility.

While there, where possible add const.
2023-05-26 09:53:01 +02:00
Zhang, Jun
c88ed92f0c Support Intel FRED LKGS
gas/ChangeLog:

	* NEWS: Support Intel FRED LKGS.
	* config/tc-i386.c: Add fred lkgs
	* doc/c-i386.texi: Document .fred, .lkgs.
	* testsuite/gas/i386/i386.exp: Add FRED LKGS tests
	* testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: New entry for fred, lkgs.
	* i386-gen.c: Add CPU_FRED CPU_LKGS.
	* i386-init.h : Regenerated.
	* i386-mnem.h : Regenerated.
	* i386-opc.h: Add fred, lkgs.
	* i386-opc.tbl: Add FRED, LKGS instructions.
	* i386-tbl.h: Regenerated.
2023-05-23 14:43:23 +08:00
liuhongt
cbf25f4705 Revert "Support Intel FRED LKGS"
This reverts commit e5a497fe38.
2023-05-23 14:42:20 +08:00
Zhang, Jun
e5a497fe38 Support Intel FRED LKGS
gas/ChangeLog:

        * NEWS: Support Intel FRED LKGS.
        * config/tc-i386.c: Add fred lkgs
        * doc/c-i386.texi: Document .fred, .lkgs.
        * testsuite/gas/i386/i386.exp: Add FRED LKGS tests
        * testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

        * i386-dis.c: New entry for fred, lkgs.
        * i386-gen.c: Add CPU_FRED CPU_LKGS.
        * i386-init.h : Regenerated.
        * i386-mnem.h : Regenerated.
        * i386-opc.h: Add fred, lkgs.
        * i386-opc.tbl: Add FRED, LKGS instructions.
        * i386-tbl.h: Regenerated.
2023-05-23 13:50:40 +08:00
Jan Beulich
2aa11c298a x86: move a few more disassembler helper functions
... such that they wouldn't need forward declarations anymore. Note that
append_seg() already was suitably placed.
2023-05-12 08:57:58 +02:00
Jan Beulich
a675ea09fb x86: move get<N>() disassembler helper functions
... such that none of them would need forward declarations anymore.
2023-05-12 08:57:37 +02:00
Jan Beulich
e4452aa670 x86: limit data passed to i386_dis_printf()
The function doesn't use "ins" for other than retrieving "info". Remove
a thus pointless level of indirection.
2023-04-28 08:24:41 +02:00
Jan Beulich
ffe983ed7a x86: limit data passed to prefix_name()
Make apparent that neither what "ins" points to nor, in particular, that
"ins->info->private_data" is actually used in the function.
2023-04-28 08:24:11 +02:00
Jan Beulich
1f506c06ef x86: rework AMX control insn disassembly
Consistently do 64-bit first, VEX.L second, VEX.W third, ModR/M fourth,
and only then prefix, resulting in fewer table entries. Note that in the
course of the re-work
- TILEZERO has a previously missing decode step through rm_table[]
  added,
- a wrong M_0 suffix for TILEZERO is also corrected to be M_1 (now an
  infix).
2023-04-28 08:19:34 +02:00
Jan Beulich
be3d663386 x86: rework AMX multiplication insn disassembly
Consistently do 64-bit first, ModR/M second, VEX.L third, VEX.W fourth,
and prefix last, resulting in fewer table entries. Note that in the
course of the re-work wrong M_0 suffixes are also corrected to be M_1
(partly infixes now).

Since it ended up confusing while testing the change, also adjust the
test name in x86-64-amx-bad.d (to be distinct from x86-64-amx.d's).
2023-04-28 08:19:19 +02:00
Alan Modra
b4617f7904 i386-dis.c UB shift and other tidies
1) i386-dis.c:12055:11: runtime error: left shift of negative value -1
Bit twiddling is best done unsigned, due to UB on overflow of signed
expressions.  Fix this by using bfd_vma rather than bfd_signed_vma
everywhere in i386-dis.c except print_displacement.

2) Return get32s and get16 value in a bfd_vma, reducing the need for
temp variables.

3) Introduce get16s and get8s functions to simplify the code.

4) With some optimisation options gcc-13 legitimately complains about
a fall-through in OP_I.  Fix that.  OP_I also doesn't need to use
"mask" which was wrong for w_mode anyway.

5) Masking with & 0xffffffff is better than casting to unsigned.  We
don't know for sure that unsigned int is 32-bit.

6) We also don't know that unsigned char is 8 bits.  Mask codep
accesses everywhere.  I don't expect binutils will work on anything
other than an 8-bit char host, but if we are masking codep accesses in
some places we might as well be consistent.  (Better would be to use
stdint.h types more in binutils.)
2023-04-26 12:06:33 +09:30
Alan Modra
ea5c591c02 Revert "x86: work around compiler diagnosing dangling pointer"
This reverts commit 983db9932a.
2023-04-24 21:00:00 +09:30
Alan Modra
5b720e50c7 gcc-13 i386-dis.c warning
opcodes/i386-dis.c: In function ‘print_insn’:
opcodes/i386-dis.c:9865:22: error: storing the address of local
variable ‘priv’ in ‘*info.private_data’ [-Werror=dangling-pointer=]

	* i386-dis.c (print_insn): Clear info->private_data before
	returning.
2023-04-24 20:59:38 +09:30
Jan Beulich
983db9932a x86: work around compiler diagnosing dangling pointer
For quite come time print_insn() has been storing the address of a local
variable into info->private_data. Since the compiler can't know that the
field won't be accessed again after print_insn() returns, it may kind of
legitimately diagnose this. And recent enough gcc does as of the
introduction of the fetch_error() return paths (replacing setjmp()-based
error handling).

Utilizing that neither prefix_name() nor i386_dis_printf() actually use
info->private_data, zap the pointer in fetch_error(), after having
retrieved it for local use.
2023-04-24 10:37:12 +02:00
Tom Tromey
da9a978aae Fix -Wmaybe-uninitialized warning in opcodes/i386-dis.c
A recent change in opcodes/i386-dis.c caused a build failure on my
x86-64 Fedora 36 system, which uses:

$ gcc --version
gcc (GCC) 12.2.1 20221121 (Red Hat 12.2.1-4)
[...]

The error is:

../../binutils-gdb/opcodes/i386-dis.c: In function ‘OP_J’:
../../binutils-gdb/opcodes/i386-dis.c:12705:22: error: ‘val’ may be used uninitialized [-Werror=maybe-uninitialized]
12705 |           disp = val & 0x8000 ? val - 0x10000 : val;
      |                  ~~~~^~~~~~~~

This patch fixes the warning.

opcodes/ChangeLog
2023-04-21  Tom Tromey  <tromey@adacore.com>

	* i386-dis.c (OP_J): Check result of get16.
2023-04-21 09:06:03 -06:00
Jan Beulich
32c8e7265a x86: drop (explicit) BFD64 dependency from disassembler
get64() is unreachable when !BFD64 (due to a check relatively early in
print_insn()). Let's avoid the associated #ifdef-ary (or else we should
extend it to remove more dead code).
2023-04-21 12:10:23 +02:00
Jan Beulich
d82c06b68e x86: drop use of setjmp() from disassembler
With the longjmp() uses all gone, the setjmp() isn't necessary anymore
either.
2023-04-21 12:09:59 +02:00
Jan Beulich
a82b3c5656 x86: change fetch error handling for get<N>()
Make them return boolean and convert FETCH_DATA() uses to fetch_code().
With this no further users of FETCH_DATA() remain, so the macro and its
backing function are dropped as well.

Leave value types as they were for the helper functions, even if I don't
think that beyond get64() use of bfd_{,signed_}vma is really necessary.
With type change of "disp" in OP_E_memory(), change the 2nd parameter of
print_displacement() to a signed type as well, though (eliminating the
need for a local variable of signed type). This also eliminates the need
for custom printing of '-' in Intel syntax displacement expressions.

While there drop forward declarations which aren't really needed.
2023-04-21 12:09:35 +02:00
Jan Beulich
9760136327 x86: change fetch error handling when processing operands
Make the handler functions all return boolean and convert FETCH_DATA()
uses to fetch_code().
2023-04-21 12:09:11 +02:00