Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
"mtfsb0 4*cr7+lt" doesn't make all that much sense, but unfortunately
glibc uses just that instead of "mtfsb0 28" to clear the fpscr xe bit.
So for backwards compatibility accept cr field expressions when
assembling mtfsb operands, but disassemble to a plain number.
PR 24390
include/
* opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
opcodes/
* ppc-opc.c (BTF): Define.
(powerpc_opcodes): Use for mtfsb*.
* ppc-dis.c (print_insn_powerpc): Print fields with both
PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
gas/
* testsuite/gas/ppc/476.d: Update mtfsb*.
* testsuite/gas/ppc/a2.d: Likewise.
PPC_INT_FMT is redundant now that bfd.h pulls in inttypes.h if
available. Apparently MacOS Mojave defines int64_t as long long even
though long is also 64 bits, which confuses the logic selecting
PPC_INT_FMT (and BFD_PRI64 too). Hopefully inttypes.h is available on
Mojave.
PR 24028
include/
* opcode/ppc.h (PPC_INT_FMT): Delete.
opcodes/
* ppc-dis.c (print_insn_powerpc): Replace PPC_INT_FMT uses with
PRId64/PRIx64.
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields. That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
e_li r3, IV_table@l+0x00
which was being assembled to
8: 70 60 00 00 e_li r3,0
a: R_PPC_ADDR16_LO IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.
Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation. In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant. Thus @l should only produce a 16-bit
value, I think. So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.
include/
* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
mask and shift value.
(ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li
specially.
gas/
* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
TLS tweaks. Handle e_li. Warn on unexpected operand field
for lo16/hi16/ha16 relocs.
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions. Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field. This patch
changes that to using the operand extract function to provide non-zero
defaults.
I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.
The patch does change the error you get on invalid assembly like
ld 3,4
You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".
gas/
* config/tc-ppc.c (md_assemble): Delay counting of optional
operands until one is encountered. Allow for the possibility
of optional base regs, ie. PPC_OPERAND_PARENS. Call
ppc_optional_operand_value with extra args.
include/
* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
Mention use of "extract" function to provide default value.
(PPC_OPERAND_OPTIONAL_VALUE): Delete.
(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
* ppc-dis.c (operand_value_powerpc): Init "invalid".
(skip_optional_operands): Count optional operands, and update
ppc_optional_operand_value call.
* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
(extract_vlensi): Likewise.
(extract_fxm): Return default value for missing optional operand.
(extract_ls, extract_raq, extract_tbr): Likewise.
(insert_sxl, extract_sxl): New functions.
(insert_esync, extract_esync): Remove Power9 handling and simplify.
(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
flag and extra entry.
(powerpc_operands <SXL>): Likewise, and use insert_sxl and
extract_sxl.
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors. Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs. The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl. I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of
simplified mnemonics for special purpose register access. Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.
gas/
* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* testsuite/gas/ppc/broadway.d,
* testsuite/gas/ppc/broadway.s: New test for broadway.
* testsuite/gas/ppc/ppc.exp: Run new test.
include/
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
support disjointed BAT.
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
PPC_OPCODE_* renumbered to fill the gaps left by previous patches,
and reordered chronologically just because. I kept PPC_OPCODE_TMR
because presumably it might be used in future APUinfo for e6500.
include/
* opcode/ppc.h (PPC_OPCODE_*): Renumber and order chronologically.
(PPC_OPCODE_SPE): Comment on this and other bits used for APUinfo.
opcodes/
* ppc-dis.c (ppc_opts): Formatting. Set PPC_OPCODE_TMR for e6500.
* ppc-opc.c (powerpc_opcodes <mftmr, mttmr>): Remove now
unnecessary E6500.
This bit is also useless as it can be replaced with PPC_OPCODE_POWER9.
Defining the VSX2 and VSX3 selection based on cpu bits also lets the
assembler/disassembler distinguish between the power7 VSX opcodes and
the power8 ones. Note that this change means -mvsx now reverts back
to just adding the power7 VSX insns.
include/
* opcode/ppc.h (PPC_OPCODE_VSX3): Delete.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_VSX3.
* ppc-opc.c (PPCVSX2): Define as PPC_OPCODE_POWER8.
(PPCVSX3): Define as PPC_OPCODE_POWER9.
This bit is worse than useless. Using it prevents the assembler and
disassembler distinguishing between opcodes added for power8 and those
added for power9.
include/
* opcode/ppc.h (PPC_OPCODE_ALTIVEC2): Delete.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2.
* ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
(PPCVEC3): Define as PPC_OPCODE_POWER9.
This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases. For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.
binutils/
* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
"raw" option.
(lookup_powerpc): Don't special case -1 dialect. Handle
PPC_OPCODE_RAW.
(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
lookup_powerpc call, pass it on second.
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".
PR 21118
gas/
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
include/
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.
L field of dcbf and wclr is 2 bits.
PR 20641
include/
* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
* ppc-opc.c (L): Make compulsory.
(LOPT): New, optional form of L.
(HTM_R): Define as LOPT.
(L0, L1): Delete.
(L32OPT): New, optional for 32-bit L.
(L2OPT): New, 2-bit L for dcbf.
(SVC_LEC): Update.
(L2): Define.
(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
<dcbf>: Use L2OPT.
<tlbiel, tlbie>: Use LOPT.
<wclr, wclrall>: Use L2.
gas/
* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.
Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.
include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.
This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.
opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.
gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.
gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.
* config/tc-ppc.c (md_assemble): Emit APUinfo section for
PPC_OPCODE_E500.
gas/testsuite/
* gas/ppc/e500.s: Add eieio, mbar and lwsync
* gas/ppc/e500.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_E500): Define.
opcodes/
* ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
touch floating point regs and are enabled by COM, PPC or PPCCOM.
Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
Treat lwsync as msync on e500.
* config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test.
Test the new "deprecated" opcode field.
include/opcode/
* ppc.h (struct powerpc_opcode): New field "deprecated".
(PPC_OPCODE_NOPOWER4): Delete.
opcodes/
* ppc-opc.c (PPCNONE): Define.
(NOPOWER4): Delete.
(powerpc_opcodes): Initialize the new "deprecated" field.
