For quite some time we've been using combinations of bits for
specifying various registers in operands and templates. I think it was
Alan who had indicated that likely the debug printing would need
adjustment as a result. Here we go.
Accumulator handling for GPRs gets changed to match that for FPU regs.
For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their
original uses replaced by direct checks of the two bits of interest,
which is cheaper than operand_type_equal() invocations.
For SIMD registers nothing similar appears to be needed, as respective
operands get stripped from the (copy of the) template before pt() is
reached.
The type change on pi() is to silence a compiler diagnostic. Arguably
its other parameter could also be const-qualified.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
The .code16gcc directive to support 16-bit mode with 32-bit address.
For IRET without a suffix, generate 16-bit IRET with a warning to
return from an interrupt handler in 16-bit mode.
PR gas/24485
* config/tc-i386.c (process_suffix): Issue a warning to IRET
without a suffix for .code16gcc.
* testsuite/gas/i386/jump16.s: Add tests for iretX.
* testsuite/gas/i386/jump16.d: Updated.
* testsuite/gas/i386/jump16.e: New file.
The .code16gcc directive supports 16bit mode with 32-bit address. Since
IRET (opcode 0xcf) in 16bit mode returns from an interrupt in 16bit mode,
we shouldn't add 0x66 prefix for IRET.
PR gas/24485
* config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE
to IRET for .code16gcc.
* testsuite/gas/i386/jump16.s: Add IRET tests.
* testsuite/gas/i386/jump16.d: Updated.
The fix H.J. implemented for PR gas/22791 in the thread starting at
[PATCH] x86-64: Treat PC32 relocation with branch as PLT32
https://sourceware.org/ml/binutils/2018-02/msg00065.html
is causing problems on Solaris/x86. The native linker is strongly
preferred there, and there's no intention of implementing the linker
optimization he plans there. Besides, the kernel runtime linker,
otherwise has no need to deal with that reloc at all, and instead of
adding (possibly even more) workarounds with no benefit, it seems
appropriate to disable the R_X86_64_PLT32 generation as branch marker on
Solaris/x86 in the first place.
The patch itself is trivial, the only complication is adapting the
testsuite. Since I've found no way to have conditional sections in the
.d files, I've instead used the solution already found elsewhere of
having separate .d files for the affected tests in an i386/solaris
subdirectory and skipping the original ones.
Tested on amd64-pc-solaris2.11 and x86_64-pc-linux-gnu without
regressions.
* config/tc-i386.c (need_plt32_p) [TE_SOLARIS]: Return FALSE.
* testsuite/gas/i386/solaris/solaris.exp: New driver.
* testsuite/gas/i386/solaris/reloc64.d,
testsuite/gas/i386/solaris/x86-64-jump.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d,
testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d,
testsuite/gas/i386/solaris/x86-64-nop-3.d,
testsuite/gas/i386/solaris/x86-64-nop-4.d,
testsuite/gas/i386/solaris/x86-64-nop-5.d,
testsuite/gas/i386/solaris/x86-64-relax-2.d,
testsuite/gas/i386/solaris/x86-64-relax-3.d: New tests.
* testsuite/gas/i386/reloc64.d,
testsuite/gas/i386/x86-64-jump.d,
testsuite/gas/i386/x86-64-mpx-branch-1.d,
testsuite/gas/i386/x86-64-mpx-branch-2.d,
testsuite/gas/i386/x86-64-nop-3.d,
testsuite/gas/i386/x86-64-nop-4.d,
testsuite/gas/i386/x86-64-nop-5.d,
testsuite/gas/i386/x86-64-relax-2.d,
testsuite/gas/i386/x86-64-relax-3.d: Skip on *-*-solaris*.
Update EVEX vector load/store optimization:
1. There is no need to check AVX since AVX2 is required for AVX512F.
2. We need to check both operands for ZMM register since AT&T syntax
may not set zmmword on the first operand.
3. Update Opcode_SIMD_IntD check and set.
4. Since the VEX prefix has 2 or 3 bytes, the EVEX prefix has 4 bytes,
EVEX Disp8 has 1 byte and VEX Disp32 has 4 bytes, we choose EVEX Disp8
over VEX Disp32.
* config/tc-i386.c (optimize_encoding): Don't check AVX for
EVEX vector load/store optimization. Check both operands for
ZMM register. Update EVEX vector load/store opcode check.
Choose EVEX Disp8 over VEX Disp32.
* testsuite/gas/i386/optimize-1.d: Updated.
* testsuite/gas/i386/optimize-1a.d: Likewise.
* testsuite/gas/i386/optimize-2.d: Likewise.
* testsuite/gas/i386/optimize-4.d: Likewise.
* testsuite/gas/i386/optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
* testsuite/gas/i386/optimize-1.s: Add ZMM register load
test.
* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
Since not all AVX512F processors support AVX512VL, we can optimize
512-bit EVEX to 128-bit EVEX encoding for upper 16 vector registers
only when AVX512VL is enabled explicitly at command-line or via
".arch .avx512vl" directive.
PR gas/24352
* config/tc-i386.c (optimize_encoding): Check only
cpu_arch_flags.bitfield.cpuavx512vl.
* testsuite/gas/i386/i386.exp: Run x86-64-optimize-2b.
* testsuite/gas/i386/x86-64-optimize-2.d: Revert the last
change.
* testsuite/gas/i386/x86-64-optimize-2b.d: New file.
* testsuite/gas/i386/x86-64-optimize-2b.s: Likewise.
Since all AVX512 processors support AVX, we can encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX vector
register clearing instructions at -O1.
* config/tc-i386.c (optimize_encoding): Encode 256-bit/512-bit
VEX/EVEX vector register clearing instructions with 128-bit VEX
vector register clearing instructions at -O1.
* doc/c-i386.texi: Update -O1 and -O2 documentation.
* testsuite/gas/i386/i386.exp: Run optimize-1a and
x86-64-optimize-2a.
* testsuite/gas/i386/optimize-1a.d: New file.
* testsuite/gas/i386/x86-64-optimize-2a.d: Likewise.
Set optimize to INT_MAX, instead of -1, for -Os so that -Os will include
-O2 optimization.
PR gas/24353
* config/tc-i386.c (md_parse_option): Set optimize to INT_MAX
for -Os.
* testsuite/gas/i386/optimize-2.s: Add a test.
* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
* testsuite/gas/i386/optimize-2.d: Updated.
* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16
vector registers only when AVX512VL is enabled. We can't optimize
EVEX to 128-bit VEX encoding when AVX isn't enabled.
PR gas/24352
* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
with 128-bit VEX encoding only when AVX is enabled and with
128-bit EVEX encoding only when AVX512VL is enabled.
* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
* testsuite/gas/i386/optimize-6.s: New file.
* testsuite/gas/i386/optimize-6a.d: Likewise.
* testsuite/gas/i386/optimize-6b.d: Likewise.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
For PLT expressions, we should subtract the PLT relocation size only for
jump instructions. Since PLT relocations are PC relative, we only allow
"symbol@PLT" in PLT expression.
gas/
PR gas/23997
* config/tc-i386.c (x86_cons): Check for invalid PLT expression.
(md_apply_fix): Subtract the PLT relocation size only for jump
instructions.
* testsuite/gas/i386/reloc32.s: Add test for invalid PLT
expression.
* testsuite/gas/i386/reloc64.s: Likewise.
* testsuite/gas/i386/ilp32/reloc64.s: Likewise.
* testsuite/gas/i386/reloc32.l: Updated.
* testsuite/gas/i386/reloc64.l: Likewise.
* testsuite/gas/i386/ilp32/reloc64.l: Likewise.
ld/
PR gas/23997
* testsuite/ld-i386/i386.exp: Run PR gas/23997 test.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-x86-64/pr23997a.s: New file.
* testsuite/ld-x86-64/pr23997b.c: Likewise.
* testsuite/ld-x86-64/pr23997c.c: Likewise.
Linkers group input note sections with the same name into one output
note section with the same name. One output note section is placed in
one PT_NOTE segment. New linkers merge all input .note.gnu.property
sections into one output .note.gnu.property section with a single
NT_GNU_PROPERTY_TYPE_0 note in a single PT_NOTE segment. Since older
linkers treat input .note.gnu.property section as a generic note section
and just concatenate all input .note.gnu.property sections into one
output .note.gnu.property section without merging them, we may
see one or more NT_GNU_PROPERTY_TYPE_0 notes in PT_NOTE segment, which
are invalid.
GNU_PROPERTY_X86_UINT32_VALID was defined to address this issue such
that linker sets the bit for non-relocatable outputs. But it isn't
sufficient:
1. It doesn't cover generic properties.
2. When -mx86-used-note=yes is passed to x86 assembler, the
GNU_PROPERTY_X86_UINT32_VALID bit is set in GNU_PROPERTY_X86_ISA_1_USED
property in object file and older linkers generate invalid
NT_GNU_PROPERTY_TYPE_0 notes with the GNU_PROPERTY_X86_UINT32_VALID bit
set.
I am proposing the following changes:
1. Add PT_GNU_PROPERTY segment type:
# define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
which covers .note.gnu.property section.
2. Remove GNU_PROPERTY_X86_UINT32_VALID.
bfd/
PR ld/23900
* elf.c (get_program_header_size): Add a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
(_bfd_elf_map_sections_to_segments): Create a PT_GNU_PROPERTY
segment for NOTE_GNU_PROPERTY_SECTION_NAME.
* elfxx-x86.c (_bfd_elf_link_setup_gnu_properties): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
binutils/
PR ld/23900
* readelf.c (get_segment_type): Support PT_GNU_PROPERTY.
(decode_x86_isa): Don't check GNU_PROPERTY_X86_UINT32_VALID.
(decode_x86_feature_1): Likewise.
(decode_x86_feature_2): Likewise.
(print_gnu_property_note): Remove GNU_PROPERTY_X86_UINT32_VALID
check.
* testsuite/binutils-all/i386/empty.d: Updated.
* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
* testsuite/binutils-all/x86-64/empty.d: Likewise.
* testsuite/binutils-all/i386/pr21231b.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0x7fffffff.
* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.
gas/
PR ld/23900
* config/tc-i386.c (x86_cleanup): Don't set
GNU_PROPERTY_X86_UINT32_VALID.
* testsuite/gas/i386/property-1.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
include/
PR ld/23900
* elf/common.h (PT_GNU_PROPERTY): New.
(GNU_PROPERTY_X86_UINT32_VALID): Removed.
ld/
PR ld/23900
* testsuite/ld-elf/elf.exp: Run PR ld/23900 test.
* testsuite/ld-elf/pr23900-1-32.rd: New file.
* testsuite/ld-elf/pr23900-1-64.rd: Likewise.
* testsuite/ld-elf/pr23900-1.d: Likewise.
* testsuite/ld-elf/pr23900-1.s: Likewise.
* testsuite/ld-elf/pr23900-2.s: Likewise.
* testsuite/ld-elf/pr23900-2a.d: Likewise.
* testsuite/ld-elf/pr23900-2b.d: Likewise.
* testsuite/ld-i386/ibt-plt-1.d: Adjusted.
* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
* testsuite/ld-i386/pr23372c.d: Expect <None>
for GNU_PROPERTY_X86_ISA_1_USED.
* testsuite/ld-x86-64/pr23372c-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372c.d: Likewise.
* testsuite/ld-x86-64/pr23372d-x32.d: Likewise.
* testsuite/ld-x86-64/pr23372d.d: Likewise.
* testsuite/ld-x86-64/property-x86-5a.s: Change
GNU_PROPERTY_X86_ISA_1_USED bits to 0.
* testsuite/ld-x86-64/property-x86-5b.s: Likewise.
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of
64-bit mode. The respective templates should specify neither VexWIG nor
VexW0, but instead the setting of the bit should be determined from
- REX.W in 64-bit mode,
- the setting established through -mvexwig= / -mevexwig= otherwise.
This implies that the evex-wig2 testcase needs to go away, as being
wrong altogether.
A few test additions desirable here will only happen in later patches,
as the disassembler needs adjustments first.
Once again SSE2AVX templates are left alone, for it being unclear what
the behavior there should be.
Add -mvexwig=[0|1] option to x86 assembler to control how the assembler
should encode the VEX.W bit in WIG VEX instructions.
* gas/NEWS: Mention -mvexwig=[0|1] option.
* config/tc-i386.c (vexwig): New.
(build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG
VEX instructions.
(OPTION_MVEXWIG): New.
(md_longopts): Add -mvexwig=.
(md_parse_option): Handle OPTION_MVEXWIG.
(md_show_usage): Show -mvexwig=[0|1].
* doc/c-i386.texi: Document -mvexwig=[0|1].
* testsuite/gas/i386/avx-wig.d: New file.
* testsuite/gas/i386/avx-wig.s: Likewise.
* testsuite/gas/i386/avx2-wig.d: Likewise.
* testsuite/gas/i386/avx2-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx-wig.s: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.d: Likewise.
* testsuite/gas/i386/x86-64-avx2-wig.s: Likewise.
* testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig,
x86-64-avx-wig and x86-64-avx2-wig.
Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions. Set
VexW=3 on VEX/EVEX WIG instructions. Update assembler to check
VEXWIG when setting the VEX.W bit.
gas/
PR gas/23642
* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
the VEX.W bit.
(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.
opcodes/
PR gas/23642
* i386-opc.h (VEXWIG): New.
* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
* i386-tbl.h: Regenerated.
Just like other insns having byte and word forms, these can also make
use of the W modifier, which at the same time allows simplifying some
other code a little bit.
When encoding VEX, we can swap destination and source only if there are
more than 1 register operand.
* config/tc-i386.c (build_vex_prefix): Swap destination and
source only if there are more than 1 register operand.
Various moves come in load and store forms, and just like on the GPR
and FPU sides there would better be only one pattern. In some cases this
is not feasible because the opcodes are too different, but quite a few
cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and
Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse
operand handling there simply needs to match "straight" operand one),
and fix a long standing, but so far only latent bug with when to zap
found_reverse_match.
Also once again drop IgnoreSize where pointlessly applied to templates
touched anyway as well as *word when redundant with Reg*.
In quite a few cases the .s suffix or {load} / {store} prefixes did not
work as intended, or produced errors when they're supposed to be ignored
when it is not possible to carry out the request.
The change here re-purposes(?) the .s suffix to no longer mean "store"
(if that's what 's' did stand for), since the forms used in the base
templates are not consistently loads (and we unlikely want to change
that). The pseudo prefixes will now fulfill what their names say, i.e.
{load} now only ever produces a load form encoding (if available) while
{store} only ever produces a store form one (again if available). This
requires minimal test suite adjustments, while the majority of the
changes there are simply additions.
Add -mx86-used-note=[yes|no] option to generate (or not) GNU property
notes with GNU_PROPERTY_X86_FEATURE_2_USED and GNU_PROPERTY_X86_ISA_1_USED
properties. If the assembly input contains no instructions, set the
GNU_PROPERTY_X86_UINT32_VALID bit in GNU_PROPERTY_X86_FEATURE_2_USED
property. Add a --enable-x86-used-note configure time option to set the
default behavior. Set the default if the configure option is not used
to "no".
* NEWS: Mention -mx86-used-note=[no|yes].
* configure.ac: Add --enable-x86-used-note. Define
DEFAULT_X86_USED_NOTE.
* config.in: Regenerated.
* configure: Likewise.
* config/tc-i386.c (x86_isa_1_used): New.
(x86_feature_2_used): Likewise.
(x86_used_note): Likewise.
(_i386_insn): Add has_regmmx, has_regxmm, has_regymm and
has_regzmm.
(build_modrm_byte): Set i.has_regmmx, i.has_regzmm.
i.has_regymm and i.has_regxmm.
(x86_cleanup): New function.
(output_insn): Update x86_isa_1_used and x86_feature_2_used.
(OPTION_X86_USED_NOTE): New.
(md_longopts): Add -mx86-used-note=.
(md_parse_option): Handle OPTION_X86_USED_NOTE.
(md_show_usage): Display -mx86-used-note=.
* config/tc-i386.h (x86_cleanup): New prototype.
(md_cleanup): New.
* doc/c-i386.texi: Document -mx86-used-note=.
There are separate CPUID feature bits for fxsave/fxrstor and cmovCC
instructions. This patch adds CpuCMOV and CpuFXSR to replace Cpu686
on corresponding instructions.
gas/
* config/tc-i386.c (cpu_arch): Add .cmov and .fxsr.
(cpu_noarch): Add nocmov and nofxsr.
* doc/c-i386.texi: Document cmov and fxsr.
opcodes/
* i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
(cpu_flags): Add CpuCMOV and CpuFXSR.
* i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
For 32-bit x86 assembler, --64 and --x32 are unsupported if BFD64 is
undefined. Even if BFD64 is defined, --64 and --x32 still may not be
supported if x86-64 support isn't compiled in:
[hjl@gnu-hsw-1 gas]$ ./as-new --64 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for x86_64
[hjl@gnu-hsw-1 gas]$ ./as-new --x32 -o x.o x.s
Assembler messages:
Fatal error: no compiled in support for 32bit x86_64
[hjl@gnu-hsw-1 gas]$
This patch removes --32/--64/--x32 from md_show_usage if BFD64 is
undefined and runs code64-inval only if BFD64 is undefined.
* config/tc-i386.c (md_show_usage): Don't display --32/--64/--x32
if BFD64 is undefined.
* testsuite/gas/i386/i386.exp (gas_bfd64_check): New.
Run code64-inval if gas_bfd64_check fails.
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
Instead of hitting the abort() in output_insn() (commented by "There
should be no other prefixes for instructions with VEX prefix"), report
a proper diagnostic instead, just like we do e.g. for invalid REP
prefixes.
In commit b5014f7af2 I've removed (instead of replaced) a conditional,
resulting in addressing forms not allowing 8-bit displacements to now
get their displacements scaled under certain circumstances. Re-add the
missing conditional.
For
movsd (%esi), %ss:(%edi), %ss:(%eax)
we got
[hjl@gnu-tools-1 tmp]$ as -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: too many memory references for `movsd'
munmap_chunk(): invalid pointer
x.s:1: Internal error (Aborted).
Please report this bug.
[hjl@gnu-tools-1 tmp]$
struct _i386_insn has
const seg_entry *seg[2];
3 memory references will overflow the seg array. We should issue an
error if there are more than 2 memory references.
PR gas/23453
* config/tc-i386.c (parse_operands): Check for more than 2
memory references.
* testsuite/gas/i386/inval.s: Add a movsd test with 3 memory
references.
* testsuite/gas/i386/x86-64-inval.s: Likewise.
* testsuite/gas/i386/inval.l: Updated.
* testsuite/gas/i386/x86-64-inval.l: Likewise.
Expand Broadcast to 3 bits so that the number of bytes to broadcast
can be computed as 1 << (Broadcast - 1). Use it to simplify x86
assembler.
gas/
* config/tc-i386.c (Broadcast_Operation): Add bytes.
(build_evex_prefix): Use i.broadcast->bytes.
(match_broadcast_size): New function.
(check_VecOperands): Use the broadcast field to compute the
number of bytes to broadcast directly. Set i.broadcast->bytes.
Use match_broadcast_size.
opcodes/
* i386-gen.c (adjust_broadcast_modifier): New function.
(process_i386_opcode_modifier): Add an argument for operands.
Adjust the Broadcast value based on operands.
(output_i386_opcode): Pass operand_types to
process_i386_opcode_modifier.
(process_i386_opcodes): Pass NULL as operands to
process_i386_opcode_modifier.
* i386-opc.h (BYTE_BROADCAST): New.
(WORD_BROADCAST): Likewise.
(DWORD_BROADCAST): Likewise.
(QWORD_BROADCAST): Likewise.
(i386_opcode_modifier): Expand broadcast to 3 bits.
* i386-tbl.h: Regenerated.
Use unsigned int to iterate through multi-length vector operands to avoid
sign-extension.
* config/tc-i386.c (build_vex_prefix): Use unsigned int to
iterate through multi-length vector operands.
(build_evex_prefix): Likewise.
Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source
here is ambiguous and hence
- in source files should be qualified with a suitable suffix or operand
size specifier (not doing so is an error in Intel mode, and will gain
a diagnostic in AT&T mode in the future),
- in disassembly should be properly suffixed (the Intel operand size
specifiers were emitted correctly already).
Remove broadcast_not_on_src_operand since it is unused.
* config/tc-i386.c (i386_error): Remove
broadcast_not_on_src_operand.
(match_template): Likewse.
Determine VEX/EVEXE vector length from the last multi-length vector
operand.
* config/tc-i386.c (build_vex_prefix): Determine vector
length from the last multi-length vector operand.
(build_evex_prefix): Likewise.
