The custom parsing done there and in one of its callers allowed various
bogus constructs to be accepted. Insist on a non-zero leading digit when
parsing numbers, don't lose upper bits, and insist on proper separation
of operands.
Commit 1ac26e9f7a replaced ISSPACE with is_whitespace, but the
former returns true on EOL while the latter does not. Sprinkle
is_end_of_stmt tests to fix this bug.
The same segfault can be triggered by a ".relax_hint" with no
following instructions. Fix that too.
* config/tc-nds32.c (nds32_lookup_pseudo_opcode): Use
is_end_of_stmt along with is_whitespace.
(nds32_relax_relocs, nds32_relax_hint, nds32_flag),
(ict_model: Likewise.
(nds32_elf_append_relax_relocs): Return on no opcode.
* testsuite/gas/nds32/nds32.exp: Find .d files automatically.
* testsuite/gas/nds32/pr33229.d,
* testsuite/gas/nds32/pr33229.s: New test.
Process a new aarch64-specific CFI directive: .cfi_mte_tagged_frame
(LLVM uses this CFI directive already). The CFI directive, when
present for a function, indicates that the stack frame for the
function may modify the MTE tags of the stack space it uses. The
assembler emits char 'G' in the CIE augmentation string to indicate
the same.
ChangeLog:
* gas/config/tc-aarch64.c (s_aarch64_mte_tagged_frame): New
definition.
* gas/config/tc-aarch64.h (tc_fde_entry_extras): Add
memtag_frame_p.
(tc_cie_entry_extras): Likewise.
(tc_fde_entry_init_extra): Likewise.
(tc_cie_fde_equivalent_extra): Likewise.
(tc_cie_entry_init_extra): Likewise.
* gas/doc/c-aarch64.texi: Add documentation for
.cfi_mte_tagged_frame directive.
* gas/testsuite/gas/aarch64/mte_tagged_stack.d: New test.
* gas/testsuite/gas/aarch64/mte_tagged_stack.s: New test.
Add a new flag -menable-sysreg-checking to restore previous behaviour.
This existing behaviour is quite inconsistent, so the gating will
probably be updated in the future. (In particular, many system
registers are currently gated with the architecture version they were
released with instead of the lower architecture version that they
actually require).
This patch retains the +d128 requirement for msrr/mrrs.
Co-Authored-By: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
When parsing immediate values, register names should not be
misinterpreted as symbols. However, for backwards compatibility we need
to permit some newer register names within older instructions. The
current mechanism for doing so depends on the list of explicit
architecture requirements for the instructions, which is fragile and
easy to forget, and grows increasingly messy as more architecture
features are added.
This patch add explicit flags to each opcode to indicate which set of
register names is disallowed in each instance. These flags are
mandatory for all opcodes with immediate operands, which ensures that
the choice of disallowed names will always be deliberate and explicit.
This patch should have no functional change.
So far, SFrame sections were of type SHT_PROGBITS.
As per ELF specification, SHT_PROGBITS indicates that the section holds
information defined by the program, whose format and meaning are
determined solely by the program.
On the linker side, SHT_PROGBITS should be reserved for the simple "cat
contents after applying relocs" semantics.
Currently, the only way to know that a section contains SFrame stack
trace data is if consumer checks for section name. Such a check for
section name is not quite conformant to ELF principles.
Some of this was discussed here
https://sourceware.org/pipermail/binutils/2025-March/140181.html
With this change, the SFrame sections generated by gas, ld will have
section type set to SHT_GNU_SFRAME. The new section type is defined in
the SHT_LOOS/SHT_HIOS space. The SFrame parsing routine
_bfd_elf_parse_sframe () now admits sections only when the the section
type is SHT_GNU_SFRAME.
No special handling / validation is done at the moment for the case of
manual creation of SFrame sections via obj_elf_section (). Add function
level comments for now to add a note about this.
Although the default handling for (sh_type >= SHT_LOOS && sh_type <=
SHT_HIOS) is sufficient when SHT_GNU_SFRAME is in that range, it makes
sense to add it as a case of its own.
bfd/
* elf-sframe.c (_bfd_elf_parse_sframe): Check if section type is
SHT_GNU_SFRAME.
(_bfd_elf_set_section_sframe): Set SHT_GNU_SFRAME for output
SFrame section.
* elflink.c (obj_elf_section): Use section type for check
instead of section name.
* elfxx-x86.c: Set SHT_GNU_SFRAME for SFrame sections for
.plt* sections.
* elf.c (bfd_section_from_shdr): Add case for SHT_GNU_SFRAME.
binutils/
* readelf.c (get_os_specific_section_type_name): Add
SHT_GNU_SFRAME.
gas/
* NEWS: Announce emitted SFrame sections have SHT_GNU_SFRAME
set.
* config/obj-elf.c (obj_elf_attach_to_group): Add comments to
indicate no special handling for SFrame yet.
* dw2gencfi.c (cfi_finish): Set SHT_GNU_SFRAME for emitted
SFrame section.
ld/
* NEWS: Announce emitted SFrame sections have SHT_GNU_SFRAME
set.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe.exp: Add new test.
* gas/cfi-sframe/cfi-sframe-common-1b.d: New test.
* gas/cfi-sframe/cfi-sframe-common-1b.s: New test.
include/
* elf/common.h (SHT_GNU_SFRAME): Add new section type for SFrame
stack trace information.
libsframe/doc/
* sframe-spec.texi: Add expected ELF section type.
Just as with all HI/LO 16-bit partial relocations the newly-introduced
MIPSr6 PC-relative R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations require
pairing for correct borrow propagation from the low part to the high
part with REL targets, another case for PR 19977.
Unlike with absolute relocation, there is a complication here in that
both parts represent a calculation that is relative to the PC at the
individual relocation's location rather than both referring to the
location of the R_MIPS_PCHI16 relocation, normally applied to an AUIPC
instruction, the location of which is used for the run-time calculation
executed by hardware.
To take this semantics into account, the addend of the R_MIPS_PCLO16
relocation matching a given R_MIPS_PCHI16 relocation is expected to be
adjusted in the source assembly file for the distance between the two
relocations in a single pair, so that once both relocations have been
calculated by the linker, the expression calculated at run time is such
as if the combined 32-bit immediate was added at the location of the
AUIPC instruction.
So for matching R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations into pairs
GAS needs to check for the distance between the two relocations to be
equal to the difference between the addends supplied, and then the
linker has to subtract the low part of the distance between the two
relocations from the low part in calculating the high part, so as to
factor in any borrow.
A further complication is that `_bfd_mips_elf_lo16_reloc' handler is
supplied with the addend differently depending on whether it has been
called by GAS via `bfd_install_relocation', or by the generic linker via
`bfd_perform_relocation'. In the former case the addend is supplied
with the relocation itself while in the latter one it comes from the
field being relocated.
We currently ignore the addend supplied with the relocation and it works
for calculating absolute high-part relocations, because the same addend
has been previously supplied with them when `_bfd_mips_elf_hi16_reloc'
was called, however this approach does not work for the PC-relative case
because as noted above the low-part addend is different and we need to
consistently apply the distance adjustment both with GAS and LD.
Since the supplied addend and one retrieved from field being relocated
won't ever be both nonzero, just use the sum of the two values.
The low-part addend in `mips_elf_add_lo16_rel_addend' always comes from
the field being relocated, so there's no complication there, we just
need to apply the same adjustment.
New linker test cases verify that the same ultimate machine code is
produced both for ELF and S-record output formats, ensuring that the
both the MIPS/ELF linker and the generic linker behave in the correct
way, consistent with each other.
FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption
Standard and 128-bit destination element polynomial multiply long
instructions, when the PE is not in Streaming SVE mode.
FEAT_PCDPHINT - Producer-consumer data placement hints - is an optional
ISA extension that provides hint instructions to indicate:
- a store in the current execution thread is generating data at a specific
location, which a thread of execution on one or more other observers is
waiting on.
- the thread of execution on the current PE will read a location that may not
yet have been written with the value to be consumed.
This extension introduces:
- STSHH, a hint instruction, with operands (policies) keep and strm
- PRFM *IR*, a new prefetch memory operand.
This introduces initial support to generate .sframe from CFI directives
in assembler on s390 64-bit (s390x). Due to SFrame V2 format
limitations it has the following limitations, some of them getting
addressed by subsequent patches, which cause generation of SFrame FDE
to be skipped:
- SFrame FP/RA tracking only supports register contents being saved on
the stack (i.e. .cfi_offset). It does not support FP/RA register
contents being saved in other registers (i.e. .cfi_register). GCC on
s390x can be observed to save the FP/RA register contents in floating-
point registers, but only in leaf functions.
This issue is detailed further and resolved in the subsequent commit
"s390: Represent FP/RA saved in register in SFrame".
- SFrame FP/RA tracking cannot represent FP without RA saved. This is
because the format assumes SFrame FDE offset2 to be the RA offset, if
there are two offsets, and offset3 to be the FP offset, if there are
three offsets. There is no mean to distinguish whether offset2 is the
RA or FP offset, if there are only two offsets.
This issue is detailed further and resolved in the subsequent commit
"s390: Represent FP without RA saved in SFrame".
- SFrame assumes a dedicated FP register number. The s390x ELF ABI [1]
does only designate register 11 as preferred FP register number. In
general GCC and Clang on s390x use register 11 as frame pointer.
GCC on s390x can be observed to use register 14 as frame pointer in
the stack clash protector in the function prologue.
glibc on s390x contains hand-written assembler code that uses
register 12 as frame pointer.
This s390x support is largely based on the AArch64 support from commit
b52c4ee466 ("gas: generate .sframe from CFI directives").
The SFrame ABI/arch identifier SFRAME_ABI_S390X_ENDIAN_BIG is introduced
for s390x and added to the SFrame format specification.
The s390x ELF ABI [1] specifies the following C calling conventions for
s390x architecture:
- Register 15 is the stack pointer (SP).
- Register 14 contains the return address (RA) at function entry.
- There is no dedicated frame pointer register. Register 11 is the
preferred frame pointer (FP). [2] GCC and Clang in general use
register 11 as frame pointer.
- The CFA is defined as SP at call site +160. [3] The SP at call site
can therefore be derived from the CFA using a SP value offset from CFA
of -160.
The s390x ELF ABI [1] does not assign any standard save slot to each
register in the register save area of a stack frame. Neither the
return address (RA, r14) nor preferred frame pointer (FP, r11)
necessarily need to be saved. Therefore SFrame RA and FP tracking is
used.
Support for SFrame on s390 is only enabled for the 64-bit s390x ELF ABI
(z/Architecture with 64-bit addressing mode). It is disabled for the
32-bit s390 ELF ABI (ESA/390 or z/Architecture with 32-bit addressing
mode).
s390x-specific SFrame assembler and linker tests are added, including
error tests for use of a non-preferred frame pointer (FP) register and
specification of a non-default return address (RA) register.
[1]: s390x ELF ABI, https://github.com/IBM/s390x-abi/releases
[2]: s390x ELF ABI, commit f00421825979 ("Add information about the frame
pointer register"),
https://github.com/IBM/s390x-abi/commit/f00421825979
[3]: s390x ELF ABI, commit 4e38ad9c8a88 ("Document the CFA"),
https://github.com/IBM/s390x-abi/commit/4e38ad9c8a88
include/
* sframe.h: Add reference to s390x architecture in comments.
(SFRAME_ABI_S390X_ENDIAN_BIG): Define SFrame ABI/arch identifier
for s390x.
(SFRAME_S390X_SP_VAL_OFFSET): Define s390x-specific SP value
offset from CFA.
libsframe/
* sframe.c (need_swapping): Add SFRAME_ABI_S390X_ENDIAN_BIG.
* doc/sframe-spec.texi (SFRAME_ABI_S390X_ENDIAN_BIG, s390x,
SFRAME_S390X_SP_VAL_OFFSET): Document SFrame ABI/arch identifier
for s390x, add references to s390x architecture, and document
s390x-specifics, such as the SP value offset from CFA of -160.
gas/
* config/tc-s390.h: s390x support to generate .sframe from CFI
directives in assembler.
(support_sframe_p): Define.
(SFRAME_CFA_SP_REG, SFRAME_CFA_FP_REG, SFRAME_CFA_RA_REG):
Define.
(sframe_ra_tracking_p): Define.
(sframe_cfa_ra_offset): Define.
(sframe_get_abi_arch): Define.
* config/tc-s390.c: s390x support to generate .sframe from CFI
directives in assembler.
(s390_sframe_cfa_sp_reg, s390_sframe_cfa_fp_reg,
s390_sframe_cfa_ra_reg): New. Initialize to DWARF register
numbers of stack pointer (SP, r15), preferred frame pointer
(FP, r11), and return address (RA, r14) registers.
(s390_support_sframe_p): New function. Return true if s390x.
(s390_sframe_ra_tracking_p): New function. Return true.
(s390_sframe_cfa_ra_offset): New function. Return
SFRAME_CFA_FIXED_RA_INVALID.
(s390_sframe_get_abi_arch): New function. Return
SFRAME_ABI_S390X_ENDIAN_BIG if s390x, otherwise zero.
* gen-sframe.c: Add reference to s390x architecture in comments.
(sframe_xlate_do_val_offset): Add support for s390x-specific
SFRAME_S390X_SP_VAL_OFFSET.
* NEWS: Add news entry.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe.exp: Enable common SFrame tests for
s390x. Add s390x-specific SFrame (error) tests.
* gas/cfi-sframe/cfi-sframe-s390x-1.d: New s390x-specific SFrame
test.
* gas/cfi-sframe/cfi-sframe-s390x-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-2.d: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-2.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-err-1.d: New s390x-specific
SFrame error test that uses a non-default frame-pointer register
as CFA base register.
* gas/cfi-sframe/cfi-sframe-s390x-err-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-err-2.d: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-err-2.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-err-3.d: New s390x-specific
SFrame error test that uses a non-default return address
register.
* gas/cfi-sframe/cfi-sframe-s390x-err-3.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-offset-1.d: New s390x-
specific SFrame test that saves RA and FP individually on the
stack.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-offset-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-offset-err-1.d: New
s390x-specific SFrame error test that saves FP and RA
individually, to trigger FP without RA saved.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-offset-err-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-register-err-1.d: New
s390x-specific SFrame error test that saves FP and RA
individually in registers.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-register-err-1.s:
Likewise.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-register-err-2.d: New
s390x-specific SFrame error test that saves RA and FP
individually in registers.
* gas/cfi-sframe/cfi-sframe-s390x-fpra-register-err-2.s:
Likewise.
ld/testsuite/
* ld-s390/s390.exp: Add simple SFrame test.
* ld-s390/sframe-simple-1.d: New simple SFrame test.
* ld-s390/sframe-bar.s: Likewise.
* ld-s390/sframe-foo.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The v850 md_convert_frag function oddly calls subseg_change twice
(commit 1cd986c585). Neither call is needed, because that is done
in size_seg.
Convert the fr_opcode fixup field back (to an opindex, not fx_r_type)
using a cast rather than a union, since we used casts when setting up
those values. I guess the union was added to silence compiler
warnings about wrong-size casts, but unfortunately results in the
wrong value being retrieved on big-endian hosts.
Change "buffer" to a char* as there is no need to make it an
unsigned char*, and that way requires fewer casts. Finally, fix
formatting and use uintptr_t when make the rs_machine_dependent frags.
Remove subseg_change calls from cr16, crx, mn10200, mn10300, and sh
md_convert_frag too.
Rename the old enum alpha_macro_arg to alpha_macro_argset, and create
a union alpha_macro_arg to use in all the alpha_macro.emit functions.
This avoids intptr_t casts on retrieving index values and void* casts
on storing them in the alpha_macros array.
The point here is that when valueT is 64 bits and int is 32 bits,
1 << align doesn't work for shifts larger than the size of int. (Not
that anyone is likely to use such large alignments in real code.)
This patch removes many unneeded casts to char or unsigned char. It's
worth noting that safe-ctype.h macros ISDIGIT and the like cope with
either signed or unsigned char.
In some cases a cast to unsigned char is replaced by anding with 0xff,
which accomplishes the same thing but doesn't rely on char being eight
bits. The patch also removes pointer casts, and a few unsigned char
pointer variables.
Use standard sign extend and range checking using unsigned
expressions that don't rely on implementation defined right shifts or
size of short and int.
Calls to md_number_to_chars don't need to cast their value arg (*).
Remove those casts. avr_output_property_recode made a call to
md_number_to_chars with size of 1. Simplify that. tc-bpf.c
md_convert_frag used write_insn_bytes that simply copied input to
output. Dispense with that nonsense, and similarly in a couple of
other places where md_number_to_chars was called with size 1.
*) unless the value arg is an expression that needs a cast, eg. tic54x
emit_insn where the shift left could trigger signed overflow UB
without a cast.
This removes assorted unneeded casts of void* pointers, and casts when
passing args to void* parameters or storing to void* pointers. The
patch also changes obj-coff.c stack_push to take a void* parameter,
and replaces an odd memcpy in tc-metag.c find_insn_templates with a
simple assignment.
This removes a bunch of casts involving const pointers, in some cases
by making variables const pointers so a cast is not needed. In a
couple of places the cast hid errors with "&array" written rather than
"array", see iq2000_macro_defs and s_pru_align. tc-xgate.c cmp_opcode
is changed to be the standard qsort predicate to avoid a function
cast.
bfd_{h_,}put_* and bfd_{h_,}get_* have "void *" pointer params
nowadays. We don't need casts on their pointer args. We also don't
need to cast values passed to bfd_put.
This removes many unnecessary NULL casts. I'm also adding a few arg
casts in concat calls, to make the code consistent. Advice from quite
a few years ago was that it's better to use the exact type for args
corresponding to function ellipses, in case NULL is defined as plain
0. (I think that happened with some early 64-bit systems. Plain NULL
ought to be OK nowadays.)
Enumeration constants are integer types, so there should be no need to
cast such constants to int in expressions. (Perhaps some older gccs
warned, I checked back to gcc-4.5.) Remove some of those unnecessary
casts. Also remove unnecessary casts to bfd_reloc_code_real_type.
Many frag_var calls have unnecessary casts on arguments, no doubt from
the days when binutils was written for K&R C. (ie. functions were not
prototyped so you needed to cast anything that didn't match the
expected type after default promotions, as you still do for args
matching a function ellipsis.) Remove those casts.
* config/tc-alpha.c (s_alpha_comm): Use offset_T for cur_size
to avoid need for casts. Remove casts from frag_var args.
* config/tc-ia64.c (obj_elf_vms_common): Remove casts from
frag_var args.
* config/tc-m32r.c (m32r_scomm): Likewise.
* config/tc-m68hc11.c (build_jump_insn): Likewise.
(build_dbranch_insn): Likewise.
* config/tc-m68k.c (md_assemble): Likewise.
* config/tc-microblaze.c (microblaze_s_lcomm): Likewise.
* config/tc-mmix.c (s_loc): Likewise.
* config/tc-ppc.c (ppc_elf_lcomm, ppc_comm): Likewise.
* config/tc-score.c (s3_s_score_lcomm): Likewise.
* config/tc-score7.c (s7_s_score_lcomm): Likewise.
* config/tc-sh.c (sh_cons_align): Likewise.
* config/tc-sparc.c (s_reserve, s_common): Likewise.
(sparc_cons_align): Likewise.
* config/tc-tic4x.c (tic4x_seg_alloc, tic4x_bss): Likewise.
* config/tc-tic54x.c (tic54x_bss, tic54x_space): Likewise.
(tic54x_usect, tic54x_field): Likewise.
* config/tc-tic6x.c (s_tic6x_scomm): Likewise.
* config/tc-v850.c (v850_offset, v850_comm): Likewise.
* frags.c (frag_align, frag_align_pattern, frag_align_code): Likewise.
* gen-sframe.c (output_sframe_row_entry): Likewise.
(output_sframe_funcdesc): Likewise.
* read.c (s_fill, do_org, s_space, emit_leb128_expr): Likewise.
* symbols.c (colon)): Likewise.
Use "intptr_t" or "uintptr_t" for these conversions, not "long" which
is wrong on LLP64 systems, or "size_t" which is better but still not
the correct type.
* config/tc-alpha.c (emit_ldXu, emit_ldX, emit_uldXu, emit_uldX),
(emit_stX, emit_ustX, emit_sextX): Use correct type when
converting vlgsize pointer to in. Use "int" rather than
"long" for result.
* config/tc-ia64.c (generate_unwind_image): Use intptr_t cast
when passing personality_routine to frag_var.
* config/tc-ppc.c (ppc_frob_symbol <coff>): Use uintptr_t cast
when converting symbol pointer to valueT.
* config/tc-v850.c (md_assemble): Use intptr_t cast when
loading integer opindex.
This patch add support for FEAT_PoPS feature which can be enabled
through +pops command line flag.
This patch also adds support for following DC instructions and the
spec can be found here [1].
1. "dc cigdvaps" enabled on passing +memtag+pops command line flags.
2. "dc civaps" enabled on passing +pops command line flag.
[1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point
matrix multiply-accumulate to single-precision instruction.
FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix
multiply-accumulate to single-precision instruction.
FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix
multiply-accumulate to half-precision instruction.
FEAT_CMPBR - Compare and branch instructions. This patch adds these
instructions:
- CB<CC> (register)
- CB<CC> (immediate)
- CBH<CC>
- CBB<CC>
where CC is one of the following:
- EQ
- NE
- GT
- GE
- LT
- LE
- HI
- HS
- LO
- LS
FEAT_OCCMO support was introduced, but the feature flags were missing.
This patch adds these flags, as well as splitting up the tests to test
occmo vs occmo+memtag operands.
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in
Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also
introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE
and BFMUL.
They can be used like their %al/%cl counterparts everywhere else;
there's no apparent reason why they shouldn't be usable as accumulator /
shift count respectively. Enforcing such a restriction only makes
writing heavily macro-ized code more cumbersome.
