gas/
* config/tc-arm.c (encode_thumb2_ldmstm): New function.
(do_t_ldmstm): Generate 16-bit push/pop. Use encode_thumb2_ldmstm.
(do_t_push_pop): Use encode_thumb2_ldmstm.
gas/testsuite/
* gas/arm/thumb2_ldmstm.d: New test.
* gas/arm/thumb2_ldmstm.s: New test.
(parse_qfloat_immediate): Disallow integer syntax for floating-point
immediates. Fix hex immediates, handle 0.0 and -0.0 specially.
(parse_neon_mov): Set immisfloat bit for operand if it parsed as a
float.
(neon_cmode_for_move_imm): Reject non-float immediates for float
operands.
(neon_move_immediate): Pass immisfloat bit to neon_cmode_for_move_imm.
gas/
* config/tc-arm.c (do_t_add_sub): Use Rd and Rs.
gas/testsuite/
* gas/arm/thumb2_add.d: Add test for missing operand.
* gas/arm/thumb2_add.s: Ditto.
(do_neon_qshl_imm): Likewise.
(do_neon_rshl): New function. Handle rounding variants of
v{q}shl-by-register.
(insns): Use do_neon_rshl for vrshl, vqrshl.
gas/
* config/tc-arm.c (arm_force_relocation): Return 1 for relocs against
function symbols.
gas/testsuite/
* gas/arm/thumbrel.s: New test.
* gas/arm/thumbrel.d: New test.
gas/
* config/tc-arm.c (arm_is_eabi): New function.
* config/tc-arm.h (arm_is_eabi): New prototype.
(THUMB_IS_FUNC): Use ELF function type for EABI objects.
* doc/c-arm.texi (.thumb_func): Update documentation.
* arm-dis.c (last_is_thumb): Delete.
(enum map_type, last_type): New.
(print_insn_data): New.
(get_sym_code_type): Take MAP_TYPE argument. Check the type of
the right symbol. Handle $d.
(print_insn): Check for mapping symbols even without a normal
symbol. Adjust searching. If $d is found see how much data
to print. Handle data.
gas/
* config/tc-arm.h (md_cons_align): Define.
(mapping_state): New prototype.
* config/tc-arm.c (mapping_state): Make global.
gas/testsuite/
* gas/arm/arm7t.d, gas/arm/neon-ldst-rm.d, gas/arm/thumb2_pool.d,
gas/arm/tls.d: Update for $d support.
* gas/arm/mapshort.d, gas/arm/mapshort.s: New test.
* gas/elf/section2.e-armeabi: Update.
* gas/elf/section2.e-armelf: New file.
* gas/elf/elf.exp: Use it.
ld/testsuite/
* ld-arm/mixed-app.d, ld-arm/tls-app.d, ld-arm/tls-lib.d: Update
for $d support.
(arm_fix_adjustable) [OBJ_ELF]: Use it on coff targets too.
* gas/arm/local_label_coff.s: New test.
* gas/arm/local_label_coff.d: New test.
* gas/arm/local_label_elf.s: New test.
* gas/arm/local_label_elf.d: New test.
* gas/arm/local_label_wince.s: New test.
* gas/arm/local_label_wince.d: New test.
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
gas/
* config/tc-arm.c (do_neon_dyadic_if_i): Remove.
(do_neon_dyadic_if_i_d): Avoid setting U bit.
(do_neon_mac_maybe_scalar): Ditto.
(do_neon_dyadic_narrow): Force operand type to NT_integer.
(insns): Remove out of date comments.
gas/testsuite/
* gas/arm/neon-cov.s: Test .u and .s aliases for .i suffixes.
* gas/arm/neon-cov.d: Adjust expected output.
opcodes/
* arm-dis.c (neon_opcode): Fix suffix on VMOVN.
* config/tc-arm.c (s_arm_unwind_save_mmxwr): Correct condition for
merging with previous long opcode.
gas/testsuite:
* gas/arm/unwind.s: Test not merging iWMMXt register save with
previous long opcode.
* gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Update.
to use ARM instructions on non-ARM-supporting cores.
(autoselect_thumb_from_cpu_variant): New function. Switch on Thumb
mode automatically based on cpu variant.
(md_begin): Call above function.
* coff-arm.c (coff_arm_rtype_to_howto) [COFF_WITH_PE]: Handle ARM_SECREL.
(coff_arm_reloc_type_lookup): Map BFD_RELOC_32_SECREL to ARM_SECREL.
* pe-arm.c [COFF_SECTION_ALIGNMENT_ENTRIES]: Define.
* pei-arm.c [TARGET_UNDERSCORE]: Define for ARM_WINCE like in pe-arm.c.
[COFF_SECTION_ALIGNMENT_ENTRIES]: Define.
* config/tc-arm.c: Move "dwarf2dbg.h" inclusion out of OBJ_ELF only block.
(pe_directive_secrel) [TE_PE]: New function.
(md_pseudo_table) [!OBJ_ELF]: Handle 2byte, 4byte, 8byte, file, loc, loc_mark_labels.
[TE_PE]: Handle secrel32.
(output_relax_insn): Remove OBJ_ELF around dwarf2_emit_insn call.
(output_inst): Remove OBJ_ELF around dwarf2_emit_insn call.
(arm_frob_label): Remove OBJ_ELF around dwarf2_emit_label call.
(md_section_align): Only round section sizes here for AOUT targets.
(tc_arm_regname_to_dw2regnum): Move out for OBJ_ELF only block.
(tc_pe_dwarf2_emit_offset): New function.
(md_apply_fix) [TE_PE]: Handle BFD_RELOC_32_SECREL.
(cons_fix_new_arm): Handle O_secrel.
* config/tc-arm.h : Move DWARF2_LINE_MIN_INSN_LENGTH, DWARF2_DEFAULT_RETURN_COLUMN and DWARF2_CIE_DATA_ALIGNMENT out of OBJ_ELF only block.
[TE_PE]: Define O_secrel, TC_DWARF2_EMIT_OFFSET, and declare tc_pe_dwarf2_emit_offset.
* ld-pe/pe.exp: Enable tests on arm-wince-pe.
* ld-pe/secrel.d: Adjust test to work on arm-wince-pe too.
* config/tc-arm.c (parse_operands): Handle invalid register name
for OP_RIWR_RIWC.
gas/testsuite:
* gas/arm/iwmmxt-bad.s: Test invalid register names for wldrw and
wstrw.
* gas/arm/iwmmxt-bad.l: Update.
* config/tc-arm.c (enum operand_parse_code): Add OP_RIWC_RIWG.
(parse_operands): Handle it.
(insns): Use it for tmcr and tmrc.
gas/testsuite:
* gas/arm/iwmmxt.s: Test tmcr and tmrc with wcgr registers.
* gas/arm/iwmmxt.d: Update.
bfd/
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* reloc.c: Add BFD_RELOC_ARM_T32_ADD_IMM.
gas/
* tc-arm.c (do_t_add_sub): Use addw/subw when source is PC.
(md_convert_frag): Use correct reloc for add_pc. Use
BFD_RELOC_ARM_T32_ADD_IMM for normal add/sum.
(md_apply_fix): Handle BFD_RELOC_ARM_T32_ADD_IMM.
(arm_force_relocation): Handle BFD_RELOC_ARM_T32_ADD_IMM.
gas/testsuite/
* gas/arm/thumb2_add.d: New test.
* gas/arm/thumb2_add.s: New test.
* config/tc-arm.c (s_arm_unwind_save_vfp_armv6): New. Parse
a directive saving VFP registers for ARMv6 or later.
(s_arm_unwind_save): Add parameter arch_v6 and call
s_arm_unwind_save_vfp or s_arm_unwind_save_vfp_armv6 as
appropriate.
(md_pseudo_table): Add entry for new "vsave" directive.
* doc/c-arm.texi: Correct error in example for "save"
directive (fstmdf -> fstmdx). Also document "vsave" directive.
to R_ARM_LDC_SB_G{0,1,2} respectively.
bfd/
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
gas/
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
gas/testsuite/
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
ld/testsuite/
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
(arm_it): Add uncond_value field. Add isvec and issingle to operand
array.
(arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and
REG_TYPE_NSDQ (single, double or quad vector reg).
(reg_expected_msgs): Update.
(BAD_FPU): Add macro for unsupported FPU instruction error.
(parse_neon_type): Support 'd' as an alias for .f64.
(parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ
sets of registers.
(parse_vfp_reg_list): Don't update first arg on error.
(parse_neon_mov): Support extra syntax for VFP moves.
(operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO,
OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ.
(parse_operands): Support isvec, issingle operands fields, new parse
codes above.
(do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs,
msr variants.
(do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above.
(NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez.
(NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros.
(NEON_SHAPE_DEF): New macro. Define table of possible instruction
shapes.
(neon_shape): Redefine in terms of above.
(neon_shape_class): New enumeration, table of shape classes.
(neon_shape_el): New enumeration. One element of a shape.
(neon_shape_el_size): Register widths of above, where appropriate.
(neon_shape_info): New struct. Info for shape table.
(neon_shape_tab): New array.
(neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL.
(neon_check_shape): Rewrite as...
(neon_select_shape): New function to classify instruction shapes,
driven by new table neon_shape_tab array.
(neon_quad): New function. Return 1 if shape should set Q flag in
instructions (or equivalent), 0 otherwise.
(type_chk_of_el_type): Support F64.
(el_type_of_type_chk): Likewise.
(neon_check_type): Add support for VFP type checking (VFP data
elements fill their containing registers).
(do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE
in thumb mode for VFP instructions.
(do_vfp_nsyn_opcode): New function. Look up the opcode in argument,
and encode the current instruction as if it were that opcode.
(try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS
arguments, call function in PFN.
(do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul)
(do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str)
(do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul)
(do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push)
(do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions.
Redirect Neon-syntax VFP instructions to VFP instruction handlers.
(do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm)
(do_neon_qshl_imm, do_neon_logic, do_neon_bitfield)
(neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh)
(do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri)
(do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext)
(do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn)
(do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long)
(do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt)
(do_neon_swp): Use neon_select_shape not neon_check_shape. Use
neon_quad.
(vfp_or_neon_is_neon): New function. Call if a mnemonic shared
between VFP and Neon turns out to belong to Neon. Perform
architecture check and fill in condition field if appropriate.
(do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg)
(do_neon_cvt): Add support for VFP variants of instructions.
(neon_cvt_flavour): Extend to cover VFP conversions.
(do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP
vmov variants.
(do_neon_ldr_str): Handle single-precision VFP load/store.
(do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use
NS_NULL not NS_IGNORE.
(opcode_tag): Add OT_csuffixF for operands which either take a
conditional suffix, or have 0xF in the condition field.
(md_assemble): Add support for OT_csuffixF.
(NCE): Replace macro with...
(NCE_tag, NCE, NCEF): New macros.
(nCE): Replace macro with...
(nCE_tag, nCE, nCEF): New macros.
(insns): Add support for VFP insns or VFP versions of insns msr,
mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop,
vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia,
vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared
VFP/Neon insns together.
