Commit Graph

23 Commits

Author SHA1 Message Date
Kuan-Lin Chen
80d49d6a1b RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions
bfd/
	* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.

gas/
	* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
	(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
	* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
	* testsuite/gas/riscv/b-ext-64.d: Likewise.
	* testsuite/gas/riscv/b-ext.s: Likewise.
	* testsuite/gas/riscv/b-ext.d: Likewise.

include/
	* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
	* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.

opcodes/
	* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-16 14:38:19 +08:00
Nelson Chu
cb4ff67af3 RISC-V: PR27348, Remove obsolete Xcustom support.
include/
    PR 27348
    * opcode/riscv-opc.h: Remove obsolete Xcustom support.
2021-02-05 11:04:59 +08:00
Nelson Chu
24075dcc85 RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
bfd/
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Removed
    INSN_CLASS_ZB*.
    * testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
    * testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
    * testsuite/gas/riscv/bitmanip-insns.s: Removed.
include/
    * opcode/riscv-opc.h: Removed macros for zb* extensions.
    * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*.
opcodes/
    * riscv-opc.c (MASK_RVB_IMM): Removed.
    (riscv_opcodes): Removed zb* instructions.
    (riscv_ext_version_table): Removed versions for zb*.
2021-02-04 16:52:13 +08:00
Nelson Chu
dcd709e056 RISC-V: Comments tidy and improvement.
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces.  But sometimes it should be more
cleaner when the comments only include a word or codes.  Therefore, I made
the following changes after referring to other target/generic codes,

* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.

Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.

bfd/
    * elfnn-riscv.c: Comments tidy and improvement.
    * elfxx-riscv.c: Likewise.
    * elfxx-riscv.h: Likewise.
gas/
    * config/tc-riscv.c: Comments tidy and improvement.  Also update
    comment "fallthru" to "Fall through" that end with a period and
    two spaces.
include/
    * elf/riscv.h: Comments tidy and improvement.
    * opcode/riscv-opc.h: Likewise.
    * opcode/riscv.h: Likewise.
opcodes/
    * riscv-dis.c: Comments tidy and improvement.
    * riscv-opc.c: Likewise.
2021-01-15 17:28:07 +08:00
Philipp Tomsich
aa881ecde4 RISC-V: Add pause hint instruction.
Add support for the pause hint instruction, as specified in the
Zihintpause extension.  The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set).  The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Added
    INSN_CLASS_ZIHINTPAUSE.
    * testsuite/gas/riscv/pause.d: New testcase.  Adding coverage for
    the pause hint instruction.
    * testsuite/gas/riscv/pause.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
    for pause hint instruction.
    * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
2021-01-07 16:45:43 +08:00
Claire Xenia Wolf
2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future.  Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them.  Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.

This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101

2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
            Jim Wilson  <jimw@sifive.com>
            Andrew Waterman  <andrew@sifive.com>
            Maxim Blinov  <maxim.blinov@embecosm.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
    (riscv_get_default_ext_version): Do not check the default_isa_spec when
    the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
    * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
    * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
    * testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
    * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
    (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
    frozen extensions.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
    (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
2021-01-07 11:44:54 +08:00
Alan Modra
250d07de5c Update year range in copyright notice of binutils files 2021-01-01 10:31:05 +10:30
Nelson Chu
08ccfccf0e RISC-V: Support debug and float CSR as the unprivileged ones.
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec.  For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec.  User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly.  Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them.  However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.

	gas/
	* config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
	checking into riscv_csr_address.
	(riscv_csr_version_check): Likewise.
	(riscv_csr_address): New function.  Return the suitable CSR address
	after checking the ISA dependency and versions.  Issue warnings	if
	we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
	CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
	priv spec versions for them.
	(reg_csr_lookup_internal): Call riscv_csr_address to find the
	suitable CSR address.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
	priv spec warnings here.  These warnings are added by accident.
	Remove them and only focus on the ISA dependency warnings.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
	dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
	than the privileged ones.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Support the unprivileged CSR.  The versions
	of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
	* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.

	opcodes/
	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
	unprivileged CSR can also be initialized.
2020-06-30 09:54:55 +08:00
Nelson Chu
83d7d99e75 RISC-V: Cleanup the include/opcode/riscv-opc.h.
The include/opcode/riscv-opc.h file is no longer automatically generated,
so we remove the misleading comments and add new ones.  Besides, the CAUSE_*
macros and DECLARE_CAUSE are unused for binutils and gdb.  Therefore, remove
them, too.

	include/
	* opcode/riscv-opc.h: Cleanup and remove the unused macros.
2020-06-30 09:38:00 +08:00
Nelson Chu
d8af286fff RISC-V: Drop the privileged spec v1.9 support.
There is a conflict between v1.9 and v1.9.1 - CSR MISA address.  MISA is
0xf10 in v1.9, but change to 0x301 in v1.9.1.  The change made MISA writable,
but may also cause risk of compatibility.  Binutils already support the
-mpriv-spec options and ELF priv attributes, which can used to choose what
privileged spec you want, and then give a correponding CSR name and address
to use.  But Gdb and other tools don't have the simialr mechanism for now.
However, there are two things can be confirmed,

1. If we don't have a way to control the priv specs, then the changes, like
MISA, will cause risk and hard to maintain.

2. We get the guarantee that the CSR address won't be reused in the future
specs, even if it is dropped.

I'm not sure if Gdb needs to care about the priv spec versions, it is still
discussing.  But drop the priv spec v1.9, and make sure that we won't reuse
the CSR address is a useful solution for now.  Also, we might drop the v1.9.1
in a year or two.  After that, specs above v1.10 should be compatible anyway.

	gas/
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.

	include/
	* opcode/riscv-opc.h: Update the defined versions of CSR from
	PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1.  Also, drop the
	MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9.
	* opcode/riscv.h (enum riscv_priv_spec_class): Remove
	PRIV_SPEC_CLASS_1P9.

	opcodes/
	* riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
2020-06-12 09:41:20 +08:00
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
2020-05-20 17:22:48 +01:00
Nelson Chu
d1a89da5de RISC-V: Update CSR to privileged spec 1.11.
gas/
	* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
	* testsuite/gas/riscv/alias-csr.s: Likewise.
	* testsuite/gas/riscv/no-aliases-csr.d: Move this
	to priv-reg-pseudo-noalias.
	* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
	* testsuite/gas/riscv/bad-csr.l: Likewise.
	* testsuite/gas/riscv/bad-csr.s: Likewise.
	* testsuite/gas/riscv/satp.d: Removed.  Already included in priv-reg.
	* testsuite/gas/riscv/satp.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
	csr instruction, including alias-csr testcase.
	* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
	* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
	pseudo instruction with objdump -Mno-aliases.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
	* testsuite/gas/riscv/priv-reg.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Update CSR to 1.11.

	gdb/
	* features/riscv/32bit-csr.xml: Regenerated.
	* features/riscv/64bit-csr.xml: Regenerated.
2020-03-30 12:24:53 -07:00
Nelson Chu
bd0cf5a6ba RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set.  We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information.  We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option.  Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.

	gas/
	* config/tc-riscv.c (enum riscv_csr_class): New enum.  Used to decide
	whether or not this CSR is legal in the current ISA string.
	(struct riscv_csr_extra): New structure to hold all extra information
	of CSR.
	(riscv_init_csr_hash): New function.  According to the DECLARE_CSR and
	DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
	Call hash_reg_name to insert CSR address into reg_names_hash.
	(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
	(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
	Decide whether the CSR is valid according to the csr_extra_hash.
	(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
	not a boolean.  This is same as riscv_init_csr_hash, so keep the
	consistent usage.

	* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
	* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase.  The source
	file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
	f-ext CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase.  The
	source file is `priv-reg.s`, and the ISA is rv64if, so the
	rv32-only CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.

	include/
	* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
	record riscv_csr_class.

	opcodes/
	* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.

	gdb/
	* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
	* riscv-tdep.h: Likewise.
	* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
	rv32-only CSR.
	* features/riscv/64bit-csr.xml: Regernated.

	binutils/
	* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-20 16:49:09 -08:00
Palmer Dabbelt
64a336ac13 RISC-V: Add fence.tso instruction
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
2018-10-02 08:26:32 -07:00
Jim Wilson
e6f372ba66 RISC-V: Add missing hint instructions from RV128I.
gas/
	* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test.  Add disabled
	future test for RV128 support.
	* testsuite/gas/riscv/c-zero-reg.s: Likewise.

	include/
	* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
	(MATCH_C_SRAI64, MASK_C_SRAI64): New.
	(MATCH_C_SLLI64, MASK_C_SLLI64): New.

	opcodes/
	* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
	(match_c_slli64, match_srxi_as_c_srxi): New.
	(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
	<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
	<c.slli, c.srli, c.srai>: Use match_s_slli.
	<c.slli64, c.srli64, c.srai64>: New.
2018-05-08 15:46:19 -07:00
Jim Wilson
645a2c5b46 RISC-V: Add 2 missing privileged registers.
gas/
	* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
	* testsuite/gas/riscv/priv-reg.d: Likewise.

	include/
	* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL.  Rename
	DECLARE_CSR entry.  Add alias to map sbadaddr to CSR_STVAL.
	(CSR_MBADADDR): Rename to CSR_MTVAL.  Rename DECLARE_CSR entry.
	Add alias to map mbadaddr to CSR_MTVAL.
2018-01-04 14:17:53 -08:00
Jim Wilson
d9be0c189a RISC-V: Add missing privileged spec registers.
gas/
	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.

	include/
	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
	Sort to match privileged spec documentation order.
	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
2017-12-28 13:21:46 -08:00
Palmer Dabbelt
1270b047fd RISC-V: Add satp as an alias for sptbr
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page
Table Base Register) to satp (Supervisor Address Translation and
Protection) to reflect the fact it could be used for more than just
paging.  This patch adds an alias, as they're the same register.

include/ChangeLog

2017-11-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * opcode/riscv-opc.h (sptbr): Rename to satp.
        (CSR_SPTBR): Rename to CSR_SATP.
        (sptbr): Alias to CSR_SATP.

gas/ChangeLog

2017-11-06  Palmer Dabbelt  <palmer@dabbelt.com>

        * testsuite/gas/riscv/satp.d: New test.
        testsuite/gas/riscv/satp.s: Likewise.
        testsuite/gas/riscv/riscv.exp: Likewise.
        config/tc-riscv.c (md_begin): Handle CSR aliases.
2017-11-07 09:00:37 -08:00
Andrew Waterman
858f82bf7e RISC-V: Add physical memory protection CSRs
2017-03-27  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_PMPCFG0): New define.
       (CSR_PMPCFG1): Likewise.
       (CSR_PMPCFG2): Likewise.
       (CSR_PMPCFG3): Likewise.
       (CSR_PMPADDR0): Likewise.
       (CSR_PMPADDR1): Likewise.
       (CSR_PMPADDR2): Likewise.
       (CSR_PMPADDR3): Likewise.
       (CSR_PMPADDR4): Likewise.
       (CSR_PMPADDR5): Likewise.
       (CSR_PMPADDR6): Likewise.
       (CSR_PMPADDR7): Likewise.
       (CSR_PMPADDR8): Likewise.
       (CSR_PMPADDR9): Likewise.
       (CSR_PMPADDR10): Likewise.
       (CSR_PMPADDR11): Likewise.
       (CSR_PMPADDR12): Likewise.
       (CSR_PMPADDR13): Likewise.
       (CSR_PMPADDR14): Likewise.
       (CSR_PMPADDR15): Likewise.
       (pmpcfg0): Declare register.
       (pmpcfg1): Likewise.
       (pmpcfg2): Likewise.
       (pmpcfg3): Likewise.
       (pmpaddr0): Likewise.
       (pmpaddr1): Likewise.
       (pmpaddr2): Likewise.
       (pmpaddr3): Likewise.
       (pmpaddr4): Likewise.
       (pmpaddr5): Likewise.
       (pmpaddr6): Likewise.
       (pmpaddr7): Likewise.
       (pmpaddr8): Likewise.
       (pmpaddr9): Likewise.
       (pmpaddr10): Likewise.
       (pmpaddr11): Likewise.
       (pmpaddr12): Likewise.
       (pmpaddr13): Likewise.
       (pmpaddr14): Likewise.
       (pmpaddr15): Likewise.
2017-03-31 09:35:11 -07:00
Andrew Waterman
742d14b39b Add new counter-enable CSRs
include/ChangeLog:

2017-02-22  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
       (CSR_MCOUNTEREN): Likewise.
       (scounteren): Declare register.
       (mcounteren): Likewise.
2017-02-24 09:24:58 -08:00
Andrew Waterman
f98d33be3a Add SFENCE.VMA instruction
include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.
2017-02-15 10:35:00 -08:00
Kito Cheng
cc917fd93d Add support for the Q extension to the RISCV ISA.
gas    * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
        extension.
        (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
        enabled and no other ABI is specified.

include * opcode/riscv-opc.h: Add support for the "q" ISA extension.

opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
        extension.
        * riscv-opcodes/all-opcodes: Likewise.
2017-01-03 17:42:01 +00:00
Nick Clifton
e23eba971d Add support for RISC-V architecture.
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
2016-11-01 16:45:57 +00:00