Commit Graph

18 Commits

Author SHA1 Message Date
Joel Brobecker
213516ef31 Update copyright year range in header of all files managed by GDB
This commit is the result of running the gdb/copyright.py script,
which automated the update of the copyright year range for all
source files managed by the GDB project to be updated to include
year 2023.
2023-01-01 17:01:16 +04:00
Mike Frysinger
883be19774 sim: cpu: change default init to handle all cpus
All the runtimes were only initializing a single CPU.  When SMP is
enabled, things quickly crash as none of the other CPU structs are
setup.  Change the default from 0 to the compile time value.
2022-12-25 02:10:46 -05:00
Mike Frysinger
f3e1a3e6fa sim: riscv: move arch-specific settings to internal header
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so move it all out to a new header which only
this port will include.

We can also move the machs.h include out since the model logic was all
generalized from compile-time to runtime last year.
2022-12-23 08:32:58 -05:00
Mike Frysinger
6cf3ddd23e sim: move bfd.h include out of sim-main.h
Not all arches include this in sim-main.h, and the ones that do don't
actually use bfd defines in the sim-main.h header.  Prune it to make
sim-main.h simpler so we can kill it off entirely in the future.

We add the include to the files that utilize e.g. bfd_vma though.
2022-12-22 22:06:12 -05:00
Mike Frysinger
20fea6638f sim: use bfd_vma when reading start addr from bfd info
Since SIM_ADDR is always 32-bit, it might truncate the address with
64-bit ELFs.  Since we load that addr from the bfd, use the bfd_vma
type which matches the bfd_get_start_address API.
2022-12-22 19:29:10 -05:00
Mike Frysinger
5409cab77e sim: riscv: invert sim_cpu storage 2022-12-21 00:00:01 -05:00
Joel Brobecker
4a94e36819 Automatic Copyright Year update after running gdb/copyright.py
This commit brings all the changes made by running gdb/copyright.py
as per GDB's Start of New Year Procedure.

For the avoidance of doubt, all changes in this commits were
performed by the script.
2022-01-01 19:13:23 +04:00
Mike Frysinger
c8c6ef3807 sim: riscv: switch to new target-newlib-syscall
Use the new target-newlib-syscall module.  This is needed to merge all
the architectures into a single build, and riscv has a custom syscall
table for its newlib/libgloss port.
2021-11-28 13:23:58 -05:00
Mike Frysinger
8cfc9a1895 sim: callback: expose argv & environ
Pass the existing strings data to the callbacks so that common
libgloss syscalls can be implemented (which we'll do shortly).
2021-11-16 01:13:39 -05:00
Mike Frysinger
54f7a83a62 sim: keep track of program environment strings
We've been passing the environment strings to sim_create_inferior,
but most ports don't do anything with them.  A few will use ad-hoc
logic to stuff the stack for user-mode programs, but that's it.

Let's formalize this across the board by storing the strings in the
normal sim state.  This will allow (in future commits) supporting
more functionality in the run interface, and to unify some of the
libgloss syscalls.
2021-11-16 00:58:41 -05:00
Mike Frysinger
e8f20a28b1 sim: split program path out of argv vector
We use the program argv to both find the program to run (argv[0]) and
to hold the arguments to the program.  Most of the time this is fine,
but if we want to let programs specify argv[0] independently (which is
possible in standard *NIX programs), this double duty doesn't work.

So let's split the path to the program to run out into a separate
field by itself.  This simplifies the various sim_open funcs too.

By itself, this code is more of a logical cleanup than something that
is super useful.  But it will open up customization of argv[0] in a
follow up commit.  Split the changes to make it easier to review.
2021-11-15 02:53:29 -05:00
Mike Frysinger
d414eb3e7f sim: move default model to the runtime sim state
This kills off another compile-time option by moving the setting to
the individual arch runtimes.  This will allow dynamic selection by
the arch when doing a single build with multiple arches.

The sim_model_init rework is a little funky.  In the past it was
disabled entirely if no default model was set.  We maintain the
spirit of the logic by gating the fallback logic on whether the
port has defined any models.
2021-06-30 02:57:45 -04:00
Mike Frysinger
1c636da093 sim: namespace sim_machs
We want to do a single build with all arches in one binary which means
we need to namespace sim_machs on a per-arch basis.  Move it from a
global variable to the sim description structure so it can be setup at
runtime.

Changing the SIM_MODEL->num from an enum to an int is unfortunate, but
we specifically don't want to maintain a centralized list anymore, and
this was never used directly in common code, just passed to per-arch
callbacks.
2021-06-30 01:52:51 -04:00
Mike Frysinger
f9a4d54332 sim: overhaul & unify endian settings management
The m4 macro has 2 args: the "wire" settings (which represents the
hardwired port behavior), and the default settings (which are used
if nothing else is specified).  If none are specified, the arch is
expected to support both, and the value will be probed based on the
user runtime options or the input program.

Only two arches today set the default value (bpf & mips).  We can
probably let this go as it only shows up in one scenario: the sim
is invoked, but with no inputs, and no user endian selection.  This
means bpf will not behave like the other arches: an error is shown
and forces the user to make a choice.  If an input program is used
though, we'll still switch the default to that.  This allows us to
remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting.

For the ports that set a "wire" endian, move it to the runtime init
of the respective sim_open calls.  This allows us to change the
WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting
if they want to force a specific endianness.

With all the endian logic moved to runtime selection, we can move
the configure call up to the common dir so we only process it once
across all ports.

The ppc arch was picking the wire endian based on the target used,
but since we weren't doing that for other biendian arches, we can
let this go too.  We'll rely on the input selecting the endian, or
make the user decide.
2021-06-17 23:20:13 -04:00
Mike Frysinger
10c23a2c6f sim: riscv: invert sim_state storage 2021-05-17 01:02:09 -04:00
Mike Frysinger
6df01ab8ab sim: switch config.h usage to defs.h
The defs.h header will take care of including the various config.h
headers.  For now, it's just config.h, but we'll add more when we
integrate gnulib in.

This header should be used instead of config.h, and should be the
first include in every .c file.  We won't rely on the old behavior
where we expected files to include the port's sim-main.h which then
includes the common sim-basics.h which then includes config.h.  We
have a ton of code that includes things before sim-main.h, and it
sometimes needs to be that way.  Creating a dedicated header avoids
the ordering mess and implicit inclusion that shows up otherwise.
2021-05-16 22:38:41 -04:00
Mike Frysinger
d5a71b1131 sim: cgen: move cgen_cpu_max_extra_bytes logic into the common code
Every arch handles this the same way, so move it to the common code.
This will also make unifying the sim_cpu structure easier.
2021-04-12 00:14:32 -04:00
Mike Frysinger
b9249c461c sim: riscv: new port
This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.
2021-02-04 19:02:19 -05:00