This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F'
or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx'
extension already contains "fmv.h" instruction (as well as 'Zfh').
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction.
* testsuite/gas/riscv/zqinx.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]"
instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's 'Zhinx' testcases.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Use different registers for
better encode space testing. Make indentation consistent.
Add tests for instruction with rounding mode. Change march
to minimum required extensions. Remove source line.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Likewise.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.s: Likewise.
Also use even-numbered registers to use valid register pairs.
* testsuite/gas/riscv/zqinx.d: Likewise.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: jiawei <jiawei@iscas.ac.cn>
FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but
presently they aren't. This fixes disassembly of these insns with
-Mno-aliases.
For disassembly to pick up aliases in favor of underlying insns (helping
readability in the common case), the aliases need to come ahead of the
"base" insns. Slightly more code movement is needed because of insns
with the same name needing to stay next to each other.
Note that the "rorw" alias entry also has the missing INSN_ALIAS added
here.
Clone a few testcases to exercise -Mno-aliases some more, better
covering the differences between the default and that disassembly mode.
At the example of
extractps $0, %xmm0, %xmm0
insertps $0, %xmm0, %eax
(both having respectively the same mistake of using the wrong kind of
destination register) it is easy to see that current behavior is far
from ideal: The former results in "unsupported instruction" for 32-bit
code simply because the 2nd template we have is a Cpu64 one. Instead we
should aim at emitting the "best" possible error, which will typically
be the one where we passed the largest number of checks. Generalize the
original "specific_error" approach by making it apply to the entire
matching loop, utilizing that line numbers increase as we pass further
checks.
While in some cases deriving an AT&T-style suffix from an Intel syntax
memory operand size specifier is necessary, in many cases this is not
only pointless, but has led to the introduction of various workarounds:
Excessive use of IgnoreSize and NoRex64 as well as the ToDword and
ToQword attributes. Suppress suffix derivation when we can clearly tell
that the memory operand's size isn't going to be needed to infer the
possible need for the low byte/word opcode bit or an operand size prefix
(0x66 or REX.W).
As a result ToDword and ToQword can be dropped entirely, plus a fair
number of IgnoreSize and NoRex64 can also be got rid of. Note that
IgnoreSize needs to remain on legacy encoded SIMD insns with GPR
operand, to avoid emitting an operand size prefix in 16-bit mode. (Since
16-bit code using SIMD insns isn't well tested, clone an existing
testcase just enough to cover a few insns which are potentially
problematic but are being touched here.)
Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI
isn't included there. This is to fulfill the request of not allowing L
and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
Since we have the same behaviors of CALL and CALL_PLT relocs in linker for now,
3b1450b38c
And the psabi already deprecate the CALL reloc,
a0dced8501
Therefore, we should always generate R_RISCV_CALL_PLT reloc for call, even if
it has @plt postfix. I believe LLVM (https://reviews.llvm.org/D132530) already
support this, so GNU as should do the same thing.
gas/
* config/tc-riscv.c (riscv_ip): Always generate CALL_PLT reloc for
call, even if it has @plt postfix.
* testsuite/gas/riscv/no-relax-reloc.d: Updated CALL to CALL_PLT.
* testsuite/gas/riscv/relax-reloc.d: Likewise.
ld/
* testsuite/ld-riscv-elf/variant_cc-r.d: Updated CALL to CALL_PLT.
It looks like I copied the SIZE init across from
binutils/testsuite/config/default.exp without some necessary editing.
* testsuite/config/default.exp (SIZE): Adjust relative path.
Vector CSRs are also required on smaller vector subsets.
Not only that the most of vector CSRs are general purpose (and must be
accessible for every vector subsets), current minimum vector subset 'Zve32x'
requires fixed point arithmetic, making remaining non-general purpose
(fixed point arithmetic only) CSRs mandatory for such subsets.
So, those CSRs must be accessible from 'Zve32x', not just from 'V'.
This commit fixes this issue which caused CSR accessibility warnings.
gas/ChangeLog:
* config/tc-riscv.c (riscv_csr_address): Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR
requirement from 'V' to 'Zve32x'.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
PR 29559
* dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at
the end of the list of children, not at the start of the CU
information.
* testsuite/gas/elf/dwarf-3-func.d: Update expected output.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
PR 29517
* dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant.
(GAS_ABBREV_SUBPROG): New defined constant.
(GAS_ABBREV_NO_TYPE): New defined constant.
(out_debug_abbrev): Use the new defined constants when emitting
abbreviation numbers. Generate an abbreviation for an unspecified
type.
(out_debug_info): Use the new defined constants when referring to
abbreviations. Generate a use of the no_type abbreviation.
Reference the use when generating DIEs for functions.
* testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly
extended output from the assembler.
* testsuite/gas/elf/dwarf-5-func-global.d: Likewise.
* testsuite/gas/elf/dwarf-5-func-local.d: Likewise.
* testsuite/gas/elf/dwarf-5-func.d: Likewise.
PR 29519
* config/tc-aarch64.c (s_unreq): Use find_end_of_line().
(s_aarch64_cpu): Likewise.
(s_aarch64_arch): Likewise.
(s_aarch64_arch_extension): Likewise.
* testsuite/gas/aarch64/pr29519.d: New test driver file.
* testsuite/gas/aarch64/pr29519.s: New test source file.
There's been a long-standing bug in the arm backend where
target-specific directives did not correctly handle lines with
multiple statements. This patch fixes the issue for all the cases
I've been able to find.
It does result in a slight change in behaviour when errors are
encountered: where, previously,
.cpu arm6 bar
would result in the error "junk at end of line, first unrecognized
character is `b'", we now get "unknown cpu `arm6 bar'", which I think
is slightly more helpful anyway. Similar errors are generated for
other directives.
Instructions that can load immediate support using constant
variable like ".equ var, 123 li.w/d resgister, var".
gas/
* config/loongarch-parse.y
* config/tc-loongarch.c
Add four testcases.One is a program using constant variable,
one test using label is unsupported, and another two test
almost instructions that can load immediate.
gas/
* testsuite/gas/loongarch/li.d
* testsuite/gas/loongarch/li.s
* testsuite/gas/loongarch/imm_ins_label-fail.d
* testsuite/gas/loongarch/imm_ins_label-fail.l
* testsuite/gas/loongarch/imm_ins_label-fail.s
* testsuite/gas/loongarch/imm_ins.d
* testsuite/gas/loongarch/imm_ins.s
* testsuite/gas/loongarch/imm_ins_32.d
* testsuite/gas/loongarch/imm_ins_32.s
When displaying operands, invalid opcodes may overflow operand buffer
due to additional styling characters. Each style is encoded with 3
bytes. Define MAX_OPERAND_BUFFER_SIZE for operand buffer size and
increase it from 100 bytes to 128 bytes to accommodate 9 sets of styles
in an operand.
gas/
PR binutils/29483
* testsuite/gas/i386/i386.exp: Run pr29483.
* testsuite/gas/i386/pr29483.d: New file.
* testsuite/gas/i386/pr29483.s: Likewise.
opcodes/
PR binutils/29483
* i386-dis.c (MAX_OPERAND_BUFFER_SIZE): New.
(obuf): Replace 100 with MAX_OPERAND_BUFFER_SIZE.
(staging_area): Likewise.
(op_out): Likewise.
This changes readelf output a little, removing the 0x prefix on hex
output when the value is 0, except in cases where a fixed field
width is shown. %#010x is not a good replacement for 0x%08x.
Commit 53f2b36a54 exposed a bug in sb_scrub_and_add_sb that could
result in losing input. If scrubbing results in expansion past the
holding capacity of do_scrub_chars output buffer, then do_scrub_chars
stashes the extra input for the next call. That call never came
because sb_scrub_and_add_sb wrongly decided it was done. Fix that by
allowing sb_scrub_and_add_sb to see whether there is pending input.
Also allow a little extra space so that in most cases we won't need
to resize the output buffer.
sb_scrub_and_add_sb also limited output to the size of the input,
rather than the actual output buffer size. Fixing that resulted in a
fail of gas/testsuite/macros/dot with an extra warning: "end of file
not at end of a line; newline inserted". OK, so the macro in dot.s
really does finish without end-of-line. Apparently the macro
expansion code relied on do_scrub_chars returning early. So fix that
too by adding a newline if needed in macro_expand_body.
PR 29466
* app.c (do_scrub_pending): New function.
* as.h: Declare it.
* input-scrub.c (input_scrub_include_sb): Add extra space for
two .linefile directives.
* sb.c (sb_scrub_and_add_sb): Take into account pending input.
Allow output to max.
* macro.c (macro_expand_body): Add terminating newline.
* testsuite/config/default.exp (SIZE, SIZEFLAGS): Define.
* testsuite/gas/macros/app5.d,
* testsuite/gas/macros/app5.s: New test.
* testsuite/gas/macros/macros.exp: Run it.
It is unclear to me why the corresponding MOV (no Q suffix) can be
issued without REX.W, but MOVQ has to have that prefix (bit). Add
NoRex64 and in exchange drop Size64.
While the x/y/z suffix isn't necessary to use in this case, it is still
odd that these forms don't support broadcast (unlike their AVX512F /
AVX512DQ counterparts). The lack thereof can e.g. make macro-ized
programming more difficult.
The commit 1369522f36 ("Recognize the new ELF
compression type for ZSTD.") added the new ELF compression type but it
accidentally broke a GAS testcase. Since testing for the section type
"2048" (SHF_COMPRESSED) is not going to be portable in the long term, it
now tests SHF_LINK_ORDER ("128") instead.
Using SHF_LINK_ORDER (with possibly sh_link == 0) is an idea by Jan Beulich.
gas/ChangeLog:
* testsuite/gas/elf/section10.s: Use SHF_LINK_ORDER to test
mixed numeric and alpha values.
* testsuite/gas/elf/section10.d: Reflect the change above.
This patch extends assembler support for the use of register names to
allow for pseudo-registers, e.g. ra_auth_code register.
This is done particularly with CFI directives in mind, allowing for
expressions of the type:
.cfi_register ra_auth_code, 12
gas/Changelog:
* config/tc-arm.c (tc_arm_regname_to_dw2regnum): Add
REG_TYPE_PSEUDO handling.
* testsuite/gas/arm/cfi-pacbti-m-readelf.d: New.
* testsuite/gas/arm/cfi-pacbti-m.s: New.
This patch modifies the internal `struct reg_entry' numbering of DWARF
pseudo-registers to match values assigned in DWARF standards (see "4.1
DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and
amends the unwinder .save directive-processing code to correctly handle
mixed register-type save directives.
The mechanism for splitting the register list is also re-written to
comply with register ordering on push statements, being that registers
are stored on the stack in numerical order, with the lowest numbered
register at the lowest address [2].
Consequently, the parsing of the hypothetical directive
.save{r4-r7, r10, ra_auth_core, lr}
has been changed such as rather than producing
.save{r4-r7, r10}
.save{ra_auth_code}
.save{lr}
as was the case with previous implementation, now produces:
.save{lr}
.save{ra_auth_code}
.save{r4-r7, r10}
[1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst>
[2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push>
gas/Changelog:
* config/tc-arm.c (REG_RA_AUTH_CODE): New.
(parse_dot_save): Likewise.
(parse_reg_list): Remove obsolete code.
(reg_names): Set ra_auth_code to 143.
(s_arm_unwind_save): Handle core and pseudo-register lists via
parse_dot_save.
(s_arm_unwind_save_mixed): Deleted.
(s_arm_unwind_save_pseudo): Handle one register at a time.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
This syntactic sugar is present in both classical and emerging
architectures, like Alpha, SPARC and RISC-V, and assembler macros
doing the same thing can already be found in the wild e.g. [1], proving
the feature's popularity. It's better to provide support directly in the
assembler so downstream users wouldn't have to re-invent this over and
over again.
[1]: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/loongarch/sysdep.h;h=c586df819cd90;hb=HEAD#l28
Also re-order the jump/branch opcodes while at it, so that insns are
sorted in ascending order according to opcodes, and the label form
preceding the real definition.
These two macros print either a 16 digit hex number or an 8 digit
hex number. Unfortunately they depend on both target and host, which
means that the output for 32-bit targets may be either 8 or 16 hex
digits.
Replace them in most cases with code that prints a bfd_vma using
PRIx64. In some cases, deliberately lose the leading zeros.
This change some output, notably in base/offset fields of m68k
disassembly which I think looks better that way, and in error
messages. I've kept leading zeros in symbol dumps (objdump -t)
and in PE header dumps.
bfd/
* bfd-in.h (fprintf_vma, sprintf_vma, printf_vma): Delete.
* bfd-in2.h: Regenerate.
* bfd.c (bfd_sprintf_vma): Don't use sprintf_vma.
(bfd_fprintf_vma): Don't use fprintf_vma.
* coff-rs6000.c (xcoff_reloc_type_tls): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(xcoff_ppc_relocate_section): Likewise.
* cofflink.c (_bfd_coff_write_global_sym): Likewise.
* mmo.c (mmo_write_symbols_and_terminator): Likewise.
* srec.c (srec_write_symbols): Likewise.
* elf32-xtensa.c (print_r_reloc): Similarly for fprintf_vma.
* pei-x86_64.c (pex64_dump_xdata): Likewise.
(pex64_bfd_print_pdata_section): Likewise.
* som.c (som_print_symbol): Likewise.
* ecoff.c (_bfd_ecoff_print_symbol): Use bfd_fprintf_vma.
opcodes/
* dis-buf.c (perror_memory, generic_print_address): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* i386-dis.c (print_operand_value, print_displacement): Likewise.
* m68k-dis.c (print_base, print_indexed): Likewise.
* ns32k-dis.c (print_insn_arg): Likewise.
* ia64-gen.c (_opcode_int64_low, _opcode_int64_high): Delete.
(opcode_fprintf_vma): Delete.
(print_main_table): Use PRIx64 to print opcode.
binutils/
* od-macho.c: Replace all uses of printf_vma with bfd_printf_vma.
* objcopy.c (copy_object): Don't use sprintf_vma. Instead use
PRIx64 to print bfd_vma values.
(copy_main): Likewise.
* readelf.c (CHECK_ENTSIZE_VALUES): Likewise.
(dynamic_section_mips_val): Likewise.
(print_vma): Don't use printf_vma. Instead use PRIx64 to print
bfd_vma values.
(dump_ia64_vms_dynamic_fixups): Likewise.
(process_version_sections): Likewise.
* rddbg.c (stab_context): Likewise.
gas/
* config/tc-i386.c (offset_in_range): Don't use sprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(md_assemble): Likewise.
* config/tc-mips.c (load_register, macro): Likewise.
* messages.c (as_internal_value_out_of_range): Likewise.
* read.c (emit_expr_with_reloc): Likewise.
* config/tc-ia64.c (note_register_values): Don't use fprintf_vma.
Instead use PRIx64 to print bfd_vma values.
(print_dependency): Likewise.
* listing.c (list_symbol_table): Use bfd_sprintf_vma.
* symbols.c (print_symbol_value_1): Use %p to print pointers.
(print_binary): Likewise.
(print_expr_1): Use PRIx64 to print bfd_vma values.
* write.c (print_fixup): Use %p to print pointers. Don't use
fprintf_vma.
* testsuite/gas/all/overflow.l: Update expected output.
* testsuite/gas/m68k/mcf-mov3q.d: Likewise.
* testsuite/gas/m68k/operands.d: Likewise.
* testsuite/gas/s12z/truncated.d: Likewise.
ld/
* deffilep.y (def_file_print): Don't use fprintf_vma. Instead
use PRIx64 to print bfd_vma values.
* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Don't use
sprintf_vma. Instead use PRIx64 to print bfd_vma values.
* emultempl/pe.em (gld${EMULATION_NAME}_finish): Likewise.
* ldlang.c (lang_map): Use %V to print region origin.
(lang_one_common): Don't use sprintf_vma.
* ldmisc.c (vfinfo): Don't use fprintf_vma or sprintf_vma.
* pe-dll.c (pe_dll_generate_def_file): Likewise.
gdb/
* remote.c (remote_target::trace_set_readonly_regions): Replace
uses of sprintf_vma with bfd_sprintf_vma.
